1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_types.h" 19 #include "qdf_util.h" 20 #include "qdf_types.h" 21 #include "qdf_lock.h" 22 #include "qdf_mem.h" 23 #include "qdf_nbuf.h" 24 #include "hal_hw_headers.h" 25 #include "hal_internal.h" 26 #include "hal_api.h" 27 #include "target_type.h" 28 #include "wcss_version.h" 29 #include "qdf_module.h" 30 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 36 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 37 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 38 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 40 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 44 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 56 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 57 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 58 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 60 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 61 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 62 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 63 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 64 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 65 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 66 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 68 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 69 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 71 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 72 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 73 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 74 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 76 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 78 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 79 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 80 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 81 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 82 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 83 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 84 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 85 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 86 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 87 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 88 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 90 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 92 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 94 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 95 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 96 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 97 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 98 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 99 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 100 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 105 106 #include "hal_6290_tx.h" 107 #include "hal_6290_rx.h" 108 #include <hal_generic_api.h> 109 #include <hal_wbm.h> 110 111 struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = { 112 /* init and setup */ 113 hal_srng_dst_hw_init_generic, 114 hal_srng_src_hw_init_generic, 115 hal_get_hw_hptp_generic, 116 hal_reo_setup_generic, 117 hal_setup_link_idle_list_generic, 118 119 /* tx */ 120 hal_tx_desc_set_dscp_tid_table_id_6290, 121 hal_tx_set_dscp_tid_map_6290, 122 hal_tx_update_dscp_tid_6290, 123 hal_tx_desc_set_lmac_id_6290, 124 hal_tx_desc_set_buf_addr_generic, 125 hal_tx_desc_set_search_type_generic, 126 hal_tx_desc_set_search_index_generic, 127 hal_tx_comp_get_status_generic, 128 hal_tx_comp_get_release_reason_generic, 129 130 /* rx */ 131 hal_rx_msdu_start_nss_get_6290, 132 hal_rx_mon_hw_desc_get_mpdu_status_6290, 133 hal_rx_get_tlv_6290, 134 hal_rx_proc_phyrx_other_receive_info_tlv_6290, 135 hal_rx_dump_msdu_start_tlv_6290, 136 hal_rx_dump_msdu_end_tlv_6290, 137 hal_get_link_desc_size_6290, 138 hal_rx_mpdu_start_tid_get_6290, 139 hal_rx_msdu_start_reception_type_get_6290, 140 hal_rx_msdu_end_da_idx_get_6290, 141 hal_rx_msdu_desc_info_get_ptr_generic, 142 hal_rx_link_desc_msdu0_ptr_generic, 143 hal_reo_status_get_header_generic, 144 hal_rx_status_get_tlv_info_generic, 145 hal_rx_wbm_err_info_get_generic, 146 hal_rx_dump_mpdu_start_tlv_generic, 147 }; 148 149 struct hal_hw_srng_config hw_srng_table_6290[] = { 150 /* TODO: max_rings can populated by querying HW capabilities */ 151 { /* REO_DST */ 152 .start_ring_id = HAL_SRNG_REO2SW1, 153 .max_rings = 4, 154 .entry_size = sizeof(struct reo_destination_ring) >> 2, 155 .lmac_ring = FALSE, 156 .ring_dir = HAL_SRNG_DST_RING, 157 .reg_start = { 158 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 159 SEQ_WCSS_UMAC_REO_REG_OFFSET), 160 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 161 SEQ_WCSS_UMAC_REO_REG_OFFSET) 162 }, 163 .reg_size = { 164 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 165 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 166 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 167 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 168 }, 169 .max_size = HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 170 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 171 }, 172 { /* REO_EXCEPTION */ 173 /* Designating REO2TCL ring as exception ring. This ring is 174 * similar to other REO2SW rings though it is named as REO2TCL. 175 * Any of theREO2SW rings can be used as exception ring. 176 */ 177 .start_ring_id = HAL_SRNG_REO2TCL, 178 .max_rings = 1, 179 .entry_size = sizeof(struct reo_destination_ring) >> 2, 180 .lmac_ring = FALSE, 181 .ring_dir = HAL_SRNG_DST_RING, 182 .reg_start = { 183 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 184 SEQ_WCSS_UMAC_REO_REG_OFFSET), 185 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 186 SEQ_WCSS_UMAC_REO_REG_OFFSET) 187 }, 188 /* Single ring - provide ring size if multiple rings of this 189 * type are supported 190 */ 191 .reg_size = {}, 192 .max_size = HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 193 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 194 }, 195 { /* REO_REINJECT */ 196 .start_ring_id = HAL_SRNG_SW2REO, 197 .max_rings = 1, 198 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 199 .lmac_ring = FALSE, 200 .ring_dir = HAL_SRNG_SRC_RING, 201 .reg_start = { 202 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 203 SEQ_WCSS_UMAC_REO_REG_OFFSET), 204 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 205 SEQ_WCSS_UMAC_REO_REG_OFFSET) 206 }, 207 /* Single ring - provide ring size if multiple rings of this 208 * type are supported 209 */ 210 .reg_size = {}, 211 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 212 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 213 }, 214 { /* REO_CMD */ 215 .start_ring_id = HAL_SRNG_REO_CMD, 216 .max_rings = 1, 217 .entry_size = (sizeof(struct tlv_32_hdr) + 218 sizeof(struct reo_get_queue_stats)) >> 2, 219 .lmac_ring = FALSE, 220 .ring_dir = HAL_SRNG_SRC_RING, 221 .reg_start = { 222 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 223 SEQ_WCSS_UMAC_REO_REG_OFFSET), 224 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 225 SEQ_WCSS_UMAC_REO_REG_OFFSET), 226 }, 227 /* Single ring - provide ring size if multiple rings of this 228 * type are supported 229 */ 230 .reg_size = {}, 231 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 232 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 233 }, 234 { /* REO_STATUS */ 235 .start_ring_id = HAL_SRNG_REO_STATUS, 236 .max_rings = 1, 237 .entry_size = (sizeof(struct tlv_32_hdr) + 238 sizeof(struct reo_get_queue_stats_status)) >> 2, 239 .lmac_ring = FALSE, 240 .ring_dir = HAL_SRNG_DST_RING, 241 .reg_start = { 242 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 243 SEQ_WCSS_UMAC_REO_REG_OFFSET), 244 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 245 SEQ_WCSS_UMAC_REO_REG_OFFSET), 246 }, 247 /* Single ring - provide ring size if multiple rings of this 248 * type are supported 249 */ 250 .reg_size = {}, 251 .max_size = 252 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 253 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 254 }, 255 { /* TCL_DATA */ 256 .start_ring_id = HAL_SRNG_SW2TCL1, 257 .max_rings = 3, 258 .entry_size = (sizeof(struct tlv_32_hdr) + 259 sizeof(struct tcl_data_cmd)) >> 2, 260 .lmac_ring = FALSE, 261 .ring_dir = HAL_SRNG_SRC_RING, 262 .reg_start = { 263 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 264 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 265 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 266 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 267 }, 268 .reg_size = { 269 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 270 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 271 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 272 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 273 }, 274 .max_size = HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 275 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 276 }, 277 { /* TCL_CMD */ 278 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 279 .max_rings = 1, 280 .entry_size = (sizeof(struct tlv_32_hdr) + 281 sizeof(struct tcl_gse_cmd)) >> 2, 282 .lmac_ring = FALSE, 283 .ring_dir = HAL_SRNG_SRC_RING, 284 .reg_start = { 285 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 286 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 287 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 288 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 289 }, 290 /* Single ring - provide ring size if multiple rings of this 291 * type are supported 292 */ 293 .reg_size = {}, 294 .max_size = 295 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 296 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 297 }, 298 { /* TCL_STATUS */ 299 .start_ring_id = HAL_SRNG_TCL_STATUS, 300 .max_rings = 1, 301 .entry_size = (sizeof(struct tlv_32_hdr) + 302 sizeof(struct tcl_status_ring)) >> 2, 303 .lmac_ring = FALSE, 304 .ring_dir = HAL_SRNG_DST_RING, 305 .reg_start = { 306 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 307 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 308 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 309 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 310 }, 311 /* Single ring - provide ring size if multiple rings of this 312 * type are supported 313 */ 314 .reg_size = {}, 315 .max_size = 316 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 317 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 318 }, 319 { /* CE_SRC */ 320 .start_ring_id = HAL_SRNG_CE_0_SRC, 321 .max_rings = 12, 322 .entry_size = sizeof(struct ce_src_desc) >> 2, 323 .lmac_ring = FALSE, 324 .ring_dir = HAL_SRNG_SRC_RING, 325 .reg_start = { 326 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 327 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 328 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 329 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 330 }, 331 .reg_size = { 332 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 333 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 334 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 335 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 336 }, 337 .max_size = 338 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 339 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 340 }, 341 { /* CE_DST */ 342 .start_ring_id = HAL_SRNG_CE_0_DST, 343 .max_rings = 12, 344 .entry_size = 8 >> 2, 345 /*TODO: entry_size above should actually be 346 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 347 * of struct ce_dst_desc in HW header files 348 */ 349 .lmac_ring = FALSE, 350 .ring_dir = HAL_SRNG_SRC_RING, 351 .reg_start = { 352 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 353 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 354 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 355 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 356 }, 357 .reg_size = { 358 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 359 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 360 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 361 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 362 }, 363 .max_size = 364 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 365 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 366 }, 367 { /* CE_DST_STATUS */ 368 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 369 .max_rings = 12, 370 .entry_size = sizeof(struct ce_stat_desc) >> 2, 371 .lmac_ring = FALSE, 372 .ring_dir = HAL_SRNG_DST_RING, 373 .reg_start = { 374 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 375 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 376 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 377 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 378 }, 379 /* TODO: check destination status ring registers */ 380 .reg_size = { 381 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 382 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 383 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 384 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 385 }, 386 .max_size = 387 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 388 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 389 }, 390 { /* WBM_IDLE_LINK */ 391 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 392 .max_rings = 1, 393 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 394 .lmac_ring = FALSE, 395 .ring_dir = HAL_SRNG_SRC_RING, 396 .reg_start = { 397 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 398 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 399 }, 400 /* Single ring - provide ring size if multiple rings of this 401 * type are supported 402 */ 403 .reg_size = {}, 404 .max_size = 405 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 406 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 407 }, 408 { /* SW2WBM_RELEASE */ 409 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 410 .max_rings = 1, 411 .entry_size = sizeof(struct wbm_release_ring) >> 2, 412 .lmac_ring = FALSE, 413 .ring_dir = HAL_SRNG_SRC_RING, 414 .reg_start = { 415 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 416 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 417 }, 418 /* Single ring - provide ring size if multiple rings of this 419 * type are supported 420 */ 421 .reg_size = {}, 422 .max_size = 423 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 424 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 425 }, 426 { /* WBM2SW_RELEASE */ 427 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 428 .max_rings = 4, 429 .entry_size = sizeof(struct wbm_release_ring) >> 2, 430 .lmac_ring = FALSE, 431 .ring_dir = HAL_SRNG_DST_RING, 432 .reg_start = { 433 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 434 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 435 }, 436 .reg_size = { 437 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 438 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 439 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 440 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 441 }, 442 .max_size = 443 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 444 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 445 }, 446 { /* RXDMA_BUF */ 447 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 448 #ifdef IPA_OFFLOAD 449 .max_rings = 3, 450 #else 451 .max_rings = 2, 452 #endif 453 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 454 .lmac_ring = TRUE, 455 .ring_dir = HAL_SRNG_SRC_RING, 456 /* reg_start is not set because LMAC rings are not accessed 457 * from host 458 */ 459 .reg_start = {}, 460 .reg_size = {}, 461 .max_size = HAL_RXDMA_MAX_RING_SIZE, 462 }, 463 { /* RXDMA_DST */ 464 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 465 .max_rings = 1, 466 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 467 .lmac_ring = TRUE, 468 .ring_dir = HAL_SRNG_DST_RING, 469 /* reg_start is not set because LMAC rings are not accessed 470 * from host 471 */ 472 .reg_start = {}, 473 .reg_size = {}, 474 .max_size = HAL_RXDMA_MAX_RING_SIZE, 475 }, 476 { /* RXDMA_MONITOR_BUF */ 477 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 478 .max_rings = 1, 479 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 480 .lmac_ring = TRUE, 481 .ring_dir = HAL_SRNG_SRC_RING, 482 /* reg_start is not set because LMAC rings are not accessed 483 * from host 484 */ 485 .reg_start = {}, 486 .reg_size = {}, 487 .max_size = HAL_RXDMA_MAX_RING_SIZE, 488 }, 489 { /* RXDMA_MONITOR_STATUS */ 490 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 491 .max_rings = 1, 492 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 493 .lmac_ring = TRUE, 494 .ring_dir = HAL_SRNG_SRC_RING, 495 /* reg_start is not set because LMAC rings are not accessed 496 * from host 497 */ 498 .reg_start = {}, 499 .reg_size = {}, 500 .max_size = HAL_RXDMA_MAX_RING_SIZE, 501 }, 502 { /* RXDMA_MONITOR_DST */ 503 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 504 .max_rings = 1, 505 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 506 .lmac_ring = TRUE, 507 .ring_dir = HAL_SRNG_DST_RING, 508 /* reg_start is not set because LMAC rings are not accessed 509 * from host 510 */ 511 .reg_start = {}, 512 .reg_size = {}, 513 .max_size = HAL_RXDMA_MAX_RING_SIZE, 514 }, 515 { /* RXDMA_MONITOR_DESC */ 516 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 517 .max_rings = 1, 518 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 519 .lmac_ring = TRUE, 520 .ring_dir = HAL_SRNG_SRC_RING, 521 /* reg_start is not set because LMAC rings are not accessed 522 * from host 523 */ 524 .reg_start = {}, 525 .reg_size = {}, 526 .max_size = HAL_RXDMA_MAX_RING_SIZE, 527 }, 528 { /* DIR_BUF_RX_DMA_SRC */ 529 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 530 .max_rings = 1, 531 .entry_size = 2, 532 .lmac_ring = TRUE, 533 .ring_dir = HAL_SRNG_SRC_RING, 534 /* reg_start is not set because LMAC rings are not accessed 535 * from host 536 */ 537 .reg_start = {}, 538 .reg_size = {}, 539 .max_size = HAL_RXDMA_MAX_RING_SIZE, 540 }, 541 #ifdef WLAN_FEATURE_CIF_CFR 542 { /* WIFI_POS_SRC */ 543 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 544 .max_rings = 1, 545 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 546 .lmac_ring = TRUE, 547 .ring_dir = HAL_SRNG_SRC_RING, 548 /* reg_start is not set because LMAC rings are not accessed 549 * from host 550 */ 551 .reg_start = {}, 552 .reg_size = {}, 553 .max_size = HAL_RXDMA_MAX_RING_SIZE, 554 }, 555 #endif 556 }; 557 558 int32_t hal_hw_reg_offset_qca6290[] = { 559 /* dst */ 560 REG_OFFSET(DST, HP), 561 REG_OFFSET(DST, TP), 562 REG_OFFSET(DST, ID), 563 REG_OFFSET(DST, MISC), 564 REG_OFFSET(DST, HP_ADDR_LSB), 565 REG_OFFSET(DST, HP_ADDR_MSB), 566 REG_OFFSET(DST, MSI1_BASE_LSB), 567 REG_OFFSET(DST, MSI1_BASE_MSB), 568 REG_OFFSET(DST, MSI1_DATA), 569 REG_OFFSET(DST, BASE_LSB), 570 REG_OFFSET(DST, BASE_MSB), 571 REG_OFFSET(DST, PRODUCER_INT_SETUP), 572 /* src */ 573 REG_OFFSET(SRC, HP), 574 REG_OFFSET(SRC, TP), 575 REG_OFFSET(SRC, ID), 576 REG_OFFSET(SRC, MISC), 577 REG_OFFSET(SRC, TP_ADDR_LSB), 578 REG_OFFSET(SRC, TP_ADDR_MSB), 579 REG_OFFSET(SRC, MSI1_BASE_LSB), 580 REG_OFFSET(SRC, MSI1_BASE_MSB), 581 REG_OFFSET(SRC, MSI1_DATA), 582 REG_OFFSET(SRC, BASE_LSB), 583 REG_OFFSET(SRC, BASE_MSB), 584 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 585 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 586 }; 587 588 /** 589 * hal_qca6290_attach() - Attach 6290 target specific hal_soc ops, 590 * offset and srng table 591 */ 592 void hal_qca6290_attach(struct hal_soc *hal_soc) 593 { 594 hal_soc->hw_srng_table = hw_srng_table_6290; 595 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6290; 596 hal_soc->ops = &qca6290_hal_hw_txrx_ops; 597 } 598