1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "qdf_types.h" 19 #include "qdf_util.h" 20 #include "qdf_types.h" 21 #include "qdf_lock.h" 22 #include "qdf_mem.h" 23 #include "qdf_nbuf.h" 24 #include "hal_hw_headers.h" 25 #include "hal_internal.h" 26 #include "hal_api.h" 27 #include "target_type.h" 28 #include "wcss_version.h" 29 #include "qdf_module.h" 30 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 36 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 37 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 38 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 39 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 40 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 41 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 42 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 44 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 46 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 48 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 56 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 57 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 58 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 59 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 60 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 61 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 62 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 63 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 64 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 65 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 66 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 67 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 68 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 69 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 71 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 72 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 73 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 74 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 75 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 76 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 77 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 78 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 79 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 80 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 81 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 82 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 83 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 84 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 85 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 86 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 87 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 88 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 90 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 92 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 94 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 95 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 96 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 97 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 98 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 99 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 100 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 101 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 102 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 103 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 104 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 105 106 #include "hal_6290_tx.h" 107 #include "hal_6290_rx.h" 108 #include <hal_generic_api.h> 109 #include <hal_wbm.h> 110 111 struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = { 112 /* init and setup */ 113 hal_srng_dst_hw_init_generic, 114 hal_srng_src_hw_init_generic, 115 hal_reo_setup_generic, 116 hal_setup_link_idle_list_generic, 117 118 /* tx */ 119 hal_tx_desc_set_dscp_tid_table_id_6290, 120 hal_tx_set_dscp_tid_map_6290, 121 hal_tx_update_dscp_tid_6290, 122 hal_tx_desc_set_lmac_id_6290, 123 hal_tx_desc_set_buf_addr_generic, 124 hal_tx_comp_get_status_generic, 125 126 /* rx */ 127 hal_rx_msdu_start_nss_get_6290, 128 hal_rx_mon_hw_desc_get_mpdu_status_6290, 129 hal_rx_get_tlv_6290, 130 hal_rx_proc_phyrx_other_receive_info_tlv_6290, 131 hal_rx_dump_msdu_start_tlv_6290, 132 hal_rx_dump_msdu_end_tlv_6290, 133 hal_get_link_desc_size_6290, 134 hal_rx_mpdu_start_tid_get_6290, 135 hal_rx_msdu_start_reception_type_get_6290, 136 hal_rx_msdu_end_da_idx_get_6290, 137 hal_rx_msdu_desc_info_get_ptr_generic, 138 hal_rx_link_desc_msdu0_ptr_generic, 139 hal_reo_status_get_header_generic, 140 hal_rx_status_get_tlv_info_generic, 141 hal_tx_desc_set_search_type_generic, 142 hal_tx_desc_set_search_index_generic, 143 }; 144 145 struct hal_hw_srng_config hw_srng_table_6290[] = { 146 /* TODO: max_rings can populated by querying HW capabilities */ 147 { /* REO_DST */ 148 .start_ring_id = HAL_SRNG_REO2SW1, 149 .max_rings = 4, 150 .entry_size = sizeof(struct reo_destination_ring) >> 2, 151 .lmac_ring = FALSE, 152 .ring_dir = HAL_SRNG_DST_RING, 153 .reg_start = { 154 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 155 SEQ_WCSS_UMAC_REO_REG_OFFSET), 156 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 157 SEQ_WCSS_UMAC_REO_REG_OFFSET) 158 }, 159 .reg_size = { 160 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 161 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 162 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 163 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 164 }, 165 .max_size = HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 166 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 167 }, 168 { /* REO_EXCEPTION */ 169 /* Designating REO2TCL ring as exception ring. This ring is 170 * similar to other REO2SW rings though it is named as REO2TCL. 171 * Any of theREO2SW rings can be used as exception ring. 172 */ 173 .start_ring_id = HAL_SRNG_REO2TCL, 174 .max_rings = 1, 175 .entry_size = sizeof(struct reo_destination_ring) >> 2, 176 .lmac_ring = FALSE, 177 .ring_dir = HAL_SRNG_DST_RING, 178 .reg_start = { 179 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 180 SEQ_WCSS_UMAC_REO_REG_OFFSET), 181 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 182 SEQ_WCSS_UMAC_REO_REG_OFFSET) 183 }, 184 /* Single ring - provide ring size if multiple rings of this 185 * type are supported 186 */ 187 .reg_size = {}, 188 .max_size = HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 189 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 190 }, 191 { /* REO_REINJECT */ 192 .start_ring_id = HAL_SRNG_SW2REO, 193 .max_rings = 1, 194 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 195 .lmac_ring = FALSE, 196 .ring_dir = HAL_SRNG_SRC_RING, 197 .reg_start = { 198 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 199 SEQ_WCSS_UMAC_REO_REG_OFFSET), 200 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 201 SEQ_WCSS_UMAC_REO_REG_OFFSET) 202 }, 203 /* Single ring - provide ring size if multiple rings of this 204 * type are supported 205 */ 206 .reg_size = {}, 207 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 208 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 209 }, 210 { /* REO_CMD */ 211 .start_ring_id = HAL_SRNG_REO_CMD, 212 .max_rings = 1, 213 .entry_size = (sizeof(struct tlv_32_hdr) + 214 sizeof(struct reo_get_queue_stats)) >> 2, 215 .lmac_ring = FALSE, 216 .ring_dir = HAL_SRNG_SRC_RING, 217 .reg_start = { 218 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 219 SEQ_WCSS_UMAC_REO_REG_OFFSET), 220 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 221 SEQ_WCSS_UMAC_REO_REG_OFFSET), 222 }, 223 /* Single ring - provide ring size if multiple rings of this 224 * type are supported 225 */ 226 .reg_size = {}, 227 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 228 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 229 }, 230 { /* REO_STATUS */ 231 .start_ring_id = HAL_SRNG_REO_STATUS, 232 .max_rings = 1, 233 .entry_size = (sizeof(struct tlv_32_hdr) + 234 sizeof(struct reo_get_queue_stats_status)) >> 2, 235 .lmac_ring = FALSE, 236 .ring_dir = HAL_SRNG_DST_RING, 237 .reg_start = { 238 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 239 SEQ_WCSS_UMAC_REO_REG_OFFSET), 240 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 241 SEQ_WCSS_UMAC_REO_REG_OFFSET), 242 }, 243 /* Single ring - provide ring size if multiple rings of this 244 * type are supported 245 */ 246 .reg_size = {}, 247 .max_size = 248 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 249 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 250 }, 251 { /* TCL_DATA */ 252 .start_ring_id = HAL_SRNG_SW2TCL1, 253 .max_rings = 3, 254 .entry_size = (sizeof(struct tlv_32_hdr) + 255 sizeof(struct tcl_data_cmd)) >> 2, 256 .lmac_ring = FALSE, 257 .ring_dir = HAL_SRNG_SRC_RING, 258 .reg_start = { 259 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 260 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 261 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 262 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 263 }, 264 .reg_size = { 265 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 266 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 267 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 268 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 269 }, 270 .max_size = HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 271 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 272 }, 273 { /* TCL_CMD */ 274 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 275 .max_rings = 1, 276 .entry_size = (sizeof(struct tlv_32_hdr) + 277 sizeof(struct tcl_gse_cmd)) >> 2, 278 .lmac_ring = FALSE, 279 .ring_dir = HAL_SRNG_SRC_RING, 280 .reg_start = { 281 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 282 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 283 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 284 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 285 }, 286 /* Single ring - provide ring size if multiple rings of this 287 * type are supported 288 */ 289 .reg_size = {}, 290 .max_size = 291 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 292 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 293 }, 294 { /* TCL_STATUS */ 295 .start_ring_id = HAL_SRNG_TCL_STATUS, 296 .max_rings = 1, 297 .entry_size = (sizeof(struct tlv_32_hdr) + 298 sizeof(struct tcl_status_ring)) >> 2, 299 .lmac_ring = FALSE, 300 .ring_dir = HAL_SRNG_DST_RING, 301 .reg_start = { 302 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 303 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 304 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 305 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 306 }, 307 /* Single ring - provide ring size if multiple rings of this 308 * type are supported 309 */ 310 .reg_size = {}, 311 .max_size = 312 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 313 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 314 }, 315 { /* CE_SRC */ 316 .start_ring_id = HAL_SRNG_CE_0_SRC, 317 .max_rings = 12, 318 .entry_size = sizeof(struct ce_src_desc) >> 2, 319 .lmac_ring = FALSE, 320 .ring_dir = HAL_SRNG_SRC_RING, 321 .reg_start = { 322 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 323 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 324 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 325 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 326 }, 327 .reg_size = { 328 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 329 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 330 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 331 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 332 }, 333 .max_size = 334 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 335 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 336 }, 337 { /* CE_DST */ 338 .start_ring_id = HAL_SRNG_CE_0_DST, 339 .max_rings = 12, 340 .entry_size = 8 >> 2, 341 /*TODO: entry_size above should actually be 342 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 343 * of struct ce_dst_desc in HW header files 344 */ 345 .lmac_ring = FALSE, 346 .ring_dir = HAL_SRNG_SRC_RING, 347 .reg_start = { 348 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 349 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 350 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 351 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 352 }, 353 .reg_size = { 354 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 355 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 356 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 357 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 358 }, 359 .max_size = 360 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 361 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 362 }, 363 { /* CE_DST_STATUS */ 364 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 365 .max_rings = 12, 366 .entry_size = sizeof(struct ce_stat_desc) >> 2, 367 .lmac_ring = FALSE, 368 .ring_dir = HAL_SRNG_DST_RING, 369 .reg_start = { 370 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 371 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 372 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 373 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 374 }, 375 /* TODO: check destination status ring registers */ 376 .reg_size = { 377 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 378 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 379 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 380 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 381 }, 382 .max_size = 383 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 384 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 385 }, 386 { /* WBM_IDLE_LINK */ 387 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 388 .max_rings = 1, 389 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 390 .lmac_ring = FALSE, 391 .ring_dir = HAL_SRNG_SRC_RING, 392 .reg_start = { 393 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 394 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 395 }, 396 /* Single ring - provide ring size if multiple rings of this 397 * type are supported 398 */ 399 .reg_size = {}, 400 .max_size = 401 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 402 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 403 }, 404 { /* SW2WBM_RELEASE */ 405 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 406 .max_rings = 1, 407 .entry_size = sizeof(struct wbm_release_ring) >> 2, 408 .lmac_ring = FALSE, 409 .ring_dir = HAL_SRNG_SRC_RING, 410 .reg_start = { 411 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 412 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 413 }, 414 /* Single ring - provide ring size if multiple rings of this 415 * type are supported 416 */ 417 .reg_size = {}, 418 .max_size = 419 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 420 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 421 }, 422 { /* WBM2SW_RELEASE */ 423 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 424 .max_rings = 4, 425 .entry_size = sizeof(struct wbm_release_ring) >> 2, 426 .lmac_ring = FALSE, 427 .ring_dir = HAL_SRNG_DST_RING, 428 .reg_start = { 429 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 430 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 431 }, 432 .reg_size = { 433 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 434 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 435 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 436 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 437 }, 438 .max_size = 439 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 440 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 441 }, 442 { /* RXDMA_BUF */ 443 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 444 #ifdef IPA_OFFLOAD 445 .max_rings = 3, 446 #else 447 .max_rings = 2, 448 #endif 449 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 450 .lmac_ring = TRUE, 451 .ring_dir = HAL_SRNG_SRC_RING, 452 /* reg_start is not set because LMAC rings are not accessed 453 * from host 454 */ 455 .reg_start = {}, 456 .reg_size = {}, 457 .max_size = HAL_RXDMA_MAX_RING_SIZE, 458 }, 459 { /* RXDMA_DST */ 460 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 461 .max_rings = 1, 462 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 463 .lmac_ring = TRUE, 464 .ring_dir = HAL_SRNG_DST_RING, 465 /* reg_start is not set because LMAC rings are not accessed 466 * from host 467 */ 468 .reg_start = {}, 469 .reg_size = {}, 470 .max_size = HAL_RXDMA_MAX_RING_SIZE, 471 }, 472 { /* RXDMA_MONITOR_BUF */ 473 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 474 .max_rings = 1, 475 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 476 .lmac_ring = TRUE, 477 .ring_dir = HAL_SRNG_SRC_RING, 478 /* reg_start is not set because LMAC rings are not accessed 479 * from host 480 */ 481 .reg_start = {}, 482 .reg_size = {}, 483 .max_size = HAL_RXDMA_MAX_RING_SIZE, 484 }, 485 { /* RXDMA_MONITOR_STATUS */ 486 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 487 .max_rings = 1, 488 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 489 .lmac_ring = TRUE, 490 .ring_dir = HAL_SRNG_SRC_RING, 491 /* reg_start is not set because LMAC rings are not accessed 492 * from host 493 */ 494 .reg_start = {}, 495 .reg_size = {}, 496 .max_size = HAL_RXDMA_MAX_RING_SIZE, 497 }, 498 { /* RXDMA_MONITOR_DST */ 499 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 500 .max_rings = 1, 501 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 502 .lmac_ring = TRUE, 503 .ring_dir = HAL_SRNG_DST_RING, 504 /* reg_start is not set because LMAC rings are not accessed 505 * from host 506 */ 507 .reg_start = {}, 508 .reg_size = {}, 509 .max_size = HAL_RXDMA_MAX_RING_SIZE, 510 }, 511 { /* RXDMA_MONITOR_DESC */ 512 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 513 .max_rings = 1, 514 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 515 .lmac_ring = TRUE, 516 .ring_dir = HAL_SRNG_SRC_RING, 517 /* reg_start is not set because LMAC rings are not accessed 518 * from host 519 */ 520 .reg_start = {}, 521 .reg_size = {}, 522 .max_size = HAL_RXDMA_MAX_RING_SIZE, 523 }, 524 { /* DIR_BUF_RX_DMA_SRC */ 525 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 526 .max_rings = 1, 527 .entry_size = 2, 528 .lmac_ring = TRUE, 529 .ring_dir = HAL_SRNG_SRC_RING, 530 /* reg_start is not set because LMAC rings are not accessed 531 * from host 532 */ 533 .reg_start = {}, 534 .reg_size = {}, 535 .max_size = HAL_RXDMA_MAX_RING_SIZE, 536 }, 537 #ifdef WLAN_FEATURE_CIF_CFR 538 { /* WIFI_POS_SRC */ 539 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 540 .max_rings = 1, 541 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 542 .lmac_ring = TRUE, 543 .ring_dir = HAL_SRNG_SRC_RING, 544 /* reg_start is not set because LMAC rings are not accessed 545 * from host 546 */ 547 .reg_start = {}, 548 .reg_size = {}, 549 .max_size = HAL_RXDMA_MAX_RING_SIZE, 550 }, 551 #endif 552 }; 553 554 int32_t hal_hw_reg_offset_qca6290[] = { 555 /* dst */ 556 REG_OFFSET(DST, HP), 557 REG_OFFSET(DST, TP), 558 REG_OFFSET(DST, ID), 559 REG_OFFSET(DST, MISC), 560 REG_OFFSET(DST, HP_ADDR_LSB), 561 REG_OFFSET(DST, HP_ADDR_MSB), 562 REG_OFFSET(DST, MSI1_BASE_LSB), 563 REG_OFFSET(DST, MSI1_BASE_MSB), 564 REG_OFFSET(DST, MSI1_DATA), 565 REG_OFFSET(DST, BASE_LSB), 566 REG_OFFSET(DST, BASE_MSB), 567 REG_OFFSET(DST, PRODUCER_INT_SETUP), 568 /* src */ 569 REG_OFFSET(SRC, HP), 570 REG_OFFSET(SRC, TP), 571 REG_OFFSET(SRC, ID), 572 REG_OFFSET(SRC, MISC), 573 REG_OFFSET(SRC, TP_ADDR_LSB), 574 REG_OFFSET(SRC, TP_ADDR_MSB), 575 REG_OFFSET(SRC, MSI1_BASE_LSB), 576 REG_OFFSET(SRC, MSI1_BASE_MSB), 577 REG_OFFSET(SRC, MSI1_DATA), 578 REG_OFFSET(SRC, BASE_LSB), 579 REG_OFFSET(SRC, BASE_MSB), 580 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 581 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 582 }; 583 584 /** 585 * hal_qca6290_attach() - Attach 6290 target specific hal_soc ops, 586 * offset and srng table 587 */ 588 void hal_qca6290_attach(struct hal_soc *hal_soc) 589 { 590 hal_soc->hw_srng_table = hw_srng_table_6290; 591 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6290; 592 hal_soc->ops = &qca6290_hal_hw_txrx_ops; 593 } 594