1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE 16 */ 17 #include "qdf_types.h" 18 #include "qdf_util.h" 19 #include "qdf_mem.h" 20 #include "qdf_nbuf.h" 21 #include "qdf_module.h" 22 23 #include "target_type.h" 24 #include "wcss_version.h" 25 26 #include "hal_be_hw_headers.h" 27 #include "hal_internal.h" 28 #include "hal_api.h" 29 #include "hal_flow.h" 30 #include "rx_flow_search_entry.h" 31 #include "hal_rx_flow_info.h" 32 #include "hal_be_api.h" 33 #include "tcl_entrance_from_ppe_ring.h" 34 #include "sw_monitor_ring.h" 35 #include "wcss_seq_hwioreg_umac.h" 36 #include "wfss_ce_reg_seq_hwioreg.h" 37 #include <uniform_reo_status_header.h> 38 #include <wbm_release_ring_tx.h> 39 #include <phyrx_location.h> 40 #ifdef QCA_MONITOR_2_0_SUPPORT 41 #include <mon_ingress_ring.h> 42 #include <mon_destination_ring.h> 43 #endif 44 #include "rx_reo_queue_1k.h" 45 46 #include <hal_be_rx.h> 47 48 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 49 RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 50 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 51 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 52 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 53 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 54 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 55 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 56 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 57 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 58 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 59 STATUS_HEADER_REO_STATUS_NUMBER 60 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 61 STATUS_HEADER_TIMESTAMP 62 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 64 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 65 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 66 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 67 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 68 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 69 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 70 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 71 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 72 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 73 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 74 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 75 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 76 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 77 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 78 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 79 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 80 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 81 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 82 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 83 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 84 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 85 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 86 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 87 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 88 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 89 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 90 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 91 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 92 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 93 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 94 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 95 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 96 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 97 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 98 99 #include "hal_be_api_mon.h" 100 101 #define CMEM_REG_BASE 0x00100000 102 103 /* For Berryllium sw2rxdma ring size increased to 20 bits */ 104 #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF 105 106 #include "hal_5332_rx.h" 107 #include "hal_5332_tx.h" 108 #include "hal_be_rx_tlv.h" 109 #include <hal_be_generic_api.h> 110 111 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 112 #define HAL_PPE_VP_ENTRIES_MAX 32 113 /** 114 * hal_get_link_desc_size_5332(): API to get the link desc size 115 * 116 * Return: uint32_t 117 */ 118 static uint32_t hal_get_link_desc_size_5332(void) 119 { 120 return LINK_DESC_SIZE; 121 } 122 123 /** 124 * hal_rx_get_tlv_5332(): API to get the tlv 125 * 126 * @rx_tlv: TLV data extracted from the rx packet 127 * Return: uint8_t 128 */ 129 static uint8_t hal_rx_get_tlv_5332(void *rx_tlv) 130 { 131 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH); 132 } 133 134 /** 135 * hal_rx_wbm_err_msdu_continuation_get_5332 () - API to check if WBM 136 * msdu continuation bit is set 137 * 138 *@wbm_desc: wbm release ring descriptor 139 * 140 * Return: true if msdu continuation bit is set. 141 */ 142 uint8_t hal_rx_wbm_err_msdu_continuation_get_5332(void *wbm_desc) 143 { 144 uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) + 145 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET); 146 147 return (comp_desc & 148 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >> 149 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB; 150 } 151 152 /** 153 * hal_rx_proc_phyrx_other_receive_info_tlv_5332(): API to get tlv info 154 * 155 * Return: uint32_t 156 */ 157 static inline 158 void hal_rx_proc_phyrx_other_receive_info_tlv_5332(void *rx_tlv_hdr, 159 void *ppdu_info_hdl) 160 { 161 uint32_t tlv_tag, tlv_len; 162 uint32_t temp_len, other_tlv_len, other_tlv_tag; 163 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 164 void *other_tlv_hdr = NULL; 165 void *other_tlv = NULL; 166 167 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 168 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 169 temp_len = 0; 170 171 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 172 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 173 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 174 175 temp_len += other_tlv_len; 176 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 177 178 switch (other_tlv_tag) { 179 default: 180 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 181 "%s unhandled TLV type: %d, TLV len:%d", 182 __func__, other_tlv_tag, other_tlv_len); 183 break; 184 } 185 } 186 187 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 188 static inline 189 void hal_rx_get_bb_info_5332(void *rx_tlv, void *ppdu_info_hdl) 190 { 191 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 192 193 ppdu_info->cfr_info.bb_captured_channel = 194 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL); 195 196 ppdu_info->cfr_info.bb_captured_timeout = 197 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT); 198 199 ppdu_info->cfr_info.bb_captured_reason = 200 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON); 201 } 202 203 static inline 204 void hal_rx_get_rtt_info_5332(void *rx_tlv, void *ppdu_info_hdl) 205 { 206 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 207 208 ppdu_info->cfr_info.rx_location_info_valid = 209 HAL_RX_GET(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 210 RX_LOCATION_INFO_VALID); 211 212 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 213 HAL_RX_GET(rx_tlv, 214 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 215 RTT_CHE_BUFFER_POINTER_LOW32); 216 217 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 218 HAL_RX_GET(rx_tlv, 219 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 220 RTT_CHE_BUFFER_POINTER_HIGH8); 221 222 ppdu_info->cfr_info.chan_capture_status = 223 HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv); 224 225 ppdu_info->cfr_info.rx_start_ts = 226 HAL_RX_GET(rx_tlv, 227 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 228 RX_START_TS); 229 230 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) 231 HAL_RX_GET(rx_tlv, 232 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 233 RTT_CFO_MEASUREMENT); 234 235 ppdu_info->cfr_info.agc_gain_info0 = 236 HAL_RX_GET(rx_tlv, 237 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 238 GAIN_CHAIN0); 239 240 ppdu_info->cfr_info.agc_gain_info0 |= 241 (((uint32_t)HAL_RX_GET(rx_tlv, 242 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 243 GAIN_CHAIN1)) << 16); 244 245 ppdu_info->cfr_info.agc_gain_info1 = 246 HAL_RX_GET(rx_tlv, 247 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 248 GAIN_CHAIN2); 249 250 ppdu_info->cfr_info.agc_gain_info1 |= 251 (((uint32_t)HAL_RX_GET(rx_tlv, 252 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 253 GAIN_CHAIN3)) << 16); 254 255 ppdu_info->cfr_info.agc_gain_info2 = 0; 256 257 ppdu_info->cfr_info.agc_gain_info3 = 0; 258 } 259 #endif 260 261 /** 262 * hal_rx_dump_mpdu_start_tlv_5332: dump RX mpdu_start TLV in structured 263 * human readable format. 264 * @mpdu_start: pointer the rx_attention TLV in pkt. 265 * @dbg_level: log level. 266 * 267 * Return: void 268 */ 269 static inline void hal_rx_dump_mpdu_start_tlv_5332(void *mpdustart, 270 uint8_t dbg_level) 271 { 272 #ifdef CONFIG_WORD_BASED_TLV 273 struct rx_mpdu_start_compact *mpdu_info = 274 (struct rx_mpdu_start_compact *)mpdustart; 275 #else 276 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 277 struct rx_mpdu_info *mpdu_info = 278 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 279 #endif 280 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 281 "rx_mpdu_start tlv (1/5) - " 282 "rx_reo_queue_desc_addr_39_32 :%x" 283 "receive_queue_number:%x " 284 "pre_delim_err_warning:%x " 285 "first_delim_err:%x " 286 "pn_31_0:%x " 287 "pn_63_32:%x " 288 "pn_95_64:%x ", 289 mpdu_info->rx_reo_queue_desc_addr_39_32, 290 mpdu_info->receive_queue_number, 291 mpdu_info->pre_delim_err_warning, 292 mpdu_info->first_delim_err, 293 mpdu_info->pn_31_0, 294 mpdu_info->pn_63_32, 295 mpdu_info->pn_95_64); 296 297 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 298 "rx_mpdu_start tlv (2/5) - " 299 "ast_index:%x " 300 "sw_peer_id:%x " 301 "mpdu_frame_control_valid:%x " 302 "mpdu_duration_valid:%x " 303 "mac_addr_ad1_valid:%x " 304 "mac_addr_ad2_valid:%x " 305 "mac_addr_ad3_valid:%x " 306 "mac_addr_ad4_valid:%x " 307 "mpdu_sequence_control_valid :%x" 308 "mpdu_qos_control_valid:%x " 309 "mpdu_ht_control_valid:%x " 310 "frame_encryption_info_valid :%x", 311 mpdu_info->ast_index, 312 mpdu_info->sw_peer_id, 313 mpdu_info->mpdu_frame_control_valid, 314 mpdu_info->mpdu_duration_valid, 315 mpdu_info->mac_addr_ad1_valid, 316 mpdu_info->mac_addr_ad2_valid, 317 mpdu_info->mac_addr_ad3_valid, 318 mpdu_info->mac_addr_ad4_valid, 319 mpdu_info->mpdu_sequence_control_valid, 320 mpdu_info->mpdu_qos_control_valid, 321 mpdu_info->mpdu_ht_control_valid, 322 mpdu_info->frame_encryption_info_valid); 323 324 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 325 "rx_mpdu_start tlv (3/5) - " 326 "mpdu_fragment_number:%x " 327 "more_fragment_flag:%x " 328 "fr_ds:%x " 329 "to_ds:%x " 330 "encrypted:%x " 331 "mpdu_retry:%x " 332 "mpdu_sequence_number:%x ", 333 mpdu_info->mpdu_fragment_number, 334 mpdu_info->more_fragment_flag, 335 mpdu_info->fr_ds, 336 mpdu_info->to_ds, 337 mpdu_info->encrypted, 338 mpdu_info->mpdu_retry, 339 mpdu_info->mpdu_sequence_number); 340 341 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 342 "rx_mpdu_start tlv (4/5) - " 343 "mpdu_frame_control_field:%x " 344 "mpdu_duration_field:%x ", 345 mpdu_info->mpdu_frame_control_field, 346 mpdu_info->mpdu_duration_field); 347 348 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 349 "rx_mpdu_start tlv (5/5) - " 350 "mac_addr_ad1_31_0:%x " 351 "mac_addr_ad1_47_32:%x " 352 "mac_addr_ad2_15_0:%x " 353 "mac_addr_ad2_47_16:%x " 354 "mac_addr_ad3_31_0:%x " 355 "mac_addr_ad3_47_32:%x " 356 "mpdu_sequence_control_field :%x", 357 mpdu_info->mac_addr_ad1_31_0, 358 mpdu_info->mac_addr_ad1_47_32, 359 mpdu_info->mac_addr_ad2_15_0, 360 mpdu_info->mac_addr_ad2_47_16, 361 mpdu_info->mac_addr_ad3_31_0, 362 mpdu_info->mac_addr_ad3_47_32, 363 mpdu_info->mpdu_sequence_control_field); 364 } 365 366 /** 367 * hal_rx_dump_msdu_end_tlv_5332: dump RX msdu_end TLV in structured 368 * human readable format. 369 * @ msdu_end: pointer the msdu_end TLV in pkt. 370 * @ dbg_level: log level. 371 * 372 * Return: void 373 */ 374 static void hal_rx_dump_msdu_end_tlv_5332(void *msduend, 375 uint8_t dbg_level) 376 { 377 #ifdef CONFIG_WORD_BASED_TLV 378 struct rx_msdu_end_compact *msdu_end = 379 (struct rx_msdu_end_compact *)msduend; 380 #else 381 struct rx_msdu_end *msdu_end = 382 (struct rx_msdu_end *)msduend; 383 #endif 384 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 385 "rx_msdu_end tlv - " 386 "key_id_octet: %d " 387 "tcp_udp_chksum: %d " 388 "sa_idx_timeout: %d " 389 "da_idx_timeout: %d " 390 "msdu_limit_error: %d " 391 "flow_idx_timeout: %d " 392 "flow_idx_invalid: %d " 393 "wifi_parser_error: %d " 394 "sa_is_valid: %d " 395 "da_is_valid: %d " 396 "da_is_mcbc: %d " 397 "tkip_mic_err: %d " 398 "l3_header_padding: %d " 399 "first_msdu: %d " 400 "last_msdu: %d " 401 "sa_idx: %d " 402 "msdu_drop: %d " 403 "reo_destination_indication: %d " 404 "flow_idx: %d " 405 "fse_metadata: %d " 406 "cce_metadata: %d " 407 "sa_sw_peer_id: %d ", 408 msdu_end->key_id_octet, 409 msdu_end->tcp_udp_chksum, 410 msdu_end->sa_idx_timeout, 411 msdu_end->da_idx_timeout, 412 msdu_end->msdu_limit_error, 413 msdu_end->flow_idx_timeout, 414 msdu_end->flow_idx_invalid, 415 msdu_end->wifi_parser_error, 416 msdu_end->sa_is_valid, 417 msdu_end->da_is_valid, 418 msdu_end->da_is_mcbc, 419 msdu_end->tkip_mic_err, 420 msdu_end->l3_header_padding, 421 msdu_end->first_msdu, 422 msdu_end->last_msdu, 423 msdu_end->sa_idx, 424 msdu_end->msdu_drop, 425 msdu_end->reo_destination_indication, 426 msdu_end->flow_idx, 427 msdu_end->fse_metadata, 428 msdu_end->cce_metadata, 429 msdu_end->sa_sw_peer_id); 430 } 431 432 /** 433 * hal_reo_status_get_header_5332 - Process reo desc info 434 * @d - Pointer to reo descriptor 435 * @b - tlv type info 436 * @h1 - Pointer to hal_reo_status_header where info to be stored 437 * 438 * Return - none. 439 * 440 */ 441 static void hal_reo_status_get_header_5332(hal_ring_desc_t ring_desc, 442 int b, void *h1) 443 { 444 uint64_t *d = (uint64_t *)ring_desc; 445 uint64_t val1 = 0; 446 struct hal_reo_status_header *h = 447 (struct hal_reo_status_header *)h1; 448 449 /* Offsets of descriptor fields defined in HW headers start 450 * from the field after TLV header 451 */ 452 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr)); 453 454 switch (b) { 455 case HAL_REO_QUEUE_STATS_STATUS_TLV: 456 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 457 STATUS_HEADER_REO_STATUS_NUMBER)]; 458 break; 459 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 460 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 461 STATUS_HEADER_REO_STATUS_NUMBER)]; 462 break; 463 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 464 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 465 STATUS_HEADER_REO_STATUS_NUMBER)]; 466 break; 467 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 468 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 469 STATUS_HEADER_REO_STATUS_NUMBER)]; 470 break; 471 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 472 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 473 STATUS_HEADER_REO_STATUS_NUMBER)]; 474 break; 475 case HAL_REO_DESC_THRES_STATUS_TLV: 476 val1 = 477 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 478 STATUS_HEADER_REO_STATUS_NUMBER)]; 479 break; 480 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 481 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 482 STATUS_HEADER_REO_STATUS_NUMBER)]; 483 break; 484 default: 485 qdf_nofl_err("ERROR: Unknown tlv\n"); 486 break; 487 } 488 h->cmd_num = 489 HAL_GET_FIELD( 490 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER, 491 val1); 492 h->exec_time = 493 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 494 CMD_EXECUTION_TIME, val1); 495 h->status = 496 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 497 REO_CMD_EXECUTION_STATUS, val1); 498 switch (b) { 499 case HAL_REO_QUEUE_STATS_STATUS_TLV: 500 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 501 STATUS_HEADER_TIMESTAMP)]; 502 break; 503 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 504 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 505 STATUS_HEADER_TIMESTAMP)]; 506 break; 507 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 508 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 509 STATUS_HEADER_TIMESTAMP)]; 510 break; 511 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 512 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 513 STATUS_HEADER_TIMESTAMP)]; 514 break; 515 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 516 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 517 STATUS_HEADER_TIMESTAMP)]; 518 break; 519 case HAL_REO_DESC_THRES_STATUS_TLV: 520 val1 = 521 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 522 STATUS_HEADER_TIMESTAMP)]; 523 break; 524 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 525 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 526 STATUS_HEADER_TIMESTAMP)]; 527 break; 528 default: 529 qdf_nofl_err("ERROR: Unknown tlv\n"); 530 break; 531 } 532 h->tstamp = 533 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1); 534 } 535 536 static 537 void *hal_rx_msdu0_buffer_addr_lsb_5332(void *link_desc_va) 538 { 539 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 540 } 541 542 static 543 void *hal_rx_msdu_desc_info_ptr_get_5332(void *msdu0) 544 { 545 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 546 } 547 548 static 549 void *hal_ent_mpdu_desc_info_5332(void *ent_ring_desc) 550 { 551 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 552 } 553 554 static 555 void *hal_dst_mpdu_desc_info_5332(void *dst_ring_desc) 556 { 557 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 558 } 559 560 /** 561 * hal_reo_config_5332(): Set reo config parameters 562 * @soc: hal soc handle 563 * @reg_val: value to be set 564 * @reo_params: reo parameters 565 * 566 * Return: void 567 */ 568 static void 569 hal_reo_config_5332(struct hal_soc *soc, 570 uint32_t reg_val, 571 struct hal_reo_params *reo_params) 572 { 573 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 574 } 575 576 /** 577 * hal_rx_msdu_desc_info_get_ptr_5332() - Get msdu desc info ptr 578 * @msdu_details_ptr - Pointer to msdu_details_ptr 579 * 580 * Return - Pointer to rx_msdu_desc_info structure. 581 * 582 */ 583 static void *hal_rx_msdu_desc_info_get_ptr_5332(void *msdu_details_ptr) 584 { 585 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 586 } 587 588 /** 589 * hal_rx_link_desc_msdu0_ptr_5332 - Get pointer to rx_msdu details 590 * @link_desc - Pointer to link desc 591 * 592 * Return - Pointer to rx_msdu_details structure 593 * 594 */ 595 static void *hal_rx_link_desc_msdu0_ptr_5332(void *link_desc) 596 { 597 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 598 } 599 600 /** 601 * hal_get_window_address_5332(): Function to get hp/tp address 602 * @hal_soc: Pointer to hal_soc 603 * @addr: address offset of register 604 * 605 * Return: modified address offset of register 606 */ 607 608 static inline qdf_iomem_t hal_get_window_address_5332(struct hal_soc *hal_soc, 609 qdf_iomem_t addr) 610 { 611 uint32_t offset = addr - hal_soc->dev_base_addr; 612 qdf_iomem_t new_offset; 613 614 /* 615 * Check if offset lies within CE register range(0x740000) 616 * or UMAC/DP register range (0x00A00000). 617 * If offset lies within CE register range, map it 618 * into CE region. 619 */ 620 if (offset < 0xA00000) { 621 offset = offset - CE_CFG_WFSS_CE_REG_BASE; 622 new_offset = (hal_soc->dev_base_addr_ce + offset); 623 624 return new_offset; 625 } else { 626 /* 627 * If offset lies within DP register range, 628 * return the address as such 629 */ 630 return addr; 631 } 632 } 633 634 static 635 void hal_compute_reo_remap_ix2_ix3_5332(uint32_t *ring, uint32_t num_rings, 636 uint32_t *remap1, uint32_t *remap2) 637 { 638 switch (num_rings) { 639 case 1: 640 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 641 HAL_REO_REMAP_IX2(ring[0], 17) | 642 HAL_REO_REMAP_IX2(ring[0], 18) | 643 HAL_REO_REMAP_IX2(ring[0], 19) | 644 HAL_REO_REMAP_IX2(ring[0], 20) | 645 HAL_REO_REMAP_IX2(ring[0], 21) | 646 HAL_REO_REMAP_IX2(ring[0], 22) | 647 HAL_REO_REMAP_IX2(ring[0], 23); 648 649 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 650 HAL_REO_REMAP_IX3(ring[0], 25) | 651 HAL_REO_REMAP_IX3(ring[0], 26) | 652 HAL_REO_REMAP_IX3(ring[0], 27) | 653 HAL_REO_REMAP_IX3(ring[0], 28) | 654 HAL_REO_REMAP_IX3(ring[0], 29) | 655 HAL_REO_REMAP_IX3(ring[0], 30) | 656 HAL_REO_REMAP_IX3(ring[0], 31); 657 break; 658 case 2: 659 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 660 HAL_REO_REMAP_IX2(ring[0], 17) | 661 HAL_REO_REMAP_IX2(ring[1], 18) | 662 HAL_REO_REMAP_IX2(ring[1], 19) | 663 HAL_REO_REMAP_IX2(ring[0], 20) | 664 HAL_REO_REMAP_IX2(ring[0], 21) | 665 HAL_REO_REMAP_IX2(ring[1], 22) | 666 HAL_REO_REMAP_IX2(ring[1], 23); 667 668 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 669 HAL_REO_REMAP_IX3(ring[0], 25) | 670 HAL_REO_REMAP_IX3(ring[1], 26) | 671 HAL_REO_REMAP_IX3(ring[1], 27) | 672 HAL_REO_REMAP_IX3(ring[0], 28) | 673 HAL_REO_REMAP_IX3(ring[0], 29) | 674 HAL_REO_REMAP_IX3(ring[1], 30) | 675 HAL_REO_REMAP_IX3(ring[1], 31); 676 break; 677 case 3: 678 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 679 HAL_REO_REMAP_IX2(ring[1], 17) | 680 HAL_REO_REMAP_IX2(ring[2], 18) | 681 HAL_REO_REMAP_IX2(ring[0], 19) | 682 HAL_REO_REMAP_IX2(ring[1], 20) | 683 HAL_REO_REMAP_IX2(ring[2], 21) | 684 HAL_REO_REMAP_IX2(ring[0], 22) | 685 HAL_REO_REMAP_IX2(ring[1], 23); 686 687 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 688 HAL_REO_REMAP_IX3(ring[0], 25) | 689 HAL_REO_REMAP_IX3(ring[1], 26) | 690 HAL_REO_REMAP_IX3(ring[2], 27) | 691 HAL_REO_REMAP_IX3(ring[0], 28) | 692 HAL_REO_REMAP_IX3(ring[1], 29) | 693 HAL_REO_REMAP_IX3(ring[2], 30) | 694 HAL_REO_REMAP_IX3(ring[0], 31); 695 break; 696 case 4: 697 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 698 HAL_REO_REMAP_IX2(ring[1], 17) | 699 HAL_REO_REMAP_IX2(ring[2], 18) | 700 HAL_REO_REMAP_IX2(ring[3], 19) | 701 HAL_REO_REMAP_IX2(ring[0], 20) | 702 HAL_REO_REMAP_IX2(ring[1], 21) | 703 HAL_REO_REMAP_IX2(ring[2], 22) | 704 HAL_REO_REMAP_IX2(ring[3], 23); 705 706 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 707 HAL_REO_REMAP_IX3(ring[1], 25) | 708 HAL_REO_REMAP_IX3(ring[2], 26) | 709 HAL_REO_REMAP_IX3(ring[3], 27) | 710 HAL_REO_REMAP_IX3(ring[0], 28) | 711 HAL_REO_REMAP_IX3(ring[1], 29) | 712 HAL_REO_REMAP_IX3(ring[2], 30) | 713 HAL_REO_REMAP_IX3(ring[3], 31); 714 break; 715 } 716 } 717 718 /** 719 * hal_rx_flow_setup_fse_5332() - Setup a flow search entry in HW FST 720 * @fst: Pointer to the Rx Flow Search Table 721 * @table_offset: offset into the table where the flow is to be setup 722 * @flow: Flow Parameters 723 * 724 * Return: Success/Failure 725 */ 726 static void * 727 hal_rx_flow_setup_fse_5332(uint8_t *rx_fst, uint32_t table_offset, 728 uint8_t *rx_flow) 729 { 730 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 731 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 732 uint8_t *fse; 733 bool fse_valid; 734 735 if (table_offset >= fst->max_entries) { 736 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 737 "HAL FSE table offset %u exceeds max entries %u", 738 table_offset, fst->max_entries); 739 return NULL; 740 } 741 742 fse = (uint8_t *)fst->base_vaddr + 743 (table_offset * HAL_RX_FST_ENTRY_SIZE); 744 745 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 746 747 if (fse_valid) { 748 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 749 "HAL FSE %pK already valid", fse); 750 return NULL; 751 } 752 753 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) = 754 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 755 qdf_htonl(flow->tuple_info.src_ip_127_96)); 756 757 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) = 758 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 759 qdf_htonl(flow->tuple_info.src_ip_95_64)); 760 761 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) = 762 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 763 qdf_htonl(flow->tuple_info.src_ip_63_32)); 764 765 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) = 766 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 767 qdf_htonl(flow->tuple_info.src_ip_31_0)); 768 769 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) = 770 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 771 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 772 773 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) = 774 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 775 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 776 777 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) = 778 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 779 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 780 781 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) = 782 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 783 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 784 785 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT); 786 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |= 787 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 788 (flow->tuple_info.dest_port)); 789 790 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT); 791 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |= 792 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 793 (flow->tuple_info.src_port)); 794 795 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL); 796 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |= 797 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 798 flow->tuple_info.l4_protocol); 799 800 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER); 801 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |= 802 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 803 flow->reo_destination_handler); 804 805 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 806 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |= 807 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 808 809 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA); 810 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) = 811 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 812 flow->fse_metadata); 813 814 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION); 815 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |= 816 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 817 REO_DESTINATION_INDICATION, 818 flow->reo_destination_indication); 819 820 /* Reset all the other fields in FSE */ 821 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9); 822 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP); 823 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT); 824 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT); 825 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP); 826 827 return fse; 828 } 829 830 #ifndef NO_RX_PKT_HDR_TLV 831 /** 832 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 833 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 834 * @ dbg_level: log level. 835 * 836 * Return: void 837 */ 838 static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs, 839 uint8_t dbg_level) 840 { 841 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 842 843 hal_verbose_debug("\n---------------\n" 844 "rx_pkt_hdr_tlv\n" 845 "---------------\n" 846 "phy_ppdu_id %llu ", 847 pkt_hdr_tlv->phy_ppdu_id); 848 849 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 850 sizeof(pkt_hdr_tlv->rx_pkt_hdr)); 851 } 852 #else 853 /** 854 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 855 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 856 * @ dbg_level: log level. 857 * 858 * Return: void 859 */ 860 static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs, 861 uint8_t dbg_level) 862 { 863 } 864 #endif 865 866 /** 867 * hal_rx_dump_pkt_tlvs_5332(): API to print RX Pkt TLVS qca5332 868 * @hal_soc_hdl: hal_soc handle 869 * @buf: pointer the pkt buffer 870 * @dbg_level: log level 871 * 872 * Return: void 873 */ 874 #ifdef CONFIG_WORD_BASED_TLV 875 static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl, 876 uint8_t *buf, uint8_t dbg_level) 877 { 878 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 879 struct rx_msdu_end_compact *msdu_end = 880 &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 881 struct rx_mpdu_start_compact *mpdu_start = 882 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 883 884 hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level); 885 hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level); 886 hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level); 887 } 888 #else 889 static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl, 890 uint8_t *buf, uint8_t dbg_level) 891 { 892 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 893 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 894 struct rx_mpdu_start *mpdu_start = 895 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 896 897 hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level); 898 hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level); 899 hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level); 900 } 901 #endif 902 903 #define HAL_NUM_TCL_BANKS_5332 24 904 905 /** 906 * hal_cmem_write_5332() - function for CMEM buffer writing 907 * @hal_soc_hdl: HAL SOC handle 908 * @offset: CMEM address 909 * @value: value to write 910 * 911 * Return: None. 912 */ 913 static void hal_cmem_write_5332(hal_soc_handle_t hal_soc_hdl, 914 uint32_t offset, 915 uint32_t value) 916 { 917 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 918 919 /* cmem region is ioremapped from CMEM_REG_BASE, hence subtracting 920 * that from offset. 921 */ 922 offset = offset - CMEM_REG_BASE; 923 pld_reg_write(hal->qdf_dev->dev, offset, value, 924 hal->dev_base_addr_cmem); 925 } 926 927 /** 928 * hal_tx_get_num_tcl_banks_5332() - Get number of banks in target 929 * 930 * Returns: number of bank 931 */ 932 static uint8_t hal_tx_get_num_tcl_banks_5332(void) 933 { 934 return HAL_NUM_TCL_BANKS_5332; 935 } 936 937 static void hal_reo_setup_5332(struct hal_soc *soc, void *reoparams, 938 int qref_reset) 939 { 940 uint32_t reg_val; 941 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 942 943 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 944 REO_REG_REG_BASE)); 945 946 hal_reo_config_5332(soc, reg_val, reo_params); 947 /* Other ring enable bits and REO_ENABLE will be set by FW */ 948 949 /* TODO: Setup destination ring mapping if enabled */ 950 951 /* TODO: Error destination ring setting is left to default. 952 * Default setting is to send all errors to release ring. 953 */ 954 955 /* Set the reo descriptor swap bits in case of BIG endian platform */ 956 hal_setup_reo_swap(soc); 957 958 HAL_REG_WRITE(soc, 959 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE), 960 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 961 962 HAL_REG_WRITE(soc, 963 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE), 964 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 965 966 HAL_REG_WRITE(soc, 967 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE), 968 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 969 970 HAL_REG_WRITE(soc, 971 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE), 972 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 973 974 /* 975 * When hash based routing is enabled, routing of the rx packet 976 * is done based on the following value: 1 _ _ _ _ The last 4 977 * bits are based on hash[3:0]. This means the possible values 978 * are 0x10 to 0x1f. This value is used to look-up the 979 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 980 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 981 * registers need to be configured to set-up the 16 entries to 982 * map the hash values to a ring number. There are 3 bits per 983 * hash entry – which are mapped as follows: 984 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 985 * 7: NOT_USED. 986 */ 987 if (reo_params->rx_hash_enabled) { 988 HAL_REG_WRITE(soc, 989 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR 990 (REO_REG_REG_BASE), reo_params->remap0); 991 992 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 993 HAL_REG_READ(soc, 994 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR( 995 REO_REG_REG_BASE))); 996 997 HAL_REG_WRITE(soc, 998 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 999 (REO_REG_REG_BASE), reo_params->remap1); 1000 1001 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1002 HAL_REG_READ(soc, 1003 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1004 REO_REG_REG_BASE))); 1005 1006 HAL_REG_WRITE(soc, 1007 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 1008 (REO_REG_REG_BASE), reo_params->remap2); 1009 1010 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1011 HAL_REG_READ(soc, 1012 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1013 REO_REG_REG_BASE))); 1014 } 1015 1016 /* TODO: Check if the following registers shoould be setup by host: 1017 * AGING_CONTROL 1018 * HIGH_MEMORY_THRESHOLD 1019 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1020 * GLOBAL_LINK_DESC_COUNT_CTRL 1021 */ 1022 1023 hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset); 1024 } 1025 1026 static uint16_t hal_get_rx_max_ba_window_qca5332(int tid) 1027 { 1028 return HAL_RX_BA_WINDOW_1024; 1029 } 1030 1031 /** 1032 * hal_qca5332_get_reo_qdesc_size()- Get the reo queue descriptor size 1033 * from the give Block-Ack window size 1034 * Return: reo queue descriptor size 1035 */ 1036 static uint32_t hal_qca5332_get_reo_qdesc_size(uint32_t ba_window_size, int tid) 1037 { 1038 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 1039 * NON_QOS_TID until HW issues are resolved. 1040 */ 1041 if (tid != HAL_NON_QOS_TID) 1042 ba_window_size = hal_get_rx_max_ba_window_qca5332(tid); 1043 1044 /* Return descriptor size corresponding to window size of 2 since 1045 * we set ba_window_size to 2 while setting up REO descriptors as 1046 * a WAR to get 2k jump exception aggregates are received without 1047 * a BA session. 1048 */ 1049 if (ba_window_size <= 1) { 1050 if (tid != HAL_NON_QOS_TID) 1051 return sizeof(struct rx_reo_queue) + 1052 sizeof(struct rx_reo_queue_ext); 1053 else 1054 return sizeof(struct rx_reo_queue); 1055 } 1056 1057 if (ba_window_size <= 105) 1058 return sizeof(struct rx_reo_queue) + 1059 sizeof(struct rx_reo_queue_ext); 1060 1061 if (ba_window_size <= 210) 1062 return sizeof(struct rx_reo_queue) + 1063 (2 * sizeof(struct rx_reo_queue_ext)); 1064 1065 if (ba_window_size <= 256) 1066 return sizeof(struct rx_reo_queue) + 1067 (3 * sizeof(struct rx_reo_queue_ext)); 1068 1069 return sizeof(struct rx_reo_queue) + 1070 (10 * sizeof(struct rx_reo_queue_ext)) + 1071 sizeof(struct rx_reo_queue_1k); 1072 } 1073 /** 1074 * hal_rx_tlv_msdu_done_copy_get_5332() - Get msdu done copy bit from rx_tlv 1075 * 1076 * Returns: msdu done copy bit 1077 */ 1078 static inline uint32_t hal_rx_tlv_msdu_done_copy_get_5332(uint8_t *buf) 1079 { 1080 return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf); 1081 } 1082 1083 static void hal_hw_txrx_ops_attach_qca5332(struct hal_soc *hal_soc) 1084 { 1085 /* init and setup */ 1086 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1087 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1088 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1089 hal_soc->ops->hal_get_window_address = hal_get_window_address_5332; 1090 hal_soc->ops->hal_cmem_write = hal_cmem_write_5332; 1091 1092 /* tx */ 1093 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5332; 1094 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5332; 1095 hal_soc->ops->hal_tx_comp_get_status = 1096 hal_tx_comp_get_status_generic_be; 1097 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1098 hal_tx_init_cmd_credit_ring_5332; 1099 hal_soc->ops->hal_tx_set_ppe_cmn_cfg = NULL; 1100 hal_soc->ops->hal_tx_set_ppe_vp_entry = NULL; 1101 hal_soc->ops->hal_tx_set_ppe_pri2tid = NULL; 1102 hal_soc->ops->hal_tx_update_ppe_pri2tid = NULL; 1103 hal_soc->ops->hal_tx_dump_ppe_vp_entry = NULL; 1104 hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = NULL; 1105 hal_soc->ops->hal_tx_enable_pri2tid_map = NULL; 1106 hal_soc->ops->hal_tx_config_rbm_mapping_be = 1107 hal_tx_config_rbm_mapping_be_5332; 1108 1109 /* rx */ 1110 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; 1111 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1112 hal_rx_mon_hw_desc_get_mpdu_status_be; 1113 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5332; 1114 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1115 hal_rx_proc_phyrx_other_receive_info_tlv_5332; 1116 1117 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5332; 1118 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1119 hal_rx_dump_mpdu_start_tlv_5332; 1120 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_5332; 1121 1122 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5332; 1123 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be; 1124 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1125 hal_rx_tlv_reception_type_get_be; 1126 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1127 hal_rx_msdu_end_da_idx_get_be; 1128 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1129 hal_rx_msdu_desc_info_get_ptr_5332; 1130 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1131 hal_rx_link_desc_msdu0_ptr_5332; 1132 hal_soc->ops->hal_reo_status_get_header = 1133 hal_reo_status_get_header_5332; 1134 hal_soc->ops->hal_rx_status_get_tlv_info = 1135 hal_rx_status_get_tlv_info_wrapper_be; 1136 hal_soc->ops->hal_rx_wbm_err_info_get = 1137 hal_rx_wbm_err_info_get_generic_be; 1138 hal_soc->ops->hal_tx_set_pcp_tid_map = 1139 hal_tx_set_pcp_tid_map_generic_be; 1140 hal_soc->ops->hal_tx_update_pcp_tid_map = 1141 hal_tx_update_pcp_tid_generic_be; 1142 hal_soc->ops->hal_tx_set_tidmap_prty = 1143 hal_tx_update_tidmap_prty_generic_be; 1144 hal_soc->ops->hal_rx_get_rx_fragment_number = 1145 hal_rx_get_rx_fragment_number_be, 1146 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1147 hal_rx_tlv_da_is_mcbc_get_be; 1148 hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err = 1149 hal_rx_tlv_is_tkip_mic_err_get_be; 1150 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1151 hal_rx_tlv_sa_is_valid_get_be; 1152 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be; 1153 hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be; 1154 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1155 hal_rx_tlv_l3_hdr_padding_get_be; 1156 hal_soc->ops->hal_rx_encryption_info_valid = 1157 hal_rx_encryption_info_valid_be; 1158 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; 1159 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1160 hal_rx_tlv_first_msdu_get_be; 1161 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1162 hal_rx_tlv_da_is_valid_get_be; 1163 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1164 hal_rx_tlv_last_msdu_get_be; 1165 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1166 hal_rx_get_mpdu_mac_ad4_valid_be; 1167 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1168 hal_rx_mpdu_start_sw_peer_id_get_be; 1169 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1170 hal_rx_msdu_peer_meta_data_get_be; 1171 #ifndef CONFIG_WORD_BASED_TLV 1172 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; 1173 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1174 hal_rx_mpdu_info_ampdu_flag_get_be; 1175 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1176 hal_rx_hw_desc_get_ppduid_get_be; 1177 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be; 1178 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 1179 hal_rx_attn_phy_ppdu_id_get_be; 1180 hal_soc->ops->hal_rx_get_filter_category = 1181 hal_rx_get_filter_category_be; 1182 #endif 1183 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be; 1184 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be; 1185 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1186 hal_rx_get_mpdu_frame_control_valid_be; 1187 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; 1188 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; 1189 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; 1190 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1191 hal_rx_get_mpdu_sequence_control_valid_be; 1192 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; 1193 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; 1194 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1195 hal_rx_mpdu_start_mpdu_qos_control_valid_get_be; 1196 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1197 hal_rx_msdu_end_sa_sw_peer_id_get_be; 1198 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1199 hal_rx_msdu0_buffer_addr_lsb_5332; 1200 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1201 hal_rx_msdu_desc_info_ptr_get_5332; 1202 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5332; 1203 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5332; 1204 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; 1205 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; 1206 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1207 hal_rx_get_mac_addr2_valid_be; 1208 hal_soc->ops->hal_reo_config = hal_reo_config_5332; 1209 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; 1210 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1211 hal_rx_msdu_flow_idx_invalid_be; 1212 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1213 hal_rx_msdu_flow_idx_timeout_be; 1214 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1215 hal_rx_msdu_fse_metadata_get_be; 1216 hal_soc->ops->hal_rx_msdu_cce_match_get = 1217 hal_rx_msdu_cce_match_get_be; 1218 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1219 hal_rx_msdu_cce_metadata_get_be; 1220 hal_soc->ops->hal_rx_msdu_get_flow_params = 1221 hal_rx_msdu_get_flow_params_be; 1222 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be; 1223 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be; 1224 #if defined(QCA_WIFI_QCA5332) && defined(WLAN_CFR_ENABLE) && \ 1225 defined(WLAN_ENH_CFR_ENABLE) 1226 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5332; 1227 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5332; 1228 #else 1229 hal_soc->ops->hal_rx_get_bb_info = NULL; 1230 hal_soc->ops->hal_rx_get_rtt_info = NULL; 1231 #endif 1232 /* rx - msdu fast path info fields */ 1233 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1234 hal_rx_msdu_packet_metadata_get_generic_be; 1235 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1236 hal_rx_mpdu_start_tlv_tag_valid_be; 1237 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1238 hal_rx_wbm_err_msdu_continuation_get_5332; 1239 1240 /* rx - TLV struct offsets */ 1241 hal_soc->ops->hal_rx_msdu_end_offset_get = 1242 hal_rx_msdu_end_offset_get_generic; 1243 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1244 hal_rx_mpdu_start_offset_get_generic; 1245 #ifndef NO_RX_PKT_HDR_TLV 1246 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1247 hal_rx_pkt_tlv_offset_get_generic; 1248 #endif 1249 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5332; 1250 1251 hal_soc->ops->hal_rx_flow_get_tuple_info = 1252 hal_rx_flow_get_tuple_info_be; 1253 hal_soc->ops->hal_rx_flow_delete_entry = 1254 hal_rx_flow_delete_entry_be; 1255 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be; 1256 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1257 hal_compute_reo_remap_ix2_ix3_5332; 1258 1259 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 1260 hal_rx_msdu_get_reo_destination_indication_be; 1261 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; 1262 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 1263 hal_rx_msdu_is_wlan_mcast_generic_be; 1264 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_5332; 1265 hal_soc->ops->hal_rx_tlv_decap_format_get = 1266 hal_rx_tlv_decap_format_get_be; 1267 #ifdef RECEIVE_OFFLOAD 1268 hal_soc->ops->hal_rx_tlv_get_offload_info = 1269 hal_rx_tlv_get_offload_info_be; 1270 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; 1271 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; 1272 #endif 1273 hal_soc->ops->hal_rx_tlv_msdu_done_get = 1274 hal_rx_tlv_msdu_done_copy_get_5332; 1275 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1276 hal_rx_msdu_start_msdu_len_get_be; 1277 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1278 hal_rx_get_frame_ctrl_field_be; 1279 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; 1280 hal_soc->ops->hal_rx_tlv_msdu_len_set = 1281 hal_rx_msdu_start_msdu_len_set_be; 1282 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; 1283 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; 1284 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be; 1285 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be; 1286 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be; 1287 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1288 hal_rx_tlv_decrypt_err_get_be; 1289 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be; 1290 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 1291 hal_rx_tlv_get_is_decrypted_be; 1292 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be; 1293 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 1294 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1295 hal_rx_priv_info_set_in_tlv_be; 1296 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1297 hal_rx_priv_info_get_from_tlv_be; 1298 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be; 1299 hal_soc->ops->hal_reo_setup = hal_reo_setup_5332; 1300 #ifdef REO_SHARED_QREF_TABLE_EN 1301 hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be; 1302 hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be; 1303 hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be; 1304 hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be; 1305 hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be; 1306 #endif 1307 /* Overwrite the default BE ops */ 1308 hal_soc->ops->hal_get_rx_max_ba_window = 1309 hal_get_rx_max_ba_window_qca5332; 1310 hal_soc->ops->hal_get_reo_qdesc_size = hal_qca5332_get_reo_qdesc_size; 1311 /* TX MONITOR */ 1312 #ifdef QCA_MONITOR_2_0_SUPPORT 1313 hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv = 1314 hal_txmon_is_mon_buf_addr_tlv_generic_be; 1315 hal_soc->ops->hal_txmon_populate_packet_info = 1316 hal_txmon_populate_packet_info_generic_be; 1317 hal_soc->ops->hal_txmon_status_parse_tlv = 1318 hal_txmon_status_parse_tlv_generic_be; 1319 hal_soc->ops->hal_txmon_status_get_num_users = 1320 hal_txmon_status_get_num_users_generic_be; 1321 #endif /* QCA_MONITOR_2_0_SUPPORT */ 1322 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1323 hal_soc->ops->hal_tx_vdev_mismatch_routing_set = 1324 hal_tx_vdev_mismatch_routing_set_generic_be; 1325 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = 1326 hal_tx_mcast_mlo_reinject_routing_set_generic_be; 1327 hal_soc->ops->hal_get_ba_aging_timeout = 1328 hal_get_ba_aging_timeout_be_generic; 1329 hal_soc->ops->hal_setup_link_idle_list = 1330 hal_setup_link_idle_list_generic_be; 1331 hal_soc->ops->hal_cookie_conversion_reg_cfg_be = 1332 hal_cookie_conversion_reg_cfg_generic_be; 1333 hal_soc->ops->hal_set_ba_aging_timeout = 1334 hal_set_ba_aging_timeout_be_generic; 1335 hal_soc->ops->hal_tx_populate_bank_register = 1336 hal_tx_populate_bank_register_be; 1337 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = 1338 hal_tx_vdev_mcast_ctrl_set_be; 1339 }; 1340 1341 struct hal_hw_srng_config hw_srng_table_5332[] = { 1342 /* TODO: max_rings can populated by querying HW capabilities */ 1343 { /* REO_DST */ 1344 .start_ring_id = HAL_SRNG_REO2SW1, 1345 .max_rings = 8, 1346 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1347 .lmac_ring = FALSE, 1348 .ring_dir = HAL_SRNG_DST_RING, 1349 .reg_start = { 1350 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1351 REO_REG_REG_BASE), 1352 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1353 REO_REG_REG_BASE) 1354 }, 1355 .reg_size = { 1356 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1357 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1358 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1359 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1360 }, 1361 .max_size = 1362 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1363 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1364 }, 1365 { /* REO_EXCEPTION */ 1366 /* Designating REO2SW0 ring as exception ring. This ring is 1367 * similar to other REO2SW rings though it is named as REO2SW0. 1368 * Any of theREO2SW rings can be used as exception ring. 1369 */ 1370 .start_ring_id = HAL_SRNG_REO2SW0, 1371 .max_rings = 1, 1372 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1373 .lmac_ring = FALSE, 1374 .ring_dir = HAL_SRNG_DST_RING, 1375 .reg_start = { 1376 HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR( 1377 REO_REG_REG_BASE), 1378 HWIO_REO_R2_REO2SW0_RING_HP_ADDR( 1379 REO_REG_REG_BASE) 1380 }, 1381 /* Single ring - provide ring size if multiple rings of this 1382 * type are supported 1383 */ 1384 .reg_size = {}, 1385 .max_size = 1386 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >> 1387 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT, 1388 }, 1389 { /* REO_REINJECT */ 1390 .start_ring_id = HAL_SRNG_SW2REO, 1391 .max_rings = 4, 1392 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1393 .lmac_ring = FALSE, 1394 .ring_dir = HAL_SRNG_SRC_RING, 1395 .reg_start = { 1396 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1397 REO_REG_REG_BASE), 1398 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1399 REO_REG_REG_BASE) 1400 }, 1401 /* Single ring - provide ring size if multiple rings of this 1402 * type are supported 1403 */ 1404 .reg_size = { 1405 HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) - 1406 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0), 1407 HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) - 1408 HWIO_REO_R2_SW2REO_RING_HP_ADDR(0) 1409 }, 1410 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1411 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1412 }, 1413 { /* REO_CMD */ 1414 .start_ring_id = HAL_SRNG_REO_CMD, 1415 .max_rings = 1, 1416 .entry_size = (sizeof(struct tlv_32_hdr) + 1417 sizeof(struct reo_get_queue_stats)) >> 2, 1418 .lmac_ring = FALSE, 1419 .ring_dir = HAL_SRNG_SRC_RING, 1420 .reg_start = { 1421 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1422 REO_REG_REG_BASE), 1423 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1424 REO_REG_REG_BASE), 1425 }, 1426 /* Single ring - provide ring size if multiple rings of this 1427 * type are supported 1428 */ 1429 .reg_size = {}, 1430 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1431 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1432 }, 1433 { /* REO_STATUS */ 1434 .start_ring_id = HAL_SRNG_REO_STATUS, 1435 .max_rings = 1, 1436 .entry_size = (sizeof(struct tlv_32_hdr) + 1437 sizeof(struct reo_get_queue_stats_status)) >> 2, 1438 .lmac_ring = FALSE, 1439 .ring_dir = HAL_SRNG_DST_RING, 1440 .reg_start = { 1441 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1442 REO_REG_REG_BASE), 1443 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1444 REO_REG_REG_BASE), 1445 }, 1446 /* Single ring - provide ring size if multiple rings of this 1447 * type are supported 1448 */ 1449 .reg_size = {}, 1450 .max_size = 1451 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1452 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1453 }, 1454 { /* TCL_DATA */ 1455 .start_ring_id = HAL_SRNG_SW2TCL1, 1456 .max_rings = 6, 1457 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 1458 .lmac_ring = FALSE, 1459 .ring_dir = HAL_SRNG_SRC_RING, 1460 .reg_start = { 1461 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1462 MAC_TCL_REG_REG_BASE), 1463 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1464 MAC_TCL_REG_REG_BASE), 1465 }, 1466 .reg_size = { 1467 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1468 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1469 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1470 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1471 }, 1472 .max_size = 1473 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1474 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1475 }, 1476 { /* TCL_CMD/CREDIT */ 1477 /* qca8074v2 and qca5332 uses this ring for data commands */ 1478 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1479 .max_rings = 1, 1480 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 1481 .lmac_ring = FALSE, 1482 .ring_dir = HAL_SRNG_SRC_RING, 1483 .reg_start = { 1484 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 1485 MAC_TCL_REG_REG_BASE), 1486 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 1487 MAC_TCL_REG_REG_BASE), 1488 }, 1489 /* Single ring - provide ring size if multiple rings of this 1490 * type are supported 1491 */ 1492 .reg_size = {}, 1493 .max_size = 1494 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 1495 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 1496 }, 1497 { /* TCL_STATUS */ 1498 .start_ring_id = HAL_SRNG_TCL_STATUS, 1499 .max_rings = 1, 1500 .entry_size = (sizeof(struct tlv_32_hdr) + 1501 sizeof(struct tcl_status_ring)) >> 2, 1502 .lmac_ring = FALSE, 1503 .ring_dir = HAL_SRNG_DST_RING, 1504 .reg_start = { 1505 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1506 MAC_TCL_REG_REG_BASE), 1507 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1508 MAC_TCL_REG_REG_BASE), 1509 }, 1510 /* Single ring - provide ring size if multiple rings of this 1511 * type are supported 1512 */ 1513 .reg_size = {}, 1514 .max_size = 1515 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1516 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1517 }, 1518 { /* CE_SRC */ 1519 .start_ring_id = HAL_SRNG_CE_0_SRC, 1520 .max_rings = 16, 1521 .entry_size = sizeof(struct ce_src_desc) >> 2, 1522 .lmac_ring = FALSE, 1523 .ring_dir = HAL_SRNG_SRC_RING, 1524 .reg_start = { 1525 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR( 1526 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE), 1527 HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR( 1528 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE), 1529 }, 1530 .reg_size = { 1531 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 1532 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 1533 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 1534 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 1535 }, 1536 .max_size = 1537 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >> 1538 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT, 1539 }, 1540 { /* CE_DST */ 1541 .start_ring_id = HAL_SRNG_CE_0_DST, 1542 .max_rings = 16, 1543 .entry_size = 8 >> 2, 1544 /*TODO: entry_size above should actually be 1545 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1546 * of struct ce_dst_desc in HW header files 1547 */ 1548 .lmac_ring = FALSE, 1549 .ring_dir = HAL_SRNG_SRC_RING, 1550 .reg_start = { 1551 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1552 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 1553 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1554 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 1555 }, 1556 .reg_size = { 1557 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 1558 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 1559 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 1560 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 1561 }, 1562 .max_size = 1563 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1564 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1565 }, 1566 { /* CE_DST_STATUS */ 1567 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1568 .max_rings = 16, 1569 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1570 .lmac_ring = FALSE, 1571 .ring_dir = HAL_SRNG_DST_RING, 1572 .reg_start = { 1573 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1574 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 1575 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1576 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 1577 }, 1578 /* TODO: check destination status ring registers */ 1579 .reg_size = { 1580 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 1581 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 1582 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 1583 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 1584 }, 1585 .max_size = 1586 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1587 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1588 }, 1589 { /* WBM_IDLE_LINK */ 1590 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1591 .max_rings = 1, 1592 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1593 .lmac_ring = FALSE, 1594 .ring_dir = HAL_SRNG_SRC_RING, 1595 .reg_start = { 1596 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 1597 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE), 1598 }, 1599 /* Single ring - provide ring size if multiple rings of this 1600 * type are supported 1601 */ 1602 .reg_size = {}, 1603 .max_size = 1604 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1605 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1606 }, 1607 { /* SW2WBM_RELEASE */ 1608 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1609 .max_rings = 1, 1610 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1611 .lmac_ring = FALSE, 1612 .ring_dir = HAL_SRNG_SRC_RING, 1613 .reg_start = { 1614 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 1615 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 1616 }, 1617 /* Single ring - provide ring size if multiple rings of this 1618 * type are supported 1619 */ 1620 .reg_size = {}, 1621 .max_size = 1622 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1623 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1624 }, 1625 { /* WBM2SW_RELEASE */ 1626 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1627 .max_rings = 8, 1628 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1629 .lmac_ring = FALSE, 1630 .ring_dir = HAL_SRNG_DST_RING, 1631 .reg_start = { 1632 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR( 1633 WBM_REG_REG_BASE), 1634 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR( 1635 WBM_REG_REG_BASE), 1636 }, 1637 .reg_size = { 1638 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR( 1639 WBM_REG_REG_BASE) - 1640 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR( 1641 WBM_REG_REG_BASE), 1642 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR( 1643 WBM_REG_REG_BASE) - 1644 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR( 1645 WBM_REG_REG_BASE), 1646 }, 1647 .max_size = 1648 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1649 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1650 }, 1651 { /* RXDMA_BUF */ 1652 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1653 #ifdef IPA_OFFLOAD 1654 .max_rings = 3, 1655 #else 1656 .max_rings = 3, 1657 #endif 1658 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1659 .lmac_ring = TRUE, 1660 .ring_dir = HAL_SRNG_SRC_RING, 1661 /* reg_start is not set because LMAC rings are not accessed 1662 * from host 1663 */ 1664 .reg_start = {}, 1665 .reg_size = {}, 1666 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1667 }, 1668 { /* RXDMA_DST */ 1669 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1670 .max_rings = 0, 1671 .entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/, 1672 .lmac_ring = TRUE, 1673 .ring_dir = HAL_SRNG_DST_RING, 1674 /* reg_start is not set because LMAC rings are not accessed 1675 * from host 1676 */ 1677 .reg_start = {}, 1678 .reg_size = {}, 1679 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1680 }, 1681 #ifdef QCA_MONITOR_2_0_SUPPORT 1682 { /* RXDMA_MONITOR_BUF */ 1683 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1684 .max_rings = 1, 1685 .entry_size = sizeof(struct mon_ingress_ring) >> 2, 1686 .lmac_ring = TRUE, 1687 .ring_dir = HAL_SRNG_SRC_RING, 1688 /* reg_start is not set because LMAC rings are not accessed 1689 * from host 1690 */ 1691 .reg_start = {}, 1692 .reg_size = {}, 1693 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 1694 }, 1695 #else 1696 {}, 1697 #endif 1698 { /* RXDMA_MONITOR_STATUS */ 1699 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1700 .max_rings = 0, 1701 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1702 .lmac_ring = TRUE, 1703 .ring_dir = HAL_SRNG_SRC_RING, 1704 /* reg_start is not set because LMAC rings are not accessed 1705 * from host 1706 */ 1707 .reg_start = {}, 1708 .reg_size = {}, 1709 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1710 }, 1711 #ifdef QCA_MONITOR_2_0_SUPPORT 1712 { /* RXDMA_MONITOR_DST */ 1713 .start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0, 1714 .max_rings = 2, 1715 .entry_size = sizeof(struct mon_destination_ring) >> 2, 1716 .lmac_ring = TRUE, 1717 .ring_dir = HAL_SRNG_DST_RING, 1718 /* reg_start is not set because LMAC rings are not accessed 1719 * from host 1720 */ 1721 .reg_start = {}, 1722 .reg_size = {}, 1723 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 1724 }, 1725 #else 1726 {}, 1727 #endif 1728 { /* RXDMA_MONITOR_DESC */ 1729 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1730 .max_rings = 0, 1731 .entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/, 1732 .lmac_ring = TRUE, 1733 .ring_dir = HAL_SRNG_DST_RING, 1734 /* reg_start is not set because LMAC rings are not accessed 1735 * from host 1736 */ 1737 .reg_start = {}, 1738 .reg_size = {}, 1739 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 1740 }, 1741 1742 { /* DIR_BUF_RX_DMA_SRC */ 1743 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1744 /* one ring for spectral and one ring for cfr */ 1745 .max_rings = 2, 1746 .entry_size = 2, 1747 .lmac_ring = TRUE, 1748 .ring_dir = HAL_SRNG_SRC_RING, 1749 /* reg_start is not set because LMAC rings are not accessed 1750 * from host 1751 */ 1752 .reg_start = {}, 1753 .reg_size = {}, 1754 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1755 }, 1756 #ifdef WLAN_FEATURE_CIF_CFR 1757 { /* WIFI_POS_SRC */ 1758 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1759 .max_rings = 1, 1760 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1761 .lmac_ring = TRUE, 1762 .ring_dir = HAL_SRNG_SRC_RING, 1763 /* reg_start is not set because LMAC rings are not accessed 1764 * from host 1765 */ 1766 .reg_start = {}, 1767 .reg_size = {}, 1768 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 1769 }, 1770 #endif 1771 /* PPE rings are not present in Miami. Added dummy entries to preserve 1772 * Array Index 1773 */ 1774 /* REO2PPE */ 1775 {}, 1776 /* PPE2TCL */ 1777 {}, 1778 /* PPE_RELEASE */ 1779 {}, 1780 #ifdef QCA_MONITOR_2_0_SUPPORT 1781 { /* TX_MONITOR_BUF */ 1782 .start_ring_id = HAL_SRNG_SW2TXMON_BUF0, 1783 .max_rings = 1, 1784 .entry_size = sizeof(struct mon_ingress_ring) >> 2, 1785 .lmac_ring = TRUE, 1786 .ring_dir = HAL_SRNG_SRC_RING, 1787 /* reg_start is not set because LMAC rings are not accessed 1788 * from host 1789 */ 1790 .reg_start = {}, 1791 .reg_size = {}, 1792 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 1793 }, 1794 { /* TX_MONITOR_DST */ 1795 .start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0, 1796 .max_rings = 2, 1797 .entry_size = sizeof(struct mon_destination_ring) >> 2, 1798 .lmac_ring = TRUE, 1799 .ring_dir = HAL_SRNG_DST_RING, 1800 /* reg_start is not set because LMAC rings are not accessed 1801 * from host 1802 */ 1803 .reg_start = {}, 1804 .reg_size = {}, 1805 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 1806 }, 1807 #else 1808 {}, 1809 {}, 1810 #endif 1811 { /* SW2RXDMA */ 1812 .start_ring_id = HAL_SRNG_SW2RXDMA_BUF0, 1813 .max_rings = 3, 1814 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1815 .lmac_ring = TRUE, 1816 .ring_dir = HAL_SRNG_SRC_RING, 1817 /* reg_start is not set because LMAC rings are not accessed 1818 * from host 1819 */ 1820 .reg_start = {}, 1821 .reg_size = {}, 1822 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 1823 .dmac_cmn_ring = TRUE, 1824 }, 1825 }; 1826 1827 /** 1828 * hal_srng_hw_reg_offset_init_qca5332() - Initialize the HW srng reg offset 1829 * applicable only for qca5332 1830 * @hal_soc: HAL Soc handle 1831 * 1832 * Return: None 1833 */ 1834 static inline void hal_srng_hw_reg_offset_init_qca5332(struct hal_soc *hal_soc) 1835 { 1836 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 1837 1838 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB), 1839 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB), 1840 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA), 1841 hw_reg_offset[DST_PRODUCER_INT2_SETUP] = 1842 REG_OFFSET(DST, PRODUCER_INT2_SETUP); 1843 } 1844 1845 /** 1846 * hal_qca5332_attach()- Attach 5332 target specific hal_soc ops, 1847 * offset and srng table 1848 * Return: void 1849 */ 1850 void hal_qca5332_attach(struct hal_soc *hal_soc) 1851 { 1852 hal_soc->hw_srng_table = hw_srng_table_5332; 1853 1854 hal_srng_hw_reg_offset_init_generic(hal_soc); 1855 hal_srng_hw_reg_offset_init_qca5332(hal_soc); 1856 1857 hal_hw_txrx_default_ops_attach_be(hal_soc); 1858 hal_hw_txrx_ops_attach_qca5332(hal_soc); 1859 hal_soc->dmac_cmn_src_rxbuf_ring = true; 1860 } 1861