1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE 16 */ 17 #include "qdf_types.h" 18 #include "qdf_util.h" 19 #include "qdf_mem.h" 20 #include "qdf_nbuf.h" 21 #include "qdf_module.h" 22 23 #include "target_type.h" 24 #include "wcss_version.h" 25 26 #include "hal_be_hw_headers.h" 27 #include "hal_internal.h" 28 #include "hal_api.h" 29 #include "hal_flow.h" 30 #include "rx_flow_search_entry.h" 31 #include "hal_rx_flow_info.h" 32 #include "hal_be_api.h" 33 #include "tcl_entrance_from_ppe_ring.h" 34 #include "sw_monitor_ring.h" 35 #include "wcss_seq_hwioreg_umac.h" 36 #include "wfss_ce_reg_seq_hwioreg.h" 37 #include <uniform_reo_status_header.h> 38 #include <wbm_release_ring_tx.h> 39 #include <phyrx_location.h> 40 #ifdef QCA_MONITOR_2_0_SUPPORT 41 #include <mon_ingress_ring.h> 42 #include <mon_destination_ring.h> 43 #endif 44 #include "rx_reo_queue_1k.h" 45 46 #include <hal_be_rx.h> 47 48 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 49 RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 50 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 51 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 52 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 53 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 54 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 55 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 56 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 57 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 58 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 59 STATUS_HEADER_REO_STATUS_NUMBER 60 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 61 STATUS_HEADER_TIMESTAMP 62 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 64 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 65 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 66 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 67 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 68 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 69 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 70 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 71 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 72 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 73 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 74 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 75 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 76 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 77 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 78 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 79 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 80 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 81 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 82 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 83 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 84 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 85 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 86 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 87 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 88 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 89 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 90 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 91 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 92 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 93 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 94 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 95 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 96 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 97 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 98 99 #ifdef QCA_MONITOR_2_0_SUPPORT 100 #include "hal_be_api_mon.h" 101 #endif 102 103 #define CMEM_REG_BASE 0x00100000 104 105 /* For Berryllium sw2rxdma ring size increased to 20 bits */ 106 #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF 107 108 #include "hal_5332_rx.h" 109 #include "hal_5332_tx.h" 110 #include "hal_be_rx_tlv.h" 111 #include <hal_be_generic_api.h> 112 113 114 /** 115 * hal_read_pmm_scratch_reg_5332(): API to read PMM Scratch register 116 * 117 * @soc: HAL soc 118 * @reg_enum: Enum of the scratch register 119 * 120 * Return: uint32_t 121 */ 122 static inline 123 uint32_t hal_read_pmm_scratch_reg_5332(struct hal_soc *soc, 124 enum hal_scratch_reg_enum reg_enum) 125 { 126 uint32_t val = 0; 127 128 pld_reg_read(soc->qdf_dev->dev, (reg_enum * 4), &val, 129 soc->dev_base_addr_pmm); 130 return val; 131 } 132 133 /** 134 * hal_get_tsf2_scratch_reg_qca5332(): API to read tsf2 scratch register 135 * 136 * @hal_soc_hdl: HAL soc context 137 * @mac_id: mac id 138 * @value: Pointer to update tsf2 value 139 * 140 * Return: void 141 */ 142 static void hal_get_tsf2_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl, 143 uint8_t mac_id, uint64_t *value) 144 { 145 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 146 uint32_t offset_lo, offset_hi; 147 enum hal_scratch_reg_enum enum_lo, enum_hi; 148 149 hal_get_tsf_enum(DEFAULT_TSF_ID, mac_id, &enum_lo, &enum_hi); 150 151 offset_lo = hal_read_pmm_scratch_reg_5332(soc, 152 enum_lo); 153 154 offset_hi = hal_read_pmm_scratch_reg_5332(soc, 155 enum_hi); 156 157 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 158 } 159 160 /** 161 * hal_get_tqm_scratch_reg_qca5332(): API to read tqm scratch register 162 * 163 * @hal_soc_hdl: HAL soc context 164 * @value: Pointer to update tqm value 165 * 166 * Return: void 167 */ 168 static void hal_get_tqm_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl, 169 uint64_t *value) 170 { 171 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 172 uint32_t offset_lo, offset_hi; 173 174 offset_lo = hal_read_pmm_scratch_reg_5332(soc, 175 PMM_TQM_CLOCK_OFFSET_LO_US); 176 177 offset_hi = hal_read_pmm_scratch_reg_5332(soc, 178 PMM_TQM_CLOCK_OFFSET_HI_US); 179 180 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 181 } 182 183 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 184 #define HAL_PPE_VP_ENTRIES_MAX 32 185 /** 186 * hal_get_link_desc_size_5332(): API to get the link desc size 187 * 188 * Return: uint32_t 189 */ 190 static uint32_t hal_get_link_desc_size_5332(void) 191 { 192 return LINK_DESC_SIZE; 193 } 194 195 /** 196 * hal_rx_get_tlv_5332(): API to get the tlv 197 * 198 * @rx_tlv: TLV data extracted from the rx packet 199 * Return: uint8_t 200 */ 201 static uint8_t hal_rx_get_tlv_5332(void *rx_tlv) 202 { 203 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH); 204 } 205 206 /** 207 * hal_rx_wbm_err_msdu_continuation_get_5332 () - API to check if WBM 208 * msdu continuation bit is set 209 * 210 *@wbm_desc: wbm release ring descriptor 211 * 212 * Return: true if msdu continuation bit is set. 213 */ 214 uint8_t hal_rx_wbm_err_msdu_continuation_get_5332(void *wbm_desc) 215 { 216 uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) + 217 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET); 218 219 return (comp_desc & 220 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >> 221 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB; 222 } 223 224 /** 225 * hal_rx_proc_phyrx_other_receive_info_tlv_5332(): API to get tlv info 226 * 227 * Return: uint32_t 228 */ 229 static inline 230 void hal_rx_proc_phyrx_other_receive_info_tlv_5332(void *rx_tlv_hdr, 231 void *ppdu_info_hdl) 232 { 233 uint32_t tlv_tag, tlv_len; 234 uint32_t temp_len, other_tlv_len, other_tlv_tag; 235 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 236 void *other_tlv_hdr = NULL; 237 void *other_tlv = NULL; 238 239 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 240 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 241 temp_len = 0; 242 243 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 244 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 245 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 246 247 temp_len += other_tlv_len; 248 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 249 250 switch (other_tlv_tag) { 251 default: 252 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 253 "%s unhandled TLV type: %d, TLV len:%d", 254 __func__, other_tlv_tag, other_tlv_len); 255 break; 256 } 257 } 258 259 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 260 static inline 261 void hal_rx_get_bb_info_5332(void *rx_tlv, void *ppdu_info_hdl) 262 { 263 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 264 265 ppdu_info->cfr_info.bb_captured_channel = 266 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL); 267 268 ppdu_info->cfr_info.bb_captured_timeout = 269 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT); 270 271 ppdu_info->cfr_info.bb_captured_reason = 272 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON); 273 } 274 275 static inline 276 void hal_rx_get_rtt_info_5332(void *rx_tlv, void *ppdu_info_hdl) 277 { 278 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 279 280 ppdu_info->cfr_info.rx_location_info_valid = 281 HAL_RX_GET(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 282 RX_LOCATION_INFO_VALID); 283 284 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 285 HAL_RX_GET(rx_tlv, 286 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 287 RTT_CHE_BUFFER_POINTER_LOW32); 288 289 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 290 HAL_RX_GET(rx_tlv, 291 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 292 RTT_CHE_BUFFER_POINTER_HIGH8); 293 294 ppdu_info->cfr_info.chan_capture_status = 295 HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv); 296 297 ppdu_info->cfr_info.rx_start_ts = 298 HAL_RX_GET(rx_tlv, 299 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 300 RX_START_TS); 301 302 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) 303 HAL_RX_GET(rx_tlv, 304 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 305 RTT_CFO_MEASUREMENT); 306 307 ppdu_info->cfr_info.agc_gain_info0 = 308 HAL_RX_GET(rx_tlv, 309 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 310 GAIN_CHAIN0); 311 312 ppdu_info->cfr_info.agc_gain_info0 |= 313 (((uint32_t)HAL_RX_GET(rx_tlv, 314 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 315 GAIN_CHAIN1)) << 16); 316 317 ppdu_info->cfr_info.agc_gain_info1 = 318 HAL_RX_GET(rx_tlv, 319 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 320 GAIN_CHAIN2); 321 322 ppdu_info->cfr_info.agc_gain_info1 |= 323 (((uint32_t)HAL_RX_GET(rx_tlv, 324 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 325 GAIN_CHAIN3)) << 16); 326 327 ppdu_info->cfr_info.agc_gain_info2 = 0; 328 329 ppdu_info->cfr_info.agc_gain_info3 = 0; 330 } 331 #endif 332 #ifdef CONFIG_WORD_BASED_TLV 333 /** 334 * hal_rx_dump_mpdu_start_tlv_5332: dump RX mpdu_start TLV in structured 335 * human readable format. 336 * @mpdu_start: pointer the rx_attention TLV in pkt. 337 * @dbg_level: log level. 338 * 339 * Return: void 340 */ 341 static inline void hal_rx_dump_mpdu_start_tlv_5332(void *mpdustart, 342 uint8_t dbg_level) 343 { 344 struct rx_mpdu_start_compact *mpdu_info = 345 (struct rx_mpdu_start_compact *)mpdustart; 346 347 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 348 "rx_mpdu_start tlv (1/5) - " 349 "rx_reo_queue_desc_addr_39_32 :%x" 350 "receive_queue_number:%x " 351 "pre_delim_err_warning:%x " 352 "first_delim_err:%x " 353 "pn_31_0:%x " 354 "pn_63_32:%x " 355 "pn_95_64:%x ", 356 mpdu_info->rx_reo_queue_desc_addr_39_32, 357 mpdu_info->receive_queue_number, 358 mpdu_info->pre_delim_err_warning, 359 mpdu_info->first_delim_err, 360 mpdu_info->pn_31_0, 361 mpdu_info->pn_63_32, 362 mpdu_info->pn_95_64); 363 364 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 365 "rx_mpdu_start tlv (2/5) - " 366 "ast_index:%x " 367 "sw_peer_id:%x " 368 "mpdu_frame_control_valid:%x " 369 "mpdu_duration_valid:%x " 370 "mac_addr_ad1_valid:%x " 371 "mac_addr_ad2_valid:%x " 372 "mac_addr_ad3_valid:%x " 373 "mac_addr_ad4_valid:%x " 374 "mpdu_sequence_control_valid :%x" 375 "mpdu_qos_control_valid:%x " 376 "mpdu_ht_control_valid:%x " 377 "frame_encryption_info_valid :%x", 378 mpdu_info->ast_index, 379 mpdu_info->sw_peer_id, 380 mpdu_info->mpdu_frame_control_valid, 381 mpdu_info->mpdu_duration_valid, 382 mpdu_info->mac_addr_ad1_valid, 383 mpdu_info->mac_addr_ad2_valid, 384 mpdu_info->mac_addr_ad3_valid, 385 mpdu_info->mac_addr_ad4_valid, 386 mpdu_info->mpdu_sequence_control_valid, 387 mpdu_info->mpdu_qos_control_valid, 388 mpdu_info->mpdu_ht_control_valid, 389 mpdu_info->frame_encryption_info_valid); 390 391 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 392 "rx_mpdu_start tlv (3/5) - " 393 "mpdu_fragment_number:%x " 394 "more_fragment_flag:%x " 395 "fr_ds:%x " 396 "to_ds:%x " 397 "encrypted:%x " 398 "mpdu_retry:%x " 399 "mpdu_sequence_number:%x ", 400 mpdu_info->mpdu_fragment_number, 401 mpdu_info->more_fragment_flag, 402 mpdu_info->fr_ds, 403 mpdu_info->to_ds, 404 mpdu_info->encrypted, 405 mpdu_info->mpdu_retry, 406 mpdu_info->mpdu_sequence_number); 407 408 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 409 "rx_mpdu_start tlv (4/5) - " 410 "mpdu_frame_control_field:%x " 411 "mpdu_duration_field:%x ", 412 mpdu_info->mpdu_frame_control_field, 413 mpdu_info->mpdu_duration_field); 414 415 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 416 "rx_mpdu_start tlv (5/5) - " 417 "mac_addr_ad1_31_0:%x " 418 "mac_addr_ad1_47_32:%x " 419 "mac_addr_ad2_15_0:%x " 420 "mac_addr_ad2_47_16:%x " 421 "mac_addr_ad3_31_0:%x " 422 "mac_addr_ad3_47_32:%x " 423 "mpdu_sequence_control_field :%x", 424 mpdu_info->mac_addr_ad1_31_0, 425 mpdu_info->mac_addr_ad1_47_32, 426 mpdu_info->mac_addr_ad2_15_0, 427 mpdu_info->mac_addr_ad2_47_16, 428 mpdu_info->mac_addr_ad3_31_0, 429 mpdu_info->mac_addr_ad3_47_32, 430 mpdu_info->mpdu_sequence_control_field); 431 } 432 433 /** 434 * hal_rx_dump_msdu_end_tlv_5332: dump RX msdu_end TLV in structured 435 * human readable format. 436 * @ msdu_end: pointer the msdu_end TLV in pkt. 437 * @ dbg_level: log level. 438 * 439 * Return: void 440 */ 441 static void hal_rx_dump_msdu_end_tlv_5332(void *msduend, 442 uint8_t dbg_level) 443 { 444 struct rx_msdu_end_compact *msdu_end = 445 (struct rx_msdu_end_compact *)msduend; 446 447 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 448 "rx_msdu_end tlv - " 449 "key_id_octet: %d " 450 "tcp_udp_chksum: %d " 451 "sa_idx_timeout: %d " 452 "da_idx_timeout: %d " 453 "msdu_limit_error: %d " 454 "flow_idx_timeout: %d " 455 "flow_idx_invalid: %d " 456 "wifi_parser_error: %d " 457 "sa_is_valid: %d " 458 "da_is_valid: %d " 459 "da_is_mcbc: %d " 460 "tkip_mic_err: %d " 461 "l3_header_padding: %d " 462 "first_msdu: %d " 463 "last_msdu: %d " 464 "sa_idx: %d " 465 "msdu_drop: %d " 466 "reo_destination_indication: %d " 467 "flow_idx: %d " 468 "fse_metadata: %d " 469 "cce_metadata: %d " 470 "sa_sw_peer_id: %d ", 471 msdu_end->key_id_octet, 472 msdu_end->tcp_udp_chksum, 473 msdu_end->sa_idx_timeout, 474 msdu_end->da_idx_timeout, 475 msdu_end->msdu_limit_error, 476 msdu_end->flow_idx_timeout, 477 msdu_end->flow_idx_invalid, 478 msdu_end->wifi_parser_error, 479 msdu_end->sa_is_valid, 480 msdu_end->da_is_valid, 481 msdu_end->da_is_mcbc, 482 msdu_end->tkip_mic_err, 483 msdu_end->l3_header_padding, 484 msdu_end->first_msdu, 485 msdu_end->last_msdu, 486 msdu_end->sa_idx, 487 msdu_end->msdu_drop, 488 msdu_end->reo_destination_indication, 489 msdu_end->flow_idx, 490 msdu_end->fse_metadata, 491 msdu_end->cce_metadata, 492 msdu_end->sa_sw_peer_id); 493 } 494 #else 495 static inline void hal_rx_dump_mpdu_start_tlv_5332(void *mpdustart, 496 uint8_t dbg_level) 497 { 498 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 499 struct rx_mpdu_info *mpdu_info = 500 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 501 502 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 503 "rx_mpdu_start tlv (1/5) - " 504 "rx_reo_queue_desc_addr_31_0 :%x" 505 "rx_reo_queue_desc_addr_39_32 :%x" 506 "receive_queue_number:%x " 507 "pre_delim_err_warning:%x " 508 "first_delim_err:%x " 509 "reserved_2a:%x " 510 "pn_31_0:%x " 511 "pn_63_32:%x " 512 "pn_95_64:%x " 513 "pn_127_96:%x " 514 "epd_en:%x " 515 "all_frames_shall_be_encrypted :%x" 516 "encrypt_type:%x " 517 "wep_key_width_for_variable_key :%x" 518 "mesh_sta:%x " 519 "bssid_hit:%x " 520 "bssid_number:%x " 521 "tid:%x " 522 "reserved_7a:%x ", 523 mpdu_info->rx_reo_queue_desc_addr_31_0, 524 mpdu_info->rx_reo_queue_desc_addr_39_32, 525 mpdu_info->receive_queue_number, 526 mpdu_info->pre_delim_err_warning, 527 mpdu_info->first_delim_err, 528 mpdu_info->reserved_2a, 529 mpdu_info->pn_31_0, 530 mpdu_info->pn_63_32, 531 mpdu_info->pn_95_64, 532 mpdu_info->pn_127_96, 533 mpdu_info->epd_en, 534 mpdu_info->all_frames_shall_be_encrypted, 535 mpdu_info->encrypt_type, 536 mpdu_info->wep_key_width_for_variable_key, 537 mpdu_info->mesh_sta, 538 mpdu_info->bssid_hit, 539 mpdu_info->bssid_number, 540 mpdu_info->tid, 541 mpdu_info->reserved_7a); 542 543 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 544 "rx_mpdu_start tlv (2/5) - " 545 "ast_index:%x " 546 "sw_peer_id:%x " 547 "mpdu_frame_control_valid:%x " 548 "mpdu_duration_valid:%x " 549 "mac_addr_ad1_valid:%x " 550 "mac_addr_ad2_valid:%x " 551 "mac_addr_ad3_valid:%x " 552 "mac_addr_ad4_valid:%x " 553 "mpdu_sequence_control_valid :%x" 554 "mpdu_qos_control_valid:%x " 555 "mpdu_ht_control_valid:%x " 556 "frame_encryption_info_valid :%x", 557 mpdu_info->ast_index, 558 mpdu_info->sw_peer_id, 559 mpdu_info->mpdu_frame_control_valid, 560 mpdu_info->mpdu_duration_valid, 561 mpdu_info->mac_addr_ad1_valid, 562 mpdu_info->mac_addr_ad2_valid, 563 mpdu_info->mac_addr_ad3_valid, 564 mpdu_info->mac_addr_ad4_valid, 565 mpdu_info->mpdu_sequence_control_valid, 566 mpdu_info->mpdu_qos_control_valid, 567 mpdu_info->mpdu_ht_control_valid, 568 mpdu_info->frame_encryption_info_valid); 569 570 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 571 "rx_mpdu_start tlv (3/5) - " 572 "mpdu_fragment_number:%x " 573 "more_fragment_flag:%x " 574 "reserved_11a:%x " 575 "fr_ds:%x " 576 "to_ds:%x " 577 "encrypted:%x " 578 "mpdu_retry:%x " 579 "mpdu_sequence_number:%x ", 580 mpdu_info->mpdu_fragment_number, 581 mpdu_info->more_fragment_flag, 582 mpdu_info->reserved_11a, 583 mpdu_info->fr_ds, 584 mpdu_info->to_ds, 585 mpdu_info->encrypted, 586 mpdu_info->mpdu_retry, 587 mpdu_info->mpdu_sequence_number); 588 589 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 590 "rx_mpdu_start tlv (4/5) - " 591 "mpdu_frame_control_field:%x " 592 "mpdu_duration_field:%x ", 593 mpdu_info->mpdu_frame_control_field, 594 mpdu_info->mpdu_duration_field); 595 596 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 597 "rx_mpdu_start tlv (5/5) - " 598 "mac_addr_ad1_31_0:%x " 599 "mac_addr_ad1_47_32:%x " 600 "mac_addr_ad2_15_0:%x " 601 "mac_addr_ad2_47_16:%x " 602 "mac_addr_ad3_31_0:%x " 603 "mac_addr_ad3_47_32:%x " 604 "mpdu_sequence_control_field :%x" 605 "mac_addr_ad4_31_0:%x " 606 "mac_addr_ad4_47_32:%x " 607 "mpdu_qos_control_field:%x ", 608 mpdu_info->mac_addr_ad1_31_0, 609 mpdu_info->mac_addr_ad1_47_32, 610 mpdu_info->mac_addr_ad2_15_0, 611 mpdu_info->mac_addr_ad2_47_16, 612 mpdu_info->mac_addr_ad3_31_0, 613 mpdu_info->mac_addr_ad3_47_32, 614 mpdu_info->mpdu_sequence_control_field, 615 mpdu_info->mac_addr_ad4_31_0, 616 mpdu_info->mac_addr_ad4_47_32, 617 mpdu_info->mpdu_qos_control_field); 618 } 619 620 static void hal_rx_dump_msdu_end_tlv_5332(void *msduend, 621 uint8_t dbg_level) 622 { 623 struct rx_msdu_end *msdu_end = 624 (struct rx_msdu_end *)msduend; 625 626 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 627 "rx_msdu_end tlv - " 628 "key_id_octet: %d " 629 "cce_super_rule: %d " 630 "cce_classify_not_done_truncat: %d " 631 "cce_classify_not_done_cce_dis: %d " 632 "rule_indication_31_0: %d " 633 "tcp_udp_chksum: %d " 634 "sa_idx_timeout: %d " 635 "da_idx_timeout: %d " 636 "msdu_limit_error: %d " 637 "flow_idx_timeout: %d " 638 "flow_idx_invalid: %d " 639 "wifi_parser_error: %d " 640 "sa_is_valid: %d " 641 "da_is_valid: %d " 642 "da_is_mcbc: %d " 643 "tkip_mic_err: %d " 644 "l3_header_padding: %d " 645 "first_msdu: %d " 646 "last_msdu: %d " 647 "sa_idx: %d " 648 "msdu_drop: %d " 649 "reo_destination_indication: %d " 650 "flow_idx: %d " 651 "fse_metadata: %d " 652 "cce_metadata: %d " 653 "sa_sw_peer_id: %d ", 654 msdu_end->key_id_octet, 655 msdu_end->cce_super_rule, 656 msdu_end->cce_classify_not_done_truncate, 657 msdu_end->cce_classify_not_done_cce_dis, 658 msdu_end->rule_indication_31_0, 659 msdu_end->tcp_udp_chksum, 660 msdu_end->sa_idx_timeout, 661 msdu_end->da_idx_timeout, 662 msdu_end->msdu_limit_error, 663 msdu_end->flow_idx_timeout, 664 msdu_end->flow_idx_invalid, 665 msdu_end->wifi_parser_error, 666 msdu_end->sa_is_valid, 667 msdu_end->da_is_valid, 668 msdu_end->da_is_mcbc, 669 msdu_end->tkip_mic_err, 670 msdu_end->l3_header_padding, 671 msdu_end->first_msdu, 672 msdu_end->last_msdu, 673 msdu_end->sa_idx, 674 msdu_end->msdu_drop, 675 msdu_end->reo_destination_indication, 676 msdu_end->flow_idx, 677 msdu_end->fse_metadata, 678 msdu_end->cce_metadata, 679 msdu_end->sa_sw_peer_id); 680 } 681 #endif 682 683 /** 684 * hal_reo_status_get_header_5332 - Process reo desc info 685 * @d - Pointer to reo descriptor 686 * @b - tlv type info 687 * @h1 - Pointer to hal_reo_status_header where info to be stored 688 * 689 * Return - none. 690 * 691 */ 692 static void hal_reo_status_get_header_5332(hal_ring_desc_t ring_desc, 693 int b, void *h1) 694 { 695 uint64_t *d = (uint64_t *)ring_desc; 696 uint64_t val1 = 0; 697 struct hal_reo_status_header *h = 698 (struct hal_reo_status_header *)h1; 699 700 /* Offsets of descriptor fields defined in HW headers start 701 * from the field after TLV header 702 */ 703 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr)); 704 705 switch (b) { 706 case HAL_REO_QUEUE_STATS_STATUS_TLV: 707 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 708 STATUS_HEADER_REO_STATUS_NUMBER)]; 709 break; 710 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 711 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 712 STATUS_HEADER_REO_STATUS_NUMBER)]; 713 break; 714 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 715 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 716 STATUS_HEADER_REO_STATUS_NUMBER)]; 717 break; 718 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 719 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 720 STATUS_HEADER_REO_STATUS_NUMBER)]; 721 break; 722 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 723 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 724 STATUS_HEADER_REO_STATUS_NUMBER)]; 725 break; 726 case HAL_REO_DESC_THRES_STATUS_TLV: 727 val1 = 728 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 729 STATUS_HEADER_REO_STATUS_NUMBER)]; 730 break; 731 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 732 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 733 STATUS_HEADER_REO_STATUS_NUMBER)]; 734 break; 735 default: 736 qdf_nofl_err("ERROR: Unknown tlv\n"); 737 break; 738 } 739 h->cmd_num = 740 HAL_GET_FIELD( 741 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER, 742 val1); 743 h->exec_time = 744 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 745 CMD_EXECUTION_TIME, val1); 746 h->status = 747 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 748 REO_CMD_EXECUTION_STATUS, val1); 749 switch (b) { 750 case HAL_REO_QUEUE_STATS_STATUS_TLV: 751 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 752 STATUS_HEADER_TIMESTAMP)]; 753 break; 754 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 755 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 756 STATUS_HEADER_TIMESTAMP)]; 757 break; 758 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 759 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 760 STATUS_HEADER_TIMESTAMP)]; 761 break; 762 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 763 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 764 STATUS_HEADER_TIMESTAMP)]; 765 break; 766 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 767 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 768 STATUS_HEADER_TIMESTAMP)]; 769 break; 770 case HAL_REO_DESC_THRES_STATUS_TLV: 771 val1 = 772 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 773 STATUS_HEADER_TIMESTAMP)]; 774 break; 775 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 776 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 777 STATUS_HEADER_TIMESTAMP)]; 778 break; 779 default: 780 qdf_nofl_err("ERROR: Unknown tlv\n"); 781 break; 782 } 783 h->tstamp = 784 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1); 785 } 786 787 static 788 void *hal_rx_msdu0_buffer_addr_lsb_5332(void *link_desc_va) 789 { 790 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 791 } 792 793 static 794 void *hal_rx_msdu_desc_info_ptr_get_5332(void *msdu0) 795 { 796 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 797 } 798 799 static 800 void *hal_ent_mpdu_desc_info_5332(void *ent_ring_desc) 801 { 802 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 803 } 804 805 static 806 void *hal_dst_mpdu_desc_info_5332(void *dst_ring_desc) 807 { 808 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 809 } 810 811 /** 812 * hal_reo_config_5332(): Set reo config parameters 813 * @soc: hal soc handle 814 * @reg_val: value to be set 815 * @reo_params: reo parameters 816 * 817 * Return: void 818 */ 819 static void 820 hal_reo_config_5332(struct hal_soc *soc, 821 uint32_t reg_val, 822 struct hal_reo_params *reo_params) 823 { 824 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 825 } 826 827 /** 828 * hal_rx_msdu_desc_info_get_ptr_5332() - Get msdu desc info ptr 829 * @msdu_details_ptr - Pointer to msdu_details_ptr 830 * 831 * Return - Pointer to rx_msdu_desc_info structure. 832 * 833 */ 834 static void *hal_rx_msdu_desc_info_get_ptr_5332(void *msdu_details_ptr) 835 { 836 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 837 } 838 839 /** 840 * hal_rx_link_desc_msdu0_ptr_5332 - Get pointer to rx_msdu details 841 * @link_desc - Pointer to link desc 842 * 843 * Return - Pointer to rx_msdu_details structure 844 * 845 */ 846 static void *hal_rx_link_desc_msdu0_ptr_5332(void *link_desc) 847 { 848 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 849 } 850 851 /** 852 * hal_get_window_address_5332(): Function to get hp/tp address 853 * @hal_soc: Pointer to hal_soc 854 * @addr: address offset of register 855 * 856 * Return: modified address offset of register 857 */ 858 859 static inline qdf_iomem_t hal_get_window_address_5332(struct hal_soc *hal_soc, 860 qdf_iomem_t addr) 861 { 862 uint32_t offset = addr - hal_soc->dev_base_addr; 863 qdf_iomem_t new_offset; 864 865 /* 866 * Check if offset lies within CE register range(0x740000) 867 * or UMAC/DP register range (0x00A00000). 868 * If offset lies within CE register range, map it 869 * into CE region. 870 */ 871 if (offset < 0xA00000) { 872 offset = offset - CE_CFG_WFSS_CE_REG_BASE; 873 new_offset = (hal_soc->dev_base_addr_ce + offset); 874 875 return new_offset; 876 } else { 877 /* 878 * If offset lies within DP register range, 879 * return the address as such 880 */ 881 return addr; 882 } 883 } 884 885 static 886 void hal_compute_reo_remap_ix2_ix3_5332(uint32_t *ring, uint32_t num_rings, 887 uint32_t *remap1, uint32_t *remap2) 888 { 889 switch (num_rings) { 890 case 1: 891 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 892 HAL_REO_REMAP_IX2(ring[0], 17) | 893 HAL_REO_REMAP_IX2(ring[0], 18) | 894 HAL_REO_REMAP_IX2(ring[0], 19) | 895 HAL_REO_REMAP_IX2(ring[0], 20) | 896 HAL_REO_REMAP_IX2(ring[0], 21) | 897 HAL_REO_REMAP_IX2(ring[0], 22) | 898 HAL_REO_REMAP_IX2(ring[0], 23); 899 900 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 901 HAL_REO_REMAP_IX3(ring[0], 25) | 902 HAL_REO_REMAP_IX3(ring[0], 26) | 903 HAL_REO_REMAP_IX3(ring[0], 27) | 904 HAL_REO_REMAP_IX3(ring[0], 28) | 905 HAL_REO_REMAP_IX3(ring[0], 29) | 906 HAL_REO_REMAP_IX3(ring[0], 30) | 907 HAL_REO_REMAP_IX3(ring[0], 31); 908 break; 909 case 2: 910 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 911 HAL_REO_REMAP_IX2(ring[0], 17) | 912 HAL_REO_REMAP_IX2(ring[1], 18) | 913 HAL_REO_REMAP_IX2(ring[1], 19) | 914 HAL_REO_REMAP_IX2(ring[0], 20) | 915 HAL_REO_REMAP_IX2(ring[0], 21) | 916 HAL_REO_REMAP_IX2(ring[1], 22) | 917 HAL_REO_REMAP_IX2(ring[1], 23); 918 919 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 920 HAL_REO_REMAP_IX3(ring[0], 25) | 921 HAL_REO_REMAP_IX3(ring[1], 26) | 922 HAL_REO_REMAP_IX3(ring[1], 27) | 923 HAL_REO_REMAP_IX3(ring[0], 28) | 924 HAL_REO_REMAP_IX3(ring[0], 29) | 925 HAL_REO_REMAP_IX3(ring[1], 30) | 926 HAL_REO_REMAP_IX3(ring[1], 31); 927 break; 928 case 3: 929 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 930 HAL_REO_REMAP_IX2(ring[1], 17) | 931 HAL_REO_REMAP_IX2(ring[2], 18) | 932 HAL_REO_REMAP_IX2(ring[0], 19) | 933 HAL_REO_REMAP_IX2(ring[1], 20) | 934 HAL_REO_REMAP_IX2(ring[2], 21) | 935 HAL_REO_REMAP_IX2(ring[0], 22) | 936 HAL_REO_REMAP_IX2(ring[1], 23); 937 938 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 939 HAL_REO_REMAP_IX3(ring[0], 25) | 940 HAL_REO_REMAP_IX3(ring[1], 26) | 941 HAL_REO_REMAP_IX3(ring[2], 27) | 942 HAL_REO_REMAP_IX3(ring[0], 28) | 943 HAL_REO_REMAP_IX3(ring[1], 29) | 944 HAL_REO_REMAP_IX3(ring[2], 30) | 945 HAL_REO_REMAP_IX3(ring[0], 31); 946 break; 947 case 4: 948 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 949 HAL_REO_REMAP_IX2(ring[1], 17) | 950 HAL_REO_REMAP_IX2(ring[2], 18) | 951 HAL_REO_REMAP_IX2(ring[3], 19) | 952 HAL_REO_REMAP_IX2(ring[0], 20) | 953 HAL_REO_REMAP_IX2(ring[1], 21) | 954 HAL_REO_REMAP_IX2(ring[2], 22) | 955 HAL_REO_REMAP_IX2(ring[3], 23); 956 957 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 958 HAL_REO_REMAP_IX3(ring[1], 25) | 959 HAL_REO_REMAP_IX3(ring[2], 26) | 960 HAL_REO_REMAP_IX3(ring[3], 27) | 961 HAL_REO_REMAP_IX3(ring[0], 28) | 962 HAL_REO_REMAP_IX3(ring[1], 29) | 963 HAL_REO_REMAP_IX3(ring[2], 30) | 964 HAL_REO_REMAP_IX3(ring[3], 31); 965 break; 966 } 967 } 968 969 /** 970 * hal_rx_flow_setup_fse_5332() - Setup a flow search entry in HW FST 971 * @fst: Pointer to the Rx Flow Search Table 972 * @table_offset: offset into the table where the flow is to be setup 973 * @flow: Flow Parameters 974 * 975 * Return: Success/Failure 976 */ 977 static void * 978 hal_rx_flow_setup_fse_5332(uint8_t *rx_fst, uint32_t table_offset, 979 uint8_t *rx_flow) 980 { 981 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 982 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 983 uint8_t *fse; 984 bool fse_valid; 985 986 if (table_offset >= fst->max_entries) { 987 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 988 "HAL FSE table offset %u exceeds max entries %u", 989 table_offset, fst->max_entries); 990 return NULL; 991 } 992 993 fse = (uint8_t *)fst->base_vaddr + 994 (table_offset * HAL_RX_FST_ENTRY_SIZE); 995 996 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 997 998 if (fse_valid) { 999 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1000 "HAL FSE %pK already valid", fse); 1001 return NULL; 1002 } 1003 1004 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) = 1005 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1006 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1007 1008 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) = 1009 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1010 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1011 1012 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) = 1013 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1014 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1015 1016 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) = 1017 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1018 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1019 1020 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) = 1021 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1022 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1023 1024 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) = 1025 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1026 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1027 1028 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) = 1029 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1030 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1031 1032 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) = 1033 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1034 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1035 1036 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT); 1037 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |= 1038 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1039 (flow->tuple_info.dest_port)); 1040 1041 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT); 1042 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |= 1043 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1044 (flow->tuple_info.src_port)); 1045 1046 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL); 1047 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |= 1048 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1049 flow->tuple_info.l4_protocol); 1050 1051 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER); 1052 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |= 1053 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1054 flow->reo_destination_handler); 1055 1056 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1057 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |= 1058 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1059 1060 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA); 1061 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) = 1062 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1063 flow->fse_metadata); 1064 1065 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION); 1066 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |= 1067 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1068 REO_DESTINATION_INDICATION, 1069 flow->reo_destination_indication); 1070 1071 /* Reset all the other fields in FSE */ 1072 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9); 1073 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP); 1074 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT); 1075 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT); 1076 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP); 1077 1078 return fse; 1079 } 1080 1081 #ifndef NO_RX_PKT_HDR_TLV 1082 /** 1083 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 1084 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 1085 * @ dbg_level: log level. 1086 * 1087 * Return: void 1088 */ 1089 static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs, 1090 uint8_t dbg_level) 1091 { 1092 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 1093 1094 hal_verbose_debug("\n---------------\n" 1095 "rx_pkt_hdr_tlv\n" 1096 "---------------\n" 1097 "phy_ppdu_id %llu ", 1098 pkt_hdr_tlv->phy_ppdu_id); 1099 1100 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 1101 sizeof(pkt_hdr_tlv->rx_pkt_hdr)); 1102 } 1103 #else 1104 /** 1105 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 1106 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 1107 * @ dbg_level: log level. 1108 * 1109 * Return: void 1110 */ 1111 static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs, 1112 uint8_t dbg_level) 1113 { 1114 } 1115 #endif 1116 1117 /** 1118 * hal_rx_dump_pkt_tlvs_5332(): API to print RX Pkt TLVS qca5332 1119 * @hal_soc_hdl: hal_soc handle 1120 * @buf: pointer the pkt buffer 1121 * @dbg_level: log level 1122 * 1123 * Return: void 1124 */ 1125 #ifdef CONFIG_WORD_BASED_TLV 1126 static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl, 1127 uint8_t *buf, uint8_t dbg_level) 1128 { 1129 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1130 struct rx_msdu_end_compact *msdu_end = 1131 &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1132 struct rx_mpdu_start_compact *mpdu_start = 1133 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1134 1135 hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level); 1136 hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level); 1137 hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level); 1138 } 1139 #else 1140 static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl, 1141 uint8_t *buf, uint8_t dbg_level) 1142 { 1143 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1144 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1145 struct rx_mpdu_start *mpdu_start = 1146 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1147 1148 hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level); 1149 hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level); 1150 hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level); 1151 } 1152 #endif 1153 1154 #define HAL_NUM_TCL_BANKS_5332 24 1155 1156 /** 1157 * hal_cmem_write_5332() - function for CMEM buffer writing 1158 * @hal_soc_hdl: HAL SOC handle 1159 * @offset: CMEM address 1160 * @value: value to write 1161 * 1162 * Return: None. 1163 */ 1164 static void hal_cmem_write_5332(hal_soc_handle_t hal_soc_hdl, 1165 uint32_t offset, 1166 uint32_t value) 1167 { 1168 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1169 1170 /* cmem region is ioremapped from CMEM_REG_BASE, hence subtracting 1171 * that from offset. 1172 */ 1173 offset = offset - CMEM_REG_BASE; 1174 pld_reg_write(hal->qdf_dev->dev, offset, value, 1175 hal->dev_base_addr_cmem); 1176 } 1177 1178 /** 1179 * hal_tx_get_num_tcl_banks_5332() - Get number of banks in target 1180 * 1181 * Returns: number of bank 1182 */ 1183 static uint8_t hal_tx_get_num_tcl_banks_5332(void) 1184 { 1185 return HAL_NUM_TCL_BANKS_5332; 1186 } 1187 1188 static void hal_reo_setup_5332(struct hal_soc *soc, void *reoparams, 1189 int qref_reset) 1190 { 1191 uint32_t reg_val; 1192 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1193 1194 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1195 REO_REG_REG_BASE)); 1196 1197 hal_reo_config_5332(soc, reg_val, reo_params); 1198 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1199 1200 /* TODO: Setup destination ring mapping if enabled */ 1201 1202 /* TODO: Error destination ring setting is left to default. 1203 * Default setting is to send all errors to release ring. 1204 */ 1205 1206 /* Set the reo descriptor swap bits in case of BIG endian platform */ 1207 hal_setup_reo_swap(soc); 1208 1209 HAL_REG_WRITE(soc, 1210 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE), 1211 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1212 1213 HAL_REG_WRITE(soc, 1214 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE), 1215 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1216 1217 HAL_REG_WRITE(soc, 1218 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE), 1219 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1220 1221 HAL_REG_WRITE(soc, 1222 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE), 1223 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1224 1225 /* 1226 * When hash based routing is enabled, routing of the rx packet 1227 * is done based on the following value: 1 _ _ _ _ The last 4 1228 * bits are based on hash[3:0]. This means the possible values 1229 * are 0x10 to 0x1f. This value is used to look-up the 1230 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1231 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1232 * registers need to be configured to set-up the 16 entries to 1233 * map the hash values to a ring number. There are 3 bits per 1234 * hash entry – which are mapped as follows: 1235 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1236 * 7: NOT_USED. 1237 */ 1238 if (reo_params->rx_hash_enabled) { 1239 HAL_REG_WRITE(soc, 1240 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR 1241 (REO_REG_REG_BASE), reo_params->remap0); 1242 1243 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1244 HAL_REG_READ(soc, 1245 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR( 1246 REO_REG_REG_BASE))); 1247 1248 HAL_REG_WRITE(soc, 1249 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 1250 (REO_REG_REG_BASE), reo_params->remap1); 1251 1252 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1253 HAL_REG_READ(soc, 1254 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1255 REO_REG_REG_BASE))); 1256 1257 HAL_REG_WRITE(soc, 1258 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 1259 (REO_REG_REG_BASE), reo_params->remap2); 1260 1261 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1262 HAL_REG_READ(soc, 1263 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1264 REO_REG_REG_BASE))); 1265 } 1266 1267 /* TODO: Check if the following registers shoould be setup by host: 1268 * AGING_CONTROL 1269 * HIGH_MEMORY_THRESHOLD 1270 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1271 * GLOBAL_LINK_DESC_COUNT_CTRL 1272 */ 1273 1274 soc->reo_qref = *reo_params->reo_qref; 1275 hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset); 1276 } 1277 1278 static uint16_t hal_get_rx_max_ba_window_qca5332(int tid) 1279 { 1280 return HAL_RX_BA_WINDOW_1024; 1281 } 1282 1283 /** 1284 * hal_qca5332_get_reo_qdesc_size()- Get the reo queue descriptor size 1285 * from the give Block-Ack window size 1286 * Return: reo queue descriptor size 1287 */ 1288 static uint32_t hal_qca5332_get_reo_qdesc_size(uint32_t ba_window_size, int tid) 1289 { 1290 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 1291 * NON_QOS_TID until HW issues are resolved. 1292 */ 1293 if (tid != HAL_NON_QOS_TID) 1294 ba_window_size = hal_get_rx_max_ba_window_qca5332(tid); 1295 1296 /* Return descriptor size corresponding to window size of 2 since 1297 * we set ba_window_size to 2 while setting up REO descriptors as 1298 * a WAR to get 2k jump exception aggregates are received without 1299 * a BA session. 1300 */ 1301 if (ba_window_size <= 1) { 1302 if (tid != HAL_NON_QOS_TID) 1303 return sizeof(struct rx_reo_queue) + 1304 sizeof(struct rx_reo_queue_ext); 1305 else 1306 return sizeof(struct rx_reo_queue); 1307 } 1308 1309 if (ba_window_size <= 105) 1310 return sizeof(struct rx_reo_queue) + 1311 sizeof(struct rx_reo_queue_ext); 1312 1313 if (ba_window_size <= 210) 1314 return sizeof(struct rx_reo_queue) + 1315 (2 * sizeof(struct rx_reo_queue_ext)); 1316 1317 if (ba_window_size <= 256) 1318 return sizeof(struct rx_reo_queue) + 1319 (3 * sizeof(struct rx_reo_queue_ext)); 1320 1321 return sizeof(struct rx_reo_queue) + 1322 (10 * sizeof(struct rx_reo_queue_ext)) + 1323 sizeof(struct rx_reo_queue_1k); 1324 } 1325 /** 1326 * hal_rx_tlv_msdu_done_copy_get_5332() - Get msdu done copy bit from rx_tlv 1327 * 1328 * Returns: msdu done copy bit 1329 */ 1330 static inline uint32_t hal_rx_tlv_msdu_done_copy_get_5332(uint8_t *buf) 1331 { 1332 return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf); 1333 } 1334 1335 static void hal_hw_txrx_ops_attach_qca5332(struct hal_soc *hal_soc) 1336 { 1337 /* init and setup */ 1338 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1339 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1340 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1341 hal_soc->ops->hal_get_window_address = hal_get_window_address_5332; 1342 hal_soc->ops->hal_cmem_write = hal_cmem_write_5332; 1343 1344 /* tx */ 1345 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5332; 1346 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5332; 1347 hal_soc->ops->hal_tx_comp_get_status = 1348 hal_tx_comp_get_status_generic_be; 1349 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1350 hal_tx_init_cmd_credit_ring_5332; 1351 hal_soc->ops->hal_tx_set_ppe_cmn_cfg = NULL; 1352 hal_soc->ops->hal_tx_set_ppe_vp_entry = NULL; 1353 hal_soc->ops->hal_tx_set_ppe_pri2tid = NULL; 1354 hal_soc->ops->hal_tx_update_ppe_pri2tid = NULL; 1355 hal_soc->ops->hal_tx_dump_ppe_vp_entry = NULL; 1356 hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = NULL; 1357 hal_soc->ops->hal_tx_enable_pri2tid_map = NULL; 1358 hal_soc->ops->hal_ppeds_cfg_ast_override_map_reg = NULL; 1359 hal_soc->ops->hal_tx_config_rbm_mapping_be = 1360 hal_tx_config_rbm_mapping_be_5332; 1361 1362 /* rx */ 1363 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; 1364 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1365 hal_rx_mon_hw_desc_get_mpdu_status_be; 1366 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5332; 1367 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1368 hal_rx_proc_phyrx_other_receive_info_tlv_5332; 1369 1370 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5332; 1371 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1372 hal_rx_dump_mpdu_start_tlv_5332; 1373 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_5332; 1374 1375 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5332; 1376 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be; 1377 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1378 hal_rx_tlv_reception_type_get_be; 1379 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1380 hal_rx_msdu_end_da_idx_get_be; 1381 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1382 hal_rx_msdu_desc_info_get_ptr_5332; 1383 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1384 hal_rx_link_desc_msdu0_ptr_5332; 1385 hal_soc->ops->hal_reo_status_get_header = 1386 hal_reo_status_get_header_5332; 1387 #ifdef QCA_MONITOR_2_0_SUPPORT 1388 hal_soc->ops->hal_rx_status_get_tlv_info = 1389 hal_rx_status_get_tlv_info_wrapper_be; 1390 #endif 1391 hal_soc->ops->hal_rx_wbm_err_info_get = 1392 hal_rx_wbm_err_info_get_generic_be; 1393 hal_soc->ops->hal_tx_set_pcp_tid_map = 1394 hal_tx_set_pcp_tid_map_generic_be; 1395 hal_soc->ops->hal_tx_update_pcp_tid_map = 1396 hal_tx_update_pcp_tid_generic_be; 1397 hal_soc->ops->hal_tx_set_tidmap_prty = 1398 hal_tx_update_tidmap_prty_generic_be; 1399 hal_soc->ops->hal_rx_get_rx_fragment_number = 1400 hal_rx_get_rx_fragment_number_be, 1401 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1402 hal_rx_tlv_da_is_mcbc_get_be; 1403 hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err = 1404 hal_rx_tlv_is_tkip_mic_err_get_be; 1405 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1406 hal_rx_tlv_sa_is_valid_get_be; 1407 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be; 1408 hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be; 1409 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1410 hal_rx_tlv_l3_hdr_padding_get_be; 1411 hal_soc->ops->hal_rx_encryption_info_valid = 1412 hal_rx_encryption_info_valid_be; 1413 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; 1414 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1415 hal_rx_tlv_first_msdu_get_be; 1416 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1417 hal_rx_tlv_da_is_valid_get_be; 1418 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1419 hal_rx_tlv_last_msdu_get_be; 1420 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1421 hal_rx_get_mpdu_mac_ad4_valid_be; 1422 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1423 hal_rx_mpdu_start_sw_peer_id_get_be; 1424 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1425 hal_rx_msdu_peer_meta_data_get_be; 1426 #ifndef CONFIG_WORD_BASED_TLV 1427 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; 1428 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1429 hal_rx_mpdu_info_ampdu_flag_get_be; 1430 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1431 hal_rx_hw_desc_get_ppduid_get_be; 1432 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be; 1433 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 1434 hal_rx_attn_phy_ppdu_id_get_be; 1435 hal_soc->ops->hal_rx_get_filter_category = 1436 hal_rx_get_filter_category_be; 1437 #endif 1438 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be; 1439 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be; 1440 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1441 hal_rx_get_mpdu_frame_control_valid_be; 1442 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; 1443 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; 1444 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; 1445 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1446 hal_rx_get_mpdu_sequence_control_valid_be; 1447 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; 1448 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; 1449 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1450 hal_rx_mpdu_start_mpdu_qos_control_valid_get_be; 1451 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1452 hal_rx_msdu_end_sa_sw_peer_id_get_be; 1453 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1454 hal_rx_msdu0_buffer_addr_lsb_5332; 1455 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1456 hal_rx_msdu_desc_info_ptr_get_5332; 1457 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5332; 1458 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5332; 1459 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; 1460 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; 1461 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1462 hal_rx_get_mac_addr2_valid_be; 1463 hal_soc->ops->hal_reo_config = hal_reo_config_5332; 1464 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; 1465 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1466 hal_rx_msdu_flow_idx_invalid_be; 1467 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1468 hal_rx_msdu_flow_idx_timeout_be; 1469 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1470 hal_rx_msdu_fse_metadata_get_be; 1471 hal_soc->ops->hal_rx_msdu_cce_match_get = 1472 hal_rx_msdu_cce_match_get_be; 1473 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1474 hal_rx_msdu_cce_metadata_get_be; 1475 hal_soc->ops->hal_rx_msdu_get_flow_params = 1476 hal_rx_msdu_get_flow_params_be; 1477 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be; 1478 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be; 1479 #if defined(QCA_WIFI_QCA5332) && defined(WLAN_CFR_ENABLE) && \ 1480 defined(WLAN_ENH_CFR_ENABLE) 1481 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5332; 1482 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5332; 1483 #else 1484 hal_soc->ops->hal_rx_get_bb_info = NULL; 1485 hal_soc->ops->hal_rx_get_rtt_info = NULL; 1486 #endif 1487 /* rx - msdu fast path info fields */ 1488 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1489 hal_rx_msdu_packet_metadata_get_generic_be; 1490 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1491 hal_rx_mpdu_start_tlv_tag_valid_be; 1492 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1493 hal_rx_wbm_err_msdu_continuation_get_5332; 1494 1495 /* rx - TLV struct offsets */ 1496 hal_soc->ops->hal_rx_msdu_end_offset_get = 1497 hal_rx_msdu_end_offset_get_generic; 1498 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1499 hal_rx_mpdu_start_offset_get_generic; 1500 #ifndef NO_RX_PKT_HDR_TLV 1501 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1502 hal_rx_pkt_tlv_offset_get_generic; 1503 #endif 1504 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5332; 1505 1506 hal_soc->ops->hal_rx_flow_get_tuple_info = 1507 hal_rx_flow_get_tuple_info_be; 1508 hal_soc->ops->hal_rx_flow_delete_entry = 1509 hal_rx_flow_delete_entry_be; 1510 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be; 1511 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1512 hal_compute_reo_remap_ix2_ix3_5332; 1513 1514 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 1515 hal_rx_msdu_get_reo_destination_indication_be; 1516 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; 1517 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 1518 hal_rx_msdu_is_wlan_mcast_generic_be; 1519 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_5332; 1520 hal_soc->ops->hal_rx_tlv_decap_format_get = 1521 hal_rx_tlv_decap_format_get_be; 1522 #ifdef RECEIVE_OFFLOAD 1523 hal_soc->ops->hal_rx_tlv_get_offload_info = 1524 hal_rx_tlv_get_offload_info_be; 1525 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; 1526 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; 1527 #endif 1528 hal_soc->ops->hal_rx_tlv_msdu_done_get = 1529 hal_rx_tlv_msdu_done_copy_get_5332; 1530 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1531 hal_rx_msdu_start_msdu_len_get_be; 1532 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1533 hal_rx_get_frame_ctrl_field_be; 1534 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; 1535 hal_soc->ops->hal_rx_tlv_msdu_len_set = 1536 hal_rx_msdu_start_msdu_len_set_be; 1537 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; 1538 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; 1539 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be; 1540 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be; 1541 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be; 1542 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1543 hal_rx_tlv_decrypt_err_get_be; 1544 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be; 1545 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 1546 hal_rx_tlv_get_is_decrypted_be; 1547 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be; 1548 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 1549 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1550 hal_rx_priv_info_set_in_tlv_be; 1551 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1552 hal_rx_priv_info_get_from_tlv_be; 1553 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be; 1554 hal_soc->ops->hal_reo_setup = hal_reo_setup_5332; 1555 #ifdef REO_SHARED_QREF_TABLE_EN 1556 hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be; 1557 hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be; 1558 hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be; 1559 hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be; 1560 hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be; 1561 #endif 1562 /* Overwrite the default BE ops */ 1563 hal_soc->ops->hal_get_rx_max_ba_window = 1564 hal_get_rx_max_ba_window_qca5332; 1565 hal_soc->ops->hal_get_reo_qdesc_size = hal_qca5332_get_reo_qdesc_size; 1566 /* TX MONITOR */ 1567 #ifdef QCA_MONITOR_2_0_SUPPORT 1568 hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv = 1569 hal_txmon_is_mon_buf_addr_tlv_generic_be; 1570 hal_soc->ops->hal_txmon_populate_packet_info = 1571 hal_txmon_populate_packet_info_generic_be; 1572 hal_soc->ops->hal_txmon_status_parse_tlv = 1573 hal_txmon_status_parse_tlv_generic_be; 1574 hal_soc->ops->hal_txmon_status_get_num_users = 1575 hal_txmon_status_get_num_users_generic_be; 1576 #endif /* QCA_MONITOR_2_0_SUPPORT */ 1577 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1578 hal_soc->ops->hal_tx_vdev_mismatch_routing_set = 1579 hal_tx_vdev_mismatch_routing_set_generic_be; 1580 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = 1581 hal_tx_mcast_mlo_reinject_routing_set_generic_be; 1582 hal_soc->ops->hal_get_ba_aging_timeout = 1583 hal_get_ba_aging_timeout_be_generic; 1584 hal_soc->ops->hal_setup_link_idle_list = 1585 hal_setup_link_idle_list_generic_be; 1586 hal_soc->ops->hal_cookie_conversion_reg_cfg_be = 1587 hal_cookie_conversion_reg_cfg_generic_be; 1588 hal_soc->ops->hal_set_ba_aging_timeout = 1589 hal_set_ba_aging_timeout_be_generic; 1590 hal_soc->ops->hal_tx_populate_bank_register = 1591 hal_tx_populate_bank_register_be; 1592 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = 1593 hal_tx_vdev_mcast_ctrl_set_be; 1594 hal_soc->ops->hal_get_tsf2_scratch_reg = 1595 hal_get_tsf2_scratch_reg_qca5332; 1596 hal_soc->ops->hal_get_tqm_scratch_reg = 1597 hal_get_tqm_scratch_reg_qca5332; 1598 #ifdef CONFIG_WORD_BASED_TLV 1599 hal_soc->ops->hal_rx_mpdu_start_wmask_get = 1600 hal_rx_mpdu_start_wmask_get_be; 1601 hal_soc->ops->hal_rx_msdu_end_wmask_get = 1602 hal_rx_msdu_end_wmask_get_be; 1603 #endif 1604 }; 1605 1606 struct hal_hw_srng_config hw_srng_table_5332[] = { 1607 /* TODO: max_rings can populated by querying HW capabilities */ 1608 { /* REO_DST */ 1609 .start_ring_id = HAL_SRNG_REO2SW1, 1610 .max_rings = 8, 1611 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1612 .lmac_ring = FALSE, 1613 .ring_dir = HAL_SRNG_DST_RING, 1614 .reg_start = { 1615 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1616 REO_REG_REG_BASE), 1617 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1618 REO_REG_REG_BASE) 1619 }, 1620 .reg_size = { 1621 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1622 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1623 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1624 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1625 }, 1626 .max_size = 1627 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1628 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1629 }, 1630 { /* REO_EXCEPTION */ 1631 /* Designating REO2SW0 ring as exception ring. This ring is 1632 * similar to other REO2SW rings though it is named as REO2SW0. 1633 * Any of theREO2SW rings can be used as exception ring. 1634 */ 1635 .start_ring_id = HAL_SRNG_REO2SW0, 1636 .max_rings = 1, 1637 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1638 .lmac_ring = FALSE, 1639 .ring_dir = HAL_SRNG_DST_RING, 1640 .reg_start = { 1641 HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR( 1642 REO_REG_REG_BASE), 1643 HWIO_REO_R2_REO2SW0_RING_HP_ADDR( 1644 REO_REG_REG_BASE) 1645 }, 1646 /* Single ring - provide ring size if multiple rings of this 1647 * type are supported 1648 */ 1649 .reg_size = {}, 1650 .max_size = 1651 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >> 1652 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT, 1653 }, 1654 { /* REO_REINJECT */ 1655 .start_ring_id = HAL_SRNG_SW2REO, 1656 .max_rings = 4, 1657 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1658 .lmac_ring = FALSE, 1659 .ring_dir = HAL_SRNG_SRC_RING, 1660 .reg_start = { 1661 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1662 REO_REG_REG_BASE), 1663 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1664 REO_REG_REG_BASE) 1665 }, 1666 /* Single ring - provide ring size if multiple rings of this 1667 * type are supported 1668 */ 1669 .reg_size = { 1670 HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) - 1671 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0), 1672 HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) - 1673 HWIO_REO_R2_SW2REO_RING_HP_ADDR(0) 1674 }, 1675 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1676 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1677 }, 1678 { /* REO_CMD */ 1679 .start_ring_id = HAL_SRNG_REO_CMD, 1680 .max_rings = 1, 1681 .entry_size = (sizeof(struct tlv_32_hdr) + 1682 sizeof(struct reo_get_queue_stats)) >> 2, 1683 .lmac_ring = FALSE, 1684 .ring_dir = HAL_SRNG_SRC_RING, 1685 .reg_start = { 1686 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1687 REO_REG_REG_BASE), 1688 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1689 REO_REG_REG_BASE), 1690 }, 1691 /* Single ring - provide ring size if multiple rings of this 1692 * type are supported 1693 */ 1694 .reg_size = {}, 1695 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1696 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1697 }, 1698 { /* REO_STATUS */ 1699 .start_ring_id = HAL_SRNG_REO_STATUS, 1700 .max_rings = 1, 1701 .entry_size = (sizeof(struct tlv_32_hdr) + 1702 sizeof(struct reo_get_queue_stats_status)) >> 2, 1703 .lmac_ring = FALSE, 1704 .ring_dir = HAL_SRNG_DST_RING, 1705 .reg_start = { 1706 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1707 REO_REG_REG_BASE), 1708 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1709 REO_REG_REG_BASE), 1710 }, 1711 /* Single ring - provide ring size if multiple rings of this 1712 * type are supported 1713 */ 1714 .reg_size = {}, 1715 .max_size = 1716 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1717 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1718 }, 1719 { /* TCL_DATA */ 1720 .start_ring_id = HAL_SRNG_SW2TCL1, 1721 .max_rings = 6, 1722 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 1723 .lmac_ring = FALSE, 1724 .ring_dir = HAL_SRNG_SRC_RING, 1725 .reg_start = { 1726 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1727 MAC_TCL_REG_REG_BASE), 1728 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1729 MAC_TCL_REG_REG_BASE), 1730 }, 1731 .reg_size = { 1732 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1733 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1734 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1735 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1736 }, 1737 .max_size = 1738 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1739 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1740 }, 1741 { /* TCL_CMD/CREDIT */ 1742 /* qca8074v2 and qca5332 uses this ring for data commands */ 1743 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1744 .max_rings = 1, 1745 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 1746 .lmac_ring = FALSE, 1747 .ring_dir = HAL_SRNG_SRC_RING, 1748 .reg_start = { 1749 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 1750 MAC_TCL_REG_REG_BASE), 1751 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 1752 MAC_TCL_REG_REG_BASE), 1753 }, 1754 /* Single ring - provide ring size if multiple rings of this 1755 * type are supported 1756 */ 1757 .reg_size = {}, 1758 .max_size = 1759 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 1760 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 1761 }, 1762 { /* TCL_STATUS */ 1763 .start_ring_id = HAL_SRNG_TCL_STATUS, 1764 .max_rings = 1, 1765 .entry_size = (sizeof(struct tlv_32_hdr) + 1766 sizeof(struct tcl_status_ring)) >> 2, 1767 .lmac_ring = FALSE, 1768 .ring_dir = HAL_SRNG_DST_RING, 1769 .reg_start = { 1770 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1771 MAC_TCL_REG_REG_BASE), 1772 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1773 MAC_TCL_REG_REG_BASE), 1774 }, 1775 /* Single ring - provide ring size if multiple rings of this 1776 * type are supported 1777 */ 1778 .reg_size = {}, 1779 .max_size = 1780 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1781 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1782 }, 1783 { /* CE_SRC */ 1784 .start_ring_id = HAL_SRNG_CE_0_SRC, 1785 .max_rings = 16, 1786 .entry_size = sizeof(struct ce_src_desc) >> 2, 1787 .lmac_ring = FALSE, 1788 .ring_dir = HAL_SRNG_SRC_RING, 1789 .reg_start = { 1790 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR( 1791 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE), 1792 HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR( 1793 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE), 1794 }, 1795 .reg_size = { 1796 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 1797 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 1798 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 1799 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 1800 }, 1801 .max_size = 1802 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >> 1803 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT, 1804 }, 1805 { /* CE_DST */ 1806 .start_ring_id = HAL_SRNG_CE_0_DST, 1807 .max_rings = 16, 1808 .entry_size = 8 >> 2, 1809 /*TODO: entry_size above should actually be 1810 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1811 * of struct ce_dst_desc in HW header files 1812 */ 1813 .lmac_ring = FALSE, 1814 .ring_dir = HAL_SRNG_SRC_RING, 1815 .reg_start = { 1816 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1817 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 1818 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1819 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 1820 }, 1821 .reg_size = { 1822 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 1823 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 1824 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 1825 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 1826 }, 1827 .max_size = 1828 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1829 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1830 }, 1831 { /* CE_DST_STATUS */ 1832 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1833 .max_rings = 16, 1834 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1835 .lmac_ring = FALSE, 1836 .ring_dir = HAL_SRNG_DST_RING, 1837 .reg_start = { 1838 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1839 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 1840 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1841 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 1842 }, 1843 /* TODO: check destination status ring registers */ 1844 .reg_size = { 1845 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 1846 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 1847 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 1848 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 1849 }, 1850 .max_size = 1851 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1852 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1853 }, 1854 { /* WBM_IDLE_LINK */ 1855 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1856 .max_rings = 1, 1857 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1858 .lmac_ring = FALSE, 1859 .ring_dir = HAL_SRNG_SRC_RING, 1860 .reg_start = { 1861 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 1862 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE), 1863 }, 1864 /* Single ring - provide ring size if multiple rings of this 1865 * type are supported 1866 */ 1867 .reg_size = {}, 1868 .max_size = 1869 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1870 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1871 }, 1872 { /* SW2WBM_RELEASE */ 1873 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1874 .max_rings = 1, 1875 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1876 .lmac_ring = FALSE, 1877 .ring_dir = HAL_SRNG_SRC_RING, 1878 .reg_start = { 1879 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 1880 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 1881 }, 1882 /* Single ring - provide ring size if multiple rings of this 1883 * type are supported 1884 */ 1885 .reg_size = {}, 1886 .max_size = 1887 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1888 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1889 }, 1890 { /* WBM2SW_RELEASE */ 1891 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1892 .max_rings = 8, 1893 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1894 .lmac_ring = FALSE, 1895 .ring_dir = HAL_SRNG_DST_RING, 1896 .reg_start = { 1897 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR( 1898 WBM_REG_REG_BASE), 1899 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR( 1900 WBM_REG_REG_BASE), 1901 }, 1902 .reg_size = { 1903 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR( 1904 WBM_REG_REG_BASE) - 1905 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR( 1906 WBM_REG_REG_BASE), 1907 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR( 1908 WBM_REG_REG_BASE) - 1909 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR( 1910 WBM_REG_REG_BASE), 1911 }, 1912 .max_size = 1913 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1914 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1915 }, 1916 { /* RXDMA_BUF */ 1917 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1918 #ifdef IPA_OFFLOAD 1919 .max_rings = 3, 1920 #else 1921 .max_rings = 3, 1922 #endif 1923 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1924 .lmac_ring = TRUE, 1925 .ring_dir = HAL_SRNG_SRC_RING, 1926 /* reg_start is not set because LMAC rings are not accessed 1927 * from host 1928 */ 1929 .reg_start = {}, 1930 .reg_size = {}, 1931 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1932 }, 1933 { /* RXDMA_DST */ 1934 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1935 .max_rings = 0, 1936 .entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/, 1937 .lmac_ring = TRUE, 1938 .ring_dir = HAL_SRNG_DST_RING, 1939 /* reg_start is not set because LMAC rings are not accessed 1940 * from host 1941 */ 1942 .reg_start = {}, 1943 .reg_size = {}, 1944 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1945 }, 1946 #ifdef QCA_MONITOR_2_0_SUPPORT 1947 { /* RXDMA_MONITOR_BUF */ 1948 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1949 .max_rings = 1, 1950 .entry_size = sizeof(struct mon_ingress_ring) >> 2, 1951 .lmac_ring = TRUE, 1952 .ring_dir = HAL_SRNG_SRC_RING, 1953 /* reg_start is not set because LMAC rings are not accessed 1954 * from host 1955 */ 1956 .reg_start = {}, 1957 .reg_size = {}, 1958 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 1959 }, 1960 #else 1961 {}, 1962 #endif 1963 { /* RXDMA_MONITOR_STATUS */ 1964 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1965 .max_rings = 0, 1966 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1967 .lmac_ring = TRUE, 1968 .ring_dir = HAL_SRNG_SRC_RING, 1969 /* reg_start is not set because LMAC rings are not accessed 1970 * from host 1971 */ 1972 .reg_start = {}, 1973 .reg_size = {}, 1974 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1975 }, 1976 #ifdef QCA_MONITOR_2_0_SUPPORT 1977 { /* RXDMA_MONITOR_DST */ 1978 .start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0, 1979 .max_rings = 2, 1980 .entry_size = sizeof(struct mon_destination_ring) >> 2, 1981 .lmac_ring = TRUE, 1982 .ring_dir = HAL_SRNG_DST_RING, 1983 /* reg_start is not set because LMAC rings are not accessed 1984 * from host 1985 */ 1986 .reg_start = {}, 1987 .reg_size = {}, 1988 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 1989 }, 1990 #else 1991 {}, 1992 #endif 1993 { /* RXDMA_MONITOR_DESC */ 1994 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1995 .max_rings = 0, 1996 .entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/, 1997 .lmac_ring = TRUE, 1998 .ring_dir = HAL_SRNG_DST_RING, 1999 /* reg_start is not set because LMAC rings are not accessed 2000 * from host 2001 */ 2002 .reg_start = {}, 2003 .reg_size = {}, 2004 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2005 }, 2006 2007 { /* DIR_BUF_RX_DMA_SRC */ 2008 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2009 /* one ring for spectral and one ring for cfr */ 2010 .max_rings = 2, 2011 .entry_size = 2, 2012 .lmac_ring = TRUE, 2013 .ring_dir = HAL_SRNG_SRC_RING, 2014 /* reg_start is not set because LMAC rings are not accessed 2015 * from host 2016 */ 2017 .reg_start = {}, 2018 .reg_size = {}, 2019 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2020 }, 2021 #ifdef WLAN_FEATURE_CIF_CFR 2022 { /* WIFI_POS_SRC */ 2023 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2024 .max_rings = 1, 2025 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2026 .lmac_ring = TRUE, 2027 .ring_dir = HAL_SRNG_SRC_RING, 2028 /* reg_start is not set because LMAC rings are not accessed 2029 * from host 2030 */ 2031 .reg_start = {}, 2032 .reg_size = {}, 2033 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2034 }, 2035 #endif 2036 /* PPE rings are not present in Miami. Added dummy entries to preserve 2037 * Array Index 2038 */ 2039 /* REO2PPE */ 2040 {}, 2041 /* PPE2TCL */ 2042 {}, 2043 /* PPE_RELEASE */ 2044 {}, 2045 #ifdef QCA_MONITOR_2_0_SUPPORT 2046 { /* TX_MONITOR_BUF */ 2047 .start_ring_id = HAL_SRNG_SW2TXMON_BUF0, 2048 .max_rings = 1, 2049 .entry_size = sizeof(struct mon_ingress_ring) >> 2, 2050 .lmac_ring = TRUE, 2051 .ring_dir = HAL_SRNG_SRC_RING, 2052 /* reg_start is not set because LMAC rings are not accessed 2053 * from host 2054 */ 2055 .reg_start = {}, 2056 .reg_size = {}, 2057 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2058 }, 2059 { /* TX_MONITOR_DST */ 2060 .start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0, 2061 .max_rings = 2, 2062 .entry_size = sizeof(struct mon_destination_ring) >> 2, 2063 .lmac_ring = TRUE, 2064 .ring_dir = HAL_SRNG_DST_RING, 2065 /* reg_start is not set because LMAC rings are not accessed 2066 * from host 2067 */ 2068 .reg_start = {}, 2069 .reg_size = {}, 2070 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2071 }, 2072 #else 2073 {}, 2074 {}, 2075 #endif 2076 { /* SW2RXDMA */ 2077 .start_ring_id = HAL_SRNG_SW2RXDMA_BUF0, 2078 .max_rings = 3, 2079 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2080 .lmac_ring = TRUE, 2081 .ring_dir = HAL_SRNG_SRC_RING, 2082 /* reg_start is not set because LMAC rings are not accessed 2083 * from host 2084 */ 2085 .reg_start = {}, 2086 .reg_size = {}, 2087 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2088 .dmac_cmn_ring = TRUE, 2089 }, 2090 }; 2091 2092 /** 2093 * hal_srng_hw_reg_offset_init_qca5332() - Initialize the HW srng reg offset 2094 * applicable only for qca5332 2095 * @hal_soc: HAL Soc handle 2096 * 2097 * Return: None 2098 */ 2099 static inline void hal_srng_hw_reg_offset_init_qca5332(struct hal_soc *hal_soc) 2100 { 2101 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 2102 2103 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB), 2104 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB), 2105 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA), 2106 hw_reg_offset[DST_PRODUCER_INT2_SETUP] = 2107 REG_OFFSET(DST, PRODUCER_INT2_SETUP); 2108 } 2109 2110 /** 2111 * hal_qca5332_attach()- Attach 5332 target specific hal_soc ops, 2112 * offset and srng table 2113 * Return: void 2114 */ 2115 void hal_qca5332_attach(struct hal_soc *hal_soc) 2116 { 2117 hal_soc->hw_srng_table = hw_srng_table_5332; 2118 2119 hal_srng_hw_reg_offset_init_generic(hal_soc); 2120 hal_srng_hw_reg_offset_init_qca5332(hal_soc); 2121 2122 hal_hw_txrx_default_ops_attach_be(hal_soc); 2123 hal_hw_txrx_ops_attach_qca5332(hal_soc); 2124 hal_soc->dmac_cmn_src_rxbuf_ring = true; 2125 } 2126