1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE 16 */ 17 #include "qdf_types.h" 18 #include "qdf_util.h" 19 #include "qdf_mem.h" 20 #include "qdf_nbuf.h" 21 #include "qdf_module.h" 22 23 #include "target_type.h" 24 #include "wcss_version.h" 25 26 #include "hal_be_hw_headers.h" 27 #include "hal_internal.h" 28 #include "hal_api.h" 29 #include "hal_flow.h" 30 #include "rx_flow_search_entry.h" 31 #include "hal_rx_flow_info.h" 32 #include "hal_be_api.h" 33 #include "tcl_entrance_from_ppe_ring.h" 34 #include "sw_monitor_ring.h" 35 #include "wcss_seq_hwioreg_umac.h" 36 #include "wfss_ce_reg_seq_hwioreg.h" 37 #include <uniform_reo_status_header.h> 38 #include <wbm_release_ring_tx.h> 39 #include <phyrx_location.h> 40 #ifdef QCA_MONITOR_2_0_SUPPORT 41 #include <mon_ingress_ring.h> 42 #include <mon_destination_ring.h> 43 #endif 44 #include "rx_reo_queue_1k.h" 45 46 #include <hal_be_rx.h> 47 48 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 49 RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 50 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 51 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 52 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 53 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 54 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 55 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 56 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 57 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 58 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 59 STATUS_HEADER_REO_STATUS_NUMBER 60 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 61 STATUS_HEADER_TIMESTAMP 62 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 64 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 65 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 66 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 67 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 68 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 69 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 70 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 71 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 72 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 73 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 74 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 75 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 76 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 77 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 78 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 79 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 80 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 81 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 82 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 83 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 84 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 85 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 86 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 87 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 88 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 89 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 90 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 91 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 92 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 93 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 94 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 95 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 96 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 97 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 98 99 #include "hal_be_api_mon.h" 100 101 #define CMEM_REG_BASE 0x00100000 102 103 /* For Berryllium sw2rxdma ring size increased to 20 bits */ 104 #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF 105 106 #ifdef CONFIG_WORD_BASED_TLV 107 #ifndef BIG_ENDIAN_HOST 108 struct rx_msdu_end_compact_qca5332 { 109 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 110 sw_frame_group_id : 7, // [8:2] 111 reserved_0 : 7, // [15:9] 112 phy_ppdu_id : 16; // [31:16] 113 uint32_t ip_hdr_chksum : 16, // [15:0] 114 reported_mpdu_length : 14, // [29:16] 115 reserved_1a : 2; // [31:30] 116 uint32_t key_id_octet : 8, // [7:0] 117 cce_super_rule : 6, // [13:8] 118 cce_classify_not_done_truncate : 1, // [14:14] 119 cce_classify_not_done_cce_dis : 1, // [15:15] 120 cumulative_l3_checksum : 16; // [31:16] 121 uint32_t rule_indication_31_0 : 32; // [31:0] 122 uint32_t rule_indication_63_32 : 32; // [31:0] 123 uint32_t da_offset : 6, // [5:0] 124 sa_offset : 6, // [11:6] 125 da_offset_valid : 1, // [12:12] 126 sa_offset_valid : 1, // [13:13] 127 reserved_5a : 2, // [15:14] 128 l3_type : 16; // [31:16] 129 uint32_t ipv6_options_crc : 32; // [31:0] 130 uint32_t tcp_seq_number : 32; // [31:0] 131 uint32_t tcp_ack_number : 32; // [31:0] 132 uint32_t tcp_flag : 9, // [8:0] 133 lro_eligible : 1, // [9:9] 134 reserved_9a : 6, // [15:10] 135 window_size : 16; // [31:16] 136 uint32_t tcp_udp_chksum : 16, // [15:0] 137 sa_idx_timeout : 1, // [16:16] 138 da_idx_timeout : 1, // [17:17] 139 msdu_limit_error : 1, // [18:18] 140 flow_idx_timeout : 1, // [19:19] 141 flow_idx_invalid : 1, // [20:20] 142 wifi_parser_error : 1, // [21:21] 143 amsdu_parser_error : 1, // [22:22] 144 sa_is_valid : 1, // [23:23] 145 da_is_valid : 1, // [24:24] 146 da_is_mcbc : 1, // [25:25] 147 l3_header_padding : 2, // [27:26] 148 first_msdu : 1, // [28:28] 149 last_msdu : 1, // [29:29] 150 tcp_udp_chksum_fail_copy : 1, // [30:30] 151 ip_chksum_fail_copy : 1; // [31:31] 152 uint32_t sa_idx : 16, // [15:0] 153 da_idx_or_sw_peer_id : 16; // [31:16] 154 uint32_t msdu_drop : 1, // [0:0] 155 reo_destination_indication : 5, // [5:1] 156 flow_idx : 20, // [25:6] 157 use_ppe : 1, // [26:26] 158 reserved_12a : 5; // [31:27] 159 uint32_t fse_metadata : 32; // [31:0] 160 uint32_t cce_metadata : 16, // [15:0] 161 sa_sw_peer_id : 16; // [31:16] 162 uint32_t aggregation_count : 8, // [7:0] 163 flow_aggregation_continuation : 1, // [8:8] 164 fisa_timeout : 1, // [9:9] 165 reserved_15a : 22; // [31:10] 166 uint32_t cumulative_l4_checksum : 16, // [15:0] 167 cumulative_ip_length : 16; // [31:16] 168 uint32_t reserved_17a : 6, // [5:0] 169 service_code : 9, // [14:6] 170 priority_valid : 1, // [15:15] 171 intra_bss : 1, // [16:16] 172 dest_chip_id : 2, // [18:17] 173 multicast_echo : 1, // [19:19] 174 wds_learning_event : 1, // [20:20] 175 wds_roaming_event : 1, // [21:21] 176 wds_keep_alive_event : 1, // [22:22] 177 reserved_17b : 9; // [31:23] 178 uint32_t msdu_length : 14, // [13:0] 179 stbc : 1, // [14:14] 180 ipsec_esp : 1, // [15:15] 181 l3_offset : 7, // [22:16] 182 ipsec_ah : 1, // [23:23] 183 l4_offset : 8; // [31:24] 184 uint32_t msdu_number : 8, // [7:0] 185 decap_format : 2, // [9:8] 186 ipv4_proto : 1, // [10:10] 187 ipv6_proto : 1, // [11:11] 188 tcp_proto : 1, // [12:12] 189 udp_proto : 1, // [13:13] 190 ip_frag : 1, // [14:14] 191 tcp_only_ack : 1, // [15:15] 192 da_is_bcast_mcast : 1, // [16:16] 193 toeplitz_hash_sel : 2, // [18:17] 194 ip_fixed_header_valid : 1, // [19:19] 195 ip_extn_header_valid : 1, // [20:20] 196 tcp_udp_header_valid : 1, // [21:21] 197 mesh_control_present : 1, // [22:22] 198 ldpc : 1, // [23:23] 199 ip4_protocol_ip6_next_header : 8; // [31:24] 200 uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] 201 uint32_t flow_id_toeplitz : 32; // [31:0] 202 uint32_t user_rssi : 8, // [7:0] 203 pkt_type : 4, // [11:8] 204 sgi : 2, // [13:12] 205 rate_mcs : 4, // [17:14] 206 receive_bandwidth : 3, // [20:18] 207 reception_type : 3, // [23:21] 208 mimo_ss_bitmap : 8; // [31:24] 209 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 210 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 211 uint32_t sw_phy_meta_data : 32; // [31:0] 212 uint32_t vlan_ctag_ci : 16, // [15:0] 213 vlan_stag_ci : 16; // [31:16] 214 uint32_t reserved_27a : 32; // [31:0] 215 uint32_t reserved_28a : 32; // [31:0] 216 uint32_t reserved_29a : 32; // [31:0] 217 uint32_t first_mpdu : 1, // [0:0] 218 reserved_30a : 1, // [1:1] 219 mcast_bcast : 1, // [2:2] 220 ast_index_not_found : 1, // [3:3] 221 ast_index_timeout : 1, // [4:4] 222 power_mgmt : 1, // [5:5] 223 non_qos : 1, // [6:6] 224 null_data : 1, // [7:7] 225 mgmt_type : 1, // [8:8] 226 ctrl_type : 1, // [9:9] 227 more_data : 1, // [10:10] 228 eosp : 1, // [11:11] 229 a_msdu_error : 1, // [12:12] 230 fragment_flag : 1, // [13:13] 231 order : 1, // [14:14] 232 cce_match : 1, // [15:15] 233 overflow_err : 1, // [16:16] 234 msdu_length_err : 1, // [17:17] 235 tcp_udp_chksum_fail : 1, // [18:18] 236 ip_chksum_fail : 1, // [19:19] 237 sa_idx_invalid : 1, // [20:20] 238 da_idx_invalid : 1, // [21:21] 239 reserved_30b : 1, // [22:22] 240 rx_in_tx_decrypt_byp : 1, // [23:23] 241 encrypt_required : 1, // [24:24] 242 directed : 1, // [25:25] 243 buffer_fragment : 1, // [26:26] 244 mpdu_length_err : 1, // [27:27] 245 tkip_mic_err : 1, // [28:28] 246 decrypt_err : 1, // [29:29] 247 unencrypted_frame_err : 1, // [30:30] 248 fcs_err : 1; // [31:31] 249 uint32_t reserved_31a : 10, // [9:0] 250 decrypt_status_code : 3, // [12:10] 251 rx_bitmap_not_updated : 1, // [13:13] 252 reserved_31b : 17, // [30:14] 253 msdu_done : 1; // [31:31] 254 255 }; 256 257 struct rx_mpdu_start_compact_qca5332 { 258 struct rxpt_classify_info rxpt_classify_info_details; 259 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 260 uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] 261 receive_queue_number : 16, // [23:8] 262 pre_delim_err_warning : 1, // [24:24] 263 first_delim_err : 1, // [25:25] 264 reserved_2a : 6; // [31:26] 265 uint32_t pn_31_0 : 32; // [31:0] 266 uint32_t pn_63_32 : 32; // [31:0] 267 uint32_t pn_95_64 : 32; // [31:0] 268 uint32_t pn_127_96 : 32; // [31:0] 269 uint32_t epd_en : 1, // [0:0] 270 all_frames_shall_be_encrypted : 1, // [1:1] 271 encrypt_type : 4, // [5:2] 272 wep_key_width_for_variable_key : 2, // [7:6] 273 mesh_sta : 2, // [9:8] 274 bssid_hit : 1, // [10:10] 275 bssid_number : 4, // [14:11] 276 tid : 4, // [18:15] 277 reserved_7a : 13; // [31:19] 278 uint32_t peer_meta_data : 32; // [31:0] 279 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 280 sw_frame_group_id : 7, // [8:2] 281 ndp_frame : 1, // [9:9] 282 phy_err : 1, // [10:10] 283 phy_err_during_mpdu_header : 1, // [11:11] 284 protocol_version_err : 1, // [12:12] 285 ast_based_lookup_valid : 1, // [13:13] 286 ranging : 1, // [14:14] 287 reserved_9a : 1, // [15:15] 288 phy_ppdu_id : 16; // [31:16] 289 uint32_t ast_index : 16, // [15:0] 290 sw_peer_id : 16; // [31:16] 291 uint32_t mpdu_frame_control_valid : 1, // [0:0] 292 mpdu_duration_valid : 1, // [1:1] 293 mac_addr_ad1_valid : 1, // [2:2] 294 mac_addr_ad2_valid : 1, // [3:3] 295 mac_addr_ad3_valid : 1, // [4:4] 296 mac_addr_ad4_valid : 1, // [5:5] 297 mpdu_sequence_control_valid : 1, // [6:6] 298 mpdu_qos_control_valid : 1, // [7:7] 299 mpdu_ht_control_valid : 1, // [8:8] 300 frame_encryption_info_valid : 1, // [9:9] 301 mpdu_fragment_number : 4, // [13:10] 302 more_fragment_flag : 1, // [14:14] 303 reserved_11a : 1, // [15:15] 304 fr_ds : 1, // [16:16] 305 to_ds : 1, // [17:17] 306 encrypted : 1, // [18:18] 307 mpdu_retry : 1, // [19:19] 308 mpdu_sequence_number : 12; // [31:20] 309 uint32_t key_id_octet : 8, // [7:0] 310 new_peer_entry : 1, // [8:8] 311 decrypt_needed : 1, // [9:9] 312 decap_type : 2, // [11:10] 313 rx_insert_vlan_c_tag_padding : 1, // [12:12] 314 rx_insert_vlan_s_tag_padding : 1, // [13:13] 315 strip_vlan_c_tag_decap : 1, // [14:14] 316 strip_vlan_s_tag_decap : 1, // [15:15] 317 pre_delim_count : 12, // [27:16] 318 ampdu_flag : 1, // [28:28] 319 bar_frame : 1, // [29:29] 320 raw_mpdu : 1, // [30:30] 321 reserved_12 : 1; // [31:31] 322 uint32_t mpdu_length : 14, // [13:0] 323 first_mpdu : 1, // [14:14] 324 mcast_bcast : 1, // [15:15] 325 ast_index_not_found : 1, // [16:16] 326 ast_index_timeout : 1, // [17:17] 327 power_mgmt : 1, // [18:18] 328 non_qos : 1, // [19:19] 329 null_data : 1, // [20:20] 330 mgmt_type : 1, // [21:21] 331 ctrl_type : 1, // [22:22] 332 more_data : 1, // [23:23] 333 eosp : 1, // [24:24] 334 fragment_flag : 1, // [25:25] 335 order : 1, // [26:26] 336 u_apsd_trigger : 1, // [27:27] 337 encrypt_required : 1, // [28:28] 338 directed : 1, // [29:29] 339 amsdu_present : 1, // [30:30] 340 reserved_13 : 1; // [31:31] 341 uint32_t mpdu_frame_control_field : 16, // [15:0] 342 mpdu_duration_field : 16; // [31:16] 343 uint32_t mac_addr_ad1_31_0 : 32; // [31:0] 344 uint32_t mac_addr_ad1_47_32 : 16, // [15:0] 345 mac_addr_ad2_15_0 : 16; // [31:16] 346 uint32_t mac_addr_ad2_47_16 : 32; // [31:0] 347 uint32_t mac_addr_ad3_31_0 : 32; // [31:0] 348 uint32_t mac_addr_ad3_47_32 : 16, // [15:0] 349 mpdu_sequence_control_field : 16; // [31:16] 350 uint32_t mac_addr_ad4_31_0 : 32; // [31:0] 351 uint32_t mac_addr_ad4_47_32 : 16, // [15:0] 352 mpdu_qos_control_field : 16; // [31:16] 353 uint32_t mpdu_ht_control_field : 32; // [31:0] 354 uint32_t vdev_id : 8, // [7:0] 355 service_code : 9, // [16:8] 356 priority_valid : 1, // [17:17] 357 src_info : 12, // [29:18] 358 reserved_23a : 1, // [30:30] 359 multi_link_addr_ad1_ad2_valid : 1; // [31:31] 360 uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] 361 uint32_t multi_link_addr_ad1_47_32 : 16, // [15:0] 362 multi_link_addr_ad2_15_0 : 16; // [31:16] 363 uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] 364 uint32_t reserved_27a : 32; // [31:0] 365 uint32_t reserved_28a : 32; // [31:0] 366 uint32_t reserved_29a : 32; // [31:0] 367 }; 368 #else 369 struct rx_msdu_end_compact_qca5332 { 370 uint32_t phy_ppdu_id : 16, // [31:16] 371 reserved_0 : 7, // [15:9] 372 sw_frame_group_id : 7, // [8:2] 373 rxpcu_mpdu_filter_in_category : 2; // [1:0] 374 uint32_t reserved_1a : 2, // [31:30] 375 reported_mpdu_length : 14, // [29:16] 376 ip_hdr_chksum : 16; // [15:0] 377 uint32_t cumulative_l3_checksum : 16, // [31:16] 378 cce_classify_not_done_cce_dis : 1, // [15:15] 379 cce_classify_not_done_truncate : 1, // [14:14] 380 cce_super_rule : 6, // [13:8] 381 key_id_octet : 8; // [7:0] 382 uint32_t rule_indication_31_0 : 32; // [31:0] 383 uint32_t rule_indication_63_32 : 32; // [31:0] 384 uint32_t l3_type : 16, // [31:16] 385 reserved_5a : 2, // [15:14] 386 sa_offset_valid : 1, // [13:13] 387 da_offset_valid : 1, // [12:12] 388 sa_offset : 6, // [11:6] 389 da_offset : 6; // [5:0] 390 uint32_t ipv6_options_crc : 32; // [31:0] 391 uint32_t tcp_seq_number : 32; // [31:0] 392 uint32_t tcp_ack_number : 32; // [31:0] 393 uint32_t window_size : 16, // [31:16] 394 reserved_9a : 6, // [15:10] 395 lro_eligible : 1, // [9:9] 396 tcp_flag : 9; // [8:0] 397 uint32_t ip_chksum_fail_copy : 1, // [31:31] 398 tcp_udp_chksum_fail_copy : 1, // [30:30] 399 last_msdu : 1, // [29:29] 400 first_msdu : 1, // [28:28] 401 l3_header_padding : 2, // [27:26] 402 da_is_mcbc : 1, // [25:25] 403 da_is_valid : 1, // [24:24] 404 sa_is_valid : 1, // [23:23] 405 amsdu_parser_error : 1, // [22:22] 406 wifi_parser_error : 1, // [21:21] 407 flow_idx_invalid : 1, // [20:20] 408 flow_idx_timeout : 1, // [19:19] 409 msdu_limit_error : 1, // [18:18] 410 da_idx_timeout : 1, // [17:17] 411 sa_idx_timeout : 1, // [16:16] 412 tcp_udp_chksum : 16; // [15:0] 413 uint32_t da_idx_or_sw_peer_id : 16, // [31:16] 414 sa_idx : 16; // [15:0] 415 uint32_t reserved_12a : 5, // [31:27] 416 use_ppe : 1, // [26:26] 417 flow_idx : 20, // [25:6] 418 reo_destination_indication : 5, // [5:1] 419 msdu_drop : 1; // [0:0] 420 uint32_t fse_metadata : 32; // [31:0] 421 uint32_t sa_sw_peer_id : 16, // [31:16] 422 cce_metadata : 16; // [15:0] 423 uint32_t reserved_15a : 22, // [31:10] 424 fisa_timeout : 1, // [9:9] 425 flow_aggregation_continuation : 1, // [8:8] 426 aggregation_count : 8; // [7:0] 427 uint32_t cumulative_ip_length : 16, // [31:16] 428 cumulative_l4_checksum : 16; // [15:0] 429 uint32_t reserved_17b : 9, // [31:23] 430 wds_keep_alive_event : 1, // [22:22] 431 wds_roaming_event : 1, // [21:21] 432 wds_learning_event : 1, // [20:20] 433 multicast_echo : 1, // [19:19] 434 dest_chip_id : 2, // [18:17] 435 intra_bss : 1, // [16:16] 436 priority_valid : 1, // [15:15] 437 service_code : 9, // [14:6] 438 reserved_17a : 6; // [5:0] 439 uint32_t l4_offset : 8, // [31:24] 440 ipsec_ah : 1, // [23:23] 441 l3_offset : 7, // [22:16] 442 ipsec_esp : 1, // [15:15] 443 stbc : 1, // [14:14] 444 msdu_length : 14; // [13:0] 445 uint32_t ip4_protocol_ip6_next_header : 8, // [31:24] 446 ldpc : 1, // [23:23] 447 mesh_control_present : 1, // [22:22] 448 tcp_udp_header_valid : 1, // [21:21] 449 ip_extn_header_valid : 1, // [20:20] 450 ip_fixed_header_valid : 1, // [19:19] 451 toeplitz_hash_sel : 2, // [18:17] 452 da_is_bcast_mcast : 1, // [16:16] 453 tcp_only_ack : 1, // [15:15] 454 ip_frag : 1, // [14:14] 455 udp_proto : 1, // [13:13] 456 tcp_proto : 1, // [12:12] 457 ipv6_proto : 1, // [11:11] 458 ipv4_proto : 1, // [10:10] 459 decap_format : 2, // [9:8] 460 msdu_number : 8; // [7:0] 461 uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] 462 uint32_t flow_id_toeplitz : 32; // [31:0] 463 uint32_t mimo_ss_bitmap : 8, // [31:24] 464 reception_type : 3, // [23:21] 465 receive_bandwidth : 3, // [20:18] 466 rate_mcs : 4, // [17:14] 467 sgi : 2, // [13:12] 468 pkt_type : 4, // [11:8] 469 user_rssi : 8; // [7:0] 470 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 471 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 472 uint32_t sw_phy_meta_data : 32; // [31:0] 473 uint32_t vlan_stag_ci : 16, // [31:16] 474 vlan_ctag_ci : 16; // [15:0] 475 uint32_t reserved_27a : 32; // [31:0] 476 uint32_t reserved_28a : 32; // [31:0] 477 uint32_t reserved_29a : 32; // [31:0] 478 uint32_t fcs_err : 1, // [31:31] 479 unencrypted_frame_err : 1, // [30:30] 480 decrypt_err : 1, // [29:29] 481 tkip_mic_err : 1, // [28:28] 482 mpdu_length_err : 1, // [27:27] 483 buffer_fragment : 1, // [26:26] 484 directed : 1, // [25:25] 485 encrypt_required : 1, // [24:24] 486 rx_in_tx_decrypt_byp : 1, // [23:23] 487 reserved_30b : 1, // [22:22] 488 da_idx_invalid : 1, // [21:21] 489 sa_idx_invalid : 1, // [20:20] 490 ip_chksum_fail : 1, // [19:19] 491 tcp_udp_chksum_fail : 1, // [18:18] 492 msdu_length_err : 1, // [17:17] 493 overflow_err : 1, // [16:16] 494 cce_match : 1, // [15:15] 495 order : 1, // [14:14] 496 fragment_flag : 1, // [13:13] 497 a_msdu_error : 1, // [12:12] 498 eosp : 1, // [11:11] 499 more_data : 1, // [10:10] 500 ctrl_type : 1, // [9:9] 501 mgmt_type : 1, // [8:8] 502 null_data : 1, // [7:7] 503 non_qos : 1, // [6:6] 504 power_mgmt : 1, // [5:5] 505 ast_index_timeout : 1, // [4:4] 506 ast_index_not_found : 1, // [3:3] 507 mcast_bcast : 1, // [2:2] 508 reserved_30a : 1, // [1:1] 509 first_mpdu : 1; // [0:0] 510 uint32_t msdu_done : 1, // [31:31] 511 reserved_31b : 17, // [30:14] 512 rx_bitmap_not_updated : 1, // [13:13] 513 decrypt_status_code : 3, // [12:10] 514 reserved_31a : 10; // [9:0] 515 }; 516 517 struct rx_mpdu_start_compact_qca5332 { 518 struct rxpt_classify_info rxpt_classify_info_details; 519 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 520 uint32_t reserved_2a : 6, // [31:26] 521 first_delim_err : 1, // [25:25] 522 pre_delim_err_warning : 1, // [24:24] 523 receive_queue_number : 16, // [23:8] 524 rx_reo_queue_desc_addr_39_32 : 8; // [7:0] 525 uint32_t pn_31_0 : 32; // [31:0] 526 uint32_t pn_63_32 : 32; // [31:0] 527 uint32_t pn_95_64 : 32; // [31:0] 528 uint32_t pn_127_96 : 32; // [31:0] 529 uint32_t reserved_7a : 13, // [31:19] 530 tid : 4, // [18:15] 531 bssid_number : 4, // [14:11] 532 bssid_hit : 1, // [10:10] 533 mesh_sta : 2, // [9:8] 534 wep_key_width_for_variable_key : 2, // [7:6] 535 encrypt_type : 4, // [5:2] 536 all_frames_shall_be_encrypted : 1, // [1:1] 537 epd_en : 1; // [0:0] 538 uint32_t peer_meta_data : 32; // [31:0] 539 uint32_t phy_ppdu_id : 16, // [31:16] 540 reserved_9a : 1, // [15:15] 541 ranging : 1, // [14:14] 542 ast_based_lookup_valid : 1, // [13:13] 543 protocol_version_err : 1, // [12:12] 544 phy_err_during_mpdu_header : 1, // [11:11] 545 phy_err : 1, // [10:10] 546 ndp_frame : 1, // [9:9] 547 sw_frame_group_id : 7, // [8:2] 548 rxpcu_mpdu_filter_in_category : 2; // [1:0] 549 uint32_t sw_peer_id : 16, // [31:16] 550 ast_index : 16; // [15:0] 551 uint32_t mpdu_sequence_number : 12, // [31:20] 552 mpdu_retry : 1, // [19:19] 553 encrypted : 1, // [18:18] 554 to_ds : 1, // [17:17] 555 fr_ds : 1, // [16:16] 556 reserved_11a : 1, // [15:15] 557 more_fragment_flag : 1, // [14:14] 558 mpdu_fragment_number : 4, // [13:10] 559 frame_encryption_info_valid : 1, // [9:9] 560 mpdu_ht_control_valid : 1, // [8:8] 561 mpdu_qos_control_valid : 1, // [7:7] 562 mpdu_sequence_control_valid : 1, // [6:6] 563 mac_addr_ad4_valid : 1, // [5:5] 564 mac_addr_ad3_valid : 1, // [4:4] 565 mac_addr_ad2_valid : 1, // [3:3] 566 mac_addr_ad1_valid : 1, // [2:2] 567 mpdu_duration_valid : 1, // [1:1] 568 mpdu_frame_control_valid : 1; // [0:0] 569 uint32_t reserved_12 : 1, // [31:31] 570 raw_mpdu : 1, // [30:30] 571 bar_frame : 1, // [29:29] 572 ampdu_flag : 1, // [28:28] 573 pre_delim_count : 12, // [27:16] 574 strip_vlan_s_tag_decap : 1, // [15:15] 575 strip_vlan_c_tag_decap : 1, // [14:14] 576 rx_insert_vlan_s_tag_padding : 1, // [13:13] 577 rx_insert_vlan_c_tag_padding : 1, // [12:12] 578 decap_type : 2, // [11:10] 579 decrypt_needed : 1, // [9:9] 580 new_peer_entry : 1, // [8:8] 581 key_id_octet : 8; // [7:0] 582 uint32_t reserved_13 : 1, // [31:31] 583 amsdu_present : 1, // [30:30] 584 directed : 1, // [29:29] 585 encrypt_required : 1, // [28:28] 586 u_apsd_trigger : 1, // [27:27] 587 order : 1, // [26:26] 588 fragment_flag : 1, // [25:25] 589 eosp : 1, // [24:24] 590 more_data : 1, // [23:23] 591 ctrl_type : 1, // [22:22] 592 mgmt_type : 1, // [21:21] 593 null_data : 1, // [20:20] 594 non_qos : 1, // [19:19] 595 power_mgmt : 1, // [18:18] 596 ast_index_timeout : 1, // [17:17] 597 ast_index_not_found : 1, // [16:16] 598 mcast_bcast : 1, // [15:15] 599 first_mpdu : 1, // [14:14] 600 mpdu_length : 14; // [13:0] 601 uint32_t mpdu_duration_field : 16, // [31:16] 602 mpdu_frame_control_field : 16; // [15:0] 603 uint32_t mac_addr_ad1_31_0 : 32; // [31:0] 604 uint32_t mac_addr_ad2_15_0 : 16, // [31:16] 605 mac_addr_ad1_47_32 : 16; // [15:0] 606 uint32_t mac_addr_ad2_47_16 : 32; // [31:0] 607 uint32_t mac_addr_ad3_31_0 : 32; // [31:0] 608 uint32_t mpdu_sequence_control_field : 16, // [31:16] 609 mac_addr_ad3_47_32 : 16; // [15:0] 610 uint32_t mac_addr_ad4_31_0 : 32; // [31:0] 611 uint32_t mpdu_qos_control_field : 16, // [31:16] 612 mac_addr_ad4_47_32 : 16; // [15:0] 613 uint32_t mpdu_ht_control_field : 32; // [31:0] 614 uint32_t multi_link_addr_ad1_ad2_valid : 1, // [31:31] 615 reserved_23a : 1, // [30:30] 616 src_info : 12, // [29:18] 617 priority_valid : 1, // [17:17] 618 service_code : 9, // [16:8] 619 vdev_id : 8; // [7:0] 620 uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] 621 uint32_t multi_link_addr_ad2_15_0 : 16, // [31:16] 622 multi_link_addr_ad1_47_32 : 16; // [15:0] 623 uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] 624 uint32_t reserved_27a : 32; // [31:0] 625 uint32_t reserved_28a : 32; // [31:0] 626 uint32_t reserved_29a : 32; // [31:0] 627 }; 628 #endif /* BIG_ENDIAN_HOST */ 629 630 /* TLV struct for word based Tlv */ 631 typedef struct rx_mpdu_start_compact_qca5332 hal_rx_mpdu_start_t; 632 typedef struct rx_msdu_end_compact_qca5332 hal_rx_msdu_end_t; 633 #endif /* CONFIG_WORD_BASED_TLV */ 634 635 #include "hal_5332_rx.h" 636 #include "hal_5332_tx.h" 637 #include "hal_be_rx_tlv.h" 638 #include <hal_be_generic_api.h> 639 640 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 641 #define HAL_PPE_VP_ENTRIES_MAX 32 642 /** 643 * hal_get_link_desc_size_5332(): API to get the link desc size 644 * 645 * Return: uint32_t 646 */ 647 static uint32_t hal_get_link_desc_size_5332(void) 648 { 649 return LINK_DESC_SIZE; 650 } 651 652 /** 653 * hal_rx_get_tlv_5332(): API to get the tlv 654 * 655 * @rx_tlv: TLV data extracted from the rx packet 656 * Return: uint8_t 657 */ 658 static uint8_t hal_rx_get_tlv_5332(void *rx_tlv) 659 { 660 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH); 661 } 662 663 /** 664 * hal_rx_wbm_err_msdu_continuation_get_5332 () - API to check if WBM 665 * msdu continuation bit is set 666 * 667 *@wbm_desc: wbm release ring descriptor 668 * 669 * Return: true if msdu continuation bit is set. 670 */ 671 uint8_t hal_rx_wbm_err_msdu_continuation_get_5332(void *wbm_desc) 672 { 673 uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) + 674 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET); 675 676 return (comp_desc & 677 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >> 678 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB; 679 } 680 681 /** 682 * hal_rx_proc_phyrx_other_receive_info_tlv_5332(): API to get tlv info 683 * 684 * Return: uint32_t 685 */ 686 static inline 687 void hal_rx_proc_phyrx_other_receive_info_tlv_5332(void *rx_tlv_hdr, 688 void *ppdu_info_hdl) 689 { 690 uint32_t tlv_tag, tlv_len; 691 uint32_t temp_len, other_tlv_len, other_tlv_tag; 692 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 693 void *other_tlv_hdr = NULL; 694 void *other_tlv = NULL; 695 696 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 697 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 698 temp_len = 0; 699 700 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 701 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 702 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 703 704 temp_len += other_tlv_len; 705 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 706 707 switch (other_tlv_tag) { 708 default: 709 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 710 "%s unhandled TLV type: %d, TLV len:%d", 711 __func__, other_tlv_tag, other_tlv_len); 712 break; 713 } 714 } 715 716 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 717 static inline 718 void hal_rx_get_bb_info_5332(void *rx_tlv, void *ppdu_info_hdl) 719 { 720 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 721 722 ppdu_info->cfr_info.bb_captured_channel = 723 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL); 724 725 ppdu_info->cfr_info.bb_captured_timeout = 726 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT); 727 728 ppdu_info->cfr_info.bb_captured_reason = 729 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON); 730 } 731 732 static inline 733 void hal_rx_get_rtt_info_5332(void *rx_tlv, void *ppdu_info_hdl) 734 { 735 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 736 737 ppdu_info->cfr_info.rx_location_info_valid = 738 HAL_RX_GET(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 739 RX_LOCATION_INFO_VALID); 740 741 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 742 HAL_RX_GET(rx_tlv, 743 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 744 RTT_CHE_BUFFER_POINTER_LOW32); 745 746 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 747 HAL_RX_GET(rx_tlv, 748 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 749 RTT_CHE_BUFFER_POINTER_HIGH8); 750 751 ppdu_info->cfr_info.chan_capture_status = 752 HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv); 753 754 ppdu_info->cfr_info.rx_start_ts = 755 HAL_RX_GET(rx_tlv, 756 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 757 RX_START_TS); 758 759 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) 760 HAL_RX_GET(rx_tlv, 761 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 762 RTT_CFO_MEASUREMENT); 763 764 ppdu_info->cfr_info.agc_gain_info0 = 765 HAL_RX_GET(rx_tlv, 766 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 767 GAIN_CHAIN0); 768 769 ppdu_info->cfr_info.agc_gain_info0 |= 770 (((uint32_t)HAL_RX_GET(rx_tlv, 771 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 772 GAIN_CHAIN1)) << 16); 773 774 ppdu_info->cfr_info.agc_gain_info1 = 775 HAL_RX_GET(rx_tlv, 776 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 777 GAIN_CHAIN2); 778 779 ppdu_info->cfr_info.agc_gain_info1 |= 780 (((uint32_t)HAL_RX_GET(rx_tlv, 781 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 782 GAIN_CHAIN3)) << 16); 783 784 ppdu_info->cfr_info.agc_gain_info2 = 0; 785 786 ppdu_info->cfr_info.agc_gain_info3 = 0; 787 } 788 #endif 789 790 /** 791 * hal_rx_dump_mpdu_start_tlv_5332: dump RX mpdu_start TLV in structured 792 * human readable format. 793 * @mpdu_start: pointer the rx_attention TLV in pkt. 794 * @dbg_level: log level. 795 * 796 * Return: void 797 */ 798 static inline void hal_rx_dump_mpdu_start_tlv_5332(void *mpdustart, 799 uint8_t dbg_level) 800 { 801 #ifdef CONFIG_WORD_BASED_TLV 802 struct rx_mpdu_start_compact_qca5332 *mpdu_info = 803 (struct rx_mpdu_start_compact_qca5332 *)mpdustart; 804 #else 805 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 806 struct rx_mpdu_info *mpdu_info = 807 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 808 #endif 809 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 810 "rx_mpdu_start tlv (1/5) - " 811 "rx_reo_queue_desc_addr_31_0 :%x" 812 "rx_reo_queue_desc_addr_39_32 :%x" 813 "receive_queue_number:%x " 814 "pre_delim_err_warning:%x " 815 "first_delim_err:%x " 816 "reserved_2a:%x " 817 "pn_31_0:%x " 818 "pn_63_32:%x " 819 "pn_95_64:%x " 820 "pn_127_96:%x " 821 "epd_en:%x " 822 "all_frames_shall_be_encrypted :%x" 823 "encrypt_type:%x " 824 "wep_key_width_for_variable_key :%x" 825 "mesh_sta:%x " 826 "bssid_hit:%x " 827 "bssid_number:%x " 828 "tid:%x " 829 "reserved_7a:%x ", 830 mpdu_info->rx_reo_queue_desc_addr_31_0, 831 mpdu_info->rx_reo_queue_desc_addr_39_32, 832 mpdu_info->receive_queue_number, 833 mpdu_info->pre_delim_err_warning, 834 mpdu_info->first_delim_err, 835 mpdu_info->reserved_2a, 836 mpdu_info->pn_31_0, 837 mpdu_info->pn_63_32, 838 mpdu_info->pn_95_64, 839 mpdu_info->pn_127_96, 840 mpdu_info->epd_en, 841 mpdu_info->all_frames_shall_be_encrypted, 842 mpdu_info->encrypt_type, 843 mpdu_info->wep_key_width_for_variable_key, 844 mpdu_info->mesh_sta, 845 mpdu_info->bssid_hit, 846 mpdu_info->bssid_number, 847 mpdu_info->tid, 848 mpdu_info->reserved_7a); 849 850 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 851 "rx_mpdu_start tlv (2/5) - " 852 "ast_index:%x " 853 "sw_peer_id:%x " 854 "mpdu_frame_control_valid:%x " 855 "mpdu_duration_valid:%x " 856 "mac_addr_ad1_valid:%x " 857 "mac_addr_ad2_valid:%x " 858 "mac_addr_ad3_valid:%x " 859 "mac_addr_ad4_valid:%x " 860 "mpdu_sequence_control_valid :%x" 861 "mpdu_qos_control_valid:%x " 862 "mpdu_ht_control_valid:%x " 863 "frame_encryption_info_valid :%x", 864 mpdu_info->ast_index, 865 mpdu_info->sw_peer_id, 866 mpdu_info->mpdu_frame_control_valid, 867 mpdu_info->mpdu_duration_valid, 868 mpdu_info->mac_addr_ad1_valid, 869 mpdu_info->mac_addr_ad2_valid, 870 mpdu_info->mac_addr_ad3_valid, 871 mpdu_info->mac_addr_ad4_valid, 872 mpdu_info->mpdu_sequence_control_valid, 873 mpdu_info->mpdu_qos_control_valid, 874 mpdu_info->mpdu_ht_control_valid, 875 mpdu_info->frame_encryption_info_valid); 876 877 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 878 "rx_mpdu_start tlv (3/5) - " 879 "mpdu_fragment_number:%x " 880 "more_fragment_flag:%x " 881 "reserved_11a:%x " 882 "fr_ds:%x " 883 "to_ds:%x " 884 "encrypted:%x " 885 "mpdu_retry:%x " 886 "mpdu_sequence_number:%x ", 887 mpdu_info->mpdu_fragment_number, 888 mpdu_info->more_fragment_flag, 889 mpdu_info->reserved_11a, 890 mpdu_info->fr_ds, 891 mpdu_info->to_ds, 892 mpdu_info->encrypted, 893 mpdu_info->mpdu_retry, 894 mpdu_info->mpdu_sequence_number); 895 896 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 897 "rx_mpdu_start tlv (4/5) - " 898 "mpdu_frame_control_field:%x " 899 "mpdu_duration_field:%x ", 900 mpdu_info->mpdu_frame_control_field, 901 mpdu_info->mpdu_duration_field); 902 903 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 904 "rx_mpdu_start tlv (5/5) - " 905 "mac_addr_ad1_31_0:%x " 906 "mac_addr_ad1_47_32:%x " 907 "mac_addr_ad2_15_0:%x " 908 "mac_addr_ad2_47_16:%x " 909 "mac_addr_ad3_31_0:%x " 910 "mac_addr_ad3_47_32:%x " 911 "mpdu_sequence_control_field :%x" 912 "mac_addr_ad4_31_0:%x " 913 "mac_addr_ad4_47_32:%x " 914 "mpdu_qos_control_field:%x ", 915 mpdu_info->mac_addr_ad1_31_0, 916 mpdu_info->mac_addr_ad1_47_32, 917 mpdu_info->mac_addr_ad2_15_0, 918 mpdu_info->mac_addr_ad2_47_16, 919 mpdu_info->mac_addr_ad3_31_0, 920 mpdu_info->mac_addr_ad3_47_32, 921 mpdu_info->mpdu_sequence_control_field, 922 mpdu_info->mac_addr_ad4_31_0, 923 mpdu_info->mac_addr_ad4_47_32, 924 mpdu_info->mpdu_qos_control_field); 925 } 926 927 /** 928 * hal_rx_dump_msdu_end_tlv_5332: dump RX msdu_end TLV in structured 929 * human readable format. 930 * @ msdu_end: pointer the msdu_end TLV in pkt. 931 * @ dbg_level: log level. 932 * 933 * Return: void 934 */ 935 static void hal_rx_dump_msdu_end_tlv_5332(void *msduend, 936 uint8_t dbg_level) 937 { 938 #ifdef CONFIG_WORD_BASED_TLV 939 struct rx_msdu_end_compact_qca5332 *msdu_end = 940 (struct rx_msdu_end_compact_qca5332 *)msduend; 941 #else 942 struct rx_msdu_end *msdu_end = 943 (struct rx_msdu_end *)msduend; 944 #endif 945 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 946 "rx_msdu_end tlv - " 947 "key_id_octet: %d " 948 "cce_super_rule: %d " 949 "cce_classify_not_done_truncat: %d " 950 "cce_classify_not_done_cce_dis: %d " 951 "rule_indication_31_0: %d " 952 "tcp_udp_chksum: %d " 953 "sa_idx_timeout: %d " 954 "da_idx_timeout: %d " 955 "msdu_limit_error: %d " 956 "flow_idx_timeout: %d " 957 "flow_idx_invalid: %d " 958 "wifi_parser_error: %d " 959 "sa_is_valid: %d " 960 "da_is_valid: %d " 961 "da_is_mcbc: %d " 962 "tkip_mic_err: %d " 963 "l3_header_padding: %d " 964 "first_msdu: %d " 965 "last_msdu: %d " 966 "sa_idx: %d " 967 "msdu_drop: %d " 968 "reo_destination_indication: %d " 969 "flow_idx: %d " 970 "fse_metadata: %d " 971 "cce_metadata: %d " 972 "sa_sw_peer_id: %d ", 973 msdu_end->key_id_octet, 974 msdu_end->cce_super_rule, 975 msdu_end->cce_classify_not_done_truncate, 976 msdu_end->cce_classify_not_done_cce_dis, 977 msdu_end->rule_indication_31_0, 978 msdu_end->tcp_udp_chksum, 979 msdu_end->sa_idx_timeout, 980 msdu_end->da_idx_timeout, 981 msdu_end->msdu_limit_error, 982 msdu_end->flow_idx_timeout, 983 msdu_end->flow_idx_invalid, 984 msdu_end->wifi_parser_error, 985 msdu_end->sa_is_valid, 986 msdu_end->da_is_valid, 987 msdu_end->da_is_mcbc, 988 msdu_end->tkip_mic_err, 989 msdu_end->l3_header_padding, 990 msdu_end->first_msdu, 991 msdu_end->last_msdu, 992 msdu_end->sa_idx, 993 msdu_end->msdu_drop, 994 msdu_end->reo_destination_indication, 995 msdu_end->flow_idx, 996 msdu_end->fse_metadata, 997 msdu_end->cce_metadata, 998 msdu_end->sa_sw_peer_id); 999 } 1000 1001 /** 1002 * hal_reo_status_get_header_5332 - Process reo desc info 1003 * @d - Pointer to reo descriptior 1004 * @b - tlv type info 1005 * @h1 - Pointer to hal_reo_status_header where info to be stored 1006 * 1007 * Return - none. 1008 * 1009 */ 1010 static void hal_reo_status_get_header_5332(hal_ring_desc_t ring_desc, 1011 int b, void *h1) 1012 { 1013 uint64_t *d = (uint64_t *)ring_desc; 1014 uint64_t val1 = 0; 1015 struct hal_reo_status_header *h = 1016 (struct hal_reo_status_header *)h1; 1017 1018 /* Offsets of descriptor fields defined in HW headers start 1019 * from the field after TLV header 1020 */ 1021 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr)); 1022 1023 switch (b) { 1024 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1025 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1026 STATUS_HEADER_REO_STATUS_NUMBER)]; 1027 break; 1028 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1029 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1030 STATUS_HEADER_REO_STATUS_NUMBER)]; 1031 break; 1032 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1033 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1034 STATUS_HEADER_REO_STATUS_NUMBER)]; 1035 break; 1036 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1037 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1038 STATUS_HEADER_REO_STATUS_NUMBER)]; 1039 break; 1040 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1041 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1042 STATUS_HEADER_REO_STATUS_NUMBER)]; 1043 break; 1044 case HAL_REO_DESC_THRES_STATUS_TLV: 1045 val1 = 1046 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1047 STATUS_HEADER_REO_STATUS_NUMBER)]; 1048 break; 1049 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1050 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1051 STATUS_HEADER_REO_STATUS_NUMBER)]; 1052 break; 1053 default: 1054 qdf_nofl_err("ERROR: Unknown tlv\n"); 1055 break; 1056 } 1057 h->cmd_num = 1058 HAL_GET_FIELD( 1059 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER, 1060 val1); 1061 h->exec_time = 1062 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1063 CMD_EXECUTION_TIME, val1); 1064 h->status = 1065 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1066 REO_CMD_EXECUTION_STATUS, val1); 1067 switch (b) { 1068 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1069 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1070 STATUS_HEADER_TIMESTAMP)]; 1071 break; 1072 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1073 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1074 STATUS_HEADER_TIMESTAMP)]; 1075 break; 1076 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1077 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1078 STATUS_HEADER_TIMESTAMP)]; 1079 break; 1080 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1081 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1082 STATUS_HEADER_TIMESTAMP)]; 1083 break; 1084 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1085 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1086 STATUS_HEADER_TIMESTAMP)]; 1087 break; 1088 case HAL_REO_DESC_THRES_STATUS_TLV: 1089 val1 = 1090 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1091 STATUS_HEADER_TIMESTAMP)]; 1092 break; 1093 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1094 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1095 STATUS_HEADER_TIMESTAMP)]; 1096 break; 1097 default: 1098 qdf_nofl_err("ERROR: Unknown tlv\n"); 1099 break; 1100 } 1101 h->tstamp = 1102 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1); 1103 } 1104 1105 static 1106 void *hal_rx_msdu0_buffer_addr_lsb_5332(void *link_desc_va) 1107 { 1108 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1109 } 1110 1111 static 1112 void *hal_rx_msdu_desc_info_ptr_get_5332(void *msdu0) 1113 { 1114 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1115 } 1116 1117 static 1118 void *hal_ent_mpdu_desc_info_5332(void *ent_ring_desc) 1119 { 1120 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1121 } 1122 1123 static 1124 void *hal_dst_mpdu_desc_info_5332(void *dst_ring_desc) 1125 { 1126 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1127 } 1128 1129 /** 1130 * hal_reo_config_5332(): Set reo config parameters 1131 * @soc: hal soc handle 1132 * @reg_val: value to be set 1133 * @reo_params: reo parameters 1134 * 1135 * Return: void 1136 */ 1137 static void 1138 hal_reo_config_5332(struct hal_soc *soc, 1139 uint32_t reg_val, 1140 struct hal_reo_params *reo_params) 1141 { 1142 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1143 } 1144 1145 /** 1146 * hal_rx_msdu_desc_info_get_ptr_5332() - Get msdu desc info ptr 1147 * @msdu_details_ptr - Pointer to msdu_details_ptr 1148 * 1149 * Return - Pointer to rx_msdu_desc_info structure. 1150 * 1151 */ 1152 static void *hal_rx_msdu_desc_info_get_ptr_5332(void *msdu_details_ptr) 1153 { 1154 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1155 } 1156 1157 /** 1158 * hal_rx_link_desc_msdu0_ptr_5332 - Get pointer to rx_msdu details 1159 * @link_desc - Pointer to link desc 1160 * 1161 * Return - Pointer to rx_msdu_details structure 1162 * 1163 */ 1164 static void *hal_rx_link_desc_msdu0_ptr_5332(void *link_desc) 1165 { 1166 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1167 } 1168 1169 /** 1170 * hal_get_window_address_5332(): Function to get hp/tp address 1171 * @hal_soc: Pointer to hal_soc 1172 * @addr: address offset of register 1173 * 1174 * Return: modified address offset of register 1175 */ 1176 1177 static inline qdf_iomem_t hal_get_window_address_5332(struct hal_soc *hal_soc, 1178 qdf_iomem_t addr) 1179 { 1180 uint32_t offset = addr - hal_soc->dev_base_addr; 1181 qdf_iomem_t new_offset; 1182 1183 /* 1184 * Check if offset lies within CE register range(0x740000) 1185 * or UMAC/DP register range (0x00A00000). 1186 * If offset lies within CE register range, map it 1187 * into CE region. 1188 */ 1189 if (offset < 0xA00000) { 1190 offset = offset - CE_CFG_WFSS_CE_REG_BASE; 1191 new_offset = (hal_soc->dev_base_addr_ce + offset); 1192 1193 return new_offset; 1194 } else { 1195 /* 1196 * If offset lies within DP register range, 1197 * return the address as such 1198 */ 1199 return addr; 1200 } 1201 } 1202 1203 static 1204 void hal_compute_reo_remap_ix2_ix3_5332(uint32_t *ring, uint32_t num_rings, 1205 uint32_t *remap1, uint32_t *remap2) 1206 { 1207 switch (num_rings) { 1208 case 1: 1209 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1210 HAL_REO_REMAP_IX2(ring[0], 17) | 1211 HAL_REO_REMAP_IX2(ring[0], 18) | 1212 HAL_REO_REMAP_IX2(ring[0], 19) | 1213 HAL_REO_REMAP_IX2(ring[0], 20) | 1214 HAL_REO_REMAP_IX2(ring[0], 21) | 1215 HAL_REO_REMAP_IX2(ring[0], 22) | 1216 HAL_REO_REMAP_IX2(ring[0], 23); 1217 1218 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1219 HAL_REO_REMAP_IX3(ring[0], 25) | 1220 HAL_REO_REMAP_IX3(ring[0], 26) | 1221 HAL_REO_REMAP_IX3(ring[0], 27) | 1222 HAL_REO_REMAP_IX3(ring[0], 28) | 1223 HAL_REO_REMAP_IX3(ring[0], 29) | 1224 HAL_REO_REMAP_IX3(ring[0], 30) | 1225 HAL_REO_REMAP_IX3(ring[0], 31); 1226 break; 1227 case 2: 1228 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1229 HAL_REO_REMAP_IX2(ring[0], 17) | 1230 HAL_REO_REMAP_IX2(ring[1], 18) | 1231 HAL_REO_REMAP_IX2(ring[1], 19) | 1232 HAL_REO_REMAP_IX2(ring[0], 20) | 1233 HAL_REO_REMAP_IX2(ring[0], 21) | 1234 HAL_REO_REMAP_IX2(ring[1], 22) | 1235 HAL_REO_REMAP_IX2(ring[1], 23); 1236 1237 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1238 HAL_REO_REMAP_IX3(ring[0], 25) | 1239 HAL_REO_REMAP_IX3(ring[1], 26) | 1240 HAL_REO_REMAP_IX3(ring[1], 27) | 1241 HAL_REO_REMAP_IX3(ring[0], 28) | 1242 HAL_REO_REMAP_IX3(ring[0], 29) | 1243 HAL_REO_REMAP_IX3(ring[1], 30) | 1244 HAL_REO_REMAP_IX3(ring[1], 31); 1245 break; 1246 case 3: 1247 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1248 HAL_REO_REMAP_IX2(ring[1], 17) | 1249 HAL_REO_REMAP_IX2(ring[2], 18) | 1250 HAL_REO_REMAP_IX2(ring[0], 19) | 1251 HAL_REO_REMAP_IX2(ring[1], 20) | 1252 HAL_REO_REMAP_IX2(ring[2], 21) | 1253 HAL_REO_REMAP_IX2(ring[0], 22) | 1254 HAL_REO_REMAP_IX2(ring[1], 23); 1255 1256 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1257 HAL_REO_REMAP_IX3(ring[0], 25) | 1258 HAL_REO_REMAP_IX3(ring[1], 26) | 1259 HAL_REO_REMAP_IX3(ring[2], 27) | 1260 HAL_REO_REMAP_IX3(ring[0], 28) | 1261 HAL_REO_REMAP_IX3(ring[1], 29) | 1262 HAL_REO_REMAP_IX3(ring[2], 30) | 1263 HAL_REO_REMAP_IX3(ring[0], 31); 1264 break; 1265 case 4: 1266 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1267 HAL_REO_REMAP_IX2(ring[1], 17) | 1268 HAL_REO_REMAP_IX2(ring[2], 18) | 1269 HAL_REO_REMAP_IX2(ring[3], 19) | 1270 HAL_REO_REMAP_IX2(ring[0], 20) | 1271 HAL_REO_REMAP_IX2(ring[1], 21) | 1272 HAL_REO_REMAP_IX2(ring[2], 22) | 1273 HAL_REO_REMAP_IX2(ring[3], 23); 1274 1275 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1276 HAL_REO_REMAP_IX3(ring[1], 25) | 1277 HAL_REO_REMAP_IX3(ring[2], 26) | 1278 HAL_REO_REMAP_IX3(ring[3], 27) | 1279 HAL_REO_REMAP_IX3(ring[0], 28) | 1280 HAL_REO_REMAP_IX3(ring[1], 29) | 1281 HAL_REO_REMAP_IX3(ring[2], 30) | 1282 HAL_REO_REMAP_IX3(ring[3], 31); 1283 break; 1284 } 1285 } 1286 1287 /** 1288 * hal_rx_flow_setup_fse_5332() - Setup a flow search entry in HW FST 1289 * @fst: Pointer to the Rx Flow Search Table 1290 * @table_offset: offset into the table where the flow is to be setup 1291 * @flow: Flow Parameters 1292 * 1293 * Return: Success/Failure 1294 */ 1295 static void * 1296 hal_rx_flow_setup_fse_5332(uint8_t *rx_fst, uint32_t table_offset, 1297 uint8_t *rx_flow) 1298 { 1299 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1300 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1301 uint8_t *fse; 1302 bool fse_valid; 1303 1304 if (table_offset >= fst->max_entries) { 1305 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1306 "HAL FSE table offset %u exceeds max entries %u", 1307 table_offset, fst->max_entries); 1308 return NULL; 1309 } 1310 1311 fse = (uint8_t *)fst->base_vaddr + 1312 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1313 1314 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1315 1316 if (fse_valid) { 1317 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1318 "HAL FSE %pK already valid", fse); 1319 return NULL; 1320 } 1321 1322 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) = 1323 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1324 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1325 1326 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) = 1327 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1328 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1329 1330 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) = 1331 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1332 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1333 1334 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) = 1335 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1336 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1337 1338 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) = 1339 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1340 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1341 1342 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) = 1343 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1344 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1345 1346 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) = 1347 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1348 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1349 1350 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) = 1351 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1352 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1353 1354 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT); 1355 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |= 1356 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1357 (flow->tuple_info.dest_port)); 1358 1359 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT); 1360 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |= 1361 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1362 (flow->tuple_info.src_port)); 1363 1364 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL); 1365 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |= 1366 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1367 flow->tuple_info.l4_protocol); 1368 1369 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER); 1370 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |= 1371 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1372 flow->reo_destination_handler); 1373 1374 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1375 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |= 1376 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1377 1378 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA); 1379 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) = 1380 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1381 flow->fse_metadata); 1382 1383 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION); 1384 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |= 1385 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1386 REO_DESTINATION_INDICATION, 1387 flow->reo_destination_indication); 1388 1389 /* Reset all the other fields in FSE */ 1390 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9); 1391 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP); 1392 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT); 1393 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT); 1394 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP); 1395 1396 return fse; 1397 } 1398 1399 #ifndef NO_RX_PKT_HDR_TLV 1400 /** 1401 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 1402 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 1403 * @ dbg_level: log level. 1404 * 1405 * Return: void 1406 */ 1407 static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs, 1408 uint8_t dbg_level) 1409 { 1410 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 1411 1412 hal_verbose_debug("\n---------------\n" 1413 "rx_pkt_hdr_tlv\n" 1414 "---------------\n" 1415 "phy_ppdu_id %llu ", 1416 pkt_hdr_tlv->phy_ppdu_id); 1417 1418 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 1419 sizeof(pkt_hdr_tlv->rx_pkt_hdr)); 1420 } 1421 #else 1422 /** 1423 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 1424 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 1425 * @ dbg_level: log level. 1426 * 1427 * Return: void 1428 */ 1429 static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs, 1430 uint8_t dbg_level) 1431 { 1432 } 1433 #endif 1434 1435 /** 1436 * hal_rx_dump_pkt_tlvs_5332(): API to print RX Pkt TLVS qca5332 1437 * @hal_soc_hdl: hal_soc handle 1438 * @buf: pointer the pkt buffer 1439 * @dbg_level: log level 1440 * 1441 * Return: void 1442 */ 1443 #ifdef CONFIG_WORD_BASED_TLV 1444 static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl, 1445 uint8_t *buf, uint8_t dbg_level) 1446 { 1447 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1448 struct rx_msdu_end_compact_qca5332 *msdu_end = 1449 &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1450 struct rx_mpdu_start_compact_qca5332 *mpdu_start = 1451 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1452 1453 hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level); 1454 hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level); 1455 hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level); 1456 } 1457 #else 1458 static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl, 1459 uint8_t *buf, uint8_t dbg_level) 1460 { 1461 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1462 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1463 struct rx_mpdu_start *mpdu_start = 1464 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1465 1466 hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level); 1467 hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level); 1468 hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level); 1469 } 1470 #endif 1471 1472 #define HAL_NUM_TCL_BANKS_5332 24 1473 1474 /** 1475 * hal_cmem_write_5332() - function for CMEM buffer writing 1476 * @hal_soc_hdl: HAL SOC handle 1477 * @offset: CMEM address 1478 * @value: value to write 1479 * 1480 * Return: None. 1481 */ 1482 static void hal_cmem_write_5332(hal_soc_handle_t hal_soc_hdl, 1483 uint32_t offset, 1484 uint32_t value) 1485 { 1486 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1487 1488 /* cmem region is ioremapped from CMEM_REG_BASE, hence subtracting 1489 * that from offset. 1490 */ 1491 offset = offset - CMEM_REG_BASE; 1492 pld_reg_write(hal->qdf_dev->dev, offset, value, 1493 hal->dev_base_addr_cmem); 1494 } 1495 1496 /** 1497 * hal_tx_get_num_tcl_banks_5332() - Get number of banks in target 1498 * 1499 * Returns: number of bank 1500 */ 1501 static uint8_t hal_tx_get_num_tcl_banks_5332(void) 1502 { 1503 return HAL_NUM_TCL_BANKS_5332; 1504 } 1505 1506 static void hal_reo_setup_5332(struct hal_soc *soc, void *reoparams, 1507 int qref_reset) 1508 { 1509 uint32_t reg_val; 1510 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1511 1512 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1513 REO_REG_REG_BASE)); 1514 1515 hal_reo_config_5332(soc, reg_val, reo_params); 1516 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1517 1518 /* TODO: Setup destination ring mapping if enabled */ 1519 1520 /* TODO: Error destination ring setting is left to default. 1521 * Default setting is to send all errors to release ring. 1522 */ 1523 1524 /* Set the reo descriptor swap bits in case of BIG endian platform */ 1525 hal_setup_reo_swap(soc); 1526 1527 HAL_REG_WRITE(soc, 1528 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE), 1529 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1530 1531 HAL_REG_WRITE(soc, 1532 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE), 1533 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1534 1535 HAL_REG_WRITE(soc, 1536 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE), 1537 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1538 1539 HAL_REG_WRITE(soc, 1540 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE), 1541 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1542 1543 /* 1544 * When hash based routing is enabled, routing of the rx packet 1545 * is done based on the following value: 1 _ _ _ _ The last 4 1546 * bits are based on hash[3:0]. This means the possible values 1547 * are 0x10 to 0x1f. This value is used to look-up the 1548 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1549 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1550 * registers need to be configured to set-up the 16 entries to 1551 * map the hash values to a ring number. There are 3 bits per 1552 * hash entry – which are mapped as follows: 1553 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1554 * 7: NOT_USED. 1555 */ 1556 if (reo_params->rx_hash_enabled) { 1557 HAL_REG_WRITE(soc, 1558 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR 1559 (REO_REG_REG_BASE), reo_params->remap0); 1560 1561 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1562 HAL_REG_READ(soc, 1563 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR( 1564 REO_REG_REG_BASE))); 1565 1566 HAL_REG_WRITE(soc, 1567 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 1568 (REO_REG_REG_BASE), reo_params->remap1); 1569 1570 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1571 HAL_REG_READ(soc, 1572 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1573 REO_REG_REG_BASE))); 1574 1575 HAL_REG_WRITE(soc, 1576 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 1577 (REO_REG_REG_BASE), reo_params->remap2); 1578 1579 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1580 HAL_REG_READ(soc, 1581 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1582 REO_REG_REG_BASE))); 1583 } 1584 1585 /* TODO: Check if the following registers shoould be setup by host: 1586 * AGING_CONTROL 1587 * HIGH_MEMORY_THRESHOLD 1588 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1589 * GLOBAL_LINK_DESC_COUNT_CTRL 1590 */ 1591 1592 hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset); 1593 } 1594 1595 static uint16_t hal_get_rx_max_ba_window_qca5332(int tid) 1596 { 1597 return HAL_RX_BA_WINDOW_1024; 1598 } 1599 1600 /** 1601 * hal_qca5332_get_reo_qdesc_size()- Get the reo queue descriptor size 1602 * from the give Block-Ack window size 1603 * Return: reo queue descriptor size 1604 */ 1605 static uint32_t hal_qca5332_get_reo_qdesc_size(uint32_t ba_window_size, int tid) 1606 { 1607 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 1608 * NON_QOS_TID until HW issues are resolved. 1609 */ 1610 if (tid != HAL_NON_QOS_TID) 1611 ba_window_size = hal_get_rx_max_ba_window_qca5332(tid); 1612 1613 /* Return descriptor size corresponding to window size of 2 since 1614 * we set ba_window_size to 2 while setting up REO descriptors as 1615 * a WAR to get 2k jump exception aggregates are received without 1616 * a BA session. 1617 */ 1618 if (ba_window_size <= 1) { 1619 if (tid != HAL_NON_QOS_TID) 1620 return sizeof(struct rx_reo_queue) + 1621 sizeof(struct rx_reo_queue_ext); 1622 else 1623 return sizeof(struct rx_reo_queue); 1624 } 1625 1626 if (ba_window_size <= 105) 1627 return sizeof(struct rx_reo_queue) + 1628 sizeof(struct rx_reo_queue_ext); 1629 1630 if (ba_window_size <= 210) 1631 return sizeof(struct rx_reo_queue) + 1632 (2 * sizeof(struct rx_reo_queue_ext)); 1633 1634 if (ba_window_size <= 256) 1635 return sizeof(struct rx_reo_queue) + 1636 (3 * sizeof(struct rx_reo_queue_ext)); 1637 1638 return sizeof(struct rx_reo_queue) + 1639 (10 * sizeof(struct rx_reo_queue_ext)) + 1640 sizeof(struct rx_reo_queue_1k); 1641 } 1642 /** 1643 * hal_rx_tlv_msdu_done_copy_get_5332() - Get msdu done copy bit from rx_tlv 1644 * 1645 * Returns: msdu done copy bit 1646 */ 1647 static inline uint32_t hal_rx_tlv_msdu_done_copy_get_5332(uint8_t *buf) 1648 { 1649 return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf); 1650 } 1651 1652 static void hal_hw_txrx_ops_attach_qca5332(struct hal_soc *hal_soc) 1653 { 1654 /* init and setup */ 1655 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1656 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1657 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1658 hal_soc->ops->hal_get_window_address = hal_get_window_address_5332; 1659 hal_soc->ops->hal_cmem_write = hal_cmem_write_5332; 1660 1661 /* tx */ 1662 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5332; 1663 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5332; 1664 hal_soc->ops->hal_tx_comp_get_status = 1665 hal_tx_comp_get_status_generic_be; 1666 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1667 hal_tx_init_cmd_credit_ring_5332; 1668 hal_soc->ops->hal_tx_set_ppe_cmn_cfg = NULL; 1669 hal_soc->ops->hal_tx_set_ppe_vp_entry = NULL; 1670 hal_soc->ops->hal_tx_set_ppe_pri2tid = NULL; 1671 hal_soc->ops->hal_tx_update_ppe_pri2tid = NULL; 1672 hal_soc->ops->hal_tx_dump_ppe_vp_entry = NULL; 1673 hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = NULL; 1674 hal_soc->ops->hal_tx_enable_pri2tid_map = NULL; 1675 hal_soc->ops->hal_tx_config_rbm_mapping_be = 1676 hal_tx_config_rbm_mapping_be_5332; 1677 1678 /* rx */ 1679 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; 1680 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1681 hal_rx_mon_hw_desc_get_mpdu_status_be; 1682 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5332; 1683 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1684 hal_rx_proc_phyrx_other_receive_info_tlv_5332; 1685 1686 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5332; 1687 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1688 hal_rx_dump_mpdu_start_tlv_5332; 1689 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_5332; 1690 1691 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5332; 1692 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be; 1693 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1694 hal_rx_tlv_reception_type_get_be; 1695 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1696 hal_rx_msdu_end_da_idx_get_be; 1697 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1698 hal_rx_msdu_desc_info_get_ptr_5332; 1699 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1700 hal_rx_link_desc_msdu0_ptr_5332; 1701 hal_soc->ops->hal_reo_status_get_header = 1702 hal_reo_status_get_header_5332; 1703 hal_soc->ops->hal_rx_status_get_tlv_info = 1704 hal_rx_status_get_tlv_info_wrapper_be; 1705 hal_soc->ops->hal_rx_wbm_err_info_get = 1706 hal_rx_wbm_err_info_get_generic_be; 1707 hal_soc->ops->hal_tx_set_pcp_tid_map = 1708 hal_tx_set_pcp_tid_map_generic_be; 1709 hal_soc->ops->hal_tx_update_pcp_tid_map = 1710 hal_tx_update_pcp_tid_generic_be; 1711 hal_soc->ops->hal_tx_set_tidmap_prty = 1712 hal_tx_update_tidmap_prty_generic_be; 1713 hal_soc->ops->hal_rx_get_rx_fragment_number = 1714 hal_rx_get_rx_fragment_number_be, 1715 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1716 hal_rx_tlv_da_is_mcbc_get_be; 1717 hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err = 1718 hal_rx_tlv_is_tkip_mic_err_get_be; 1719 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1720 hal_rx_tlv_sa_is_valid_get_be; 1721 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be; 1722 hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be; 1723 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1724 hal_rx_tlv_l3_hdr_padding_get_be; 1725 hal_soc->ops->hal_rx_encryption_info_valid = 1726 hal_rx_encryption_info_valid_be; 1727 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; 1728 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1729 hal_rx_tlv_first_msdu_get_be; 1730 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1731 hal_rx_tlv_da_is_valid_get_be; 1732 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1733 hal_rx_tlv_last_msdu_get_be; 1734 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1735 hal_rx_get_mpdu_mac_ad4_valid_be; 1736 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1737 hal_rx_mpdu_start_sw_peer_id_get_be; 1738 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1739 hal_rx_mpdu_peer_meta_data_get_be; 1740 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be; 1741 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be; 1742 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1743 hal_rx_get_mpdu_frame_control_valid_be; 1744 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; 1745 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; 1746 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; 1747 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; 1748 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1749 hal_rx_get_mpdu_sequence_control_valid_be; 1750 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; 1751 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; 1752 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1753 hal_rx_hw_desc_get_ppduid_get_be; 1754 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1755 hal_rx_mpdu_start_mpdu_qos_control_valid_get_be; 1756 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1757 hal_rx_msdu_end_sa_sw_peer_id_get_be; 1758 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1759 hal_rx_msdu0_buffer_addr_lsb_5332; 1760 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1761 hal_rx_msdu_desc_info_ptr_get_5332; 1762 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5332; 1763 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5332; 1764 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; 1765 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; 1766 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1767 hal_rx_get_mac_addr2_valid_be; 1768 hal_soc->ops->hal_rx_get_filter_category = 1769 hal_rx_get_filter_category_be; 1770 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be; 1771 hal_soc->ops->hal_reo_config = hal_reo_config_5332; 1772 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; 1773 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1774 hal_rx_msdu_flow_idx_invalid_be; 1775 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1776 hal_rx_msdu_flow_idx_timeout_be; 1777 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1778 hal_rx_msdu_fse_metadata_get_be; 1779 hal_soc->ops->hal_rx_msdu_cce_match_get = 1780 hal_rx_msdu_cce_match_get_be; 1781 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1782 hal_rx_msdu_cce_metadata_get_be; 1783 hal_soc->ops->hal_rx_msdu_get_flow_params = 1784 hal_rx_msdu_get_flow_params_be; 1785 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be; 1786 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be; 1787 #if defined(QCA_WIFI_QCA5332) && defined(WLAN_CFR_ENABLE) && \ 1788 defined(WLAN_ENH_CFR_ENABLE) 1789 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5332; 1790 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5332; 1791 #else 1792 hal_soc->ops->hal_rx_get_bb_info = NULL; 1793 hal_soc->ops->hal_rx_get_rtt_info = NULL; 1794 #endif 1795 /* rx - msdu fast path info fields */ 1796 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1797 hal_rx_msdu_packet_metadata_get_generic_be; 1798 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1799 hal_rx_mpdu_start_tlv_tag_valid_be; 1800 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1801 hal_rx_wbm_err_msdu_continuation_get_5332; 1802 1803 /* rx - TLV struct offsets */ 1804 hal_soc->ops->hal_rx_msdu_end_offset_get = 1805 hal_rx_msdu_end_offset_get_generic; 1806 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1807 hal_rx_mpdu_start_offset_get_generic; 1808 #ifndef NO_RX_PKT_HDR_TLV 1809 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1810 hal_rx_pkt_tlv_offset_get_generic; 1811 #endif 1812 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5332; 1813 1814 hal_soc->ops->hal_rx_flow_get_tuple_info = 1815 hal_rx_flow_get_tuple_info_be; 1816 hal_soc->ops->hal_rx_flow_delete_entry = 1817 hal_rx_flow_delete_entry_be; 1818 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be; 1819 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1820 hal_compute_reo_remap_ix2_ix3_5332; 1821 1822 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 1823 hal_rx_msdu_get_reo_destination_indication_be; 1824 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; 1825 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 1826 hal_rx_msdu_is_wlan_mcast_generic_be; 1827 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_5332; 1828 hal_soc->ops->hal_rx_tlv_decap_format_get = 1829 hal_rx_tlv_decap_format_get_be; 1830 #ifdef RECEIVE_OFFLOAD 1831 hal_soc->ops->hal_rx_tlv_get_offload_info = 1832 hal_rx_tlv_get_offload_info_be; 1833 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; 1834 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; 1835 #endif 1836 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 1837 hal_rx_attn_phy_ppdu_id_get_be; 1838 hal_soc->ops->hal_rx_tlv_msdu_done_get = 1839 hal_rx_tlv_msdu_done_copy_get_5332; 1840 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1841 hal_rx_msdu_start_msdu_len_get_be; 1842 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1843 hal_rx_get_frame_ctrl_field_be; 1844 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; 1845 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1846 hal_rx_mpdu_info_ampdu_flag_get_be; 1847 hal_soc->ops->hal_rx_tlv_msdu_len_set = 1848 hal_rx_msdu_start_msdu_len_set_be; 1849 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; 1850 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; 1851 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be; 1852 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be; 1853 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be; 1854 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1855 hal_rx_tlv_decrypt_err_get_be; 1856 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be; 1857 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 1858 hal_rx_tlv_get_is_decrypted_be; 1859 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be; 1860 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 1861 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1862 hal_rx_priv_info_set_in_tlv_be; 1863 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1864 hal_rx_priv_info_get_from_tlv_be; 1865 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be; 1866 hal_soc->ops->hal_reo_setup = hal_reo_setup_5332; 1867 #ifdef REO_SHARED_QREF_TABLE_EN 1868 hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be; 1869 hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be; 1870 hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be; 1871 hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be; 1872 hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be; 1873 #endif 1874 /* Overwrite the default BE ops */ 1875 hal_soc->ops->hal_get_rx_max_ba_window = 1876 hal_get_rx_max_ba_window_qca5332; 1877 hal_soc->ops->hal_get_reo_qdesc_size = hal_qca5332_get_reo_qdesc_size; 1878 /* TX MONITOR */ 1879 #ifdef QCA_MONITOR_2_0_SUPPORT 1880 hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv = 1881 hal_txmon_is_mon_buf_addr_tlv_generic_be; 1882 hal_soc->ops->hal_txmon_populate_packet_info = 1883 hal_txmon_populate_packet_info_generic_be; 1884 hal_soc->ops->hal_txmon_status_parse_tlv = 1885 hal_txmon_status_parse_tlv_generic_be; 1886 hal_soc->ops->hal_txmon_status_get_num_users = 1887 hal_txmon_status_get_num_users_generic_be; 1888 #endif /* QCA_MONITOR_2_0_SUPPORT */ 1889 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1890 hal_soc->ops->hal_tx_vdev_mismatch_routing_set = 1891 hal_tx_vdev_mismatch_routing_set_generic_be; 1892 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = 1893 hal_tx_mcast_mlo_reinject_routing_set_generic_be; 1894 hal_soc->ops->hal_get_ba_aging_timeout = 1895 hal_get_ba_aging_timeout_be_generic; 1896 hal_soc->ops->hal_setup_link_idle_list = 1897 hal_setup_link_idle_list_generic_be; 1898 hal_soc->ops->hal_cookie_conversion_reg_cfg_be = 1899 hal_cookie_conversion_reg_cfg_generic_be; 1900 hal_soc->ops->hal_set_ba_aging_timeout = 1901 hal_set_ba_aging_timeout_be_generic; 1902 hal_soc->ops->hal_tx_populate_bank_register = 1903 hal_tx_populate_bank_register_be; 1904 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = 1905 hal_tx_vdev_mcast_ctrl_set_be; 1906 }; 1907 1908 struct hal_hw_srng_config hw_srng_table_5332[] = { 1909 /* TODO: max_rings can populated by querying HW capabilities */ 1910 { /* REO_DST */ 1911 .start_ring_id = HAL_SRNG_REO2SW1, 1912 .max_rings = 8, 1913 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1914 .lmac_ring = FALSE, 1915 .ring_dir = HAL_SRNG_DST_RING, 1916 .reg_start = { 1917 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1918 REO_REG_REG_BASE), 1919 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1920 REO_REG_REG_BASE) 1921 }, 1922 .reg_size = { 1923 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1924 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1925 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1926 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1927 }, 1928 .max_size = 1929 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1930 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1931 }, 1932 { /* REO_EXCEPTION */ 1933 /* Designating REO2SW0 ring as exception ring. This ring is 1934 * similar to other REO2SW rings though it is named as REO2SW0. 1935 * Any of theREO2SW rings can be used as exception ring. 1936 */ 1937 .start_ring_id = HAL_SRNG_REO2SW0, 1938 .max_rings = 1, 1939 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1940 .lmac_ring = FALSE, 1941 .ring_dir = HAL_SRNG_DST_RING, 1942 .reg_start = { 1943 HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR( 1944 REO_REG_REG_BASE), 1945 HWIO_REO_R2_REO2SW0_RING_HP_ADDR( 1946 REO_REG_REG_BASE) 1947 }, 1948 /* Single ring - provide ring size if multiple rings of this 1949 * type are supported 1950 */ 1951 .reg_size = {}, 1952 .max_size = 1953 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >> 1954 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT, 1955 }, 1956 { /* REO_REINJECT */ 1957 .start_ring_id = HAL_SRNG_SW2REO, 1958 .max_rings = 4, 1959 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1960 .lmac_ring = FALSE, 1961 .ring_dir = HAL_SRNG_SRC_RING, 1962 .reg_start = { 1963 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1964 REO_REG_REG_BASE), 1965 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1966 REO_REG_REG_BASE) 1967 }, 1968 /* Single ring - provide ring size if multiple rings of this 1969 * type are supported 1970 */ 1971 .reg_size = { 1972 HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) - 1973 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0), 1974 HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) - 1975 HWIO_REO_R2_SW2REO_RING_HP_ADDR(0) 1976 }, 1977 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1978 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1979 }, 1980 { /* REO_CMD */ 1981 .start_ring_id = HAL_SRNG_REO_CMD, 1982 .max_rings = 1, 1983 .entry_size = (sizeof(struct tlv_32_hdr) + 1984 sizeof(struct reo_get_queue_stats)) >> 2, 1985 .lmac_ring = FALSE, 1986 .ring_dir = HAL_SRNG_SRC_RING, 1987 .reg_start = { 1988 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1989 REO_REG_REG_BASE), 1990 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1991 REO_REG_REG_BASE), 1992 }, 1993 /* Single ring - provide ring size if multiple rings of this 1994 * type are supported 1995 */ 1996 .reg_size = {}, 1997 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1998 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1999 }, 2000 { /* REO_STATUS */ 2001 .start_ring_id = HAL_SRNG_REO_STATUS, 2002 .max_rings = 1, 2003 .entry_size = (sizeof(struct tlv_32_hdr) + 2004 sizeof(struct reo_get_queue_stats_status)) >> 2, 2005 .lmac_ring = FALSE, 2006 .ring_dir = HAL_SRNG_DST_RING, 2007 .reg_start = { 2008 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2009 REO_REG_REG_BASE), 2010 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2011 REO_REG_REG_BASE), 2012 }, 2013 /* Single ring - provide ring size if multiple rings of this 2014 * type are supported 2015 */ 2016 .reg_size = {}, 2017 .max_size = 2018 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2019 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2020 }, 2021 { /* TCL_DATA */ 2022 .start_ring_id = HAL_SRNG_SW2TCL1, 2023 .max_rings = 6, 2024 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 2025 .lmac_ring = FALSE, 2026 .ring_dir = HAL_SRNG_SRC_RING, 2027 .reg_start = { 2028 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2029 MAC_TCL_REG_REG_BASE), 2030 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2031 MAC_TCL_REG_REG_BASE), 2032 }, 2033 .reg_size = { 2034 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2035 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2036 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2037 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2038 }, 2039 .max_size = 2040 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2041 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2042 }, 2043 { /* TCL_CMD/CREDIT */ 2044 /* qca8074v2 and qca5332 uses this ring for data commands */ 2045 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2046 .max_rings = 1, 2047 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 2048 .lmac_ring = FALSE, 2049 .ring_dir = HAL_SRNG_SRC_RING, 2050 .reg_start = { 2051 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2052 MAC_TCL_REG_REG_BASE), 2053 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2054 MAC_TCL_REG_REG_BASE), 2055 }, 2056 /* Single ring - provide ring size if multiple rings of this 2057 * type are supported 2058 */ 2059 .reg_size = {}, 2060 .max_size = 2061 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2062 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2063 }, 2064 { /* TCL_STATUS */ 2065 .start_ring_id = HAL_SRNG_TCL_STATUS, 2066 .max_rings = 1, 2067 .entry_size = (sizeof(struct tlv_32_hdr) + 2068 sizeof(struct tcl_status_ring)) >> 2, 2069 .lmac_ring = FALSE, 2070 .ring_dir = HAL_SRNG_DST_RING, 2071 .reg_start = { 2072 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2073 MAC_TCL_REG_REG_BASE), 2074 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2075 MAC_TCL_REG_REG_BASE), 2076 }, 2077 /* Single ring - provide ring size if multiple rings of this 2078 * type are supported 2079 */ 2080 .reg_size = {}, 2081 .max_size = 2082 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2083 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2084 }, 2085 { /* CE_SRC */ 2086 .start_ring_id = HAL_SRNG_CE_0_SRC, 2087 .max_rings = 16, 2088 .entry_size = sizeof(struct ce_src_desc) >> 2, 2089 .lmac_ring = FALSE, 2090 .ring_dir = HAL_SRNG_SRC_RING, 2091 .reg_start = { 2092 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR( 2093 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE), 2094 HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR( 2095 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE), 2096 }, 2097 .reg_size = { 2098 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 2099 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 2100 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 2101 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 2102 }, 2103 .max_size = 2104 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >> 2105 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT, 2106 }, 2107 { /* CE_DST */ 2108 .start_ring_id = HAL_SRNG_CE_0_DST, 2109 .max_rings = 16, 2110 .entry_size = 8 >> 2, 2111 /*TODO: entry_size above should actually be 2112 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2113 * of struct ce_dst_desc in HW header files 2114 */ 2115 .lmac_ring = FALSE, 2116 .ring_dir = HAL_SRNG_SRC_RING, 2117 .reg_start = { 2118 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2119 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 2120 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2121 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 2122 }, 2123 .reg_size = { 2124 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2125 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2126 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2127 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2128 }, 2129 .max_size = 2130 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2131 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2132 }, 2133 { /* CE_DST_STATUS */ 2134 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2135 .max_rings = 16, 2136 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2137 .lmac_ring = FALSE, 2138 .ring_dir = HAL_SRNG_DST_RING, 2139 .reg_start = { 2140 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2141 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 2142 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2143 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 2144 }, 2145 /* TODO: check destination status ring registers */ 2146 .reg_size = { 2147 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2148 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2149 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2150 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2151 }, 2152 .max_size = 2153 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2154 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2155 }, 2156 { /* WBM_IDLE_LINK */ 2157 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2158 .max_rings = 1, 2159 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2160 .lmac_ring = FALSE, 2161 .ring_dir = HAL_SRNG_SRC_RING, 2162 .reg_start = { 2163 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2164 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE), 2165 }, 2166 /* Single ring - provide ring size if multiple rings of this 2167 * type are supported 2168 */ 2169 .reg_size = {}, 2170 .max_size = 2171 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2172 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2173 }, 2174 { /* SW2WBM_RELEASE */ 2175 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2176 .max_rings = 1, 2177 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2178 .lmac_ring = FALSE, 2179 .ring_dir = HAL_SRNG_SRC_RING, 2180 .reg_start = { 2181 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2182 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2183 }, 2184 /* Single ring - provide ring size if multiple rings of this 2185 * type are supported 2186 */ 2187 .reg_size = {}, 2188 .max_size = 2189 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2190 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2191 }, 2192 { /* WBM2SW_RELEASE */ 2193 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2194 .max_rings = 8, 2195 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2196 .lmac_ring = FALSE, 2197 .ring_dir = HAL_SRNG_DST_RING, 2198 .reg_start = { 2199 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR( 2200 WBM_REG_REG_BASE), 2201 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR( 2202 WBM_REG_REG_BASE), 2203 }, 2204 .reg_size = { 2205 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR( 2206 WBM_REG_REG_BASE) - 2207 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR( 2208 WBM_REG_REG_BASE), 2209 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR( 2210 WBM_REG_REG_BASE) - 2211 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR( 2212 WBM_REG_REG_BASE), 2213 }, 2214 .max_size = 2215 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2216 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2217 }, 2218 { /* RXDMA_BUF */ 2219 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2220 #ifdef IPA_OFFLOAD 2221 .max_rings = 3, 2222 #else 2223 .max_rings = 3, 2224 #endif 2225 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2226 .lmac_ring = TRUE, 2227 .ring_dir = HAL_SRNG_SRC_RING, 2228 /* reg_start is not set because LMAC rings are not accessed 2229 * from host 2230 */ 2231 .reg_start = {}, 2232 .reg_size = {}, 2233 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2234 }, 2235 { /* RXDMA_DST */ 2236 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2237 .max_rings = 0, 2238 .entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/, 2239 .lmac_ring = TRUE, 2240 .ring_dir = HAL_SRNG_DST_RING, 2241 /* reg_start is not set because LMAC rings are not accessed 2242 * from host 2243 */ 2244 .reg_start = {}, 2245 .reg_size = {}, 2246 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2247 }, 2248 #ifdef QCA_MONITOR_2_0_SUPPORT 2249 { /* RXDMA_MONITOR_BUF */ 2250 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2251 .max_rings = 1, 2252 .entry_size = sizeof(struct mon_ingress_ring) >> 2, 2253 .lmac_ring = TRUE, 2254 .ring_dir = HAL_SRNG_SRC_RING, 2255 /* reg_start is not set because LMAC rings are not accessed 2256 * from host 2257 */ 2258 .reg_start = {}, 2259 .reg_size = {}, 2260 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2261 }, 2262 #else 2263 {}, 2264 #endif 2265 { /* RXDMA_MONITOR_STATUS */ 2266 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2267 .max_rings = 0, 2268 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2269 .lmac_ring = TRUE, 2270 .ring_dir = HAL_SRNG_SRC_RING, 2271 /* reg_start is not set because LMAC rings are not accessed 2272 * from host 2273 */ 2274 .reg_start = {}, 2275 .reg_size = {}, 2276 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2277 }, 2278 #ifdef QCA_MONITOR_2_0_SUPPORT 2279 { /* RXDMA_MONITOR_DST */ 2280 .start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0, 2281 .max_rings = 2, 2282 .entry_size = sizeof(struct mon_destination_ring) >> 2, 2283 .lmac_ring = TRUE, 2284 .ring_dir = HAL_SRNG_DST_RING, 2285 /* reg_start is not set because LMAC rings are not accessed 2286 * from host 2287 */ 2288 .reg_start = {}, 2289 .reg_size = {}, 2290 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2291 }, 2292 #else 2293 {}, 2294 #endif 2295 { /* RXDMA_MONITOR_DESC */ 2296 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2297 .max_rings = 0, 2298 .entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/, 2299 .lmac_ring = TRUE, 2300 .ring_dir = HAL_SRNG_DST_RING, 2301 /* reg_start is not set because LMAC rings are not accessed 2302 * from host 2303 */ 2304 .reg_start = {}, 2305 .reg_size = {}, 2306 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2307 }, 2308 2309 { /* DIR_BUF_RX_DMA_SRC */ 2310 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2311 /* one ring for spectral and one ring for cfr */ 2312 .max_rings = 2, 2313 .entry_size = 2, 2314 .lmac_ring = TRUE, 2315 .ring_dir = HAL_SRNG_SRC_RING, 2316 /* reg_start is not set because LMAC rings are not accessed 2317 * from host 2318 */ 2319 .reg_start = {}, 2320 .reg_size = {}, 2321 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2322 }, 2323 #ifdef WLAN_FEATURE_CIF_CFR 2324 { /* WIFI_POS_SRC */ 2325 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2326 .max_rings = 1, 2327 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2328 .lmac_ring = TRUE, 2329 .ring_dir = HAL_SRNG_SRC_RING, 2330 /* reg_start is not set because LMAC rings are not accessed 2331 * from host 2332 */ 2333 .reg_start = {}, 2334 .reg_size = {}, 2335 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2336 }, 2337 #endif 2338 /* PPE rings are not present in Miami. Added dummy entries to preserve 2339 * Array Index 2340 */ 2341 /* REO2PPE */ 2342 {}, 2343 /* PPE2TCL */ 2344 {}, 2345 /* PPE_RELEASE */ 2346 {}, 2347 #ifdef QCA_MONITOR_2_0_SUPPORT 2348 { /* TX_MONITOR_BUF */ 2349 .start_ring_id = HAL_SRNG_SW2TXMON_BUF0, 2350 .max_rings = 1, 2351 .entry_size = sizeof(struct mon_ingress_ring) >> 2, 2352 .lmac_ring = TRUE, 2353 .ring_dir = HAL_SRNG_SRC_RING, 2354 /* reg_start is not set because LMAC rings are not accessed 2355 * from host 2356 */ 2357 .reg_start = {}, 2358 .reg_size = {}, 2359 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2360 }, 2361 { /* TX_MONITOR_DST */ 2362 .start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0, 2363 .max_rings = 2, 2364 .entry_size = sizeof(struct mon_destination_ring) >> 2, 2365 .lmac_ring = TRUE, 2366 .ring_dir = HAL_SRNG_DST_RING, 2367 /* reg_start is not set because LMAC rings are not accessed 2368 * from host 2369 */ 2370 .reg_start = {}, 2371 .reg_size = {}, 2372 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2373 }, 2374 #else 2375 {}, 2376 {}, 2377 #endif 2378 { /* SW2RXDMA */ 2379 .start_ring_id = HAL_SRNG_SW2RXDMA_BUF0, 2380 .max_rings = 3, 2381 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2382 .lmac_ring = TRUE, 2383 .ring_dir = HAL_SRNG_SRC_RING, 2384 /* reg_start is not set because LMAC rings are not accessed 2385 * from host 2386 */ 2387 .reg_start = {}, 2388 .reg_size = {}, 2389 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2390 .dmac_cmn_ring = TRUE, 2391 }, 2392 }; 2393 2394 /** 2395 * hal_srng_hw_reg_offset_init_qca5332() - Initialize the HW srng reg offset 2396 * applicable only for qca5332 2397 * @hal_soc: HAL Soc handle 2398 * 2399 * Return: None 2400 */ 2401 static inline void hal_srng_hw_reg_offset_init_qca5332(struct hal_soc *hal_soc) 2402 { 2403 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 2404 2405 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB), 2406 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB), 2407 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA), 2408 hw_reg_offset[DST_PRODUCER_INT2_SETUP] = 2409 REG_OFFSET(DST, PRODUCER_INT2_SETUP); 2410 } 2411 2412 /** 2413 * hal_qca5332_attach()- Attach 5332 target specific hal_soc ops, 2414 * offset and srng table 2415 * Return: void 2416 */ 2417 void hal_qca5332_attach(struct hal_soc *hal_soc) 2418 { 2419 hal_soc->hw_srng_table = hw_srng_table_5332; 2420 2421 hal_srng_hw_reg_offset_init_generic(hal_soc); 2422 hal_srng_hw_reg_offset_init_qca5332(hal_soc); 2423 2424 hal_hw_txrx_default_ops_attach_be(hal_soc); 2425 hal_hw_txrx_ops_attach_qca5332(hal_soc); 2426 hal_soc->dmac_cmn_src_rxbuf_ring = true; 2427 } 2428