1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE 16 */ 17 #include "qdf_types.h" 18 #include "qdf_util.h" 19 #include "qdf_mem.h" 20 #include "qdf_nbuf.h" 21 #include "qdf_module.h" 22 23 #include "target_type.h" 24 #include "wcss_version.h" 25 26 #include "hal_be_hw_headers.h" 27 #include "hal_internal.h" 28 #include "hal_api.h" 29 #include "hal_flow.h" 30 #include "rx_flow_search_entry.h" 31 #include "hal_rx_flow_info.h" 32 #include "hal_be_api.h" 33 #include "tcl_entrance_from_ppe_ring.h" 34 #include "sw_monitor_ring.h" 35 #include "wcss_seq_hwioreg_umac.h" 36 #include "wfss_ce_reg_seq_hwioreg.h" 37 #include <uniform_reo_status_header.h> 38 #include <wbm_release_ring_tx.h> 39 #include <phyrx_location.h> 40 #ifdef QCA_MONITOR_2_0_SUPPORT 41 #include <mon_ingress_ring.h> 42 #include <mon_destination_ring.h> 43 #endif 44 #include "rx_reo_queue_1k.h" 45 46 #include <hal_be_rx.h> 47 48 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 49 RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 50 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 51 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 52 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 53 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 54 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 55 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 56 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 57 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 58 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 59 STATUS_HEADER_REO_STATUS_NUMBER 60 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 61 STATUS_HEADER_TIMESTAMP 62 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 64 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 65 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 66 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 67 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 68 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 69 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 70 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 71 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 72 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 73 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 74 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 75 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 76 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 77 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 78 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 79 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 80 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 81 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 82 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 83 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 84 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 85 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 86 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 87 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 88 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 89 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 90 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 91 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 92 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 93 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 94 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 95 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 96 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 97 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 98 99 #include "hal_be_api_mon.h" 100 101 #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0 102 #define CMEM_REG_BASE 0x0010e000 103 104 #define CMEM_WINDOW_ADDRESS_5332 \ 105 ((CMEM_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 106 #endif 107 108 #define CE_WINDOW_ADDRESS_5332 \ 109 ((CE_CFG_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 110 111 #define UMAC_WINDOW_ADDRESS_5332 \ 112 ((UMAC_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 113 114 #ifdef CONFIG_WIFI_EMULATION_WIFI_3_0 115 #define WINDOW_CONFIGURATION_VALUE_5332 \ 116 ((CE_WINDOW_ADDRESS_5332 << 6) |\ 117 (UMAC_WINDOW_ADDRESS_5332 << 12) | \ 118 CMEM_WINDOW_ADDRESS_5332 | \ 119 WINDOW_ENABLE_BIT) 120 #else 121 #define WINDOW_CONFIGURATION_VALUE_5332 \ 122 ((CE_WINDOW_ADDRESS_5332 << 6) |\ 123 (UMAC_WINDOW_ADDRESS_5332 << 12) | \ 124 WINDOW_ENABLE_BIT) 125 #endif 126 127 /* For Berryllium sw2rxdma ring size increased to 20 bits */ 128 #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF 129 130 #ifdef CONFIG_WORD_BASED_TLV 131 #ifndef BIG_ENDIAN_HOST 132 struct rx_msdu_end_compact_qca5332 { 133 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 134 sw_frame_group_id : 7, // [8:2] 135 reserved_0 : 7, // [15:9] 136 phy_ppdu_id : 16; // [31:16] 137 uint32_t ip_hdr_chksum : 16, // [15:0] 138 reported_mpdu_length : 14, // [29:16] 139 reserved_1a : 2; // [31:30] 140 uint32_t key_id_octet : 8, // [7:0] 141 cce_super_rule : 6, // [13:8] 142 cce_classify_not_done_truncate : 1, // [14:14] 143 cce_classify_not_done_cce_dis : 1, // [15:15] 144 cumulative_l3_checksum : 16; // [31:16] 145 uint32_t rule_indication_31_0 : 32; // [31:0] 146 uint32_t rule_indication_63_32 : 32; // [31:0] 147 uint32_t da_offset : 6, // [5:0] 148 sa_offset : 6, // [11:6] 149 da_offset_valid : 1, // [12:12] 150 sa_offset_valid : 1, // [13:13] 151 reserved_5a : 2, // [15:14] 152 l3_type : 16; // [31:16] 153 uint32_t ipv6_options_crc : 32; // [31:0] 154 uint32_t tcp_seq_number : 32; // [31:0] 155 uint32_t tcp_ack_number : 32; // [31:0] 156 uint32_t tcp_flag : 9, // [8:0] 157 lro_eligible : 1, // [9:9] 158 reserved_9a : 6, // [15:10] 159 window_size : 16; // [31:16] 160 uint32_t tcp_udp_chksum : 16, // [15:0] 161 sa_idx_timeout : 1, // [16:16] 162 da_idx_timeout : 1, // [17:17] 163 msdu_limit_error : 1, // [18:18] 164 flow_idx_timeout : 1, // [19:19] 165 flow_idx_invalid : 1, // [20:20] 166 wifi_parser_error : 1, // [21:21] 167 amsdu_parser_error : 1, // [22:22] 168 sa_is_valid : 1, // [23:23] 169 da_is_valid : 1, // [24:24] 170 da_is_mcbc : 1, // [25:25] 171 l3_header_padding : 2, // [27:26] 172 first_msdu : 1, // [28:28] 173 last_msdu : 1, // [29:29] 174 tcp_udp_chksum_fail_copy : 1, // [30:30] 175 ip_chksum_fail_copy : 1; // [31:31] 176 uint32_t sa_idx : 16, // [15:0] 177 da_idx_or_sw_peer_id : 16; // [31:16] 178 uint32_t msdu_drop : 1, // [0:0] 179 reo_destination_indication : 5, // [5:1] 180 flow_idx : 20, // [25:6] 181 use_ppe : 1, // [26:26] 182 reserved_12a : 5; // [31:27] 183 uint32_t fse_metadata : 32; // [31:0] 184 uint32_t cce_metadata : 16, // [15:0] 185 sa_sw_peer_id : 16; // [31:16] 186 uint32_t aggregation_count : 8, // [7:0] 187 flow_aggregation_continuation : 1, // [8:8] 188 fisa_timeout : 1, // [9:9] 189 reserved_15a : 22; // [31:10] 190 uint32_t cumulative_l4_checksum : 16, // [15:0] 191 cumulative_ip_length : 16; // [31:16] 192 uint32_t reserved_17a : 6, // [5:0] 193 service_code : 9, // [14:6] 194 priority_valid : 1, // [15:15] 195 intra_bss : 1, // [16:16] 196 dest_chip_id : 2, // [18:17] 197 multicast_echo : 1, // [19:19] 198 wds_learning_event : 1, // [20:20] 199 wds_roaming_event : 1, // [21:21] 200 wds_keep_alive_event : 1, // [22:22] 201 reserved_17b : 9; // [31:23] 202 uint32_t msdu_length : 14, // [13:0] 203 stbc : 1, // [14:14] 204 ipsec_esp : 1, // [15:15] 205 l3_offset : 7, // [22:16] 206 ipsec_ah : 1, // [23:23] 207 l4_offset : 8; // [31:24] 208 uint32_t msdu_number : 8, // [7:0] 209 decap_format : 2, // [9:8] 210 ipv4_proto : 1, // [10:10] 211 ipv6_proto : 1, // [11:11] 212 tcp_proto : 1, // [12:12] 213 udp_proto : 1, // [13:13] 214 ip_frag : 1, // [14:14] 215 tcp_only_ack : 1, // [15:15] 216 da_is_bcast_mcast : 1, // [16:16] 217 toeplitz_hash_sel : 2, // [18:17] 218 ip_fixed_header_valid : 1, // [19:19] 219 ip_extn_header_valid : 1, // [20:20] 220 tcp_udp_header_valid : 1, // [21:21] 221 mesh_control_present : 1, // [22:22] 222 ldpc : 1, // [23:23] 223 ip4_protocol_ip6_next_header : 8; // [31:24] 224 uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] 225 uint32_t flow_id_toeplitz : 32; // [31:0] 226 uint32_t user_rssi : 8, // [7:0] 227 pkt_type : 4, // [11:8] 228 sgi : 2, // [13:12] 229 rate_mcs : 4, // [17:14] 230 receive_bandwidth : 3, // [20:18] 231 reception_type : 3, // [23:21] 232 mimo_ss_bitmap : 8; // [31:24] 233 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 234 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 235 uint32_t sw_phy_meta_data : 32; // [31:0] 236 uint32_t vlan_ctag_ci : 16, // [15:0] 237 vlan_stag_ci : 16; // [31:16] 238 uint32_t reserved_27a : 32; // [31:0] 239 uint32_t reserved_28a : 32; // [31:0] 240 uint32_t reserved_29a : 32; // [31:0] 241 uint32_t first_mpdu : 1, // [0:0] 242 reserved_30a : 1, // [1:1] 243 mcast_bcast : 1, // [2:2] 244 ast_index_not_found : 1, // [3:3] 245 ast_index_timeout : 1, // [4:4] 246 power_mgmt : 1, // [5:5] 247 non_qos : 1, // [6:6] 248 null_data : 1, // [7:7] 249 mgmt_type : 1, // [8:8] 250 ctrl_type : 1, // [9:9] 251 more_data : 1, // [10:10] 252 eosp : 1, // [11:11] 253 a_msdu_error : 1, // [12:12] 254 fragment_flag : 1, // [13:13] 255 order : 1, // [14:14] 256 cce_match : 1, // [15:15] 257 overflow_err : 1, // [16:16] 258 msdu_length_err : 1, // [17:17] 259 tcp_udp_chksum_fail : 1, // [18:18] 260 ip_chksum_fail : 1, // [19:19] 261 sa_idx_invalid : 1, // [20:20] 262 da_idx_invalid : 1, // [21:21] 263 reserved_30b : 1, // [22:22] 264 rx_in_tx_decrypt_byp : 1, // [23:23] 265 encrypt_required : 1, // [24:24] 266 directed : 1, // [25:25] 267 buffer_fragment : 1, // [26:26] 268 mpdu_length_err : 1, // [27:27] 269 tkip_mic_err : 1, // [28:28] 270 decrypt_err : 1, // [29:29] 271 unencrypted_frame_err : 1, // [30:30] 272 fcs_err : 1; // [31:31] 273 uint32_t reserved_31a : 10, // [9:0] 274 decrypt_status_code : 3, // [12:10] 275 rx_bitmap_not_updated : 1, // [13:13] 276 reserved_31b : 17, // [30:14] 277 msdu_done : 1; // [31:31] 278 279 }; 280 281 struct rx_mpdu_start_compact_qca5332 { 282 struct rxpt_classify_info rxpt_classify_info_details; 283 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 284 uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] 285 receive_queue_number : 16, // [23:8] 286 pre_delim_err_warning : 1, // [24:24] 287 first_delim_err : 1, // [25:25] 288 reserved_2a : 6; // [31:26] 289 uint32_t pn_31_0 : 32; // [31:0] 290 uint32_t pn_63_32 : 32; // [31:0] 291 uint32_t pn_95_64 : 32; // [31:0] 292 uint32_t pn_127_96 : 32; // [31:0] 293 uint32_t epd_en : 1, // [0:0] 294 all_frames_shall_be_encrypted : 1, // [1:1] 295 encrypt_type : 4, // [5:2] 296 wep_key_width_for_variable_key : 2, // [7:6] 297 mesh_sta : 2, // [9:8] 298 bssid_hit : 1, // [10:10] 299 bssid_number : 4, // [14:11] 300 tid : 4, // [18:15] 301 reserved_7a : 13; // [31:19] 302 uint32_t peer_meta_data : 32; // [31:0] 303 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 304 sw_frame_group_id : 7, // [8:2] 305 ndp_frame : 1, // [9:9] 306 phy_err : 1, // [10:10] 307 phy_err_during_mpdu_header : 1, // [11:11] 308 protocol_version_err : 1, // [12:12] 309 ast_based_lookup_valid : 1, // [13:13] 310 ranging : 1, // [14:14] 311 reserved_9a : 1, // [15:15] 312 phy_ppdu_id : 16; // [31:16] 313 uint32_t ast_index : 16, // [15:0] 314 sw_peer_id : 16; // [31:16] 315 uint32_t mpdu_frame_control_valid : 1, // [0:0] 316 mpdu_duration_valid : 1, // [1:1] 317 mac_addr_ad1_valid : 1, // [2:2] 318 mac_addr_ad2_valid : 1, // [3:3] 319 mac_addr_ad3_valid : 1, // [4:4] 320 mac_addr_ad4_valid : 1, // [5:5] 321 mpdu_sequence_control_valid : 1, // [6:6] 322 mpdu_qos_control_valid : 1, // [7:7] 323 mpdu_ht_control_valid : 1, // [8:8] 324 frame_encryption_info_valid : 1, // [9:9] 325 mpdu_fragment_number : 4, // [13:10] 326 more_fragment_flag : 1, // [14:14] 327 reserved_11a : 1, // [15:15] 328 fr_ds : 1, // [16:16] 329 to_ds : 1, // [17:17] 330 encrypted : 1, // [18:18] 331 mpdu_retry : 1, // [19:19] 332 mpdu_sequence_number : 12; // [31:20] 333 uint32_t key_id_octet : 8, // [7:0] 334 new_peer_entry : 1, // [8:8] 335 decrypt_needed : 1, // [9:9] 336 decap_type : 2, // [11:10] 337 rx_insert_vlan_c_tag_padding : 1, // [12:12] 338 rx_insert_vlan_s_tag_padding : 1, // [13:13] 339 strip_vlan_c_tag_decap : 1, // [14:14] 340 strip_vlan_s_tag_decap : 1, // [15:15] 341 pre_delim_count : 12, // [27:16] 342 ampdu_flag : 1, // [28:28] 343 bar_frame : 1, // [29:29] 344 raw_mpdu : 1, // [30:30] 345 reserved_12 : 1; // [31:31] 346 uint32_t mpdu_length : 14, // [13:0] 347 first_mpdu : 1, // [14:14] 348 mcast_bcast : 1, // [15:15] 349 ast_index_not_found : 1, // [16:16] 350 ast_index_timeout : 1, // [17:17] 351 power_mgmt : 1, // [18:18] 352 non_qos : 1, // [19:19] 353 null_data : 1, // [20:20] 354 mgmt_type : 1, // [21:21] 355 ctrl_type : 1, // [22:22] 356 more_data : 1, // [23:23] 357 eosp : 1, // [24:24] 358 fragment_flag : 1, // [25:25] 359 order : 1, // [26:26] 360 u_apsd_trigger : 1, // [27:27] 361 encrypt_required : 1, // [28:28] 362 directed : 1, // [29:29] 363 amsdu_present : 1, // [30:30] 364 reserved_13 : 1; // [31:31] 365 uint32_t mpdu_frame_control_field : 16, // [15:0] 366 mpdu_duration_field : 16; // [31:16] 367 uint32_t mac_addr_ad1_31_0 : 32; // [31:0] 368 uint32_t mac_addr_ad1_47_32 : 16, // [15:0] 369 mac_addr_ad2_15_0 : 16; // [31:16] 370 uint32_t mac_addr_ad2_47_16 : 32; // [31:0] 371 uint32_t mac_addr_ad3_31_0 : 32; // [31:0] 372 uint32_t mac_addr_ad3_47_32 : 16, // [15:0] 373 mpdu_sequence_control_field : 16; // [31:16] 374 uint32_t mac_addr_ad4_31_0 : 32; // [31:0] 375 uint32_t mac_addr_ad4_47_32 : 16, // [15:0] 376 mpdu_qos_control_field : 16; // [31:16] 377 uint32_t mpdu_ht_control_field : 32; // [31:0] 378 uint32_t vdev_id : 8, // [7:0] 379 service_code : 9, // [16:8] 380 priority_valid : 1, // [17:17] 381 src_info : 12, // [29:18] 382 reserved_23a : 1, // [30:30] 383 multi_link_addr_ad1_ad2_valid : 1; // [31:31] 384 uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] 385 uint32_t multi_link_addr_ad1_47_32 : 16, // [15:0] 386 multi_link_addr_ad2_15_0 : 16; // [31:16] 387 uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] 388 uint32_t reserved_27a : 32; // [31:0] 389 uint32_t reserved_28a : 32; // [31:0] 390 uint32_t reserved_29a : 32; // [31:0] 391 }; 392 #else 393 struct rx_msdu_end_compact_qca5332 { 394 uint32_t phy_ppdu_id : 16, // [31:16] 395 reserved_0 : 7, // [15:9] 396 sw_frame_group_id : 7, // [8:2] 397 rxpcu_mpdu_filter_in_category : 2; // [1:0] 398 uint32_t reserved_1a : 2, // [31:30] 399 reported_mpdu_length : 14, // [29:16] 400 ip_hdr_chksum : 16; // [15:0] 401 uint32_t cumulative_l3_checksum : 16, // [31:16] 402 cce_classify_not_done_cce_dis : 1, // [15:15] 403 cce_classify_not_done_truncate : 1, // [14:14] 404 cce_super_rule : 6, // [13:8] 405 key_id_octet : 8; // [7:0] 406 uint32_t rule_indication_31_0 : 32; // [31:0] 407 uint32_t rule_indication_63_32 : 32; // [31:0] 408 uint32_t l3_type : 16, // [31:16] 409 reserved_5a : 2, // [15:14] 410 sa_offset_valid : 1, // [13:13] 411 da_offset_valid : 1, // [12:12] 412 sa_offset : 6, // [11:6] 413 da_offset : 6; // [5:0] 414 uint32_t ipv6_options_crc : 32; // [31:0] 415 uint32_t tcp_seq_number : 32; // [31:0] 416 uint32_t tcp_ack_number : 32; // [31:0] 417 uint32_t window_size : 16, // [31:16] 418 reserved_9a : 6, // [15:10] 419 lro_eligible : 1, // [9:9] 420 tcp_flag : 9; // [8:0] 421 uint32_t ip_chksum_fail_copy : 1, // [31:31] 422 tcp_udp_chksum_fail_copy : 1, // [30:30] 423 last_msdu : 1, // [29:29] 424 first_msdu : 1, // [28:28] 425 l3_header_padding : 2, // [27:26] 426 da_is_mcbc : 1, // [25:25] 427 da_is_valid : 1, // [24:24] 428 sa_is_valid : 1, // [23:23] 429 amsdu_parser_error : 1, // [22:22] 430 wifi_parser_error : 1, // [21:21] 431 flow_idx_invalid : 1, // [20:20] 432 flow_idx_timeout : 1, // [19:19] 433 msdu_limit_error : 1, // [18:18] 434 da_idx_timeout : 1, // [17:17] 435 sa_idx_timeout : 1, // [16:16] 436 tcp_udp_chksum : 16; // [15:0] 437 uint32_t da_idx_or_sw_peer_id : 16, // [31:16] 438 sa_idx : 16; // [15:0] 439 uint32_t reserved_12a : 5, // [31:27] 440 use_ppe : 1, // [26:26] 441 flow_idx : 20, // [25:6] 442 reo_destination_indication : 5, // [5:1] 443 msdu_drop : 1; // [0:0] 444 uint32_t fse_metadata : 32; // [31:0] 445 uint32_t sa_sw_peer_id : 16, // [31:16] 446 cce_metadata : 16; // [15:0] 447 uint32_t reserved_15a : 22, // [31:10] 448 fisa_timeout : 1, // [9:9] 449 flow_aggregation_continuation : 1, // [8:8] 450 aggregation_count : 8; // [7:0] 451 uint32_t cumulative_ip_length : 16, // [31:16] 452 cumulative_l4_checksum : 16; // [15:0] 453 uint32_t reserved_17b : 9, // [31:23] 454 wds_keep_alive_event : 1, // [22:22] 455 wds_roaming_event : 1, // [21:21] 456 wds_learning_event : 1, // [20:20] 457 multicast_echo : 1, // [19:19] 458 dest_chip_id : 2, // [18:17] 459 intra_bss : 1, // [16:16] 460 priority_valid : 1, // [15:15] 461 service_code : 9, // [14:6] 462 reserved_17a : 6; // [5:0] 463 uint32_t l4_offset : 8, // [31:24] 464 ipsec_ah : 1, // [23:23] 465 l3_offset : 7, // [22:16] 466 ipsec_esp : 1, // [15:15] 467 stbc : 1, // [14:14] 468 msdu_length : 14; // [13:0] 469 uint32_t ip4_protocol_ip6_next_header : 8, // [31:24] 470 ldpc : 1, // [23:23] 471 mesh_control_present : 1, // [22:22] 472 tcp_udp_header_valid : 1, // [21:21] 473 ip_extn_header_valid : 1, // [20:20] 474 ip_fixed_header_valid : 1, // [19:19] 475 toeplitz_hash_sel : 2, // [18:17] 476 da_is_bcast_mcast : 1, // [16:16] 477 tcp_only_ack : 1, // [15:15] 478 ip_frag : 1, // [14:14] 479 udp_proto : 1, // [13:13] 480 tcp_proto : 1, // [12:12] 481 ipv6_proto : 1, // [11:11] 482 ipv4_proto : 1, // [10:10] 483 decap_format : 2, // [9:8] 484 msdu_number : 8; // [7:0] 485 uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] 486 uint32_t flow_id_toeplitz : 32; // [31:0] 487 uint32_t mimo_ss_bitmap : 8, // [31:24] 488 reception_type : 3, // [23:21] 489 receive_bandwidth : 3, // [20:18] 490 rate_mcs : 4, // [17:14] 491 sgi : 2, // [13:12] 492 pkt_type : 4, // [11:8] 493 user_rssi : 8; // [7:0] 494 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 495 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 496 uint32_t sw_phy_meta_data : 32; // [31:0] 497 uint32_t vlan_stag_ci : 16, // [31:16] 498 vlan_ctag_ci : 16; // [15:0] 499 uint32_t reserved_27a : 32; // [31:0] 500 uint32_t reserved_28a : 32; // [31:0] 501 uint32_t reserved_29a : 32; // [31:0] 502 uint32_t fcs_err : 1, // [31:31] 503 unencrypted_frame_err : 1, // [30:30] 504 decrypt_err : 1, // [29:29] 505 tkip_mic_err : 1, // [28:28] 506 mpdu_length_err : 1, // [27:27] 507 buffer_fragment : 1, // [26:26] 508 directed : 1, // [25:25] 509 encrypt_required : 1, // [24:24] 510 rx_in_tx_decrypt_byp : 1, // [23:23] 511 reserved_30b : 1, // [22:22] 512 da_idx_invalid : 1, // [21:21] 513 sa_idx_invalid : 1, // [20:20] 514 ip_chksum_fail : 1, // [19:19] 515 tcp_udp_chksum_fail : 1, // [18:18] 516 msdu_length_err : 1, // [17:17] 517 overflow_err : 1, // [16:16] 518 cce_match : 1, // [15:15] 519 order : 1, // [14:14] 520 fragment_flag : 1, // [13:13] 521 a_msdu_error : 1, // [12:12] 522 eosp : 1, // [11:11] 523 more_data : 1, // [10:10] 524 ctrl_type : 1, // [9:9] 525 mgmt_type : 1, // [8:8] 526 null_data : 1, // [7:7] 527 non_qos : 1, // [6:6] 528 power_mgmt : 1, // [5:5] 529 ast_index_timeout : 1, // [4:4] 530 ast_index_not_found : 1, // [3:3] 531 mcast_bcast : 1, // [2:2] 532 reserved_30a : 1, // [1:1] 533 first_mpdu : 1; // [0:0] 534 uint32_t msdu_done : 1, // [31:31] 535 reserved_31b : 17, // [30:14] 536 rx_bitmap_not_updated : 1, // [13:13] 537 decrypt_status_code : 3, // [12:10] 538 reserved_31a : 10; // [9:0] 539 }; 540 541 struct rx_mpdu_start_compact_qca5332 { 542 struct rxpt_classify_info rxpt_classify_info_details; 543 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 544 uint32_t reserved_2a : 6, // [31:26] 545 first_delim_err : 1, // [25:25] 546 pre_delim_err_warning : 1, // [24:24] 547 receive_queue_number : 16, // [23:8] 548 rx_reo_queue_desc_addr_39_32 : 8; // [7:0] 549 uint32_t pn_31_0 : 32; // [31:0] 550 uint32_t pn_63_32 : 32; // [31:0] 551 uint32_t pn_95_64 : 32; // [31:0] 552 uint32_t pn_127_96 : 32; // [31:0] 553 uint32_t reserved_7a : 13, // [31:19] 554 tid : 4, // [18:15] 555 bssid_number : 4, // [14:11] 556 bssid_hit : 1, // [10:10] 557 mesh_sta : 2, // [9:8] 558 wep_key_width_for_variable_key : 2, // [7:6] 559 encrypt_type : 4, // [5:2] 560 all_frames_shall_be_encrypted : 1, // [1:1] 561 epd_en : 1; // [0:0] 562 uint32_t peer_meta_data : 32; // [31:0] 563 uint32_t phy_ppdu_id : 16, // [31:16] 564 reserved_9a : 1, // [15:15] 565 ranging : 1, // [14:14] 566 ast_based_lookup_valid : 1, // [13:13] 567 protocol_version_err : 1, // [12:12] 568 phy_err_during_mpdu_header : 1, // [11:11] 569 phy_err : 1, // [10:10] 570 ndp_frame : 1, // [9:9] 571 sw_frame_group_id : 7, // [8:2] 572 rxpcu_mpdu_filter_in_category : 2; // [1:0] 573 uint32_t sw_peer_id : 16, // [31:16] 574 ast_index : 16; // [15:0] 575 uint32_t mpdu_sequence_number : 12, // [31:20] 576 mpdu_retry : 1, // [19:19] 577 encrypted : 1, // [18:18] 578 to_ds : 1, // [17:17] 579 fr_ds : 1, // [16:16] 580 reserved_11a : 1, // [15:15] 581 more_fragment_flag : 1, // [14:14] 582 mpdu_fragment_number : 4, // [13:10] 583 frame_encryption_info_valid : 1, // [9:9] 584 mpdu_ht_control_valid : 1, // [8:8] 585 mpdu_qos_control_valid : 1, // [7:7] 586 mpdu_sequence_control_valid : 1, // [6:6] 587 mac_addr_ad4_valid : 1, // [5:5] 588 mac_addr_ad3_valid : 1, // [4:4] 589 mac_addr_ad2_valid : 1, // [3:3] 590 mac_addr_ad1_valid : 1, // [2:2] 591 mpdu_duration_valid : 1, // [1:1] 592 mpdu_frame_control_valid : 1; // [0:0] 593 uint32_t reserved_12 : 1, // [31:31] 594 raw_mpdu : 1, // [30:30] 595 bar_frame : 1, // [29:29] 596 ampdu_flag : 1, // [28:28] 597 pre_delim_count : 12, // [27:16] 598 strip_vlan_s_tag_decap : 1, // [15:15] 599 strip_vlan_c_tag_decap : 1, // [14:14] 600 rx_insert_vlan_s_tag_padding : 1, // [13:13] 601 rx_insert_vlan_c_tag_padding : 1, // [12:12] 602 decap_type : 2, // [11:10] 603 decrypt_needed : 1, // [9:9] 604 new_peer_entry : 1, // [8:8] 605 key_id_octet : 8; // [7:0] 606 uint32_t reserved_13 : 1, // [31:31] 607 amsdu_present : 1, // [30:30] 608 directed : 1, // [29:29] 609 encrypt_required : 1, // [28:28] 610 u_apsd_trigger : 1, // [27:27] 611 order : 1, // [26:26] 612 fragment_flag : 1, // [25:25] 613 eosp : 1, // [24:24] 614 more_data : 1, // [23:23] 615 ctrl_type : 1, // [22:22] 616 mgmt_type : 1, // [21:21] 617 null_data : 1, // [20:20] 618 non_qos : 1, // [19:19] 619 power_mgmt : 1, // [18:18] 620 ast_index_timeout : 1, // [17:17] 621 ast_index_not_found : 1, // [16:16] 622 mcast_bcast : 1, // [15:15] 623 first_mpdu : 1, // [14:14] 624 mpdu_length : 14; // [13:0] 625 uint32_t mpdu_duration_field : 16, // [31:16] 626 mpdu_frame_control_field : 16; // [15:0] 627 uint32_t mac_addr_ad1_31_0 : 32; // [31:0] 628 uint32_t mac_addr_ad2_15_0 : 16, // [31:16] 629 mac_addr_ad1_47_32 : 16; // [15:0] 630 uint32_t mac_addr_ad2_47_16 : 32; // [31:0] 631 uint32_t mac_addr_ad3_31_0 : 32; // [31:0] 632 uint32_t mpdu_sequence_control_field : 16, // [31:16] 633 mac_addr_ad3_47_32 : 16; // [15:0] 634 uint32_t mac_addr_ad4_31_0 : 32; // [31:0] 635 uint32_t mpdu_qos_control_field : 16, // [31:16] 636 mac_addr_ad4_47_32 : 16; // [15:0] 637 uint32_t mpdu_ht_control_field : 32; // [31:0] 638 uint32_t multi_link_addr_ad1_ad2_valid : 1, // [31:31] 639 reserved_23a : 1, // [30:30] 640 src_info : 12, // [29:18] 641 priority_valid : 1, // [17:17] 642 service_code : 9, // [16:8] 643 vdev_id : 8; // [7:0] 644 uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] 645 uint32_t multi_link_addr_ad2_15_0 : 16, // [31:16] 646 multi_link_addr_ad1_47_32 : 16; // [15:0] 647 uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] 648 uint32_t reserved_27a : 32; // [31:0] 649 uint32_t reserved_28a : 32; // [31:0] 650 uint32_t reserved_29a : 32; // [31:0] 651 }; 652 #endif /* BIG_ENDIAN_HOST */ 653 654 /* TLV struct for word based Tlv */ 655 typedef struct rx_mpdu_start_compact_qca5332 hal_rx_mpdu_start_t; 656 typedef struct rx_msdu_end_compact_qca5332 hal_rx_msdu_end_t; 657 #endif /* CONFIG_WORD_BASED_TLV */ 658 659 #include "hal_5332_rx.h" 660 #include "hal_5332_tx.h" 661 #include "hal_be_rx_tlv.h" 662 #include <hal_be_generic_api.h> 663 664 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 665 #define HAL_PPE_VP_ENTRIES_MAX 32 666 /** 667 * hal_get_link_desc_size_5332(): API to get the link desc size 668 * 669 * Return: uint32_t 670 */ 671 static uint32_t hal_get_link_desc_size_5332(void) 672 { 673 return LINK_DESC_SIZE; 674 } 675 676 /** 677 * hal_rx_get_tlv_5332(): API to get the tlv 678 * 679 * @rx_tlv: TLV data extracted from the rx packet 680 * Return: uint8_t 681 */ 682 static uint8_t hal_rx_get_tlv_5332(void *rx_tlv) 683 { 684 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH); 685 } 686 687 /** 688 * hal_rx_wbm_err_msdu_continuation_get_5332 () - API to check if WBM 689 * msdu continuation bit is set 690 * 691 *@wbm_desc: wbm release ring descriptor 692 * 693 * Return: true if msdu continuation bit is set. 694 */ 695 uint8_t hal_rx_wbm_err_msdu_continuation_get_5332(void *wbm_desc) 696 { 697 uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) + 698 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET); 699 700 return (comp_desc & 701 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >> 702 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB; 703 } 704 705 /** 706 * hal_rx_proc_phyrx_other_receive_info_tlv_5332(): API to get tlv info 707 * 708 * Return: uint32_t 709 */ 710 static inline 711 void hal_rx_proc_phyrx_other_receive_info_tlv_5332(void *rx_tlv_hdr, 712 void *ppdu_info_hdl) 713 { 714 uint32_t tlv_tag, tlv_len; 715 uint32_t temp_len, other_tlv_len, other_tlv_tag; 716 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 717 void *other_tlv_hdr = NULL; 718 void *other_tlv = NULL; 719 720 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 721 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 722 temp_len = 0; 723 724 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 725 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 726 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 727 728 temp_len += other_tlv_len; 729 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 730 731 switch (other_tlv_tag) { 732 default: 733 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 734 "%s unhandled TLV type: %d, TLV len:%d", 735 __func__, other_tlv_tag, other_tlv_len); 736 break; 737 } 738 } 739 740 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 741 static inline 742 void hal_rx_get_bb_info_5332(void *rx_tlv, void *ppdu_info_hdl) 743 { 744 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 745 746 ppdu_info->cfr_info.bb_captured_channel = 747 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL); 748 749 ppdu_info->cfr_info.bb_captured_timeout = 750 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT); 751 752 ppdu_info->cfr_info.bb_captured_reason = 753 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON); 754 } 755 756 static inline 757 void hal_rx_get_rtt_info_5332(void *rx_tlv, void *ppdu_info_hdl) 758 { 759 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 760 761 ppdu_info->cfr_info.rx_location_info_valid = 762 HAL_RX_GET(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 763 RX_LOCATION_INFO_VALID); 764 765 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 766 HAL_RX_GET(rx_tlv, 767 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 768 RTT_CHE_BUFFER_POINTER_LOW32); 769 770 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 771 HAL_RX_GET(rx_tlv, 772 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 773 RTT_CHE_BUFFER_POINTER_HIGH8); 774 775 ppdu_info->cfr_info.chan_capture_status = 776 HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv); 777 778 ppdu_info->cfr_info.rx_start_ts = 779 HAL_RX_GET(rx_tlv, 780 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 781 RX_START_TS); 782 783 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) 784 HAL_RX_GET(rx_tlv, 785 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 786 RTT_CFO_MEASUREMENT); 787 788 ppdu_info->cfr_info.agc_gain_info0 = 789 HAL_RX_GET(rx_tlv, 790 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 791 GAIN_CHAIN0); 792 793 ppdu_info->cfr_info.agc_gain_info0 |= 794 (((uint32_t)HAL_RX_GET(rx_tlv, 795 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 796 GAIN_CHAIN1)) << 16); 797 798 ppdu_info->cfr_info.agc_gain_info1 = 799 HAL_RX_GET(rx_tlv, 800 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 801 GAIN_CHAIN2); 802 803 ppdu_info->cfr_info.agc_gain_info1 |= 804 (((uint32_t)HAL_RX_GET(rx_tlv, 805 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 806 GAIN_CHAIN3)) << 16); 807 808 ppdu_info->cfr_info.agc_gain_info2 = 0; 809 810 ppdu_info->cfr_info.agc_gain_info3 = 0; 811 } 812 #endif 813 814 /** 815 * hal_rx_dump_mpdu_start_tlv_5332: dump RX mpdu_start TLV in structured 816 * human readable format. 817 * @mpdu_start: pointer the rx_attention TLV in pkt. 818 * @dbg_level: log level. 819 * 820 * Return: void 821 */ 822 static inline void hal_rx_dump_mpdu_start_tlv_5332(void *mpdustart, 823 uint8_t dbg_level) 824 { 825 #ifdef CONFIG_WORD_BASED_TLV 826 struct rx_mpdu_start_compact_qca5332 *mpdu_info = 827 (struct rx_mpdu_start_compact_qca5332 *)mpdustart; 828 #else 829 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 830 struct rx_mpdu_info *mpdu_info = 831 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 832 #endif 833 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 834 "rx_mpdu_start tlv (1/5) - " 835 "rx_reo_queue_desc_addr_31_0 :%x" 836 "rx_reo_queue_desc_addr_39_32 :%x" 837 "receive_queue_number:%x " 838 "pre_delim_err_warning:%x " 839 "first_delim_err:%x " 840 "reserved_2a:%x " 841 "pn_31_0:%x " 842 "pn_63_32:%x " 843 "pn_95_64:%x " 844 "pn_127_96:%x " 845 "epd_en:%x " 846 "all_frames_shall_be_encrypted :%x" 847 "encrypt_type:%x " 848 "wep_key_width_for_variable_key :%x" 849 "mesh_sta:%x " 850 "bssid_hit:%x " 851 "bssid_number:%x " 852 "tid:%x " 853 "reserved_7a:%x ", 854 mpdu_info->rx_reo_queue_desc_addr_31_0, 855 mpdu_info->rx_reo_queue_desc_addr_39_32, 856 mpdu_info->receive_queue_number, 857 mpdu_info->pre_delim_err_warning, 858 mpdu_info->first_delim_err, 859 mpdu_info->reserved_2a, 860 mpdu_info->pn_31_0, 861 mpdu_info->pn_63_32, 862 mpdu_info->pn_95_64, 863 mpdu_info->pn_127_96, 864 mpdu_info->epd_en, 865 mpdu_info->all_frames_shall_be_encrypted, 866 mpdu_info->encrypt_type, 867 mpdu_info->wep_key_width_for_variable_key, 868 mpdu_info->mesh_sta, 869 mpdu_info->bssid_hit, 870 mpdu_info->bssid_number, 871 mpdu_info->tid, 872 mpdu_info->reserved_7a); 873 874 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 875 "rx_mpdu_start tlv (2/5) - " 876 "ast_index:%x " 877 "sw_peer_id:%x " 878 "mpdu_frame_control_valid:%x " 879 "mpdu_duration_valid:%x " 880 "mac_addr_ad1_valid:%x " 881 "mac_addr_ad2_valid:%x " 882 "mac_addr_ad3_valid:%x " 883 "mac_addr_ad4_valid:%x " 884 "mpdu_sequence_control_valid :%x" 885 "mpdu_qos_control_valid:%x " 886 "mpdu_ht_control_valid:%x " 887 "frame_encryption_info_valid :%x", 888 mpdu_info->ast_index, 889 mpdu_info->sw_peer_id, 890 mpdu_info->mpdu_frame_control_valid, 891 mpdu_info->mpdu_duration_valid, 892 mpdu_info->mac_addr_ad1_valid, 893 mpdu_info->mac_addr_ad2_valid, 894 mpdu_info->mac_addr_ad3_valid, 895 mpdu_info->mac_addr_ad4_valid, 896 mpdu_info->mpdu_sequence_control_valid, 897 mpdu_info->mpdu_qos_control_valid, 898 mpdu_info->mpdu_ht_control_valid, 899 mpdu_info->frame_encryption_info_valid); 900 901 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 902 "rx_mpdu_start tlv (3/5) - " 903 "mpdu_fragment_number:%x " 904 "more_fragment_flag:%x " 905 "reserved_11a:%x " 906 "fr_ds:%x " 907 "to_ds:%x " 908 "encrypted:%x " 909 "mpdu_retry:%x " 910 "mpdu_sequence_number:%x ", 911 mpdu_info->mpdu_fragment_number, 912 mpdu_info->more_fragment_flag, 913 mpdu_info->reserved_11a, 914 mpdu_info->fr_ds, 915 mpdu_info->to_ds, 916 mpdu_info->encrypted, 917 mpdu_info->mpdu_retry, 918 mpdu_info->mpdu_sequence_number); 919 920 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 921 "rx_mpdu_start tlv (4/5) - " 922 "mpdu_frame_control_field:%x " 923 "mpdu_duration_field:%x ", 924 mpdu_info->mpdu_frame_control_field, 925 mpdu_info->mpdu_duration_field); 926 927 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 928 "rx_mpdu_start tlv (5/5) - " 929 "mac_addr_ad1_31_0:%x " 930 "mac_addr_ad1_47_32:%x " 931 "mac_addr_ad2_15_0:%x " 932 "mac_addr_ad2_47_16:%x " 933 "mac_addr_ad3_31_0:%x " 934 "mac_addr_ad3_47_32:%x " 935 "mpdu_sequence_control_field :%x" 936 "mac_addr_ad4_31_0:%x " 937 "mac_addr_ad4_47_32:%x " 938 "mpdu_qos_control_field:%x ", 939 mpdu_info->mac_addr_ad1_31_0, 940 mpdu_info->mac_addr_ad1_47_32, 941 mpdu_info->mac_addr_ad2_15_0, 942 mpdu_info->mac_addr_ad2_47_16, 943 mpdu_info->mac_addr_ad3_31_0, 944 mpdu_info->mac_addr_ad3_47_32, 945 mpdu_info->mpdu_sequence_control_field, 946 mpdu_info->mac_addr_ad4_31_0, 947 mpdu_info->mac_addr_ad4_47_32, 948 mpdu_info->mpdu_qos_control_field); 949 } 950 951 /** 952 * hal_rx_dump_msdu_end_tlv_5332: dump RX msdu_end TLV in structured 953 * human readable format. 954 * @ msdu_end: pointer the msdu_end TLV in pkt. 955 * @ dbg_level: log level. 956 * 957 * Return: void 958 */ 959 static void hal_rx_dump_msdu_end_tlv_5332(void *msduend, 960 uint8_t dbg_level) 961 { 962 #ifdef CONFIG_WORD_BASED_TLV 963 struct rx_msdu_end_compact_qca5332 *msdu_end = 964 (struct rx_msdu_end_compact_qca5332 *)msduend; 965 #else 966 struct rx_msdu_end *msdu_end = 967 (struct rx_msdu_end *)msduend; 968 #endif 969 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 970 "rx_msdu_end tlv - " 971 "key_id_octet: %d " 972 "cce_super_rule: %d " 973 "cce_classify_not_done_truncat: %d " 974 "cce_classify_not_done_cce_dis: %d " 975 "rule_indication_31_0: %d " 976 "tcp_udp_chksum: %d " 977 "sa_idx_timeout: %d " 978 "da_idx_timeout: %d " 979 "msdu_limit_error: %d " 980 "flow_idx_timeout: %d " 981 "flow_idx_invalid: %d " 982 "wifi_parser_error: %d " 983 "sa_is_valid: %d " 984 "da_is_valid: %d " 985 "da_is_mcbc: %d " 986 "tkip_mic_err: %d " 987 "l3_header_padding: %d " 988 "first_msdu: %d " 989 "last_msdu: %d " 990 "sa_idx: %d " 991 "msdu_drop: %d " 992 "reo_destination_indication: %d " 993 "flow_idx: %d " 994 "fse_metadata: %d " 995 "cce_metadata: %d " 996 "sa_sw_peer_id: %d ", 997 msdu_end->key_id_octet, 998 msdu_end->cce_super_rule, 999 msdu_end->cce_classify_not_done_truncate, 1000 msdu_end->cce_classify_not_done_cce_dis, 1001 msdu_end->rule_indication_31_0, 1002 msdu_end->tcp_udp_chksum, 1003 msdu_end->sa_idx_timeout, 1004 msdu_end->da_idx_timeout, 1005 msdu_end->msdu_limit_error, 1006 msdu_end->flow_idx_timeout, 1007 msdu_end->flow_idx_invalid, 1008 msdu_end->wifi_parser_error, 1009 msdu_end->sa_is_valid, 1010 msdu_end->da_is_valid, 1011 msdu_end->da_is_mcbc, 1012 msdu_end->tkip_mic_err, 1013 msdu_end->l3_header_padding, 1014 msdu_end->first_msdu, 1015 msdu_end->last_msdu, 1016 msdu_end->sa_idx, 1017 msdu_end->msdu_drop, 1018 msdu_end->reo_destination_indication, 1019 msdu_end->flow_idx, 1020 msdu_end->fse_metadata, 1021 msdu_end->cce_metadata, 1022 msdu_end->sa_sw_peer_id); 1023 } 1024 1025 /** 1026 * hal_reo_status_get_header_5332 - Process reo desc info 1027 * @d - Pointer to reo descriptior 1028 * @b - tlv type info 1029 * @h1 - Pointer to hal_reo_status_header where info to be stored 1030 * 1031 * Return - none. 1032 * 1033 */ 1034 static void hal_reo_status_get_header_5332(hal_ring_desc_t ring_desc, 1035 int b, void *h1) 1036 { 1037 uint64_t *d = (uint64_t *)ring_desc; 1038 uint64_t val1 = 0; 1039 struct hal_reo_status_header *h = 1040 (struct hal_reo_status_header *)h1; 1041 1042 /* Offsets of descriptor fields defined in HW headers start 1043 * from the field after TLV header 1044 */ 1045 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr)); 1046 1047 switch (b) { 1048 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1049 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1050 STATUS_HEADER_REO_STATUS_NUMBER)]; 1051 break; 1052 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1053 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1054 STATUS_HEADER_REO_STATUS_NUMBER)]; 1055 break; 1056 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1057 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1058 STATUS_HEADER_REO_STATUS_NUMBER)]; 1059 break; 1060 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1061 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1062 STATUS_HEADER_REO_STATUS_NUMBER)]; 1063 break; 1064 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1065 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1066 STATUS_HEADER_REO_STATUS_NUMBER)]; 1067 break; 1068 case HAL_REO_DESC_THRES_STATUS_TLV: 1069 val1 = 1070 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1071 STATUS_HEADER_REO_STATUS_NUMBER)]; 1072 break; 1073 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1074 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1075 STATUS_HEADER_REO_STATUS_NUMBER)]; 1076 break; 1077 default: 1078 qdf_nofl_err("ERROR: Unknown tlv\n"); 1079 break; 1080 } 1081 h->cmd_num = 1082 HAL_GET_FIELD( 1083 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER, 1084 val1); 1085 h->exec_time = 1086 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1087 CMD_EXECUTION_TIME, val1); 1088 h->status = 1089 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1090 REO_CMD_EXECUTION_STATUS, val1); 1091 switch (b) { 1092 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1093 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1094 STATUS_HEADER_TIMESTAMP)]; 1095 break; 1096 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1097 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1098 STATUS_HEADER_TIMESTAMP)]; 1099 break; 1100 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1101 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1102 STATUS_HEADER_TIMESTAMP)]; 1103 break; 1104 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1105 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1106 STATUS_HEADER_TIMESTAMP)]; 1107 break; 1108 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1109 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1110 STATUS_HEADER_TIMESTAMP)]; 1111 break; 1112 case HAL_REO_DESC_THRES_STATUS_TLV: 1113 val1 = 1114 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1115 STATUS_HEADER_TIMESTAMP)]; 1116 break; 1117 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1118 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1119 STATUS_HEADER_TIMESTAMP)]; 1120 break; 1121 default: 1122 qdf_nofl_err("ERROR: Unknown tlv\n"); 1123 break; 1124 } 1125 h->tstamp = 1126 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1); 1127 } 1128 1129 static 1130 void *hal_rx_msdu0_buffer_addr_lsb_5332(void *link_desc_va) 1131 { 1132 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1133 } 1134 1135 static 1136 void *hal_rx_msdu_desc_info_ptr_get_5332(void *msdu0) 1137 { 1138 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1139 } 1140 1141 static 1142 void *hal_ent_mpdu_desc_info_5332(void *ent_ring_desc) 1143 { 1144 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1145 } 1146 1147 static 1148 void *hal_dst_mpdu_desc_info_5332(void *dst_ring_desc) 1149 { 1150 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1151 } 1152 1153 /** 1154 * hal_reo_config_5332(): Set reo config parameters 1155 * @soc: hal soc handle 1156 * @reg_val: value to be set 1157 * @reo_params: reo parameters 1158 * 1159 * Return: void 1160 */ 1161 static void 1162 hal_reo_config_5332(struct hal_soc *soc, 1163 uint32_t reg_val, 1164 struct hal_reo_params *reo_params) 1165 { 1166 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1167 } 1168 1169 /** 1170 * hal_rx_msdu_desc_info_get_ptr_5332() - Get msdu desc info ptr 1171 * @msdu_details_ptr - Pointer to msdu_details_ptr 1172 * 1173 * Return - Pointer to rx_msdu_desc_info structure. 1174 * 1175 */ 1176 static void *hal_rx_msdu_desc_info_get_ptr_5332(void *msdu_details_ptr) 1177 { 1178 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1179 } 1180 1181 /** 1182 * hal_rx_link_desc_msdu0_ptr_5332 - Get pointer to rx_msdu details 1183 * @link_desc - Pointer to link desc 1184 * 1185 * Return - Pointer to rx_msdu_details structure 1186 * 1187 */ 1188 static void *hal_rx_link_desc_msdu0_ptr_5332(void *link_desc) 1189 { 1190 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1191 } 1192 1193 /** 1194 * hal_get_window_address_5332(): Function to get hp/tp address 1195 * @hal_soc: Pointer to hal_soc 1196 * @addr: address offset of register 1197 * 1198 * Return: modified address offset of register 1199 */ 1200 1201 static inline qdf_iomem_t hal_get_window_address_5332(struct hal_soc *hal_soc, 1202 qdf_iomem_t addr) 1203 { 1204 uint32_t offset = addr - hal_soc->dev_base_addr; 1205 qdf_iomem_t new_offset; 1206 1207 /* 1208 * If offset lies within DP register range, use 3rd window to write 1209 * into DP region. 1210 */ 1211 if ((offset ^ UMAC_BASE) < WINDOW_RANGE_MASK) { 1212 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + 1213 (offset & WINDOW_RANGE_MASK)); 1214 /* 1215 * If offset lies within CE register range, use 2nd window to write 1216 * into CE region. 1217 */ 1218 } else if ((offset ^ CE_CFG_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { 1219 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + 1220 (offset & WINDOW_RANGE_MASK)); 1221 } else { 1222 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1223 "%s: ERROR: Accessing Wrong register\n", __func__); 1224 qdf_assert_always(0); 1225 return 0; 1226 } 1227 return new_offset; 1228 } 1229 1230 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1231 { 1232 /* Write value into window configuration register */ 1233 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1234 WINDOW_CONFIGURATION_VALUE_5332); 1235 } 1236 1237 static 1238 void hal_compute_reo_remap_ix2_ix3_5332(uint32_t *ring, uint32_t num_rings, 1239 uint32_t *remap1, uint32_t *remap2) 1240 { 1241 switch (num_rings) { 1242 case 1: 1243 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1244 HAL_REO_REMAP_IX2(ring[0], 17) | 1245 HAL_REO_REMAP_IX2(ring[0], 18) | 1246 HAL_REO_REMAP_IX2(ring[0], 19) | 1247 HAL_REO_REMAP_IX2(ring[0], 20) | 1248 HAL_REO_REMAP_IX2(ring[0], 21) | 1249 HAL_REO_REMAP_IX2(ring[0], 22) | 1250 HAL_REO_REMAP_IX2(ring[0], 23); 1251 1252 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1253 HAL_REO_REMAP_IX3(ring[0], 25) | 1254 HAL_REO_REMAP_IX3(ring[0], 26) | 1255 HAL_REO_REMAP_IX3(ring[0], 27) | 1256 HAL_REO_REMAP_IX3(ring[0], 28) | 1257 HAL_REO_REMAP_IX3(ring[0], 29) | 1258 HAL_REO_REMAP_IX3(ring[0], 30) | 1259 HAL_REO_REMAP_IX3(ring[0], 31); 1260 break; 1261 case 2: 1262 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1263 HAL_REO_REMAP_IX2(ring[0], 17) | 1264 HAL_REO_REMAP_IX2(ring[1], 18) | 1265 HAL_REO_REMAP_IX2(ring[1], 19) | 1266 HAL_REO_REMAP_IX2(ring[0], 20) | 1267 HAL_REO_REMAP_IX2(ring[0], 21) | 1268 HAL_REO_REMAP_IX2(ring[1], 22) | 1269 HAL_REO_REMAP_IX2(ring[1], 23); 1270 1271 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1272 HAL_REO_REMAP_IX3(ring[0], 25) | 1273 HAL_REO_REMAP_IX3(ring[1], 26) | 1274 HAL_REO_REMAP_IX3(ring[1], 27) | 1275 HAL_REO_REMAP_IX3(ring[0], 28) | 1276 HAL_REO_REMAP_IX3(ring[0], 29) | 1277 HAL_REO_REMAP_IX3(ring[1], 30) | 1278 HAL_REO_REMAP_IX3(ring[1], 31); 1279 break; 1280 case 3: 1281 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1282 HAL_REO_REMAP_IX2(ring[1], 17) | 1283 HAL_REO_REMAP_IX2(ring[2], 18) | 1284 HAL_REO_REMAP_IX2(ring[0], 19) | 1285 HAL_REO_REMAP_IX2(ring[1], 20) | 1286 HAL_REO_REMAP_IX2(ring[2], 21) | 1287 HAL_REO_REMAP_IX2(ring[0], 22) | 1288 HAL_REO_REMAP_IX2(ring[1], 23); 1289 1290 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1291 HAL_REO_REMAP_IX3(ring[0], 25) | 1292 HAL_REO_REMAP_IX3(ring[1], 26) | 1293 HAL_REO_REMAP_IX3(ring[2], 27) | 1294 HAL_REO_REMAP_IX3(ring[0], 28) | 1295 HAL_REO_REMAP_IX3(ring[1], 29) | 1296 HAL_REO_REMAP_IX3(ring[2], 30) | 1297 HAL_REO_REMAP_IX3(ring[0], 31); 1298 break; 1299 case 4: 1300 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1301 HAL_REO_REMAP_IX2(ring[1], 17) | 1302 HAL_REO_REMAP_IX2(ring[2], 18) | 1303 HAL_REO_REMAP_IX2(ring[3], 19) | 1304 HAL_REO_REMAP_IX2(ring[0], 20) | 1305 HAL_REO_REMAP_IX2(ring[1], 21) | 1306 HAL_REO_REMAP_IX2(ring[2], 22) | 1307 HAL_REO_REMAP_IX2(ring[3], 23); 1308 1309 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1310 HAL_REO_REMAP_IX3(ring[1], 25) | 1311 HAL_REO_REMAP_IX3(ring[2], 26) | 1312 HAL_REO_REMAP_IX3(ring[3], 27) | 1313 HAL_REO_REMAP_IX3(ring[0], 28) | 1314 HAL_REO_REMAP_IX3(ring[1], 29) | 1315 HAL_REO_REMAP_IX3(ring[2], 30) | 1316 HAL_REO_REMAP_IX3(ring[3], 31); 1317 break; 1318 } 1319 } 1320 1321 /** 1322 * hal_rx_flow_setup_fse_5332() - Setup a flow search entry in HW FST 1323 * @fst: Pointer to the Rx Flow Search Table 1324 * @table_offset: offset into the table where the flow is to be setup 1325 * @flow: Flow Parameters 1326 * 1327 * Return: Success/Failure 1328 */ 1329 static void * 1330 hal_rx_flow_setup_fse_5332(uint8_t *rx_fst, uint32_t table_offset, 1331 uint8_t *rx_flow) 1332 { 1333 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1334 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1335 uint8_t *fse; 1336 bool fse_valid; 1337 1338 if (table_offset >= fst->max_entries) { 1339 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1340 "HAL FSE table offset %u exceeds max entries %u", 1341 table_offset, fst->max_entries); 1342 return NULL; 1343 } 1344 1345 fse = (uint8_t *)fst->base_vaddr + 1346 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1347 1348 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1349 1350 if (fse_valid) { 1351 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1352 "HAL FSE %pK already valid", fse); 1353 return NULL; 1354 } 1355 1356 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) = 1357 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1358 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1359 1360 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) = 1361 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1362 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1363 1364 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) = 1365 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1366 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1367 1368 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) = 1369 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1370 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1371 1372 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) = 1373 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1374 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1375 1376 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) = 1377 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1378 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1379 1380 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) = 1381 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1382 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1383 1384 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) = 1385 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1386 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1387 1388 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT); 1389 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |= 1390 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1391 (flow->tuple_info.dest_port)); 1392 1393 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT); 1394 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |= 1395 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1396 (flow->tuple_info.src_port)); 1397 1398 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL); 1399 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |= 1400 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1401 flow->tuple_info.l4_protocol); 1402 1403 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER); 1404 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |= 1405 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1406 flow->reo_destination_handler); 1407 1408 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1409 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |= 1410 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1411 1412 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA); 1413 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) = 1414 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1415 flow->fse_metadata); 1416 1417 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION); 1418 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |= 1419 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1420 REO_DESTINATION_INDICATION, 1421 flow->reo_destination_indication); 1422 1423 /* Reset all the other fields in FSE */ 1424 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9); 1425 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP); 1426 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT); 1427 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT); 1428 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP); 1429 1430 return fse; 1431 } 1432 1433 #ifndef NO_RX_PKT_HDR_TLV 1434 /** 1435 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 1436 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 1437 * @ dbg_level: log level. 1438 * 1439 * Return: void 1440 */ 1441 static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs, 1442 uint8_t dbg_level) 1443 { 1444 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 1445 1446 hal_verbose_debug("\n---------------\n" 1447 "rx_pkt_hdr_tlv\n" 1448 "---------------\n" 1449 "phy_ppdu_id %llu ", 1450 pkt_hdr_tlv->phy_ppdu_id); 1451 1452 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 1453 sizeof(pkt_hdr_tlv->rx_pkt_hdr)); 1454 } 1455 #else 1456 /** 1457 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 1458 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 1459 * @ dbg_level: log level. 1460 * 1461 * Return: void 1462 */ 1463 static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs, 1464 uint8_t dbg_level) 1465 { 1466 } 1467 #endif 1468 1469 /** 1470 * hal_rx_dump_pkt_tlvs_5332(): API to print RX Pkt TLVS qca5332 1471 * @hal_soc_hdl: hal_soc handle 1472 * @buf: pointer the pkt buffer 1473 * @dbg_level: log level 1474 * 1475 * Return: void 1476 */ 1477 #ifdef CONFIG_WORD_BASED_TLV 1478 static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl, 1479 uint8_t *buf, uint8_t dbg_level) 1480 { 1481 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1482 struct rx_msdu_end_compact_qca5332 *msdu_end = 1483 &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1484 struct rx_mpdu_start_compact_qca5332 *mpdu_start = 1485 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1486 1487 hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level); 1488 hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level); 1489 hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level); 1490 } 1491 #else 1492 static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl, 1493 uint8_t *buf, uint8_t dbg_level) 1494 { 1495 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1496 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1497 struct rx_mpdu_start *mpdu_start = 1498 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1499 1500 hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level); 1501 hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level); 1502 hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level); 1503 } 1504 #endif 1505 1506 #define HAL_NUM_TCL_BANKS_5332 48 1507 1508 /** 1509 * hal_cmem_write_5332() - function for CMEM buffer writing 1510 * @hal_soc_hdl: HAL SOC handle 1511 * @offset: CMEM address 1512 * @value: value to write 1513 * 1514 * Return: None. 1515 */ 1516 static void hal_cmem_write_5332(hal_soc_handle_t hal_soc_hdl, 1517 uint32_t offset, 1518 uint32_t value) 1519 { 1520 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1521 1522 pld_reg_write(hal->qdf_dev->dev, offset, value); 1523 } 1524 1525 /** 1526 * hal_tx_get_num_tcl_banks_5332() - Get number of banks in target 1527 * 1528 * Returns: number of bank 1529 */ 1530 static uint8_t hal_tx_get_num_tcl_banks_5332(void) 1531 { 1532 return HAL_NUM_TCL_BANKS_5332; 1533 } 1534 1535 static void hal_reo_setup_5332(struct hal_soc *soc, void *reoparams) 1536 { 1537 uint32_t reg_val; 1538 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1539 1540 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1541 REO_REG_REG_BASE)); 1542 1543 hal_reo_config_5332(soc, reg_val, reo_params); 1544 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1545 1546 /* TODO: Setup destination ring mapping if enabled */ 1547 1548 /* TODO: Error destination ring setting is left to default. 1549 * Default setting is to send all errors to release ring. 1550 */ 1551 1552 /* Set the reo descriptor swap bits in case of BIG endian platform */ 1553 hal_setup_reo_swap(soc); 1554 1555 HAL_REG_WRITE(soc, 1556 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE), 1557 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1558 1559 HAL_REG_WRITE(soc, 1560 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE), 1561 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1562 1563 HAL_REG_WRITE(soc, 1564 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE), 1565 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1566 1567 HAL_REG_WRITE(soc, 1568 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE), 1569 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1570 1571 /* 1572 * When hash based routing is enabled, routing of the rx packet 1573 * is done based on the following value: 1 _ _ _ _ The last 4 1574 * bits are based on hash[3:0]. This means the possible values 1575 * are 0x10 to 0x1f. This value is used to look-up the 1576 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1577 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1578 * registers need to be configured to set-up the 16 entries to 1579 * map the hash values to a ring number. There are 3 bits per 1580 * hash entry – which are mapped as follows: 1581 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1582 * 7: NOT_USED. 1583 */ 1584 if (reo_params->rx_hash_enabled) { 1585 HAL_REG_WRITE(soc, 1586 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR 1587 (REO_REG_REG_BASE), reo_params->remap0); 1588 1589 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1590 HAL_REG_READ(soc, 1591 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR( 1592 REO_REG_REG_BASE))); 1593 1594 HAL_REG_WRITE(soc, 1595 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 1596 (REO_REG_REG_BASE), reo_params->remap1); 1597 1598 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1599 HAL_REG_READ(soc, 1600 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1601 REO_REG_REG_BASE))); 1602 1603 HAL_REG_WRITE(soc, 1604 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 1605 (REO_REG_REG_BASE), reo_params->remap2); 1606 1607 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1608 HAL_REG_READ(soc, 1609 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1610 REO_REG_REG_BASE))); 1611 } 1612 1613 /* TODO: Check if the following registers shoould be setup by host: 1614 * AGING_CONTROL 1615 * HIGH_MEMORY_THRESHOLD 1616 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1617 * GLOBAL_LINK_DESC_COUNT_CTRL 1618 */ 1619 1620 hal_reo_shared_qaddr_init((hal_soc_handle_t)soc); 1621 } 1622 1623 static uint16_t hal_get_rx_max_ba_window_qca5332(int tid) 1624 { 1625 return HAL_RX_BA_WINDOW_1024; 1626 } 1627 1628 /** 1629 * hal_qca5332_get_reo_qdesc_size()- Get the reo queue descriptor size 1630 * from the give Block-Ack window size 1631 * Return: reo queue descriptor size 1632 */ 1633 static uint32_t hal_qca5332_get_reo_qdesc_size(uint32_t ba_window_size, int tid) 1634 { 1635 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 1636 * NON_QOS_TID until HW issues are resolved. 1637 */ 1638 if (tid != HAL_NON_QOS_TID) 1639 ba_window_size = hal_get_rx_max_ba_window_qca5332(tid); 1640 1641 /* Return descriptor size corresponding to window size of 2 since 1642 * we set ba_window_size to 2 while setting up REO descriptors as 1643 * a WAR to get 2k jump exception aggregates are received without 1644 * a BA session. 1645 */ 1646 if (ba_window_size <= 1) { 1647 if (tid != HAL_NON_QOS_TID) 1648 return sizeof(struct rx_reo_queue) + 1649 sizeof(struct rx_reo_queue_ext); 1650 else 1651 return sizeof(struct rx_reo_queue); 1652 } 1653 1654 if (ba_window_size <= 105) 1655 return sizeof(struct rx_reo_queue) + 1656 sizeof(struct rx_reo_queue_ext); 1657 1658 if (ba_window_size <= 210) 1659 return sizeof(struct rx_reo_queue) + 1660 (2 * sizeof(struct rx_reo_queue_ext)); 1661 1662 if (ba_window_size <= 256) 1663 return sizeof(struct rx_reo_queue) + 1664 (3 * sizeof(struct rx_reo_queue_ext)); 1665 1666 return sizeof(struct rx_reo_queue) + 1667 (10 * sizeof(struct rx_reo_queue_ext)) + 1668 sizeof(struct rx_reo_queue_1k); 1669 } 1670 /** 1671 * hal_rx_tlv_msdu_done_copy_get_5332() - Get msdu done copy bit from rx_tlv 1672 * 1673 * Returns: msdu done copy bit 1674 */ 1675 static inline uint32_t hal_rx_tlv_msdu_done_copy_get_5332(uint8_t *buf) 1676 { 1677 return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf); 1678 } 1679 1680 static void hal_hw_txrx_ops_attach_qca5332(struct hal_soc *hal_soc) 1681 { 1682 /* init and setup */ 1683 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1684 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1685 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1686 hal_soc->ops->hal_get_window_address = hal_get_window_address_5332; 1687 hal_soc->ops->hal_cmem_write = hal_cmem_write_5332; 1688 1689 /* tx */ 1690 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5332; 1691 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5332; 1692 hal_soc->ops->hal_tx_comp_get_status = 1693 hal_tx_comp_get_status_generic_be; 1694 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1695 hal_tx_init_cmd_credit_ring_5332; 1696 hal_soc->ops->hal_tx_set_ppe_cmn_cfg = NULL; 1697 hal_soc->ops->hal_tx_set_ppe_vp_entry = NULL; 1698 hal_soc->ops->hal_tx_set_ppe_pri2tid = NULL; 1699 hal_soc->ops->hal_tx_update_ppe_pri2tid = NULL; 1700 hal_soc->ops->hal_tx_dump_ppe_vp_entry = NULL; 1701 hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = NULL; 1702 hal_soc->ops->hal_tx_enable_pri2tid_map = NULL; 1703 hal_soc->ops->hal_tx_config_rbm_mapping_be = 1704 hal_tx_config_rbm_mapping_be_5332; 1705 1706 /* rx */ 1707 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; 1708 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1709 hal_rx_mon_hw_desc_get_mpdu_status_be; 1710 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5332; 1711 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1712 hal_rx_proc_phyrx_other_receive_info_tlv_5332; 1713 1714 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5332; 1715 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1716 hal_rx_dump_mpdu_start_tlv_5332; 1717 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_5332; 1718 1719 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5332; 1720 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be; 1721 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1722 hal_rx_tlv_reception_type_get_be; 1723 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1724 hal_rx_msdu_end_da_idx_get_be; 1725 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1726 hal_rx_msdu_desc_info_get_ptr_5332; 1727 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1728 hal_rx_link_desc_msdu0_ptr_5332; 1729 hal_soc->ops->hal_reo_status_get_header = 1730 hal_reo_status_get_header_5332; 1731 hal_soc->ops->hal_rx_status_get_tlv_info = 1732 hal_rx_status_get_tlv_info_wrapper_be; 1733 hal_soc->ops->hal_rx_wbm_err_info_get = 1734 hal_rx_wbm_err_info_get_generic_be; 1735 hal_soc->ops->hal_tx_set_pcp_tid_map = 1736 hal_tx_set_pcp_tid_map_generic_be; 1737 hal_soc->ops->hal_tx_update_pcp_tid_map = 1738 hal_tx_update_pcp_tid_generic_be; 1739 hal_soc->ops->hal_tx_set_tidmap_prty = 1740 hal_tx_update_tidmap_prty_generic_be; 1741 hal_soc->ops->hal_rx_get_rx_fragment_number = 1742 hal_rx_get_rx_fragment_number_be, 1743 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1744 hal_rx_tlv_da_is_mcbc_get_be; 1745 hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err = 1746 hal_rx_tlv_is_tkip_mic_err_get_be; 1747 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1748 hal_rx_tlv_sa_is_valid_get_be; 1749 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be; 1750 hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be; 1751 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1752 hal_rx_tlv_l3_hdr_padding_get_be; 1753 hal_soc->ops->hal_rx_encryption_info_valid = 1754 hal_rx_encryption_info_valid_be; 1755 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; 1756 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1757 hal_rx_tlv_first_msdu_get_be; 1758 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1759 hal_rx_tlv_da_is_valid_get_be; 1760 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1761 hal_rx_tlv_last_msdu_get_be; 1762 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1763 hal_rx_get_mpdu_mac_ad4_valid_be; 1764 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1765 hal_rx_mpdu_start_sw_peer_id_get_be; 1766 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1767 hal_rx_mpdu_peer_meta_data_get_be; 1768 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be; 1769 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be; 1770 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1771 hal_rx_get_mpdu_frame_control_valid_be; 1772 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; 1773 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; 1774 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; 1775 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; 1776 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1777 hal_rx_get_mpdu_sequence_control_valid_be; 1778 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; 1779 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; 1780 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1781 hal_rx_hw_desc_get_ppduid_get_be; 1782 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1783 hal_rx_mpdu_start_mpdu_qos_control_valid_get_be; 1784 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1785 hal_rx_msdu_end_sa_sw_peer_id_get_be; 1786 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1787 hal_rx_msdu0_buffer_addr_lsb_5332; 1788 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1789 hal_rx_msdu_desc_info_ptr_get_5332; 1790 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5332; 1791 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5332; 1792 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; 1793 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; 1794 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1795 hal_rx_get_mac_addr2_valid_be; 1796 hal_soc->ops->hal_rx_get_filter_category = 1797 hal_rx_get_filter_category_be; 1798 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be; 1799 hal_soc->ops->hal_reo_config = hal_reo_config_5332; 1800 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; 1801 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1802 hal_rx_msdu_flow_idx_invalid_be; 1803 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1804 hal_rx_msdu_flow_idx_timeout_be; 1805 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1806 hal_rx_msdu_fse_metadata_get_be; 1807 hal_soc->ops->hal_rx_msdu_cce_match_get = 1808 hal_rx_msdu_cce_match_get_be; 1809 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1810 hal_rx_msdu_cce_metadata_get_be; 1811 hal_soc->ops->hal_rx_msdu_get_flow_params = 1812 hal_rx_msdu_get_flow_params_be; 1813 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be; 1814 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be; 1815 #if defined(QCA_WIFI_QCA5332) && defined(WLAN_CFR_ENABLE) && \ 1816 defined(WLAN_ENH_CFR_ENABLE) 1817 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5332; 1818 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5332; 1819 #else 1820 hal_soc->ops->hal_rx_get_bb_info = NULL; 1821 hal_soc->ops->hal_rx_get_rtt_info = NULL; 1822 #endif 1823 /* rx - msdu fast path info fields */ 1824 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1825 hal_rx_msdu_packet_metadata_get_generic_be; 1826 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1827 hal_rx_mpdu_start_tlv_tag_valid_be; 1828 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1829 hal_rx_wbm_err_msdu_continuation_get_5332; 1830 1831 /* rx - TLV struct offsets */ 1832 hal_soc->ops->hal_rx_msdu_end_offset_get = 1833 hal_rx_msdu_end_offset_get_generic; 1834 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1835 hal_rx_mpdu_start_offset_get_generic; 1836 #ifndef NO_RX_PKT_HDR_TLV 1837 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1838 hal_rx_pkt_tlv_offset_get_generic; 1839 #endif 1840 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5332; 1841 1842 hal_soc->ops->hal_rx_flow_get_tuple_info = 1843 hal_rx_flow_get_tuple_info_be; 1844 hal_soc->ops->hal_rx_flow_delete_entry = 1845 hal_rx_flow_delete_entry_be; 1846 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be; 1847 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1848 hal_compute_reo_remap_ix2_ix3_5332; 1849 1850 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 1851 hal_rx_msdu_get_reo_destination_indication_be; 1852 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; 1853 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 1854 hal_rx_msdu_is_wlan_mcast_generic_be; 1855 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_5332; 1856 hal_soc->ops->hal_rx_tlv_decap_format_get = 1857 hal_rx_tlv_decap_format_get_be; 1858 #ifdef RECEIVE_OFFLOAD 1859 hal_soc->ops->hal_rx_tlv_get_offload_info = 1860 hal_rx_tlv_get_offload_info_be; 1861 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; 1862 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; 1863 #endif 1864 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 1865 hal_rx_attn_phy_ppdu_id_get_be; 1866 hal_soc->ops->hal_rx_tlv_msdu_done_get = 1867 hal_rx_tlv_msdu_done_copy_get_5332; 1868 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1869 hal_rx_msdu_start_msdu_len_get_be; 1870 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1871 hal_rx_get_frame_ctrl_field_be; 1872 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; 1873 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1874 hal_rx_mpdu_info_ampdu_flag_get_be; 1875 hal_soc->ops->hal_rx_tlv_msdu_len_set = 1876 hal_rx_msdu_start_msdu_len_set_be; 1877 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; 1878 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; 1879 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be; 1880 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be; 1881 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be; 1882 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1883 hal_rx_tlv_decrypt_err_get_be; 1884 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be; 1885 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 1886 hal_rx_tlv_get_is_decrypted_be; 1887 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be; 1888 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 1889 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1890 hal_rx_priv_info_set_in_tlv_be; 1891 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1892 hal_rx_priv_info_get_from_tlv_be; 1893 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be; 1894 hal_soc->ops->hal_reo_setup = hal_reo_setup_5332; 1895 #ifdef REO_SHARED_QREF_TABLE_EN 1896 hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be; 1897 hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be; 1898 hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be; 1899 hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be; 1900 hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be; 1901 #endif 1902 /* Overwrite the default BE ops */ 1903 hal_soc->ops->hal_get_rx_max_ba_window = 1904 hal_get_rx_max_ba_window_qca5332; 1905 hal_soc->ops->hal_get_reo_qdesc_size = hal_qca5332_get_reo_qdesc_size; 1906 /* TX MONITOR */ 1907 #ifdef QCA_MONITOR_2_0_SUPPORT 1908 hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv = 1909 hal_txmon_is_mon_buf_addr_tlv_generic_be; 1910 hal_soc->ops->hal_txmon_populate_packet_info = 1911 hal_txmon_populate_packet_info_generic_be; 1912 hal_soc->ops->hal_txmon_status_parse_tlv = 1913 hal_txmon_status_parse_tlv_generic_be; 1914 hal_soc->ops->hal_txmon_status_get_num_users = 1915 hal_txmon_status_get_num_users_generic_be; 1916 #endif /* QCA_MONITOR_2_0_SUPPORT */ 1917 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1918 hal_soc->ops->hal_tx_vdev_mismatch_routing_set = 1919 hal_tx_vdev_mismatch_routing_set_generic_be; 1920 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = 1921 hal_tx_mcast_mlo_reinject_routing_set_generic_be; 1922 hal_soc->ops->hal_get_ba_aging_timeout = 1923 hal_get_ba_aging_timeout_be_generic; 1924 hal_soc->ops->hal_setup_link_idle_list = 1925 hal_setup_link_idle_list_generic_be; 1926 hal_soc->ops->hal_cookie_conversion_reg_cfg_be = 1927 hal_cookie_conversion_reg_cfg_generic_be; 1928 hal_soc->ops->hal_set_ba_aging_timeout = 1929 hal_set_ba_aging_timeout_be_generic; 1930 hal_soc->ops->hal_tx_populate_bank_register = 1931 hal_tx_populate_bank_register_be; 1932 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = 1933 hal_tx_vdev_mcast_ctrl_set_be; 1934 }; 1935 1936 struct hal_hw_srng_config hw_srng_table_5332[] = { 1937 /* TODO: max_rings can populated by querying HW capabilities */ 1938 { /* REO_DST */ 1939 .start_ring_id = HAL_SRNG_REO2SW1, 1940 .max_rings = 8, 1941 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1942 .lmac_ring = FALSE, 1943 .ring_dir = HAL_SRNG_DST_RING, 1944 .reg_start = { 1945 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1946 REO_REG_REG_BASE), 1947 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1948 REO_REG_REG_BASE) 1949 }, 1950 .reg_size = { 1951 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1952 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1953 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1954 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1955 }, 1956 .max_size = 1957 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1958 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1959 }, 1960 { /* REO_EXCEPTION */ 1961 /* Designating REO2SW0 ring as exception ring. This ring is 1962 * similar to other REO2SW rings though it is named as REO2SW0. 1963 * Any of theREO2SW rings can be used as exception ring. 1964 */ 1965 .start_ring_id = HAL_SRNG_REO2SW0, 1966 .max_rings = 1, 1967 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1968 .lmac_ring = FALSE, 1969 .ring_dir = HAL_SRNG_DST_RING, 1970 .reg_start = { 1971 HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR( 1972 REO_REG_REG_BASE), 1973 HWIO_REO_R2_REO2SW0_RING_HP_ADDR( 1974 REO_REG_REG_BASE) 1975 }, 1976 /* Single ring - provide ring size if multiple rings of this 1977 * type are supported 1978 */ 1979 .reg_size = {}, 1980 .max_size = 1981 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >> 1982 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT, 1983 }, 1984 { /* REO_REINJECT */ 1985 .start_ring_id = HAL_SRNG_SW2REO, 1986 .max_rings = 4, 1987 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1988 .lmac_ring = FALSE, 1989 .ring_dir = HAL_SRNG_SRC_RING, 1990 .reg_start = { 1991 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1992 REO_REG_REG_BASE), 1993 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1994 REO_REG_REG_BASE) 1995 }, 1996 /* Single ring - provide ring size if multiple rings of this 1997 * type are supported 1998 */ 1999 .reg_size = { 2000 HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) - 2001 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0), 2002 HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) - 2003 HWIO_REO_R2_SW2REO_RING_HP_ADDR(0) 2004 }, 2005 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 2006 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 2007 }, 2008 { /* REO_CMD */ 2009 .start_ring_id = HAL_SRNG_REO_CMD, 2010 .max_rings = 1, 2011 .entry_size = (sizeof(struct tlv_32_hdr) + 2012 sizeof(struct reo_get_queue_stats)) >> 2, 2013 .lmac_ring = FALSE, 2014 .ring_dir = HAL_SRNG_SRC_RING, 2015 .reg_start = { 2016 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 2017 REO_REG_REG_BASE), 2018 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 2019 REO_REG_REG_BASE), 2020 }, 2021 /* Single ring - provide ring size if multiple rings of this 2022 * type are supported 2023 */ 2024 .reg_size = {}, 2025 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 2026 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 2027 }, 2028 { /* REO_STATUS */ 2029 .start_ring_id = HAL_SRNG_REO_STATUS, 2030 .max_rings = 1, 2031 .entry_size = (sizeof(struct tlv_32_hdr) + 2032 sizeof(struct reo_get_queue_stats_status)) >> 2, 2033 .lmac_ring = FALSE, 2034 .ring_dir = HAL_SRNG_DST_RING, 2035 .reg_start = { 2036 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2037 REO_REG_REG_BASE), 2038 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2039 REO_REG_REG_BASE), 2040 }, 2041 /* Single ring - provide ring size if multiple rings of this 2042 * type are supported 2043 */ 2044 .reg_size = {}, 2045 .max_size = 2046 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2047 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2048 }, 2049 { /* TCL_DATA */ 2050 .start_ring_id = HAL_SRNG_SW2TCL1, 2051 .max_rings = 6, 2052 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 2053 .lmac_ring = FALSE, 2054 .ring_dir = HAL_SRNG_SRC_RING, 2055 .reg_start = { 2056 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2057 MAC_TCL_REG_REG_BASE), 2058 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2059 MAC_TCL_REG_REG_BASE), 2060 }, 2061 .reg_size = { 2062 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2063 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2064 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2065 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2066 }, 2067 .max_size = 2068 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2069 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2070 }, 2071 { /* TCL_CMD/CREDIT */ 2072 /* qca8074v2 and qca5332 uses this ring for data commands */ 2073 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2074 .max_rings = 1, 2075 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 2076 .lmac_ring = FALSE, 2077 .ring_dir = HAL_SRNG_SRC_RING, 2078 .reg_start = { 2079 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2080 MAC_TCL_REG_REG_BASE), 2081 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2082 MAC_TCL_REG_REG_BASE), 2083 }, 2084 /* Single ring - provide ring size if multiple rings of this 2085 * type are supported 2086 */ 2087 .reg_size = {}, 2088 .max_size = 2089 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2090 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2091 }, 2092 { /* TCL_STATUS */ 2093 .start_ring_id = HAL_SRNG_TCL_STATUS, 2094 .max_rings = 1, 2095 .entry_size = (sizeof(struct tlv_32_hdr) + 2096 sizeof(struct tcl_status_ring)) >> 2, 2097 .lmac_ring = FALSE, 2098 .ring_dir = HAL_SRNG_DST_RING, 2099 .reg_start = { 2100 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2101 MAC_TCL_REG_REG_BASE), 2102 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2103 MAC_TCL_REG_REG_BASE), 2104 }, 2105 /* Single ring - provide ring size if multiple rings of this 2106 * type are supported 2107 */ 2108 .reg_size = {}, 2109 .max_size = 2110 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2111 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2112 }, 2113 { /* CE_SRC */ 2114 .start_ring_id = HAL_SRNG_CE_0_SRC, 2115 .max_rings = 16, 2116 .entry_size = sizeof(struct ce_src_desc) >> 2, 2117 .lmac_ring = FALSE, 2118 .ring_dir = HAL_SRNG_SRC_RING, 2119 .reg_start = { 2120 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR( 2121 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE), 2122 HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR( 2123 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE), 2124 }, 2125 .reg_size = { 2126 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 2127 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 2128 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 2129 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 2130 }, 2131 .max_size = 2132 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >> 2133 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT, 2134 }, 2135 { /* CE_DST */ 2136 .start_ring_id = HAL_SRNG_CE_0_DST, 2137 .max_rings = 16, 2138 .entry_size = 8 >> 2, 2139 /*TODO: entry_size above should actually be 2140 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2141 * of struct ce_dst_desc in HW header files 2142 */ 2143 .lmac_ring = FALSE, 2144 .ring_dir = HAL_SRNG_SRC_RING, 2145 .reg_start = { 2146 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2147 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 2148 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2149 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 2150 }, 2151 .reg_size = { 2152 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2153 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2154 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2155 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2156 }, 2157 .max_size = 2158 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2159 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2160 }, 2161 { /* CE_DST_STATUS */ 2162 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2163 .max_rings = 16, 2164 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2165 .lmac_ring = FALSE, 2166 .ring_dir = HAL_SRNG_DST_RING, 2167 .reg_start = { 2168 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2169 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 2170 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2171 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 2172 }, 2173 /* TODO: check destination status ring registers */ 2174 .reg_size = { 2175 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2176 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2177 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2178 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2179 }, 2180 .max_size = 2181 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2182 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2183 }, 2184 { /* WBM_IDLE_LINK */ 2185 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2186 .max_rings = 1, 2187 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2188 .lmac_ring = FALSE, 2189 .ring_dir = HAL_SRNG_SRC_RING, 2190 .reg_start = { 2191 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2192 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE), 2193 }, 2194 /* Single ring - provide ring size if multiple rings of this 2195 * type are supported 2196 */ 2197 .reg_size = {}, 2198 .max_size = 2199 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2200 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2201 }, 2202 { /* SW2WBM_RELEASE */ 2203 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2204 .max_rings = 1, 2205 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2206 .lmac_ring = FALSE, 2207 .ring_dir = HAL_SRNG_SRC_RING, 2208 .reg_start = { 2209 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2210 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2211 }, 2212 /* Single ring - provide ring size if multiple rings of this 2213 * type are supported 2214 */ 2215 .reg_size = {}, 2216 .max_size = 2217 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2218 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2219 }, 2220 { /* WBM2SW_RELEASE */ 2221 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2222 .max_rings = 8, 2223 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2224 .lmac_ring = FALSE, 2225 .ring_dir = HAL_SRNG_DST_RING, 2226 .reg_start = { 2227 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR( 2228 WBM_REG_REG_BASE), 2229 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR( 2230 WBM_REG_REG_BASE), 2231 }, 2232 .reg_size = { 2233 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR( 2234 WBM_REG_REG_BASE) - 2235 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR( 2236 WBM_REG_REG_BASE), 2237 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR( 2238 WBM_REG_REG_BASE) - 2239 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR( 2240 WBM_REG_REG_BASE), 2241 }, 2242 .max_size = 2243 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2244 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2245 }, 2246 { /* RXDMA_BUF */ 2247 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2248 #ifdef IPA_OFFLOAD 2249 .max_rings = 3, 2250 #else 2251 .max_rings = 3, 2252 #endif 2253 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2254 .lmac_ring = TRUE, 2255 .ring_dir = HAL_SRNG_SRC_RING, 2256 /* reg_start is not set because LMAC rings are not accessed 2257 * from host 2258 */ 2259 .reg_start = {}, 2260 .reg_size = {}, 2261 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2262 }, 2263 { /* RXDMA_DST */ 2264 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2265 .max_rings = 0, 2266 .entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/, 2267 .lmac_ring = TRUE, 2268 .ring_dir = HAL_SRNG_DST_RING, 2269 /* reg_start is not set because LMAC rings are not accessed 2270 * from host 2271 */ 2272 .reg_start = {}, 2273 .reg_size = {}, 2274 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2275 }, 2276 #ifdef QCA_MONITOR_2_0_SUPPORT 2277 { /* RXDMA_MONITOR_BUF */ 2278 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2279 .max_rings = 1, 2280 .entry_size = sizeof(struct mon_ingress_ring) >> 2, 2281 .lmac_ring = TRUE, 2282 .ring_dir = HAL_SRNG_SRC_RING, 2283 /* reg_start is not set because LMAC rings are not accessed 2284 * from host 2285 */ 2286 .reg_start = {}, 2287 .reg_size = {}, 2288 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2289 }, 2290 #else 2291 {}, 2292 #endif 2293 { /* RXDMA_MONITOR_STATUS */ 2294 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2295 .max_rings = 0, 2296 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2297 .lmac_ring = TRUE, 2298 .ring_dir = HAL_SRNG_SRC_RING, 2299 /* reg_start is not set because LMAC rings are not accessed 2300 * from host 2301 */ 2302 .reg_start = {}, 2303 .reg_size = {}, 2304 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2305 }, 2306 #ifdef QCA_MONITOR_2_0_SUPPORT 2307 { /* RXDMA_MONITOR_DST */ 2308 .start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0, 2309 .max_rings = 2, 2310 .entry_size = sizeof(struct mon_destination_ring) >> 2, 2311 .lmac_ring = TRUE, 2312 .ring_dir = HAL_SRNG_DST_RING, 2313 /* reg_start is not set because LMAC rings are not accessed 2314 * from host 2315 */ 2316 .reg_start = {}, 2317 .reg_size = {}, 2318 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2319 }, 2320 #else 2321 {}, 2322 #endif 2323 { /* RXDMA_MONITOR_DESC */ 2324 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2325 .max_rings = 0, 2326 .entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/, 2327 .lmac_ring = TRUE, 2328 .ring_dir = HAL_SRNG_DST_RING, 2329 /* reg_start is not set because LMAC rings are not accessed 2330 * from host 2331 */ 2332 .reg_start = {}, 2333 .reg_size = {}, 2334 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2335 }, 2336 2337 { /* DIR_BUF_RX_DMA_SRC */ 2338 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2339 /* one ring for spectral and one ring for cfr */ 2340 .max_rings = 2, 2341 .entry_size = 2, 2342 .lmac_ring = TRUE, 2343 .ring_dir = HAL_SRNG_SRC_RING, 2344 /* reg_start is not set because LMAC rings are not accessed 2345 * from host 2346 */ 2347 .reg_start = {}, 2348 .reg_size = {}, 2349 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2350 }, 2351 #ifdef WLAN_FEATURE_CIF_CFR 2352 { /* WIFI_POS_SRC */ 2353 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2354 .max_rings = 1, 2355 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2356 .lmac_ring = TRUE, 2357 .ring_dir = HAL_SRNG_SRC_RING, 2358 /* reg_start is not set because LMAC rings are not accessed 2359 * from host 2360 */ 2361 .reg_start = {}, 2362 .reg_size = {}, 2363 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2364 }, 2365 #endif 2366 #ifdef QCA_MONITOR_2_0_SUPPORT 2367 { /* TX_MONITOR_BUF */ 2368 .start_ring_id = HAL_SRNG_SW2TXMON_BUF0, 2369 .max_rings = 1, 2370 .entry_size = sizeof(struct mon_ingress_ring) >> 2, 2371 .lmac_ring = TRUE, 2372 .ring_dir = HAL_SRNG_SRC_RING, 2373 /* reg_start is not set because LMAC rings are not accessed 2374 * from host 2375 */ 2376 .reg_start = {}, 2377 .reg_size = {}, 2378 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2379 }, 2380 { /* TX_MONITOR_DST */ 2381 .start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0, 2382 .max_rings = 2, 2383 .entry_size = sizeof(struct mon_destination_ring) >> 2, 2384 .lmac_ring = TRUE, 2385 .ring_dir = HAL_SRNG_DST_RING, 2386 /* reg_start is not set because LMAC rings are not accessed 2387 * from host 2388 */ 2389 .reg_start = {}, 2390 .reg_size = {}, 2391 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2392 }, 2393 #else 2394 {}, 2395 {}, 2396 #endif 2397 { /* SW2RXDMA */ 2398 .start_ring_id = HAL_SRNG_SW2RXDMA_BUF0, 2399 .max_rings = 3, 2400 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2401 .lmac_ring = TRUE, 2402 .ring_dir = HAL_SRNG_SRC_RING, 2403 /* reg_start is not set because LMAC rings are not accessed 2404 * from host 2405 */ 2406 .reg_start = {}, 2407 .reg_size = {}, 2408 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2409 }, 2410 }; 2411 2412 /** 2413 * hal_srng_hw_reg_offset_init_qca5332() - Initialize the HW srng reg offset 2414 * applicable only for qca5332 2415 * @hal_soc: HAL Soc handle 2416 * 2417 * Return: None 2418 */ 2419 static inline void hal_srng_hw_reg_offset_init_qca5332(struct hal_soc *hal_soc) 2420 { 2421 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 2422 2423 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB), 2424 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB), 2425 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA), 2426 hw_reg_offset[DST_PRODUCER_INT2_SETUP] = 2427 REG_OFFSET(DST, PRODUCER_INT2_SETUP); 2428 } 2429 2430 /** 2431 * hal_qca5332_attach()- Attach 5332 target specific hal_soc ops, 2432 * offset and srng table 2433 * Return: void 2434 */ 2435 void hal_qca5332_attach(struct hal_soc *hal_soc) 2436 { 2437 hal_soc->hw_srng_table = hw_srng_table_5332; 2438 2439 hal_srng_hw_reg_offset_init_generic(hal_soc); 2440 hal_srng_hw_reg_offset_init_qca5332(hal_soc); 2441 2442 hal_hw_txrx_default_ops_attach_be(hal_soc); 2443 hal_hw_txrx_ops_attach_qca5332(hal_soc); 2444 if (hal_soc->static_window_map) 2445 hal_write_window_register(hal_soc); 2446 hal_soc->dmac_cmn_src_rxbuf_ring = true; 2447 } 2448