1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE 16 */ 17 #include "qdf_types.h" 18 #include "qdf_util.h" 19 #include "qdf_mem.h" 20 #include "qdf_nbuf.h" 21 #include "qdf_module.h" 22 23 #include "target_type.h" 24 #include "wcss_version.h" 25 26 #include "hal_be_hw_headers.h" 27 #include "hal_internal.h" 28 #include "hal_api.h" 29 #include "hal_flow.h" 30 #include "rx_flow_search_entry.h" 31 #include "hal_rx_flow_info.h" 32 #include "hal_be_api.h" 33 #include "tcl_entrance_from_ppe_ring.h" 34 #include "sw_monitor_ring.h" 35 #include "wcss_seq_hwioreg_umac.h" 36 #include "wfss_ce_reg_seq_hwioreg.h" 37 #include <uniform_reo_status_header.h> 38 #include <wbm_release_ring_tx.h> 39 #include <phyrx_location.h> 40 #ifdef QCA_MONITOR_2_0_SUPPORT 41 #include <mon_ingress_ring.h> 42 #include <mon_destination_ring.h> 43 #endif 44 #include "rx_reo_queue_1k.h" 45 46 #include <hal_be_rx.h> 47 48 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 49 RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 50 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 51 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 52 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 53 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 54 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 55 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 56 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 57 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 58 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 59 STATUS_HEADER_REO_STATUS_NUMBER 60 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 61 STATUS_HEADER_TIMESTAMP 62 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 64 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 65 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 66 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 67 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 68 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 69 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 70 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 71 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 72 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 73 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 74 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 75 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 76 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 77 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 78 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 79 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 80 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 81 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 82 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 83 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 84 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 85 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 86 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 87 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 88 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 89 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 90 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 91 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 92 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 93 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 94 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 95 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 96 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 97 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 98 99 #ifdef QCA_MONITOR_2_0_SUPPORT 100 #include "hal_be_api_mon.h" 101 #endif 102 103 #define CMEM_REG_BASE 0x00100000 104 105 /* For Berryllium sw2rxdma ring size increased to 20 bits */ 106 #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF 107 108 #include "hal_5332_rx.h" 109 #include "hal_5332_tx.h" 110 #include "hal_be_rx_tlv.h" 111 #include <hal_be_generic_api.h> 112 113 114 /** 115 * hal_read_pmm_scratch_reg_5332() - API to read PMM Scratch register 116 * 117 * @soc: HAL soc 118 * @reg_enum: Enum of the scratch register 119 * 120 * Return: uint32_t 121 */ 122 static inline 123 uint32_t hal_read_pmm_scratch_reg_5332(struct hal_soc *soc, 124 enum hal_scratch_reg_enum reg_enum) 125 { 126 uint32_t val = 0; 127 128 pld_reg_read(soc->qdf_dev->dev, (reg_enum * 4), &val, 129 soc->dev_base_addr_pmm); 130 return val; 131 } 132 133 /** 134 * hal_get_tsf2_scratch_reg_qca5332() - API to read tsf2 scratch register 135 * 136 * @hal_soc_hdl: HAL soc context 137 * @mac_id: mac id 138 * @value: Pointer to update tsf2 value 139 * 140 * Return: void 141 */ 142 static void hal_get_tsf2_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl, 143 uint8_t mac_id, uint64_t *value) 144 { 145 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 146 uint32_t offset_lo, offset_hi; 147 enum hal_scratch_reg_enum enum_lo, enum_hi; 148 149 hal_get_tsf_enum(DEFAULT_TSF_ID, mac_id, &enum_lo, &enum_hi); 150 151 offset_lo = hal_read_pmm_scratch_reg_5332(soc, 152 enum_lo); 153 154 offset_hi = hal_read_pmm_scratch_reg_5332(soc, 155 enum_hi); 156 157 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 158 } 159 160 /** 161 * hal_get_tqm_scratch_reg_qca5332() - API to read tqm scratch register 162 * 163 * @hal_soc_hdl: HAL soc context 164 * @value: Pointer to update tqm value 165 * 166 * Return: void 167 */ 168 static void hal_get_tqm_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl, 169 uint64_t *value) 170 { 171 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 172 uint32_t offset_lo, offset_hi; 173 174 offset_lo = hal_read_pmm_scratch_reg_5332(soc, 175 PMM_TQM_CLOCK_OFFSET_LO_US); 176 177 offset_hi = hal_read_pmm_scratch_reg_5332(soc, 178 PMM_TQM_CLOCK_OFFSET_HI_US); 179 180 *value = ((uint64_t)(offset_hi) << 32 | offset_lo); 181 } 182 183 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 184 #define HAL_PPE_VP_ENTRIES_MAX 32 185 /** 186 * hal_get_link_desc_size_5332() - API to get the link desc size 187 * 188 * Return: uint32_t 189 */ 190 static uint32_t hal_get_link_desc_size_5332(void) 191 { 192 return LINK_DESC_SIZE; 193 } 194 195 /** 196 * hal_rx_get_tlv_5332() - API to get the tlv 197 * 198 * @rx_tlv: TLV data extracted from the rx packet 199 * Return: uint8_t 200 */ 201 static uint8_t hal_rx_get_tlv_5332(void *rx_tlv) 202 { 203 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH); 204 } 205 206 /** 207 * hal_rx_wbm_err_msdu_continuation_get_5332() - API to check if WBM 208 * msdu continuation bit is set 209 * 210 * @wbm_desc: wbm release ring descriptor 211 * 212 * Return: true if msdu continuation bit is set. 213 */ 214 uint8_t hal_rx_wbm_err_msdu_continuation_get_5332(void *wbm_desc) 215 { 216 uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) + 217 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET); 218 219 return (comp_desc & 220 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >> 221 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB; 222 } 223 224 /** 225 * hal_rx_proc_phyrx_other_receive_info_tlv_5332() - API to get tlv info 226 * @rx_tlv_hdr: start address of rx_pkt_tlvs 227 * @ppdu_info_hdl: PPDU info handle to fill 228 * 229 * Return: uint32_t 230 */ 231 static inline 232 void hal_rx_proc_phyrx_other_receive_info_tlv_5332(void *rx_tlv_hdr, 233 void *ppdu_info_hdl) 234 { 235 uint32_t tlv_tag, tlv_len; 236 uint32_t temp_len, other_tlv_len, other_tlv_tag; 237 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 238 void *other_tlv_hdr = NULL; 239 void *other_tlv = NULL; 240 241 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 242 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 243 temp_len = 0; 244 245 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 246 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 247 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 248 249 temp_len += other_tlv_len; 250 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 251 252 switch (other_tlv_tag) { 253 default: 254 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 255 "%s unhandled TLV type: %d, TLV len:%d", 256 __func__, other_tlv_tag, other_tlv_len); 257 break; 258 } 259 } 260 261 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 262 static inline 263 void hal_rx_get_bb_info_5332(void *rx_tlv, void *ppdu_info_hdl) 264 { 265 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 266 267 ppdu_info->cfr_info.bb_captured_channel = 268 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL); 269 270 ppdu_info->cfr_info.bb_captured_timeout = 271 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT); 272 273 ppdu_info->cfr_info.bb_captured_reason = 274 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON); 275 } 276 277 static inline 278 void hal_rx_get_rtt_info_5332(void *rx_tlv, void *ppdu_info_hdl) 279 { 280 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 281 282 ppdu_info->cfr_info.rx_location_info_valid = 283 HAL_RX_GET(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 284 RX_LOCATION_INFO_VALID); 285 286 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 287 HAL_RX_GET(rx_tlv, 288 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 289 RTT_CHE_BUFFER_POINTER_LOW32); 290 291 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 292 HAL_RX_GET(rx_tlv, 293 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 294 RTT_CHE_BUFFER_POINTER_HIGH8); 295 296 ppdu_info->cfr_info.chan_capture_status = 297 HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv); 298 299 ppdu_info->cfr_info.rx_start_ts = 300 HAL_RX_GET(rx_tlv, 301 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 302 RX_START_TS); 303 304 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) 305 HAL_RX_GET(rx_tlv, 306 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 307 RTT_CFO_MEASUREMENT); 308 309 ppdu_info->cfr_info.agc_gain_info0 = 310 HAL_RX_GET(rx_tlv, 311 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 312 GAIN_CHAIN0); 313 314 ppdu_info->cfr_info.agc_gain_info0 |= 315 (((uint32_t)HAL_RX_GET(rx_tlv, 316 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 317 GAIN_CHAIN1)) << 16); 318 319 ppdu_info->cfr_info.agc_gain_info1 = 320 HAL_RX_GET(rx_tlv, 321 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 322 GAIN_CHAIN2); 323 324 ppdu_info->cfr_info.agc_gain_info1 |= 325 (((uint32_t)HAL_RX_GET(rx_tlv, 326 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, 327 GAIN_CHAIN3)) << 16); 328 329 ppdu_info->cfr_info.agc_gain_info2 = 0; 330 331 ppdu_info->cfr_info.agc_gain_info3 = 0; 332 } 333 #endif 334 #ifdef CONFIG_WORD_BASED_TLV 335 /** 336 * hal_rx_dump_mpdu_start_tlv_5332() - dump RX mpdu_start TLV in structured 337 * human readable format. 338 * @mpdustart: pointer the rx_attention TLV in pkt. 339 * @dbg_level: log level. 340 * 341 * Return: void 342 */ 343 static inline void hal_rx_dump_mpdu_start_tlv_5332(void *mpdustart, 344 uint8_t dbg_level) 345 { 346 struct rx_mpdu_start_compact *mpdu_info = 347 (struct rx_mpdu_start_compact *)mpdustart; 348 349 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 350 "rx_mpdu_start tlv (1/5) - " 351 "rx_reo_queue_desc_addr_39_32 :%x" 352 "receive_queue_number:%x " 353 "pre_delim_err_warning:%x " 354 "first_delim_err:%x " 355 "pn_31_0:%x " 356 "pn_63_32:%x " 357 "pn_95_64:%x ", 358 mpdu_info->rx_reo_queue_desc_addr_39_32, 359 mpdu_info->receive_queue_number, 360 mpdu_info->pre_delim_err_warning, 361 mpdu_info->first_delim_err, 362 mpdu_info->pn_31_0, 363 mpdu_info->pn_63_32, 364 mpdu_info->pn_95_64); 365 366 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 367 "rx_mpdu_start tlv (2/5) - " 368 "ast_index:%x " 369 "sw_peer_id:%x " 370 "mpdu_frame_control_valid:%x " 371 "mpdu_duration_valid:%x " 372 "mac_addr_ad1_valid:%x " 373 "mac_addr_ad2_valid:%x " 374 "mac_addr_ad3_valid:%x " 375 "mac_addr_ad4_valid:%x " 376 "mpdu_sequence_control_valid :%x" 377 "mpdu_qos_control_valid:%x " 378 "mpdu_ht_control_valid:%x " 379 "frame_encryption_info_valid :%x", 380 mpdu_info->ast_index, 381 mpdu_info->sw_peer_id, 382 mpdu_info->mpdu_frame_control_valid, 383 mpdu_info->mpdu_duration_valid, 384 mpdu_info->mac_addr_ad1_valid, 385 mpdu_info->mac_addr_ad2_valid, 386 mpdu_info->mac_addr_ad3_valid, 387 mpdu_info->mac_addr_ad4_valid, 388 mpdu_info->mpdu_sequence_control_valid, 389 mpdu_info->mpdu_qos_control_valid, 390 mpdu_info->mpdu_ht_control_valid, 391 mpdu_info->frame_encryption_info_valid); 392 393 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 394 "rx_mpdu_start tlv (3/5) - " 395 "mpdu_fragment_number:%x " 396 "more_fragment_flag:%x " 397 "fr_ds:%x " 398 "to_ds:%x " 399 "encrypted:%x " 400 "mpdu_retry:%x " 401 "mpdu_sequence_number:%x ", 402 mpdu_info->mpdu_fragment_number, 403 mpdu_info->more_fragment_flag, 404 mpdu_info->fr_ds, 405 mpdu_info->to_ds, 406 mpdu_info->encrypted, 407 mpdu_info->mpdu_retry, 408 mpdu_info->mpdu_sequence_number); 409 410 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 411 "rx_mpdu_start tlv (4/5) - " 412 "mpdu_frame_control_field:%x " 413 "mpdu_duration_field:%x ", 414 mpdu_info->mpdu_frame_control_field, 415 mpdu_info->mpdu_duration_field); 416 417 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 418 "rx_mpdu_start tlv (5/5) - " 419 "mac_addr_ad1_31_0:%x " 420 "mac_addr_ad1_47_32:%x " 421 "mac_addr_ad2_15_0:%x " 422 "mac_addr_ad2_47_16:%x " 423 "mac_addr_ad3_31_0:%x " 424 "mac_addr_ad3_47_32:%x " 425 "mpdu_sequence_control_field :%x", 426 mpdu_info->mac_addr_ad1_31_0, 427 mpdu_info->mac_addr_ad1_47_32, 428 mpdu_info->mac_addr_ad2_15_0, 429 mpdu_info->mac_addr_ad2_47_16, 430 mpdu_info->mac_addr_ad3_31_0, 431 mpdu_info->mac_addr_ad3_47_32, 432 mpdu_info->mpdu_sequence_control_field); 433 } 434 435 /** 436 * hal_rx_dump_msdu_end_tlv_5332() - dump RX msdu_end TLV in structured 437 * human readable format. 438 * @msduend: pointer the msdu_end TLV in pkt. 439 * @dbg_level: log level. 440 * 441 * Return: void 442 */ 443 static void hal_rx_dump_msdu_end_tlv_5332(void *msduend, 444 uint8_t dbg_level) 445 { 446 struct rx_msdu_end_compact *msdu_end = 447 (struct rx_msdu_end_compact *)msduend; 448 449 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 450 "rx_msdu_end tlv - " 451 "key_id_octet: %d " 452 "tcp_udp_chksum: %d " 453 "sa_idx_timeout: %d " 454 "da_idx_timeout: %d " 455 "msdu_limit_error: %d " 456 "flow_idx_timeout: %d " 457 "flow_idx_invalid: %d " 458 "wifi_parser_error: %d " 459 "sa_is_valid: %d " 460 "da_is_valid: %d " 461 "da_is_mcbc: %d " 462 "tkip_mic_err: %d " 463 "l3_header_padding: %d " 464 "first_msdu: %d " 465 "last_msdu: %d " 466 "sa_idx: %d " 467 "msdu_drop: %d " 468 "reo_destination_indication: %d " 469 "flow_idx: %d " 470 "fse_metadata: %d " 471 "cce_metadata: %d " 472 "sa_sw_peer_id: %d ", 473 msdu_end->key_id_octet, 474 msdu_end->tcp_udp_chksum, 475 msdu_end->sa_idx_timeout, 476 msdu_end->da_idx_timeout, 477 msdu_end->msdu_limit_error, 478 msdu_end->flow_idx_timeout, 479 msdu_end->flow_idx_invalid, 480 msdu_end->wifi_parser_error, 481 msdu_end->sa_is_valid, 482 msdu_end->da_is_valid, 483 msdu_end->da_is_mcbc, 484 msdu_end->tkip_mic_err, 485 msdu_end->l3_header_padding, 486 msdu_end->first_msdu, 487 msdu_end->last_msdu, 488 msdu_end->sa_idx, 489 msdu_end->msdu_drop, 490 msdu_end->reo_destination_indication, 491 msdu_end->flow_idx, 492 msdu_end->fse_metadata, 493 msdu_end->cce_metadata, 494 msdu_end->sa_sw_peer_id); 495 } 496 #else 497 static inline void hal_rx_dump_mpdu_start_tlv_5332(void *mpdustart, 498 uint8_t dbg_level) 499 { 500 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 501 struct rx_mpdu_info *mpdu_info = 502 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 503 504 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 505 "rx_mpdu_start tlv (1/5) - " 506 "rx_reo_queue_desc_addr_31_0 :%x" 507 "rx_reo_queue_desc_addr_39_32 :%x" 508 "receive_queue_number:%x " 509 "pre_delim_err_warning:%x " 510 "first_delim_err:%x " 511 "reserved_2a:%x " 512 "pn_31_0:%x " 513 "pn_63_32:%x " 514 "pn_95_64:%x " 515 "pn_127_96:%x " 516 "epd_en:%x " 517 "all_frames_shall_be_encrypted :%x" 518 "encrypt_type:%x " 519 "wep_key_width_for_variable_key :%x" 520 "mesh_sta:%x " 521 "bssid_hit:%x " 522 "bssid_number:%x " 523 "tid:%x " 524 "reserved_7a:%x ", 525 mpdu_info->rx_reo_queue_desc_addr_31_0, 526 mpdu_info->rx_reo_queue_desc_addr_39_32, 527 mpdu_info->receive_queue_number, 528 mpdu_info->pre_delim_err_warning, 529 mpdu_info->first_delim_err, 530 mpdu_info->reserved_2a, 531 mpdu_info->pn_31_0, 532 mpdu_info->pn_63_32, 533 mpdu_info->pn_95_64, 534 mpdu_info->pn_127_96, 535 mpdu_info->epd_en, 536 mpdu_info->all_frames_shall_be_encrypted, 537 mpdu_info->encrypt_type, 538 mpdu_info->wep_key_width_for_variable_key, 539 mpdu_info->mesh_sta, 540 mpdu_info->bssid_hit, 541 mpdu_info->bssid_number, 542 mpdu_info->tid, 543 mpdu_info->reserved_7a); 544 545 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 546 "rx_mpdu_start tlv (2/5) - " 547 "ast_index:%x " 548 "sw_peer_id:%x " 549 "mpdu_frame_control_valid:%x " 550 "mpdu_duration_valid:%x " 551 "mac_addr_ad1_valid:%x " 552 "mac_addr_ad2_valid:%x " 553 "mac_addr_ad3_valid:%x " 554 "mac_addr_ad4_valid:%x " 555 "mpdu_sequence_control_valid :%x" 556 "mpdu_qos_control_valid:%x " 557 "mpdu_ht_control_valid:%x " 558 "frame_encryption_info_valid :%x", 559 mpdu_info->ast_index, 560 mpdu_info->sw_peer_id, 561 mpdu_info->mpdu_frame_control_valid, 562 mpdu_info->mpdu_duration_valid, 563 mpdu_info->mac_addr_ad1_valid, 564 mpdu_info->mac_addr_ad2_valid, 565 mpdu_info->mac_addr_ad3_valid, 566 mpdu_info->mac_addr_ad4_valid, 567 mpdu_info->mpdu_sequence_control_valid, 568 mpdu_info->mpdu_qos_control_valid, 569 mpdu_info->mpdu_ht_control_valid, 570 mpdu_info->frame_encryption_info_valid); 571 572 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 573 "rx_mpdu_start tlv (3/5) - " 574 "mpdu_fragment_number:%x " 575 "more_fragment_flag:%x " 576 "reserved_11a:%x " 577 "fr_ds:%x " 578 "to_ds:%x " 579 "encrypted:%x " 580 "mpdu_retry:%x " 581 "mpdu_sequence_number:%x ", 582 mpdu_info->mpdu_fragment_number, 583 mpdu_info->more_fragment_flag, 584 mpdu_info->reserved_11a, 585 mpdu_info->fr_ds, 586 mpdu_info->to_ds, 587 mpdu_info->encrypted, 588 mpdu_info->mpdu_retry, 589 mpdu_info->mpdu_sequence_number); 590 591 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 592 "rx_mpdu_start tlv (4/5) - " 593 "mpdu_frame_control_field:%x " 594 "mpdu_duration_field:%x ", 595 mpdu_info->mpdu_frame_control_field, 596 mpdu_info->mpdu_duration_field); 597 598 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level, 599 "rx_mpdu_start tlv (5/5) - " 600 "mac_addr_ad1_31_0:%x " 601 "mac_addr_ad1_47_32:%x " 602 "mac_addr_ad2_15_0:%x " 603 "mac_addr_ad2_47_16:%x " 604 "mac_addr_ad3_31_0:%x " 605 "mac_addr_ad3_47_32:%x " 606 "mpdu_sequence_control_field :%x" 607 "mac_addr_ad4_31_0:%x " 608 "mac_addr_ad4_47_32:%x " 609 "mpdu_qos_control_field:%x ", 610 mpdu_info->mac_addr_ad1_31_0, 611 mpdu_info->mac_addr_ad1_47_32, 612 mpdu_info->mac_addr_ad2_15_0, 613 mpdu_info->mac_addr_ad2_47_16, 614 mpdu_info->mac_addr_ad3_31_0, 615 mpdu_info->mac_addr_ad3_47_32, 616 mpdu_info->mpdu_sequence_control_field, 617 mpdu_info->mac_addr_ad4_31_0, 618 mpdu_info->mac_addr_ad4_47_32, 619 mpdu_info->mpdu_qos_control_field); 620 } 621 622 static void hal_rx_dump_msdu_end_tlv_5332(void *msduend, 623 uint8_t dbg_level) 624 { 625 struct rx_msdu_end *msdu_end = 626 (struct rx_msdu_end *)msduend; 627 628 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 629 "rx_msdu_end tlv - " 630 "key_id_octet: %d " 631 "cce_super_rule: %d " 632 "cce_classify_not_done_truncat: %d " 633 "cce_classify_not_done_cce_dis: %d " 634 "rule_indication_31_0: %d " 635 "tcp_udp_chksum: %d " 636 "sa_idx_timeout: %d " 637 "da_idx_timeout: %d " 638 "msdu_limit_error: %d " 639 "flow_idx_timeout: %d " 640 "flow_idx_invalid: %d " 641 "wifi_parser_error: %d " 642 "sa_is_valid: %d " 643 "da_is_valid: %d " 644 "da_is_mcbc: %d " 645 "tkip_mic_err: %d " 646 "l3_header_padding: %d " 647 "first_msdu: %d " 648 "last_msdu: %d " 649 "sa_idx: %d " 650 "msdu_drop: %d " 651 "reo_destination_indication: %d " 652 "flow_idx: %d " 653 "fse_metadata: %d " 654 "cce_metadata: %d " 655 "sa_sw_peer_id: %d ", 656 msdu_end->key_id_octet, 657 msdu_end->cce_super_rule, 658 msdu_end->cce_classify_not_done_truncate, 659 msdu_end->cce_classify_not_done_cce_dis, 660 msdu_end->rule_indication_31_0, 661 msdu_end->tcp_udp_chksum, 662 msdu_end->sa_idx_timeout, 663 msdu_end->da_idx_timeout, 664 msdu_end->msdu_limit_error, 665 msdu_end->flow_idx_timeout, 666 msdu_end->flow_idx_invalid, 667 msdu_end->wifi_parser_error, 668 msdu_end->sa_is_valid, 669 msdu_end->da_is_valid, 670 msdu_end->da_is_mcbc, 671 msdu_end->tkip_mic_err, 672 msdu_end->l3_header_padding, 673 msdu_end->first_msdu, 674 msdu_end->last_msdu, 675 msdu_end->sa_idx, 676 msdu_end->msdu_drop, 677 msdu_end->reo_destination_indication, 678 msdu_end->flow_idx, 679 msdu_end->fse_metadata, 680 msdu_end->cce_metadata, 681 msdu_end->sa_sw_peer_id); 682 } 683 #endif 684 685 /** 686 * hal_reo_status_get_header_5332() - Process reo desc info 687 * @ring_desc: Pointer to reo descriptor 688 * @b: tlv type info 689 * @h1: Pointer to hal_reo_status_header where info to be stored 690 * 691 * Return: none. 692 * 693 */ 694 static void hal_reo_status_get_header_5332(hal_ring_desc_t ring_desc, 695 int b, void *h1) 696 { 697 uint64_t *d = (uint64_t *)ring_desc; 698 uint64_t val1 = 0; 699 struct hal_reo_status_header *h = 700 (struct hal_reo_status_header *)h1; 701 702 /* Offsets of descriptor fields defined in HW headers start 703 * from the field after TLV header 704 */ 705 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr)); 706 707 switch (b) { 708 case HAL_REO_QUEUE_STATS_STATUS_TLV: 709 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 710 STATUS_HEADER_REO_STATUS_NUMBER)]; 711 break; 712 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 713 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 714 STATUS_HEADER_REO_STATUS_NUMBER)]; 715 break; 716 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 717 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 718 STATUS_HEADER_REO_STATUS_NUMBER)]; 719 break; 720 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 721 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 722 STATUS_HEADER_REO_STATUS_NUMBER)]; 723 break; 724 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 725 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 726 STATUS_HEADER_REO_STATUS_NUMBER)]; 727 break; 728 case HAL_REO_DESC_THRES_STATUS_TLV: 729 val1 = 730 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 731 STATUS_HEADER_REO_STATUS_NUMBER)]; 732 break; 733 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 734 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 735 STATUS_HEADER_REO_STATUS_NUMBER)]; 736 break; 737 default: 738 qdf_nofl_err("ERROR: Unknown tlv\n"); 739 break; 740 } 741 h->cmd_num = 742 HAL_GET_FIELD( 743 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER, 744 val1); 745 h->exec_time = 746 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 747 CMD_EXECUTION_TIME, val1); 748 h->status = 749 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 750 REO_CMD_EXECUTION_STATUS, val1); 751 switch (b) { 752 case HAL_REO_QUEUE_STATS_STATUS_TLV: 753 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 754 STATUS_HEADER_TIMESTAMP)]; 755 break; 756 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 757 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 758 STATUS_HEADER_TIMESTAMP)]; 759 break; 760 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 761 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 762 STATUS_HEADER_TIMESTAMP)]; 763 break; 764 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 765 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 766 STATUS_HEADER_TIMESTAMP)]; 767 break; 768 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 769 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 770 STATUS_HEADER_TIMESTAMP)]; 771 break; 772 case HAL_REO_DESC_THRES_STATUS_TLV: 773 val1 = 774 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 775 STATUS_HEADER_TIMESTAMP)]; 776 break; 777 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 778 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 779 STATUS_HEADER_TIMESTAMP)]; 780 break; 781 default: 782 qdf_nofl_err("ERROR: Unknown tlv\n"); 783 break; 784 } 785 h->tstamp = 786 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1); 787 } 788 789 static 790 void *hal_rx_msdu0_buffer_addr_lsb_5332(void *link_desc_va) 791 { 792 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 793 } 794 795 static 796 void *hal_rx_msdu_desc_info_ptr_get_5332(void *msdu0) 797 { 798 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 799 } 800 801 static 802 void *hal_ent_mpdu_desc_info_5332(void *ent_ring_desc) 803 { 804 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 805 } 806 807 static 808 void *hal_dst_mpdu_desc_info_5332(void *dst_ring_desc) 809 { 810 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 811 } 812 813 /** 814 * hal_reo_config_5332() - Set reo config parameters 815 * @soc: hal soc handle 816 * @reg_val: value to be set 817 * @reo_params: reo parameters 818 * 819 * Return: void 820 */ 821 static void 822 hal_reo_config_5332(struct hal_soc *soc, 823 uint32_t reg_val, 824 struct hal_reo_params *reo_params) 825 { 826 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 827 } 828 829 /** 830 * hal_rx_msdu_desc_info_get_ptr_5332() - Get msdu desc info ptr 831 * @msdu_details_ptr: Pointer to msdu_details_ptr 832 * 833 * Return: Pointer to rx_msdu_desc_info structure. 834 * 835 */ 836 static void *hal_rx_msdu_desc_info_get_ptr_5332(void *msdu_details_ptr) 837 { 838 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 839 } 840 841 /** 842 * hal_rx_link_desc_msdu0_ptr_5332() - Get pointer to rx_msdu details 843 * @link_desc: Pointer to link desc 844 * 845 * Return: Pointer to rx_msdu_details structure 846 * 847 */ 848 static void *hal_rx_link_desc_msdu0_ptr_5332(void *link_desc) 849 { 850 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 851 } 852 853 /** 854 * hal_get_window_address_5332() - Function to get hp/tp address 855 * @hal_soc: Pointer to hal_soc 856 * @addr: address offset of register 857 * 858 * Return: modified address offset of register 859 */ 860 static inline qdf_iomem_t hal_get_window_address_5332(struct hal_soc *hal_soc, 861 qdf_iomem_t addr) 862 { 863 uint32_t offset = addr - hal_soc->dev_base_addr; 864 qdf_iomem_t new_offset; 865 866 /* 867 * Check if offset lies within CE register range(0x740000) 868 * or UMAC/DP register range (0x00A00000). 869 * If offset lies within CE register range, map it 870 * into CE region. 871 */ 872 if (offset < 0xA00000) { 873 offset = offset - CE_CFG_WFSS_CE_REG_BASE; 874 new_offset = (hal_soc->dev_base_addr_ce + offset); 875 876 return new_offset; 877 } else { 878 /* 879 * If offset lies within DP register range, 880 * return the address as such 881 */ 882 return addr; 883 } 884 } 885 886 static 887 void hal_compute_reo_remap_ix2_ix3_5332(uint32_t *ring, uint32_t num_rings, 888 uint32_t *remap1, uint32_t *remap2) 889 { 890 switch (num_rings) { 891 case 1: 892 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 893 HAL_REO_REMAP_IX2(ring[0], 17) | 894 HAL_REO_REMAP_IX2(ring[0], 18) | 895 HAL_REO_REMAP_IX2(ring[0], 19) | 896 HAL_REO_REMAP_IX2(ring[0], 20) | 897 HAL_REO_REMAP_IX2(ring[0], 21) | 898 HAL_REO_REMAP_IX2(ring[0], 22) | 899 HAL_REO_REMAP_IX2(ring[0], 23); 900 901 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 902 HAL_REO_REMAP_IX3(ring[0], 25) | 903 HAL_REO_REMAP_IX3(ring[0], 26) | 904 HAL_REO_REMAP_IX3(ring[0], 27) | 905 HAL_REO_REMAP_IX3(ring[0], 28) | 906 HAL_REO_REMAP_IX3(ring[0], 29) | 907 HAL_REO_REMAP_IX3(ring[0], 30) | 908 HAL_REO_REMAP_IX3(ring[0], 31); 909 break; 910 case 2: 911 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 912 HAL_REO_REMAP_IX2(ring[0], 17) | 913 HAL_REO_REMAP_IX2(ring[1], 18) | 914 HAL_REO_REMAP_IX2(ring[1], 19) | 915 HAL_REO_REMAP_IX2(ring[0], 20) | 916 HAL_REO_REMAP_IX2(ring[0], 21) | 917 HAL_REO_REMAP_IX2(ring[1], 22) | 918 HAL_REO_REMAP_IX2(ring[1], 23); 919 920 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 921 HAL_REO_REMAP_IX3(ring[0], 25) | 922 HAL_REO_REMAP_IX3(ring[1], 26) | 923 HAL_REO_REMAP_IX3(ring[1], 27) | 924 HAL_REO_REMAP_IX3(ring[0], 28) | 925 HAL_REO_REMAP_IX3(ring[0], 29) | 926 HAL_REO_REMAP_IX3(ring[1], 30) | 927 HAL_REO_REMAP_IX3(ring[1], 31); 928 break; 929 case 3: 930 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 931 HAL_REO_REMAP_IX2(ring[1], 17) | 932 HAL_REO_REMAP_IX2(ring[2], 18) | 933 HAL_REO_REMAP_IX2(ring[0], 19) | 934 HAL_REO_REMAP_IX2(ring[1], 20) | 935 HAL_REO_REMAP_IX2(ring[2], 21) | 936 HAL_REO_REMAP_IX2(ring[0], 22) | 937 HAL_REO_REMAP_IX2(ring[1], 23); 938 939 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 940 HAL_REO_REMAP_IX3(ring[0], 25) | 941 HAL_REO_REMAP_IX3(ring[1], 26) | 942 HAL_REO_REMAP_IX3(ring[2], 27) | 943 HAL_REO_REMAP_IX3(ring[0], 28) | 944 HAL_REO_REMAP_IX3(ring[1], 29) | 945 HAL_REO_REMAP_IX3(ring[2], 30) | 946 HAL_REO_REMAP_IX3(ring[0], 31); 947 break; 948 case 4: 949 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 950 HAL_REO_REMAP_IX2(ring[1], 17) | 951 HAL_REO_REMAP_IX2(ring[2], 18) | 952 HAL_REO_REMAP_IX2(ring[3], 19) | 953 HAL_REO_REMAP_IX2(ring[0], 20) | 954 HAL_REO_REMAP_IX2(ring[1], 21) | 955 HAL_REO_REMAP_IX2(ring[2], 22) | 956 HAL_REO_REMAP_IX2(ring[3], 23); 957 958 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 959 HAL_REO_REMAP_IX3(ring[1], 25) | 960 HAL_REO_REMAP_IX3(ring[2], 26) | 961 HAL_REO_REMAP_IX3(ring[3], 27) | 962 HAL_REO_REMAP_IX3(ring[0], 28) | 963 HAL_REO_REMAP_IX3(ring[1], 29) | 964 HAL_REO_REMAP_IX3(ring[2], 30) | 965 HAL_REO_REMAP_IX3(ring[3], 31); 966 break; 967 } 968 } 969 970 /** 971 * hal_rx_flow_setup_fse_5332() - Setup a flow search entry in HW FST 972 * @rx_fst: Pointer to the Rx Flow Search Table 973 * @table_offset: offset into the table where the flow is to be setup 974 * @rx_flow: Flow Parameters 975 * 976 * Return: Success/Failure 977 */ 978 static void * 979 hal_rx_flow_setup_fse_5332(uint8_t *rx_fst, uint32_t table_offset, 980 uint8_t *rx_flow) 981 { 982 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 983 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 984 uint8_t *fse; 985 bool fse_valid; 986 987 if (table_offset >= fst->max_entries) { 988 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 989 "HAL FSE table offset %u exceeds max entries %u", 990 table_offset, fst->max_entries); 991 return NULL; 992 } 993 994 fse = (uint8_t *)fst->base_vaddr + 995 (table_offset * HAL_RX_FST_ENTRY_SIZE); 996 997 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 998 999 if (fse_valid) { 1000 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1001 "HAL FSE %pK already valid", fse); 1002 return NULL; 1003 } 1004 1005 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) = 1006 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1007 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1008 1009 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) = 1010 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1011 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1012 1013 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) = 1014 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1015 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1016 1017 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) = 1018 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1019 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1020 1021 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) = 1022 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1023 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1024 1025 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) = 1026 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1027 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1028 1029 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) = 1030 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1031 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1032 1033 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) = 1034 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1035 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1036 1037 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT); 1038 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |= 1039 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1040 (flow->tuple_info.dest_port)); 1041 1042 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT); 1043 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |= 1044 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1045 (flow->tuple_info.src_port)); 1046 1047 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL); 1048 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |= 1049 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1050 flow->tuple_info.l4_protocol); 1051 1052 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER); 1053 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |= 1054 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1055 flow->reo_destination_handler); 1056 1057 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1058 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |= 1059 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1060 1061 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA); 1062 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) = 1063 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1064 flow->fse_metadata); 1065 1066 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION); 1067 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |= 1068 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1069 REO_DESTINATION_INDICATION, 1070 flow->reo_destination_indication); 1071 1072 /* Reset all the other fields in FSE */ 1073 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9); 1074 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP); 1075 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT); 1076 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT); 1077 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP); 1078 1079 return fse; 1080 } 1081 1082 /** 1083 * hal_rx_dump_pkt_hdr_tlv_5332() - dump RX pkt header TLV in hex format 1084 * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt. 1085 * @dbg_level: log level. 1086 * 1087 * Return: void 1088 */ 1089 #ifndef NO_RX_PKT_HDR_TLV 1090 static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs, 1091 uint8_t dbg_level) 1092 { 1093 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 1094 1095 hal_verbose_debug("\n---------------\n" 1096 "rx_pkt_hdr_tlv\n" 1097 "---------------\n" 1098 "phy_ppdu_id %llu ", 1099 pkt_hdr_tlv->phy_ppdu_id); 1100 1101 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 1102 sizeof(pkt_hdr_tlv->rx_pkt_hdr)); 1103 } 1104 #else 1105 static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs, 1106 uint8_t dbg_level) 1107 { 1108 } 1109 #endif 1110 1111 /** 1112 * hal_rx_dump_pkt_tlvs_5332() - API to print RX Pkt TLVS qca5332 1113 * @hal_soc_hdl: hal_soc handle 1114 * @buf: pointer the pkt buffer 1115 * @dbg_level: log level 1116 * 1117 * Return: void 1118 */ 1119 #ifdef CONFIG_WORD_BASED_TLV 1120 static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl, 1121 uint8_t *buf, uint8_t dbg_level) 1122 { 1123 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1124 struct rx_msdu_end_compact *msdu_end = 1125 &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1126 struct rx_mpdu_start_compact *mpdu_start = 1127 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1128 1129 hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level); 1130 hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level); 1131 hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level); 1132 } 1133 #else 1134 static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl, 1135 uint8_t *buf, uint8_t dbg_level) 1136 { 1137 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1138 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1139 struct rx_mpdu_start *mpdu_start = 1140 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1141 1142 hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level); 1143 hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level); 1144 hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level); 1145 } 1146 #endif 1147 1148 #define HAL_NUM_TCL_BANKS_5332 24 1149 1150 /** 1151 * hal_cmem_write_5332() - function for CMEM buffer writing 1152 * @hal_soc_hdl: HAL SOC handle 1153 * @offset: CMEM address 1154 * @value: value to write 1155 * 1156 * Return: None. 1157 */ 1158 static void hal_cmem_write_5332(hal_soc_handle_t hal_soc_hdl, 1159 uint32_t offset, 1160 uint32_t value) 1161 { 1162 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1163 1164 /* cmem region is ioremapped from CMEM_REG_BASE, hence subtracting 1165 * that from offset. 1166 */ 1167 offset = offset - CMEM_REG_BASE; 1168 pld_reg_write(hal->qdf_dev->dev, offset, value, 1169 hal->dev_base_addr_cmem); 1170 } 1171 1172 /** 1173 * hal_tx_get_num_tcl_banks_5332() - Get number of banks in target 1174 * 1175 * Return: number of bank 1176 */ 1177 static uint8_t hal_tx_get_num_tcl_banks_5332(void) 1178 { 1179 return HAL_NUM_TCL_BANKS_5332; 1180 } 1181 1182 static void hal_reo_setup_5332(struct hal_soc *soc, void *reoparams, 1183 int qref_reset) 1184 { 1185 uint32_t reg_val; 1186 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 1187 1188 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 1189 REO_REG_REG_BASE)); 1190 1191 hal_reo_config_5332(soc, reg_val, reo_params); 1192 /* Other ring enable bits and REO_ENABLE will be set by FW */ 1193 1194 /* TODO: Setup destination ring mapping if enabled */ 1195 1196 /* TODO: Error destination ring setting is left to default. 1197 * Default setting is to send all errors to release ring. 1198 */ 1199 1200 /* Set the reo descriptor swap bits in case of BIG endian platform */ 1201 hal_setup_reo_swap(soc); 1202 1203 HAL_REG_WRITE(soc, 1204 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE), 1205 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 1206 1207 HAL_REG_WRITE(soc, 1208 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE), 1209 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1210 1211 HAL_REG_WRITE(soc, 1212 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE), 1213 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 1214 1215 HAL_REG_WRITE(soc, 1216 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE), 1217 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 1218 1219 /* 1220 * When hash based routing is enabled, routing of the rx packet 1221 * is done based on the following value: 1 _ _ _ _ The last 4 1222 * bits are based on hash[3:0]. This means the possible values 1223 * are 0x10 to 0x1f. This value is used to look-up the 1224 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 1225 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 1226 * registers need to be configured to set-up the 16 entries to 1227 * map the hash values to a ring number. There are 3 bits per 1228 * hash entry – which are mapped as follows: 1229 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 1230 * 7: NOT_USED. 1231 */ 1232 if (reo_params->rx_hash_enabled) { 1233 HAL_REG_WRITE(soc, 1234 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR 1235 (REO_REG_REG_BASE), reo_params->remap0); 1236 1237 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1238 HAL_REG_READ(soc, 1239 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR( 1240 REO_REG_REG_BASE))); 1241 1242 HAL_REG_WRITE(soc, 1243 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 1244 (REO_REG_REG_BASE), reo_params->remap1); 1245 1246 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 1247 HAL_REG_READ(soc, 1248 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1249 REO_REG_REG_BASE))); 1250 1251 HAL_REG_WRITE(soc, 1252 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 1253 (REO_REG_REG_BASE), reo_params->remap2); 1254 1255 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 1256 HAL_REG_READ(soc, 1257 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1258 REO_REG_REG_BASE))); 1259 } 1260 1261 /* TODO: Check if the following registers shoould be setup by host: 1262 * AGING_CONTROL 1263 * HIGH_MEMORY_THRESHOLD 1264 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 1265 * GLOBAL_LINK_DESC_COUNT_CTRL 1266 */ 1267 1268 soc->reo_qref = *reo_params->reo_qref; 1269 hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset); 1270 } 1271 1272 static uint16_t hal_get_rx_max_ba_window_qca5332(int tid) 1273 { 1274 return HAL_RX_BA_WINDOW_1024; 1275 } 1276 1277 /** 1278 * hal_qca5332_get_reo_qdesc_size() - Get the reo queue descriptor size 1279 * from the give Block-Ack window size 1280 * @ba_window_size: Block-Ack window size 1281 * @tid: TID 1282 * 1283 * Return: reo queue descriptor size 1284 */ 1285 static uint32_t hal_qca5332_get_reo_qdesc_size(uint32_t ba_window_size, int tid) 1286 { 1287 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 1288 * NON_QOS_TID until HW issues are resolved. 1289 */ 1290 if (tid != HAL_NON_QOS_TID) 1291 ba_window_size = hal_get_rx_max_ba_window_qca5332(tid); 1292 1293 /* Return descriptor size corresponding to window size of 2 since 1294 * we set ba_window_size to 2 while setting up REO descriptors as 1295 * a WAR to get 2k jump exception aggregates are received without 1296 * a BA session. 1297 */ 1298 if (ba_window_size <= 1) { 1299 if (tid != HAL_NON_QOS_TID) 1300 return sizeof(struct rx_reo_queue) + 1301 sizeof(struct rx_reo_queue_ext); 1302 else 1303 return sizeof(struct rx_reo_queue); 1304 } 1305 1306 if (ba_window_size <= 105) 1307 return sizeof(struct rx_reo_queue) + 1308 sizeof(struct rx_reo_queue_ext); 1309 1310 if (ba_window_size <= 210) 1311 return sizeof(struct rx_reo_queue) + 1312 (2 * sizeof(struct rx_reo_queue_ext)); 1313 1314 if (ba_window_size <= 256) 1315 return sizeof(struct rx_reo_queue) + 1316 (3 * sizeof(struct rx_reo_queue_ext)); 1317 1318 return sizeof(struct rx_reo_queue) + 1319 (10 * sizeof(struct rx_reo_queue_ext)) + 1320 sizeof(struct rx_reo_queue_1k); 1321 } 1322 1323 /** 1324 * hal_rx_tlv_msdu_done_copy_get_5332() - Get msdu done copy bit from rx_tlv 1325 * @buf: pointer the tx_tlv 1326 * 1327 * Return: msdu done copy bit 1328 */ 1329 static inline uint32_t hal_rx_tlv_msdu_done_copy_get_5332(uint8_t *buf) 1330 { 1331 return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf); 1332 } 1333 1334 static void hal_hw_txrx_ops_attach_qca5332(struct hal_soc *hal_soc) 1335 { 1336 /* init and setup */ 1337 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1338 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1339 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1340 hal_soc->ops->hal_get_window_address = hal_get_window_address_5332; 1341 hal_soc->ops->hal_cmem_write = hal_cmem_write_5332; 1342 1343 /* tx */ 1344 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5332; 1345 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5332; 1346 hal_soc->ops->hal_tx_comp_get_status = 1347 hal_tx_comp_get_status_generic_be; 1348 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1349 hal_tx_init_cmd_credit_ring_5332; 1350 hal_soc->ops->hal_tx_set_ppe_cmn_cfg = NULL; 1351 hal_soc->ops->hal_tx_set_ppe_vp_entry = NULL; 1352 hal_soc->ops->hal_tx_set_ppe_pri2tid = NULL; 1353 hal_soc->ops->hal_tx_update_ppe_pri2tid = NULL; 1354 hal_soc->ops->hal_tx_dump_ppe_vp_entry = NULL; 1355 hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = NULL; 1356 hal_soc->ops->hal_tx_enable_pri2tid_map = NULL; 1357 hal_soc->ops->hal_ppeds_cfg_ast_override_map_reg = NULL; 1358 hal_soc->ops->hal_tx_config_rbm_mapping_be = 1359 hal_tx_config_rbm_mapping_be_5332; 1360 1361 /* rx */ 1362 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; 1363 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1364 hal_rx_mon_hw_desc_get_mpdu_status_be; 1365 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5332; 1366 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1367 hal_rx_proc_phyrx_other_receive_info_tlv_5332; 1368 1369 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5332; 1370 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1371 hal_rx_dump_mpdu_start_tlv_5332; 1372 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_5332; 1373 1374 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5332; 1375 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be; 1376 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1377 hal_rx_tlv_reception_type_get_be; 1378 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1379 hal_rx_msdu_end_da_idx_get_be; 1380 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1381 hal_rx_msdu_desc_info_get_ptr_5332; 1382 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1383 hal_rx_link_desc_msdu0_ptr_5332; 1384 hal_soc->ops->hal_reo_status_get_header = 1385 hal_reo_status_get_header_5332; 1386 #ifdef QCA_MONITOR_2_0_SUPPORT 1387 hal_soc->ops->hal_rx_status_get_tlv_info = 1388 hal_rx_status_get_tlv_info_wrapper_be; 1389 #endif 1390 hal_soc->ops->hal_rx_wbm_err_info_get = 1391 hal_rx_wbm_err_info_get_generic_be; 1392 hal_soc->ops->hal_tx_set_pcp_tid_map = 1393 hal_tx_set_pcp_tid_map_generic_be; 1394 hal_soc->ops->hal_tx_update_pcp_tid_map = 1395 hal_tx_update_pcp_tid_generic_be; 1396 hal_soc->ops->hal_tx_set_tidmap_prty = 1397 hal_tx_update_tidmap_prty_generic_be; 1398 hal_soc->ops->hal_rx_get_rx_fragment_number = 1399 hal_rx_get_rx_fragment_number_be, 1400 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1401 hal_rx_tlv_da_is_mcbc_get_be; 1402 hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err = 1403 hal_rx_tlv_is_tkip_mic_err_get_be; 1404 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1405 hal_rx_tlv_sa_is_valid_get_be; 1406 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be; 1407 hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be; 1408 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1409 hal_rx_tlv_l3_hdr_padding_get_be; 1410 hal_soc->ops->hal_rx_encryption_info_valid = 1411 hal_rx_encryption_info_valid_be; 1412 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; 1413 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1414 hal_rx_tlv_first_msdu_get_be; 1415 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1416 hal_rx_tlv_da_is_valid_get_be; 1417 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1418 hal_rx_tlv_last_msdu_get_be; 1419 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1420 hal_rx_get_mpdu_mac_ad4_valid_be; 1421 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1422 hal_rx_mpdu_start_sw_peer_id_get_be; 1423 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1424 hal_rx_msdu_peer_meta_data_get_be; 1425 #ifndef CONFIG_WORD_BASED_TLV 1426 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; 1427 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1428 hal_rx_mpdu_info_ampdu_flag_get_be; 1429 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1430 hal_rx_hw_desc_get_ppduid_get_be; 1431 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be; 1432 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 1433 hal_rx_attn_phy_ppdu_id_get_be; 1434 hal_soc->ops->hal_rx_get_filter_category = 1435 hal_rx_get_filter_category_be; 1436 #endif 1437 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be; 1438 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be; 1439 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1440 hal_rx_get_mpdu_frame_control_valid_be; 1441 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; 1442 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; 1443 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; 1444 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1445 hal_rx_get_mpdu_sequence_control_valid_be; 1446 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; 1447 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; 1448 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1449 hal_rx_mpdu_start_mpdu_qos_control_valid_get_be; 1450 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1451 hal_rx_msdu_end_sa_sw_peer_id_get_be; 1452 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1453 hal_rx_msdu0_buffer_addr_lsb_5332; 1454 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1455 hal_rx_msdu_desc_info_ptr_get_5332; 1456 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5332; 1457 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5332; 1458 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; 1459 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; 1460 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1461 hal_rx_get_mac_addr2_valid_be; 1462 hal_soc->ops->hal_reo_config = hal_reo_config_5332; 1463 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; 1464 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1465 hal_rx_msdu_flow_idx_invalid_be; 1466 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1467 hal_rx_msdu_flow_idx_timeout_be; 1468 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1469 hal_rx_msdu_fse_metadata_get_be; 1470 hal_soc->ops->hal_rx_msdu_cce_match_get = 1471 hal_rx_msdu_cce_match_get_be; 1472 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1473 hal_rx_msdu_cce_metadata_get_be; 1474 hal_soc->ops->hal_rx_msdu_get_flow_params = 1475 hal_rx_msdu_get_flow_params_be; 1476 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be; 1477 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be; 1478 #if defined(QCA_WIFI_QCA5332) && defined(WLAN_CFR_ENABLE) && \ 1479 defined(WLAN_ENH_CFR_ENABLE) 1480 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5332; 1481 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5332; 1482 #else 1483 hal_soc->ops->hal_rx_get_bb_info = NULL; 1484 hal_soc->ops->hal_rx_get_rtt_info = NULL; 1485 #endif 1486 /* rx - msdu fast path info fields */ 1487 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1488 hal_rx_msdu_packet_metadata_get_generic_be; 1489 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1490 hal_rx_mpdu_start_tlv_tag_valid_be; 1491 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1492 hal_rx_wbm_err_msdu_continuation_get_5332; 1493 1494 /* rx - TLV struct offsets */ 1495 hal_soc->ops->hal_rx_msdu_end_offset_get = 1496 hal_rx_msdu_end_offset_get_generic; 1497 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1498 hal_rx_mpdu_start_offset_get_generic; 1499 #ifndef NO_RX_PKT_HDR_TLV 1500 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1501 hal_rx_pkt_tlv_offset_get_generic; 1502 #endif 1503 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5332; 1504 1505 hal_soc->ops->hal_rx_flow_get_tuple_info = 1506 hal_rx_flow_get_tuple_info_be; 1507 hal_soc->ops->hal_rx_flow_delete_entry = 1508 hal_rx_flow_delete_entry_be; 1509 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be; 1510 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1511 hal_compute_reo_remap_ix2_ix3_5332; 1512 1513 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 1514 hal_rx_msdu_get_reo_destination_indication_be; 1515 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; 1516 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 1517 hal_rx_msdu_is_wlan_mcast_generic_be; 1518 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_5332; 1519 hal_soc->ops->hal_rx_tlv_decap_format_get = 1520 hal_rx_tlv_decap_format_get_be; 1521 #ifdef RECEIVE_OFFLOAD 1522 hal_soc->ops->hal_rx_tlv_get_offload_info = 1523 hal_rx_tlv_get_offload_info_be; 1524 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; 1525 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; 1526 #endif 1527 hal_soc->ops->hal_rx_tlv_msdu_done_get = 1528 hal_rx_tlv_msdu_done_copy_get_5332; 1529 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1530 hal_rx_msdu_start_msdu_len_get_be; 1531 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1532 hal_rx_get_frame_ctrl_field_be; 1533 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; 1534 hal_soc->ops->hal_rx_tlv_msdu_len_set = 1535 hal_rx_msdu_start_msdu_len_set_be; 1536 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; 1537 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; 1538 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be; 1539 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be; 1540 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be; 1541 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1542 hal_rx_tlv_decrypt_err_get_be; 1543 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be; 1544 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 1545 hal_rx_tlv_get_is_decrypted_be; 1546 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be; 1547 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 1548 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1549 hal_rx_priv_info_set_in_tlv_be; 1550 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1551 hal_rx_priv_info_get_from_tlv_be; 1552 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be; 1553 hal_soc->ops->hal_reo_setup = hal_reo_setup_5332; 1554 #ifdef REO_SHARED_QREF_TABLE_EN 1555 hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be; 1556 hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be; 1557 hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be; 1558 hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be; 1559 hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be; 1560 #endif 1561 /* Overwrite the default BE ops */ 1562 hal_soc->ops->hal_get_rx_max_ba_window = 1563 hal_get_rx_max_ba_window_qca5332; 1564 hal_soc->ops->hal_get_reo_qdesc_size = hal_qca5332_get_reo_qdesc_size; 1565 /* TX MONITOR */ 1566 #ifdef QCA_MONITOR_2_0_SUPPORT 1567 hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv = 1568 hal_txmon_is_mon_buf_addr_tlv_generic_be; 1569 hal_soc->ops->hal_txmon_populate_packet_info = 1570 hal_txmon_populate_packet_info_generic_be; 1571 hal_soc->ops->hal_txmon_status_parse_tlv = 1572 hal_txmon_status_parse_tlv_generic_be; 1573 hal_soc->ops->hal_txmon_status_get_num_users = 1574 hal_txmon_status_get_num_users_generic_be; 1575 #endif /* QCA_MONITOR_2_0_SUPPORT */ 1576 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1577 hal_soc->ops->hal_tx_vdev_mismatch_routing_set = 1578 hal_tx_vdev_mismatch_routing_set_generic_be; 1579 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = 1580 hal_tx_mcast_mlo_reinject_routing_set_generic_be; 1581 hal_soc->ops->hal_get_ba_aging_timeout = 1582 hal_get_ba_aging_timeout_be_generic; 1583 hal_soc->ops->hal_setup_link_idle_list = 1584 hal_setup_link_idle_list_generic_be; 1585 hal_soc->ops->hal_cookie_conversion_reg_cfg_be = 1586 hal_cookie_conversion_reg_cfg_generic_be; 1587 hal_soc->ops->hal_set_ba_aging_timeout = 1588 hal_set_ba_aging_timeout_be_generic; 1589 hal_soc->ops->hal_tx_populate_bank_register = 1590 hal_tx_populate_bank_register_be; 1591 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = 1592 hal_tx_vdev_mcast_ctrl_set_be; 1593 hal_soc->ops->hal_get_tsf2_scratch_reg = 1594 hal_get_tsf2_scratch_reg_qca5332; 1595 hal_soc->ops->hal_get_tqm_scratch_reg = 1596 hal_get_tqm_scratch_reg_qca5332; 1597 #ifdef CONFIG_WORD_BASED_TLV 1598 hal_soc->ops->hal_rx_mpdu_start_wmask_get = 1599 hal_rx_mpdu_start_wmask_get_be; 1600 hal_soc->ops->hal_rx_msdu_end_wmask_get = 1601 hal_rx_msdu_end_wmask_get_be; 1602 #endif 1603 }; 1604 1605 struct hal_hw_srng_config hw_srng_table_5332[] = { 1606 /* TODO: max_rings can populated by querying HW capabilities */ 1607 { /* REO_DST */ 1608 .start_ring_id = HAL_SRNG_REO2SW1, 1609 .max_rings = 8, 1610 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1611 .lmac_ring = FALSE, 1612 .ring_dir = HAL_SRNG_DST_RING, 1613 .reg_start = { 1614 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1615 REO_REG_REG_BASE), 1616 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1617 REO_REG_REG_BASE) 1618 }, 1619 .reg_size = { 1620 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1621 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1622 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1623 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1624 }, 1625 .max_size = 1626 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1627 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1628 }, 1629 { /* REO_EXCEPTION */ 1630 /* Designating REO2SW0 ring as exception ring. This ring is 1631 * similar to other REO2SW rings though it is named as REO2SW0. 1632 * Any of theREO2SW rings can be used as exception ring. 1633 */ 1634 .start_ring_id = HAL_SRNG_REO2SW0, 1635 .max_rings = 1, 1636 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1637 .lmac_ring = FALSE, 1638 .ring_dir = HAL_SRNG_DST_RING, 1639 .reg_start = { 1640 HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR( 1641 REO_REG_REG_BASE), 1642 HWIO_REO_R2_REO2SW0_RING_HP_ADDR( 1643 REO_REG_REG_BASE) 1644 }, 1645 /* Single ring - provide ring size if multiple rings of this 1646 * type are supported 1647 */ 1648 .reg_size = {}, 1649 .max_size = 1650 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >> 1651 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT, 1652 }, 1653 { /* REO_REINJECT */ 1654 .start_ring_id = HAL_SRNG_SW2REO, 1655 .max_rings = 4, 1656 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1657 .lmac_ring = FALSE, 1658 .ring_dir = HAL_SRNG_SRC_RING, 1659 .reg_start = { 1660 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1661 REO_REG_REG_BASE), 1662 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1663 REO_REG_REG_BASE) 1664 }, 1665 /* Single ring - provide ring size if multiple rings of this 1666 * type are supported 1667 */ 1668 .reg_size = { 1669 HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) - 1670 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0), 1671 HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) - 1672 HWIO_REO_R2_SW2REO_RING_HP_ADDR(0) 1673 }, 1674 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1675 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1676 }, 1677 { /* REO_CMD */ 1678 .start_ring_id = HAL_SRNG_REO_CMD, 1679 .max_rings = 1, 1680 .entry_size = (sizeof(struct tlv_32_hdr) + 1681 sizeof(struct reo_get_queue_stats)) >> 2, 1682 .lmac_ring = FALSE, 1683 .ring_dir = HAL_SRNG_SRC_RING, 1684 .reg_start = { 1685 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1686 REO_REG_REG_BASE), 1687 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1688 REO_REG_REG_BASE), 1689 }, 1690 /* Single ring - provide ring size if multiple rings of this 1691 * type are supported 1692 */ 1693 .reg_size = {}, 1694 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1695 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1696 }, 1697 { /* REO_STATUS */ 1698 .start_ring_id = HAL_SRNG_REO_STATUS, 1699 .max_rings = 1, 1700 .entry_size = (sizeof(struct tlv_32_hdr) + 1701 sizeof(struct reo_get_queue_stats_status)) >> 2, 1702 .lmac_ring = FALSE, 1703 .ring_dir = HAL_SRNG_DST_RING, 1704 .reg_start = { 1705 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1706 REO_REG_REG_BASE), 1707 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1708 REO_REG_REG_BASE), 1709 }, 1710 /* Single ring - provide ring size if multiple rings of this 1711 * type are supported 1712 */ 1713 .reg_size = {}, 1714 .max_size = 1715 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1716 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1717 }, 1718 { /* TCL_DATA */ 1719 .start_ring_id = HAL_SRNG_SW2TCL1, 1720 .max_rings = 6, 1721 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 1722 .lmac_ring = FALSE, 1723 .ring_dir = HAL_SRNG_SRC_RING, 1724 .reg_start = { 1725 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1726 MAC_TCL_REG_REG_BASE), 1727 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1728 MAC_TCL_REG_REG_BASE), 1729 }, 1730 .reg_size = { 1731 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1732 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1733 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1734 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1735 }, 1736 .max_size = 1737 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1738 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1739 }, 1740 { /* TCL_CMD/CREDIT */ 1741 /* qca8074v2 and qca5332 uses this ring for data commands */ 1742 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1743 .max_rings = 1, 1744 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 1745 .lmac_ring = FALSE, 1746 .ring_dir = HAL_SRNG_SRC_RING, 1747 .reg_start = { 1748 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 1749 MAC_TCL_REG_REG_BASE), 1750 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 1751 MAC_TCL_REG_REG_BASE), 1752 }, 1753 /* Single ring - provide ring size if multiple rings of this 1754 * type are supported 1755 */ 1756 .reg_size = {}, 1757 .max_size = 1758 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 1759 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 1760 }, 1761 { /* TCL_STATUS */ 1762 .start_ring_id = HAL_SRNG_TCL_STATUS, 1763 .max_rings = 1, 1764 .entry_size = (sizeof(struct tlv_32_hdr) + 1765 sizeof(struct tcl_status_ring)) >> 2, 1766 .lmac_ring = FALSE, 1767 .ring_dir = HAL_SRNG_DST_RING, 1768 .reg_start = { 1769 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1770 MAC_TCL_REG_REG_BASE), 1771 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1772 MAC_TCL_REG_REG_BASE), 1773 }, 1774 /* Single ring - provide ring size if multiple rings of this 1775 * type are supported 1776 */ 1777 .reg_size = {}, 1778 .max_size = 1779 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1780 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1781 }, 1782 { /* CE_SRC */ 1783 .start_ring_id = HAL_SRNG_CE_0_SRC, 1784 .max_rings = 16, 1785 .entry_size = sizeof(struct ce_src_desc) >> 2, 1786 .lmac_ring = FALSE, 1787 .ring_dir = HAL_SRNG_SRC_RING, 1788 .reg_start = { 1789 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR( 1790 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE), 1791 HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR( 1792 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE), 1793 }, 1794 .reg_size = { 1795 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 1796 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 1797 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 1798 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 1799 }, 1800 .max_size = 1801 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >> 1802 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT, 1803 }, 1804 { /* CE_DST */ 1805 .start_ring_id = HAL_SRNG_CE_0_DST, 1806 .max_rings = 16, 1807 .entry_size = 8 >> 2, 1808 /*TODO: entry_size above should actually be 1809 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1810 * of struct ce_dst_desc in HW header files 1811 */ 1812 .lmac_ring = FALSE, 1813 .ring_dir = HAL_SRNG_SRC_RING, 1814 .reg_start = { 1815 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1816 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 1817 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1818 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 1819 }, 1820 .reg_size = { 1821 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 1822 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 1823 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 1824 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 1825 }, 1826 .max_size = 1827 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1828 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1829 }, 1830 { /* CE_DST_STATUS */ 1831 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1832 .max_rings = 16, 1833 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1834 .lmac_ring = FALSE, 1835 .ring_dir = HAL_SRNG_DST_RING, 1836 .reg_start = { 1837 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1838 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 1839 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1840 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE), 1841 }, 1842 /* TODO: check destination status ring registers */ 1843 .reg_size = { 1844 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 1845 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 1846 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 1847 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 1848 }, 1849 .max_size = 1850 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1851 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1852 }, 1853 { /* WBM_IDLE_LINK */ 1854 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1855 .max_rings = 1, 1856 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1857 .lmac_ring = FALSE, 1858 .ring_dir = HAL_SRNG_SRC_RING, 1859 .reg_start = { 1860 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 1861 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE), 1862 }, 1863 /* Single ring - provide ring size if multiple rings of this 1864 * type are supported 1865 */ 1866 .reg_size = {}, 1867 .max_size = 1868 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1869 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1870 }, 1871 { /* SW2WBM_RELEASE */ 1872 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1873 .max_rings = 1, 1874 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1875 .lmac_ring = FALSE, 1876 .ring_dir = HAL_SRNG_SRC_RING, 1877 .reg_start = { 1878 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 1879 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 1880 }, 1881 /* Single ring - provide ring size if multiple rings of this 1882 * type are supported 1883 */ 1884 .reg_size = {}, 1885 .max_size = 1886 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1887 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1888 }, 1889 { /* WBM2SW_RELEASE */ 1890 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1891 .max_rings = 8, 1892 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1893 .lmac_ring = FALSE, 1894 .ring_dir = HAL_SRNG_DST_RING, 1895 .reg_start = { 1896 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR( 1897 WBM_REG_REG_BASE), 1898 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR( 1899 WBM_REG_REG_BASE), 1900 }, 1901 .reg_size = { 1902 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR( 1903 WBM_REG_REG_BASE) - 1904 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR( 1905 WBM_REG_REG_BASE), 1906 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR( 1907 WBM_REG_REG_BASE) - 1908 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR( 1909 WBM_REG_REG_BASE), 1910 }, 1911 .max_size = 1912 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1913 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1914 }, 1915 { /* RXDMA_BUF */ 1916 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1917 #ifdef IPA_OFFLOAD 1918 .max_rings = 3, 1919 #else 1920 .max_rings = 3, 1921 #endif 1922 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1923 .lmac_ring = TRUE, 1924 .ring_dir = HAL_SRNG_SRC_RING, 1925 /* reg_start is not set because LMAC rings are not accessed 1926 * from host 1927 */ 1928 .reg_start = {}, 1929 .reg_size = {}, 1930 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1931 }, 1932 { /* RXDMA_DST */ 1933 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1934 .max_rings = 0, 1935 .entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/, 1936 .lmac_ring = TRUE, 1937 .ring_dir = HAL_SRNG_DST_RING, 1938 /* reg_start is not set because LMAC rings are not accessed 1939 * from host 1940 */ 1941 .reg_start = {}, 1942 .reg_size = {}, 1943 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1944 }, 1945 #ifdef QCA_MONITOR_2_0_SUPPORT 1946 { /* RXDMA_MONITOR_BUF */ 1947 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1948 .max_rings = 1, 1949 .entry_size = sizeof(struct mon_ingress_ring) >> 2, 1950 .lmac_ring = TRUE, 1951 .ring_dir = HAL_SRNG_SRC_RING, 1952 /* reg_start is not set because LMAC rings are not accessed 1953 * from host 1954 */ 1955 .reg_start = {}, 1956 .reg_size = {}, 1957 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 1958 }, 1959 #else 1960 {}, 1961 #endif 1962 { /* RXDMA_MONITOR_STATUS */ 1963 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1964 .max_rings = 0, 1965 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1966 .lmac_ring = TRUE, 1967 .ring_dir = HAL_SRNG_SRC_RING, 1968 /* reg_start is not set because LMAC rings are not accessed 1969 * from host 1970 */ 1971 .reg_start = {}, 1972 .reg_size = {}, 1973 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1974 }, 1975 #ifdef QCA_MONITOR_2_0_SUPPORT 1976 { /* RXDMA_MONITOR_DST */ 1977 .start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0, 1978 .max_rings = 2, 1979 .entry_size = sizeof(struct mon_destination_ring) >> 2, 1980 .lmac_ring = TRUE, 1981 .ring_dir = HAL_SRNG_DST_RING, 1982 /* reg_start is not set because LMAC rings are not accessed 1983 * from host 1984 */ 1985 .reg_start = {}, 1986 .reg_size = {}, 1987 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 1988 }, 1989 #else 1990 {}, 1991 #endif 1992 { /* RXDMA_MONITOR_DESC */ 1993 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1994 .max_rings = 0, 1995 .entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/, 1996 .lmac_ring = TRUE, 1997 .ring_dir = HAL_SRNG_DST_RING, 1998 /* reg_start is not set because LMAC rings are not accessed 1999 * from host 2000 */ 2001 .reg_start = {}, 2002 .reg_size = {}, 2003 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2004 }, 2005 2006 { /* DIR_BUF_RX_DMA_SRC */ 2007 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2008 /* one ring for spectral and one ring for cfr */ 2009 .max_rings = 2, 2010 .entry_size = 2, 2011 .lmac_ring = TRUE, 2012 .ring_dir = HAL_SRNG_SRC_RING, 2013 /* reg_start is not set because LMAC rings are not accessed 2014 * from host 2015 */ 2016 .reg_start = {}, 2017 .reg_size = {}, 2018 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2019 }, 2020 #ifdef WLAN_FEATURE_CIF_CFR 2021 { /* WIFI_POS_SRC */ 2022 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2023 .max_rings = 1, 2024 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2025 .lmac_ring = TRUE, 2026 .ring_dir = HAL_SRNG_SRC_RING, 2027 /* reg_start is not set because LMAC rings are not accessed 2028 * from host 2029 */ 2030 .reg_start = {}, 2031 .reg_size = {}, 2032 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2033 }, 2034 #endif 2035 /* PPE rings are not present in Miami. Added dummy entries to preserve 2036 * Array Index 2037 */ 2038 /* REO2PPE */ 2039 {}, 2040 /* PPE2TCL */ 2041 {}, 2042 /* PPE_RELEASE */ 2043 {}, 2044 #ifdef QCA_MONITOR_2_0_SUPPORT 2045 { /* TX_MONITOR_BUF */ 2046 .start_ring_id = HAL_SRNG_SW2TXMON_BUF0, 2047 .max_rings = 1, 2048 .entry_size = sizeof(struct mon_ingress_ring) >> 2, 2049 .lmac_ring = TRUE, 2050 .ring_dir = HAL_SRNG_SRC_RING, 2051 /* reg_start is not set because LMAC rings are not accessed 2052 * from host 2053 */ 2054 .reg_start = {}, 2055 .reg_size = {}, 2056 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2057 }, 2058 { /* TX_MONITOR_DST */ 2059 .start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0, 2060 .max_rings = 2, 2061 .entry_size = sizeof(struct mon_destination_ring) >> 2, 2062 .lmac_ring = TRUE, 2063 .ring_dir = HAL_SRNG_DST_RING, 2064 /* reg_start is not set because LMAC rings are not accessed 2065 * from host 2066 */ 2067 .reg_start = {}, 2068 .reg_size = {}, 2069 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2070 }, 2071 #else 2072 {}, 2073 {}, 2074 #endif 2075 { /* SW2RXDMA */ 2076 .start_ring_id = HAL_SRNG_SW2RXDMA_BUF0, 2077 .max_rings = 3, 2078 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2079 .lmac_ring = TRUE, 2080 .ring_dir = HAL_SRNG_SRC_RING, 2081 /* reg_start is not set because LMAC rings are not accessed 2082 * from host 2083 */ 2084 .reg_start = {}, 2085 .reg_size = {}, 2086 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2087 .dmac_cmn_ring = TRUE, 2088 }, 2089 }; 2090 2091 /** 2092 * hal_srng_hw_reg_offset_init_qca5332() - Initialize the HW srng reg offset 2093 * applicable only for qca5332 2094 * @hal_soc: HAL Soc handle 2095 * 2096 * Return: None 2097 */ 2098 static inline void hal_srng_hw_reg_offset_init_qca5332(struct hal_soc *hal_soc) 2099 { 2100 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 2101 2102 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB), 2103 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB), 2104 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA), 2105 hw_reg_offset[DST_PRODUCER_INT2_SETUP] = 2106 REG_OFFSET(DST, PRODUCER_INT2_SETUP); 2107 } 2108 2109 /** 2110 * hal_qca5332_attach() - Attach 5332 target specific hal_soc ops, 2111 * offset and srng table 2112 * @hal_soc: hal_soc handle 2113 * 2114 * Return: void 2115 */ 2116 void hal_qca5332_attach(struct hal_soc *hal_soc) 2117 { 2118 hal_soc->hw_srng_table = hw_srng_table_5332; 2119 2120 hal_srng_hw_reg_offset_init_generic(hal_soc); 2121 hal_srng_hw_reg_offset_init_qca5332(hal_soc); 2122 2123 hal_hw_txrx_default_ops_attach_be(hal_soc); 2124 hal_hw_txrx_ops_attach_qca5332(hal_soc); 2125 hal_soc->dmac_cmn_src_rxbuf_ring = true; 2126 } 2127