1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 20 ((uint8_t *)(link_desc_va) + \ 21 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET) 22 23 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 24 ((uint8_t *)(msdu0) + \ 25 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET) 26 27 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 28 ((uint8_t *)(ent_ring_desc) + \ 29 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET) 30 31 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 32 ((uint8_t *)(dst_ring_desc) + \ 33 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET) 34 35 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 36 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MPDU_FRAME_CONTROL_VALID) 37 38 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 39 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, TO_DS) 40 41 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 42 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD1_VALID) 43 44 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 45 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD2_VALID) 46 47 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 48 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, RXPCU_MPDU_FILTER_IN_CATEGORY) 49 50 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 51 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, PHY_PPDU_ID) 52 53 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 54 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, SW_FRAME_GROUP_ID) 55 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 56 do { \ 57 (reg_val) &= \ 58 ~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\ 59 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 60 (reg_val) |= \ 61 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 62 AGING_LIST_ENABLE, 1) |\ 63 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 64 AGING_FLUSH_ENABLE, 1);\ 65 HAL_REG_WRITE((soc), \ 66 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 67 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 68 (reg_val)); \ 69 (reg_val) = \ 70 HAL_REG_READ((soc), \ 71 HWIO_REO_R0_MISC_CTL_ADDR( \ 72 SEQ_WCSS_UMAC_REO_REG_OFFSET)); \ 73 (reg_val) &= \ 74 ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \ 75 (reg_val) |= \ 76 HAL_SM(HWIO_REO_R0_MISC_CTL, \ 77 FRAGMENT_DEST_RING, \ 78 (reo_params)->frag_dst_ring); \ 79 HAL_REG_WRITE((soc), \ 80 HWIO_REO_R0_MISC_CTL_ADDR( \ 81 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 82 (reg_val)); \ 83 (reg_val) = \ 84 HAL_REG_READ((soc), \ 85 HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR( \ 86 SEQ_WCSS_UMAC_REO_REG_OFFSET)); \ 87 (reg_val) &= \ 88 ~(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK); \ 89 (reg_val) |= \ 90 HAL_SM(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0, \ 91 DEST_RING_ALT_MAPPING_0, \ 92 (reo_params)->alt_dst_ind_0); \ 93 HAL_REG_WRITE((soc), \ 94 HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR( \ 95 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 96 (reg_val)); \ 97 } while (0) 98 99 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 100 ((struct rx_msdu_desc_info *) \ 101 _OFFSET_TO_BYTE_PTR((msdu_details_ptr), \ 102 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 103 104 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 105 ((struct rx_msdu_details *) \ 106 _OFFSET_TO_BYTE_PTR((link_desc),\ 107 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 108 109 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 110 (_HAL_MS( \ 111 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 112 msdu_end_tlv.rx_msdu_end), \ 113 RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET)), \ 114 RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK, \ 115 RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB)) 116 117 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 118 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 119 RX_MSDU_END_10_FIRST_MSDU_OFFSET)), \ 120 RX_MSDU_END_10_FIRST_MSDU_MASK, \ 121 RX_MSDU_END_10_FIRST_MSDU_LSB)) 122 123 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 124 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 125 RX_MSDU_END_10_LAST_MSDU_OFFSET)), \ 126 RX_MSDU_END_10_LAST_MSDU_MASK, \ 127 RX_MSDU_END_10_LAST_MSDU_LSB)) 128 129 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 130 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 131 RX_MSDU_END_10_SA_IS_VALID_OFFSET)), \ 132 RX_MSDU_END_10_SA_IS_VALID_MASK, \ 133 RX_MSDU_END_10_SA_IS_VALID_LSB)) 134 135 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 136 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 137 RX_MSDU_END_10_DA_IS_VALID_OFFSET)), \ 138 RX_MSDU_END_10_DA_IS_VALID_MASK, \ 139 RX_MSDU_END_10_DA_IS_VALID_LSB)) 140 141 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 142 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 143 RX_MSDU_END_10_DA_IS_MCBC_OFFSET)), \ 144 RX_MSDU_END_10_DA_IS_MCBC_MASK, \ 145 RX_MSDU_END_10_DA_IS_MCBC_LSB)) 146 147 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 148 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 149 RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET)), \ 150 RX_MSDU_END_10_L3_HEADER_PADDING_MASK, \ 151 RX_MSDU_END_10_L3_HEADER_PADDING_LSB)) 152 153 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 154 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 155 RX_MSDU_END_11_SA_IDX_OFFSET)), \ 156 RX_MSDU_END_11_SA_IDX_MASK, \ 157 RX_MSDU_END_11_SA_IDX_LSB)) 158 159 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 160 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 161 RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET)), \ 162 RX_MSDU_END_14_SA_SW_PEER_ID_MASK, \ 163 RX_MSDU_END_14_SA_SW_PEER_ID_LSB)) 164 165 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 166 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 167 RX_MSDU_END_14_CCE_METADATA_OFFSET)), \ 168 RX_MSDU_END_14_CCE_METADATA_MASK, \ 169 RX_MSDU_END_14_CCE_METADATA_LSB)) 170 171 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 172 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 173 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET)), \ 174 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK, \ 175 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB)) 176 177 #define HAL_RX_MPDU_SW_FRAME_GROUP_ID_GET(_rx_mpdu_info) \ 178 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 179 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), \ 180 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, \ 181 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)) \ 182 183 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 184 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 185 RX_MPDU_INFO_10_SW_PEER_ID_OFFSET)), \ 186 RX_MPDU_INFO_10_SW_PEER_ID_MASK, \ 187 RX_MPDU_INFO_10_SW_PEER_ID_LSB)) 188 189 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 190 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 191 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 192 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK, \ 193 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB)) 194 195 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 196 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 197 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET)), \ 198 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK, \ 199 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB)) 200 201 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 202 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 203 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 204 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 205 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 206 207 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 208 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 209 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 210 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 211 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 212 213 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 214 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 215 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET)), \ 216 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK, \ 217 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB)) 218 219 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 220 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 221 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 222 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 223 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 224 225 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 226 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 227 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 228 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 229 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 230 231 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 232 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 233 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET)), \ 234 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK, \ 235 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB)) 236 237 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 238 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 239 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 240 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 241 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 242 243 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 244 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 245 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 246 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 247 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 248 249 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 250 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 251 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \ 252 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \ 253 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB)) 254 255 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 256 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 257 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 258 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 259 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 260 261 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 262 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 263 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 264 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 265 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 266 267 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 268 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 269 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 270 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 271 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 272 273 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 274 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 275 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 276 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 277 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 278 279 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 280 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 281 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 282 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 283 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB)) 284 285 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 286 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 287 RX_MPDU_INFO_11_FR_DS_OFFSET)), \ 288 RX_MPDU_INFO_11_FR_DS_MASK, \ 289 RX_MPDU_INFO_11_FR_DS_LSB)) 290 291 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 292 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 293 RX_MPDU_INFO_11_TO_DS_OFFSET)), \ 294 RX_MPDU_INFO_11_TO_DS_MASK, \ 295 RX_MPDU_INFO_11_TO_DS_LSB)) 296 297 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 298 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 299 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 300 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK, \ 301 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB)) 302 303 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 304 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 305 RX_MPDU_INFO_3_PN_31_0_OFFSET)), \ 306 RX_MPDU_INFO_3_PN_31_0_MASK, \ 307 RX_MPDU_INFO_3_PN_31_0_LSB)) 308 309 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 310 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 311 RX_MPDU_INFO_4_PN_63_32_OFFSET)), \ 312 RX_MPDU_INFO_4_PN_63_32_MASK, \ 313 RX_MPDU_INFO_4_PN_63_32_LSB)) 314 315 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 316 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 317 RX_MPDU_INFO_5_PN_95_64_OFFSET)), \ 318 RX_MPDU_INFO_5_PN_95_64_MASK, \ 319 RX_MPDU_INFO_5_PN_95_64_LSB)) 320 321 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 322 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 323 RX_MPDU_INFO_6_PN_127_96_OFFSET)), \ 324 RX_MPDU_INFO_6_PN_127_96_MASK, \ 325 RX_MPDU_INFO_6_PN_127_96_LSB)) 326 327 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 328 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 329 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET)), \ 330 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK, \ 331 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB)) 332 333 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 334 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 335 RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET)), \ 336 RX_MSDU_END_10_FLOW_IDX_INVALID_MASK, \ 337 RX_MSDU_END_10_FLOW_IDX_INVALID_LSB)) 338 339 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 340 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 341 RX_MSDU_END_12_FLOW_IDX_OFFSET)), \ 342 RX_MSDU_END_12_FLOW_IDX_MASK, \ 343 RX_MSDU_END_12_FLOW_IDX_LSB)) 344 345 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 346 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 347 RX_MSDU_END_13_FSE_METADATA_OFFSET)), \ 348 RX_MSDU_END_13_FSE_METADATA_MASK, \ 349 RX_MSDU_END_13_FSE_METADATA_LSB)) 350 351 #define HAL_RX_MPDU_GET_PHY_PPDU_ID(_rx_mpdu_info) \ 352 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 353 RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET)), \ 354 RX_MPDU_INFO_9_PHY_PPDU_ID_MASK, \ 355 RX_MPDU_INFO_9_PHY_PPDU_ID_LSB)) \ 356 357 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ 358 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 359 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ 360 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ 361 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) 362 363 #ifdef GET_MSDU_AGGREGATION 364 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 365 {\ 366 struct rx_msdu_end *rx_msdu_end;\ 367 bool first_msdu, last_msdu; \ 368 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 369 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_10, FIRST_MSDU);\ 370 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_10, LAST_MSDU);\ 371 if (first_msdu && last_msdu)\ 372 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 373 else\ 374 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 375 } \ 376 377 #else 378 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 379 #endif 380 381 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 382 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 383 RX_MPDU_INFO_7_TID_OFFSET)), \ 384 RX_MPDU_INFO_7_TID_MASK, \ 385 RX_MPDU_INFO_7_TID_LSB)) 386 387 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 388 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 389 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 390 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 391 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 392 393 #define HAL_RX_REO_ENT_PHY_PPDU_ID_GET(reo_ent_desc) \ 394 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, \ 395 REO_ENTRANCE_RING_7_PHY_PPDU_ID_OFFSET)), \ 396 REO_ENTRANCE_RING_7_PHY_PPDU_ID_MASK, \ 397 REO_ENTRANCE_RING_7_PHY_PPDU_ID_LSB)) 398