1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 25 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 26 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 27 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 28 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 29 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 30 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 31 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 32 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 33 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 34 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 35 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 36 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 37 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 38 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 39 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 40 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 41 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 42 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 43 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 44 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 45 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 48 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 49 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 50 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 51 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 52 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 53 RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 54 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 55 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 56 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 57 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 58 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 59 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 60 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 61 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 62 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 63 STATUS_HEADER_REO_STATUS_NUMBER 64 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 65 STATUS_HEADER_TIMESTAMP 66 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 67 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 68 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 69 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 70 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 71 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 72 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 73 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 74 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 75 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 76 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 77 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 78 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 79 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 80 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 81 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 82 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 83 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 84 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 85 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 86 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 87 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 88 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 89 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 90 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 91 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 92 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 93 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 94 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 95 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 96 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 97 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 98 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 99 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 100 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 101 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 102 103 #define CE_WINDOW_ADDRESS_5018 \ 104 ((WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 105 106 #define UMAC_WINDOW_ADDRESS_5018 \ 107 ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 108 109 #define WINDOW_CONFIGURATION_VALUE_5018 \ 110 ((CE_WINDOW_ADDRESS_5018 << 6) |\ 111 (UMAC_WINDOW_ADDRESS_5018 << 12) | \ 112 WINDOW_ENABLE_BIT) 113 114 #include <hal_5018_tx.h> 115 #include <hal_5018_rx.h> 116 #include <hal_generic_api.h> 117 #include <hal_wbm.h> 118 119 /** 120 * hal_rx_msdu_start_nss_get_5018(): API to get the NSS 121 * Interval from rx_msdu_start 122 * 123 * @buf: pointer to the start of RX PKT TLV header 124 * Return: uint32_t(nss) 125 */ 126 static uint32_t hal_rx_msdu_start_nss_get_5018(uint8_t *buf) 127 { 128 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 129 struct rx_msdu_start *msdu_start = 130 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 131 uint8_t mimo_ss_bitmap; 132 133 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 134 135 return qdf_get_hweight8(mimo_ss_bitmap); 136 } 137 138 /** 139 * hal_rx_mon_hw_desc_get_mpdu_status_5018(): Retrieve MPDU status 140 * 141 * @ hw_desc_addr: Start address of Rx HW TLVs 142 * @ rs: Status for monitor mode 143 * 144 * Return: void 145 */ 146 static void hal_rx_mon_hw_desc_get_mpdu_status_5018(void *hw_desc_addr, 147 struct mon_rx_status *rs) 148 { 149 struct rx_msdu_start *rx_msdu_start; 150 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 151 uint32_t reg_value; 152 const uint32_t sgi_hw_to_cdp[] = { 153 CDP_SGI_0_8_US, 154 CDP_SGI_0_4_US, 155 CDP_SGI_1_6_US, 156 CDP_SGI_3_2_US, 157 }; 158 159 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 160 161 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 162 163 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 164 RX_MSDU_START_5, USER_RSSI); 165 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 166 167 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 168 rs->sgi = sgi_hw_to_cdp[reg_value]; 169 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 170 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 171 /* TODO: rs->beamformed should be set for SU beamforming also */ 172 } 173 174 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 175 /** 176 * hal_get_link_desc_size_5018(): API to get the link desc size 177 * 178 * Return: uint32_t 179 */ 180 static uint32_t hal_get_link_desc_size_5018(void) 181 { 182 return LINK_DESC_SIZE; 183 } 184 185 /** 186 * hal_rx_get_tlv_5018(): API to get the tlv 187 * 188 * @rx_tlv: TLV data extracted from the rx packet 189 * Return: uint8_t 190 */ 191 static uint8_t hal_rx_get_tlv_5018(void *rx_tlv) 192 { 193 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 194 } 195 196 /** 197 * hal_rx_proc_phyrx_other_receive_info_tlv_5018(): API to get tlv info 198 * 199 * Return: uint32_t 200 */ 201 static inline 202 void hal_rx_proc_phyrx_other_receive_info_tlv_5018(void *rx_tlv_hdr, 203 void *ppdu_info_hdl) 204 { 205 } 206 207 /** 208 * hal_rx_dump_msdu_start_tlv_5018() : dump RX msdu_start TLV in structured 209 * human readable format. 210 * @ msdu_start: pointer the msdu_start TLV in pkt. 211 * @ dbg_level: log level. 212 * 213 * Return: void 214 */ 215 static void hal_rx_dump_msdu_start_tlv_5018(void *msdustart, 216 uint8_t dbg_level) 217 { 218 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 219 220 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 221 "rx_msdu_start tlv - " 222 "rxpcu_mpdu_filter_in_category: %d " 223 "sw_frame_group_id: %d " 224 "phy_ppdu_id: %d " 225 "msdu_length: %d " 226 "ipsec_esp: %d " 227 "l3_offset: %d " 228 "ipsec_ah: %d " 229 "l4_offset: %d " 230 "msdu_number: %d " 231 "decap_format: %d " 232 "ipv4_proto: %d " 233 "ipv6_proto: %d " 234 "tcp_proto: %d " 235 "udp_proto: %d " 236 "ip_frag: %d " 237 "tcp_only_ack: %d " 238 "da_is_bcast_mcast: %d " 239 "ip4_protocol_ip6_next_header: %d " 240 "toeplitz_hash_2_or_4: %d " 241 "flow_id_toeplitz: %d " 242 "user_rssi: %d " 243 "pkt_type: %d " 244 "stbc: %d " 245 "sgi: %d " 246 "rate_mcs: %d " 247 "receive_bandwidth: %d " 248 "reception_type: %d " 249 "ppdu_start_timestamp: %d " 250 "sw_phy_meta_data: %d ", 251 msdu_start->rxpcu_mpdu_filter_in_category, 252 msdu_start->sw_frame_group_id, 253 msdu_start->phy_ppdu_id, 254 msdu_start->msdu_length, 255 msdu_start->ipsec_esp, 256 msdu_start->l3_offset, 257 msdu_start->ipsec_ah, 258 msdu_start->l4_offset, 259 msdu_start->msdu_number, 260 msdu_start->decap_format, 261 msdu_start->ipv4_proto, 262 msdu_start->ipv6_proto, 263 msdu_start->tcp_proto, 264 msdu_start->udp_proto, 265 msdu_start->ip_frag, 266 msdu_start->tcp_only_ack, 267 msdu_start->da_is_bcast_mcast, 268 msdu_start->ip4_protocol_ip6_next_header, 269 msdu_start->toeplitz_hash_2_or_4, 270 msdu_start->flow_id_toeplitz, 271 msdu_start->user_rssi, 272 msdu_start->pkt_type, 273 msdu_start->stbc, 274 msdu_start->sgi, 275 msdu_start->rate_mcs, 276 msdu_start->receive_bandwidth, 277 msdu_start->reception_type, 278 msdu_start->ppdu_start_timestamp, 279 msdu_start->sw_phy_meta_data); 280 } 281 282 /** 283 * hal_rx_dump_msdu_end_tlv_5018: dump RX msdu_end TLV in structured 284 * human readable format. 285 * @ msdu_end: pointer the msdu_end TLV in pkt. 286 * @ dbg_level: log level. 287 * 288 * Return: void 289 */ 290 static void hal_rx_dump_msdu_end_tlv_5018(void *msduend, 291 uint8_t dbg_level) 292 { 293 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 294 295 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 296 "rx_msdu_end tlv - " 297 "rxpcu_mpdu_filter_in_category: %d " 298 "sw_frame_group_id: %d " 299 "phy_ppdu_id: %d " 300 "ip_hdr_chksum: %d " 301 "reported_mpdu_length: %d " 302 "key_id_octet: %d " 303 "cce_super_rule: %d " 304 "cce_classify_not_done_truncat: %d " 305 "cce_classify_not_done_cce_dis: %d " 306 "rule_indication_31_0: %d " 307 "rule_indication_63_32: %d " 308 "da_offset: %d " 309 "sa_offset: %d " 310 "da_offset_valid: %d " 311 "sa_offset_valid: %d " 312 "ipv6_options_crc: %d " 313 "tcp_seq_number: %d " 314 "tcp_ack_number: %d " 315 "tcp_flag: %d " 316 "lro_eligible: %d " 317 "window_size: %d " 318 "tcp_udp_chksum: %d " 319 "sa_idx_timeout: %d " 320 "da_idx_timeout: %d " 321 "msdu_limit_error: %d " 322 "flow_idx_timeout: %d " 323 "flow_idx_invalid: %d " 324 "wifi_parser_error: %d " 325 "amsdu_parser_error: %d " 326 "sa_is_valid: %d " 327 "da_is_valid: %d " 328 "da_is_mcbc: %d " 329 "l3_header_padding: %d " 330 "first_msdu: %d " 331 "last_msdu: %d " 332 "sa_idx: %d " 333 "msdu_drop: %d " 334 "reo_destination_indication: %d " 335 "flow_idx: %d " 336 "fse_metadata: %d " 337 "cce_metadata: %d " 338 "sa_sw_peer_id: %d ", 339 msdu_end->rxpcu_mpdu_filter_in_category, 340 msdu_end->sw_frame_group_id, 341 msdu_end->phy_ppdu_id, 342 msdu_end->ip_hdr_chksum, 343 msdu_end->reported_mpdu_length, 344 msdu_end->key_id_octet, 345 msdu_end->cce_super_rule, 346 msdu_end->cce_classify_not_done_truncate, 347 msdu_end->cce_classify_not_done_cce_dis, 348 msdu_end->rule_indication_31_0, 349 msdu_end->rule_indication_63_32, 350 msdu_end->da_offset, 351 msdu_end->sa_offset, 352 msdu_end->da_offset_valid, 353 msdu_end->sa_offset_valid, 354 msdu_end->ipv6_options_crc, 355 msdu_end->tcp_seq_number, 356 msdu_end->tcp_ack_number, 357 msdu_end->tcp_flag, 358 msdu_end->lro_eligible, 359 msdu_end->window_size, 360 msdu_end->tcp_udp_chksum, 361 msdu_end->sa_idx_timeout, 362 msdu_end->da_idx_timeout, 363 msdu_end->msdu_limit_error, 364 msdu_end->flow_idx_timeout, 365 msdu_end->flow_idx_invalid, 366 msdu_end->wifi_parser_error, 367 msdu_end->amsdu_parser_error, 368 msdu_end->sa_is_valid, 369 msdu_end->da_is_valid, 370 msdu_end->da_is_mcbc, 371 msdu_end->l3_header_padding, 372 msdu_end->first_msdu, 373 msdu_end->last_msdu, 374 msdu_end->sa_idx, 375 msdu_end->msdu_drop, 376 msdu_end->reo_destination_indication, 377 msdu_end->flow_idx, 378 msdu_end->fse_metadata, 379 msdu_end->cce_metadata, 380 msdu_end->sa_sw_peer_id); 381 } 382 383 /** 384 * hal_rx_mpdu_start_tid_get_5018(): API to get tid 385 * from rx_msdu_start 386 * 387 * @buf: pointer to the start of RX PKT TLV header 388 * Return: uint32_t(tid value) 389 */ 390 static uint32_t hal_rx_mpdu_start_tid_get_5018(uint8_t *buf) 391 { 392 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 393 struct rx_mpdu_start *mpdu_start = 394 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 395 uint32_t tid; 396 397 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 398 399 return tid; 400 } 401 402 /** 403 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 404 * Interval from rx_msdu_start 405 * 406 * @buf: pointer to the start of RX PKT TLV header 407 * Return: uint32_t(reception_type) 408 */ 409 static uint32_t hal_rx_msdu_start_reception_type_get_5018(uint8_t *buf) 410 { 411 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 412 struct rx_msdu_start *msdu_start = 413 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 414 uint32_t reception_type; 415 416 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 417 418 return reception_type; 419 } 420 421 /** 422 * hal_rx_msdu_end_da_idx_get_5018: API to get da_idx 423 * from rx_msdu_end TLV 424 * 425 * @ buf: pointer to the start of RX PKT TLV headers 426 * Return: da index 427 */ 428 static uint16_t hal_rx_msdu_end_da_idx_get_5018(uint8_t *buf) 429 { 430 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 431 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 432 uint16_t da_idx; 433 434 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 435 436 return da_idx; 437 } 438 439 /** 440 * hal_rx_get_rx_fragment_number_5018(): Function to retrieve rx fragment number 441 * 442 * @nbuf: Network buffer 443 * Returns: rx fragment number 444 */ 445 static 446 uint8_t hal_rx_get_rx_fragment_number_5018(uint8_t *buf) 447 { 448 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 449 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 450 451 /* Return first 4 bits as fragment number */ 452 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 453 DOT11_SEQ_FRAG_MASK); 454 } 455 456 /** 457 * hal_rx_msdu_end_da_is_mcbc_get_5018(): API to check if pkt is MCBC 458 * from rx_msdu_end TLV 459 * 460 * @ buf: pointer to the start of RX PKT TLV headers 461 * Return: da_is_mcbc 462 */ 463 static uint8_t 464 hal_rx_msdu_end_da_is_mcbc_get_5018(uint8_t *buf) 465 { 466 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 467 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 468 469 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 470 } 471 472 /** 473 * hal_rx_msdu_end_sa_is_valid_get_5018(): API to get_5018 the 474 * sa_is_valid bit from rx_msdu_end TLV 475 * 476 * @ buf: pointer to the start of RX PKT TLV headers 477 * Return: sa_is_valid bit 478 */ 479 static uint8_t 480 hal_rx_msdu_end_sa_is_valid_get_5018(uint8_t *buf) 481 { 482 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 483 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 484 uint8_t sa_is_valid; 485 486 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 487 488 return sa_is_valid; 489 } 490 491 /** 492 * hal_rx_msdu_end_sa_idx_get_5018(): API to get_5018 the 493 * sa_idx from rx_msdu_end TLV 494 * 495 * @ buf: pointer to the start of RX PKT TLV headers 496 * Return: sa_idx (SA AST index) 497 */ 498 static uint16_t hal_rx_msdu_end_sa_idx_get_5018(uint8_t *buf) 499 { 500 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 501 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 502 uint16_t sa_idx; 503 504 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 505 506 return sa_idx; 507 } 508 509 /** 510 * hal_rx_desc_is_first_msdu_5018() - Check if first msdu 511 * 512 * @hal_soc_hdl: hal_soc handle 513 * @hw_desc_addr: hardware descriptor address 514 * 515 * Return: 0 - success/ non-zero failure 516 */ 517 static uint32_t hal_rx_desc_is_first_msdu_5018(void *hw_desc_addr) 518 { 519 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 520 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 521 522 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 523 } 524 525 /** 526 * hal_rx_msdu_end_l3_hdr_padding_get_5018(): API to get_5018 the 527 * l3_header padding from rx_msdu_end TLV 528 * 529 * @ buf: pointer to the start of RX PKT TLV headers 530 * Return: number of l3 header padding bytes 531 */ 532 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_5018(uint8_t *buf) 533 { 534 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 535 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 536 uint32_t l3_header_padding; 537 538 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 539 540 return l3_header_padding; 541 } 542 543 /** 544 * @ hal_rx_encryption_info_valid_5018: Returns encryption type. 545 * 546 * @ buf: rx_tlv_hdr of the received packet 547 * @ Return: encryption type 548 */ 549 inline uint32_t hal_rx_encryption_info_valid_5018(uint8_t *buf) 550 { 551 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 552 struct rx_mpdu_start *mpdu_start = 553 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 554 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 555 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 556 557 return encryption_info; 558 } 559 560 /* 561 * @ hal_rx_print_pn_5018: Prints the PN of rx packet. 562 * 563 * @ buf: rx_tlv_hdr of the received packet 564 * @ Return: void 565 */ 566 static void hal_rx_print_pn_5018(uint8_t *buf) 567 { 568 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 569 struct rx_mpdu_start *mpdu_start = 570 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 571 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 572 573 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 574 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 575 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 576 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 577 578 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 579 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 580 } 581 582 /** 583 * hal_rx_msdu_end_first_msdu_get_5018: API to get first msdu status 584 * from rx_msdu_end TLV 585 * 586 * @ buf: pointer to the start of RX PKT TLV headers 587 * Return: first_msdu 588 */ 589 static uint8_t hal_rx_msdu_end_first_msdu_get_5018(uint8_t *buf) 590 { 591 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 592 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 593 uint8_t first_msdu; 594 595 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 596 597 return first_msdu; 598 } 599 600 /** 601 * hal_rx_msdu_end_da_is_valid_get_5018: API to check if da is valid 602 * from rx_msdu_end TLV 603 * 604 * @ buf: pointer to the start of RX PKT TLV headers 605 * Return: da_is_valid 606 */ 607 static uint8_t hal_rx_msdu_end_da_is_valid_get_5018(uint8_t *buf) 608 { 609 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 610 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 611 uint8_t da_is_valid; 612 613 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 614 615 return da_is_valid; 616 } 617 618 /** 619 * hal_rx_msdu_end_last_msdu_get_5018: API to get last msdu status 620 * from rx_msdu_end TLV 621 * 622 * @ buf: pointer to the start of RX PKT TLV headers 623 * Return: last_msdu 624 */ 625 static uint8_t hal_rx_msdu_end_last_msdu_get_5018(uint8_t *buf) 626 { 627 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 628 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 629 uint8_t last_msdu; 630 631 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 632 633 return last_msdu; 634 } 635 636 /* 637 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 638 * 639 * @nbuf: Network buffer 640 * Returns: value of mpdu 4th address valid field 641 */ 642 inline bool hal_rx_get_mpdu_mac_ad4_valid_5018(uint8_t *buf) 643 { 644 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 645 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 646 bool ad4_valid = 0; 647 648 ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info); 649 650 return ad4_valid; 651 } 652 653 /** 654 * hal_rx_mpdu_start_sw_peer_id_get_5018: Retrieve sw peer_id 655 * @buf: network buffer 656 * 657 * Return: sw peer_id 658 */ 659 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_5018(uint8_t *buf) 660 { 661 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 662 struct rx_mpdu_start *mpdu_start = 663 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 664 665 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 666 &mpdu_start->rx_mpdu_info_details); 667 } 668 669 /* 670 * hal_rx_mpdu_get_to_ds_5018(): API to get the tods info 671 * from rx_mpdu_start 672 * 673 * @buf: pointer to the start of RX PKT TLV header 674 * Return: uint32_t(to_ds) 675 */ 676 static uint32_t hal_rx_mpdu_get_to_ds_5018(uint8_t *buf) 677 { 678 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 679 struct rx_mpdu_start *mpdu_start = 680 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 681 682 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 683 684 return HAL_RX_MPDU_GET_TODS(mpdu_info); 685 } 686 687 /* 688 * hal_rx_mpdu_get_fr_ds_5018(): API to get the from ds info 689 * from rx_mpdu_start 690 * 691 * @buf: pointer to the start of RX PKT TLV header 692 * Return: uint32_t(fr_ds) 693 */ 694 static uint32_t hal_rx_mpdu_get_fr_ds_5018(uint8_t *buf) 695 { 696 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 697 struct rx_mpdu_start *mpdu_start = 698 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 699 700 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 701 702 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 703 } 704 705 /* 706 * hal_rx_get_mpdu_frame_control_valid_5018(): Retrieves mpdu 707 * frame control valid 708 * 709 * @nbuf: Network buffer 710 * Returns: value of frame control valid field 711 */ 712 static uint8_t hal_rx_get_mpdu_frame_control_valid_5018(uint8_t *buf) 713 { 714 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 715 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 716 717 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 718 } 719 720 /* 721 * hal_rx_mpdu_get_addr1_5018(): API to check get address1 of the mpdu 722 * 723 * @buf: pointer to the start of RX PKT TLV headera 724 * @mac_addr: pointer to mac address 725 * Return: success/failure 726 */ 727 static QDF_STATUS hal_rx_mpdu_get_addr1_5018(uint8_t *buf, 728 uint8_t *mac_addr) 729 { 730 struct __attribute__((__packed__)) hal_addr1 { 731 uint32_t ad1_31_0; 732 uint16_t ad1_47_32; 733 }; 734 735 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 736 struct rx_mpdu_start *mpdu_start = 737 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 738 739 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 740 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 741 uint32_t mac_addr_ad1_valid; 742 743 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 744 745 if (mac_addr_ad1_valid) { 746 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 747 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 748 return QDF_STATUS_SUCCESS; 749 } 750 751 return QDF_STATUS_E_FAILURE; 752 } 753 754 /* 755 * hal_rx_mpdu_get_addr2_5018(): API to check get address2 of the mpdu 756 * in the packet 757 * 758 * @buf: pointer to the start of RX PKT TLV header 759 * @mac_addr: pointer to mac address 760 * Return: success/failure 761 */ 762 static QDF_STATUS hal_rx_mpdu_get_addr2_5018(uint8_t *buf, uint8_t *mac_addr) 763 { 764 struct __attribute__((__packed__)) hal_addr2 { 765 uint16_t ad2_15_0; 766 uint32_t ad2_47_16; 767 }; 768 769 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 770 struct rx_mpdu_start *mpdu_start = 771 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 772 773 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 774 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 775 uint32_t mac_addr_ad2_valid; 776 777 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 778 779 if (mac_addr_ad2_valid) { 780 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 781 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 782 return QDF_STATUS_SUCCESS; 783 } 784 785 return QDF_STATUS_E_FAILURE; 786 } 787 788 /* 789 * hal_rx_mpdu_get_addr3_5018(): API to get address3 of the mpdu 790 * in the packet 791 * 792 * @buf: pointer to the start of RX PKT TLV header 793 * @mac_addr: pointer to mac address 794 * Return: success/failure 795 */ 796 static QDF_STATUS hal_rx_mpdu_get_addr3_5018(uint8_t *buf, uint8_t *mac_addr) 797 { 798 struct __attribute__((__packed__)) hal_addr3 { 799 uint32_t ad3_31_0; 800 uint16_t ad3_47_32; 801 }; 802 803 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 804 struct rx_mpdu_start *mpdu_start = 805 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 806 807 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 808 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 809 uint32_t mac_addr_ad3_valid; 810 811 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 812 813 if (mac_addr_ad3_valid) { 814 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 815 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 816 return QDF_STATUS_SUCCESS; 817 } 818 819 return QDF_STATUS_E_FAILURE; 820 } 821 822 /* 823 * hal_rx_mpdu_get_addr4_5018(): API to get address4 of the mpdu 824 * in the packet 825 * 826 * @buf: pointer to the start of RX PKT TLV header 827 * @mac_addr: pointer to mac address 828 * Return: success/failure 829 */ 830 static QDF_STATUS hal_rx_mpdu_get_addr4_5018(uint8_t *buf, uint8_t *mac_addr) 831 { 832 struct __attribute__((__packed__)) hal_addr4 { 833 uint32_t ad4_31_0; 834 uint16_t ad4_47_32; 835 }; 836 837 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 838 struct rx_mpdu_start *mpdu_start = 839 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 840 841 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 842 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 843 uint32_t mac_addr_ad4_valid; 844 845 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 846 847 if (mac_addr_ad4_valid) { 848 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 849 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 850 return QDF_STATUS_SUCCESS; 851 } 852 853 return QDF_STATUS_E_FAILURE; 854 } 855 856 /* 857 * hal_rx_get_mpdu_sequence_control_valid_5018(): Get mpdu 858 * sequence control valid 859 * 860 * @nbuf: Network buffer 861 * Returns: value of sequence control valid field 862 */ 863 static uint8_t hal_rx_get_mpdu_sequence_control_valid_5018(uint8_t *buf) 864 { 865 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 866 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 867 868 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 869 } 870 871 /** 872 * hal_rx_is_unicast_5018: check packet is unicast frame or not. 873 * 874 * @ buf: pointer to rx pkt TLV. 875 * 876 * Return: true on unicast. 877 */ 878 static bool hal_rx_is_unicast_5018(uint8_t *buf) 879 { 880 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 881 struct rx_mpdu_start *mpdu_start = 882 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 883 uint32_t grp_id; 884 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 885 886 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 887 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 888 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 889 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 890 891 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 892 } 893 894 /** 895 * hal_rx_tid_get_5018: get tid based on qos control valid. 896 * @hal_soc_hdl: hal soc handle 897 * @buf: pointer to rx pkt TLV. 898 * 899 * Return: tid 900 */ 901 static uint32_t hal_rx_tid_get_5018(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 902 { 903 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 904 struct rx_mpdu_start *mpdu_start = 905 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 906 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 907 uint8_t qos_control_valid = 908 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 909 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 910 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 911 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 912 913 if (qos_control_valid) 914 return hal_rx_mpdu_start_tid_get_5018(buf); 915 916 return HAL_RX_NON_QOS_TID; 917 } 918 919 /** 920 * hal_rx_hw_desc_get_ppduid_get_5018(): retrieve ppdu id 921 * @hw_desc_addr: hw addr 922 * 923 * Return: ppdu id 924 */ 925 static uint32_t hal_rx_hw_desc_get_ppduid_get_5018(void *hw_desc_addr) 926 { 927 struct rx_mpdu_info *rx_mpdu_info; 928 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 929 930 rx_mpdu_info = 931 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 932 933 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_9, PHY_PPDU_ID); 934 } 935 936 /** 937 * hal_reo_status_get_header_5018 - Process reo desc info 938 * @d - Pointer to reo descriptior 939 * @b - tlv type info 940 * @h1 - Pointer to hal_reo_status_header where info to be stored 941 * 942 * Return - none. 943 * 944 */ 945 static void hal_reo_status_get_header_5018(uint32_t *d, int b, void *h1) 946 { 947 uint32_t val1 = 0; 948 struct hal_reo_status_header *h = 949 (struct hal_reo_status_header *)h1; 950 951 switch (b) { 952 case HAL_REO_QUEUE_STATS_STATUS_TLV: 953 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 954 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 955 break; 956 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 957 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 958 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 959 break; 960 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 961 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 962 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 963 break; 964 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 965 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 966 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 967 break; 968 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 969 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 970 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 971 break; 972 case HAL_REO_DESC_THRES_STATUS_TLV: 973 val1 = 974 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 975 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 976 break; 977 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 978 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 979 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 980 break; 981 default: 982 qdf_nofl_err("ERROR: Unknown tlv\n"); 983 break; 984 } 985 h->cmd_num = 986 HAL_GET_FIELD( 987 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 988 val1); 989 h->exec_time = 990 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 991 CMD_EXECUTION_TIME, val1); 992 h->status = 993 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 994 REO_CMD_EXECUTION_STATUS, val1); 995 switch (b) { 996 case HAL_REO_QUEUE_STATS_STATUS_TLV: 997 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 998 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 999 break; 1000 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1001 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1002 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1003 break; 1004 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1005 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1006 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1007 break; 1008 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1009 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1010 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1011 break; 1012 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1013 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1014 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1015 break; 1016 case HAL_REO_DESC_THRES_STATUS_TLV: 1017 val1 = 1018 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1019 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1020 break; 1021 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1022 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1023 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1024 break; 1025 default: 1026 qdf_nofl_err("ERROR: Unknown tlv\n"); 1027 break; 1028 } 1029 h->tstamp = 1030 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1031 } 1032 1033 /** 1034 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(): 1035 * Retrieve qos control valid bit from the tlv. 1036 * @buf: pointer to rx pkt TLV. 1037 * 1038 * Return: qos control value. 1039 */ 1040 static inline uint32_t 1041 hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(uint8_t *buf) 1042 { 1043 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1044 struct rx_mpdu_start *mpdu_start = 1045 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1046 1047 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1048 &mpdu_start->rx_mpdu_info_details); 1049 } 1050 1051 /** 1052 * hal_rx_msdu_end_sa_sw_peer_id_get_5018(): API to get the 1053 * sa_sw_peer_id from rx_msdu_end TLV 1054 * @buf: pointer to the start of RX PKT TLV headers 1055 * 1056 * Return: sa_sw_peer_id index 1057 */ 1058 static inline uint32_t 1059 hal_rx_msdu_end_sa_sw_peer_id_get_5018(uint8_t *buf) 1060 { 1061 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1062 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1063 1064 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1065 } 1066 1067 /** 1068 * hal_tx_desc_set_mesh_en_5018 - Set mesh_enable flag in Tx descriptor 1069 * @desc: Handle to Tx Descriptor 1070 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1071 * enabling the interpretation of the 'Mesh Control Present' bit 1072 * (bit 8) of QoS Control (otherwise this bit is ignored), 1073 * For native WiFi frames, this indicates that a 'Mesh Control' field 1074 * is present between the header and the LLC. 1075 * 1076 * Return: void 1077 */ 1078 static inline 1079 void hal_tx_desc_set_mesh_en_5018(void *desc, uint8_t en) 1080 { 1081 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1082 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1083 } 1084 1085 static 1086 void *hal_rx_msdu0_buffer_addr_lsb_5018(void *link_desc_va) 1087 { 1088 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1089 } 1090 1091 static 1092 void *hal_rx_msdu_desc_info_ptr_get_5018(void *msdu0) 1093 { 1094 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1095 } 1096 1097 static 1098 void *hal_ent_mpdu_desc_info_5018(void *ent_ring_desc) 1099 { 1100 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1101 } 1102 1103 static 1104 void *hal_dst_mpdu_desc_info_5018(void *dst_ring_desc) 1105 { 1106 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1107 } 1108 1109 static 1110 uint8_t hal_rx_get_fc_valid_5018(uint8_t *buf) 1111 { 1112 return HAL_RX_GET_FC_VALID(buf); 1113 } 1114 1115 static uint8_t hal_rx_get_to_ds_flag_5018(uint8_t *buf) 1116 { 1117 return HAL_RX_GET_TO_DS_FLAG(buf); 1118 } 1119 1120 static uint8_t hal_rx_get_mac_addr2_valid_5018(uint8_t *buf) 1121 { 1122 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1123 } 1124 1125 static uint8_t hal_rx_get_filter_category_5018(uint8_t *buf) 1126 { 1127 return HAL_RX_GET_FILTER_CATEGORY(buf); 1128 } 1129 1130 static uint32_t 1131 hal_rx_get_ppdu_id_5018(uint8_t *buf) 1132 { 1133 return HAL_RX_GET_PPDU_ID(buf); 1134 } 1135 1136 /** 1137 * hal_reo_config_5018(): Set reo config parameters 1138 * @soc: hal soc handle 1139 * @reg_val: value to be set 1140 * @reo_params: reo parameters 1141 * 1142 * Return: void 1143 */ 1144 static void 1145 hal_reo_config_5018(struct hal_soc *soc, 1146 uint32_t reg_val, 1147 struct hal_reo_params *reo_params) 1148 { 1149 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1150 } 1151 1152 /** 1153 * hal_rx_msdu_desc_info_get_ptr_5018() - Get msdu desc info ptr 1154 * @msdu_details_ptr - Pointer to msdu_details_ptr 1155 * 1156 * Return - Pointer to rx_msdu_desc_info structure. 1157 * 1158 */ 1159 static void *hal_rx_msdu_desc_info_get_ptr_5018(void *msdu_details_ptr) 1160 { 1161 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1162 } 1163 1164 /** 1165 * hal_rx_link_desc_msdu0_ptr_5018 - Get pointer to rx_msdu details 1166 * @link_desc - Pointer to link desc 1167 * 1168 * Return - Pointer to rx_msdu_details structure 1169 * 1170 */ 1171 static void *hal_rx_link_desc_msdu0_ptr_5018(void *link_desc) 1172 { 1173 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1174 } 1175 1176 /** 1177 * hal_rx_msdu_flow_idx_get_5018: API to get flow index 1178 * from rx_msdu_end TLV 1179 * @buf: pointer to the start of RX PKT TLV headers 1180 * 1181 * Return: flow index value from MSDU END TLV 1182 */ 1183 static inline uint32_t hal_rx_msdu_flow_idx_get_5018(uint8_t *buf) 1184 { 1185 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1186 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1187 1188 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1189 } 1190 1191 /** 1192 * hal_rx_msdu_flow_idx_invalid_5018: API to get flow index invalid 1193 * from rx_msdu_end TLV 1194 * @buf: pointer to the start of RX PKT TLV headers 1195 * 1196 * Return: flow index invalid value from MSDU END TLV 1197 */ 1198 static bool hal_rx_msdu_flow_idx_invalid_5018(uint8_t *buf) 1199 { 1200 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1201 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1202 1203 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1204 } 1205 1206 /** 1207 * hal_rx_msdu_flow_idx_timeout_5018: API to get flow index timeout 1208 * from rx_msdu_end TLV 1209 * @buf: pointer to the start of RX PKT TLV headers 1210 * 1211 * Return: flow index timeout value from MSDU END TLV 1212 */ 1213 static bool hal_rx_msdu_flow_idx_timeout_5018(uint8_t *buf) 1214 { 1215 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1216 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1217 1218 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1219 } 1220 1221 /** 1222 * hal_rx_msdu_fse_metadata_get_5018: API to get FSE metadata 1223 * from rx_msdu_end TLV 1224 * @buf: pointer to the start of RX PKT TLV headers 1225 * 1226 * Return: fse metadata value from MSDU END TLV 1227 */ 1228 static uint32_t hal_rx_msdu_fse_metadata_get_5018(uint8_t *buf) 1229 { 1230 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1231 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1232 1233 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1234 } 1235 1236 /** 1237 * hal_rx_msdu_cce_metadata_get_5018: API to get CCE metadata 1238 * from rx_msdu_end TLV 1239 * @buf: pointer to the start of RX PKT TLV headers 1240 * 1241 * Return: cce_metadata 1242 */ 1243 static uint16_t 1244 hal_rx_msdu_cce_metadata_get_5018(uint8_t *buf) 1245 { 1246 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1247 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1248 1249 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1250 } 1251 1252 /** 1253 * hal_rx_msdu_get_flow_params_5018: API to get flow index, flow index invalid 1254 * and flow index timeout from rx_msdu_end TLV 1255 * @buf: pointer to the start of RX PKT TLV headers 1256 * @flow_invalid: pointer to return value of flow_idx_valid 1257 * @flow_timeout: pointer to return value of flow_idx_timeout 1258 * @flow_index: pointer to return value of flow_idx 1259 * 1260 * Return: none 1261 */ 1262 static inline void 1263 hal_rx_msdu_get_flow_params_5018(uint8_t *buf, 1264 bool *flow_invalid, 1265 bool *flow_timeout, 1266 uint32_t *flow_index) 1267 { 1268 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1269 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1270 1271 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1272 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1273 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1274 } 1275 1276 /** 1277 * hal_rx_tlv_get_tcp_chksum_5018() - API to get tcp checksum 1278 * @buf: rx_tlv_hdr 1279 * 1280 * Return: tcp checksum 1281 */ 1282 static uint16_t 1283 hal_rx_tlv_get_tcp_chksum_5018(uint8_t *buf) 1284 { 1285 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1286 } 1287 1288 /** 1289 * hal_rx_get_rx_sequence_5018(): Function to retrieve rx sequence number 1290 * 1291 * @nbuf: Network buffer 1292 * Returns: rx sequence number 1293 */ 1294 static 1295 uint16_t hal_rx_get_rx_sequence_5018(uint8_t *buf) 1296 { 1297 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1298 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1299 1300 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1301 } 1302 1303 /** 1304 * hal_get_window_address_5018(): Function to get hp/tp address 1305 * @hal_soc: Pointer to hal_soc 1306 * @addr: address offset of register 1307 * 1308 * Return: modified address offset of register 1309 */ 1310 static inline qdf_iomem_t hal_get_window_address_5018(struct hal_soc *hal_soc, 1311 qdf_iomem_t addr) 1312 { 1313 uint32_t offset = addr - hal_soc->dev_base_addr; 1314 qdf_iomem_t new_offset; 1315 1316 /* 1317 * If offset lies within DP register range, use 3rd window to write 1318 * into DP region. 1319 */ 1320 if ((offset ^ SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) { 1321 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + 1322 (offset & WINDOW_RANGE_MASK)); 1323 /* 1324 * If offset lies within CE register range, use 2nd window to write 1325 * into CE region. 1326 */ 1327 } else if ((offset ^ WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { 1328 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + 1329 (offset & WINDOW_RANGE_MASK)); 1330 } else { 1331 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1332 "%s: ERROR: Accessing Wrong register\n", __func__); 1333 qdf_assert_always(0); 1334 return 0; 1335 } 1336 return new_offset; 1337 } 1338 1339 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1340 { 1341 /* Write value into window configuration register */ 1342 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1343 WINDOW_CONFIGURATION_VALUE_5018); 1344 } 1345 1346 struct hal_hw_txrx_ops qca5018_hal_hw_txrx_ops = { 1347 1348 /* init and setup */ 1349 hal_srng_dst_hw_init_generic, 1350 hal_srng_src_hw_init_generic, 1351 hal_get_hw_hptp_generic, 1352 hal_reo_setup_generic, 1353 hal_setup_link_idle_list_generic, 1354 hal_get_window_address_5018, 1355 1356 /* tx */ 1357 hal_tx_desc_set_dscp_tid_table_id_5018, 1358 hal_tx_set_dscp_tid_map_5018, 1359 hal_tx_update_dscp_tid_5018, 1360 hal_tx_desc_set_lmac_id_5018, 1361 hal_tx_desc_set_buf_addr_generic, 1362 hal_tx_desc_set_search_type_generic, 1363 hal_tx_desc_set_search_index_generic, 1364 hal_tx_desc_set_cache_set_num_generic, 1365 hal_tx_comp_get_status_generic, 1366 hal_tx_comp_get_release_reason_generic, 1367 hal_get_wbm_internal_error_generic, 1368 hal_tx_desc_set_mesh_en_5018, 1369 1370 /* rx */ 1371 hal_rx_msdu_start_nss_get_5018, 1372 hal_rx_mon_hw_desc_get_mpdu_status_5018, 1373 hal_rx_get_tlv_5018, 1374 hal_rx_proc_phyrx_other_receive_info_tlv_5018, 1375 hal_rx_dump_msdu_start_tlv_5018, 1376 hal_rx_dump_msdu_end_tlv_5018, 1377 hal_get_link_desc_size_5018, 1378 hal_rx_mpdu_start_tid_get_5018, 1379 hal_rx_msdu_start_reception_type_get_5018, 1380 hal_rx_msdu_end_da_idx_get_5018, 1381 hal_rx_msdu_desc_info_get_ptr_5018, 1382 hal_rx_link_desc_msdu0_ptr_5018, 1383 hal_reo_status_get_header_5018, 1384 hal_rx_status_get_tlv_info_generic, 1385 hal_rx_wbm_err_info_get_generic, 1386 hal_rx_dump_mpdu_start_tlv_generic, 1387 1388 hal_tx_set_pcp_tid_map_generic, 1389 hal_tx_update_pcp_tid_generic, 1390 hal_tx_update_tidmap_prty_generic, 1391 hal_rx_get_rx_fragment_number_5018, 1392 hal_rx_msdu_end_da_is_mcbc_get_5018, 1393 hal_rx_msdu_end_sa_is_valid_get_5018, 1394 hal_rx_msdu_end_sa_idx_get_5018, 1395 hal_rx_desc_is_first_msdu_5018, 1396 hal_rx_msdu_end_l3_hdr_padding_get_5018, 1397 hal_rx_encryption_info_valid_5018, 1398 hal_rx_print_pn_5018, 1399 hal_rx_msdu_end_first_msdu_get_5018, 1400 hal_rx_msdu_end_da_is_valid_get_5018, 1401 hal_rx_msdu_end_last_msdu_get_5018, 1402 hal_rx_get_mpdu_mac_ad4_valid_5018, 1403 hal_rx_mpdu_start_sw_peer_id_get_5018, 1404 hal_rx_mpdu_get_to_ds_5018, 1405 hal_rx_mpdu_get_fr_ds_5018, 1406 hal_rx_get_mpdu_frame_control_valid_5018, 1407 hal_rx_mpdu_get_addr1_5018, 1408 hal_rx_mpdu_get_addr2_5018, 1409 hal_rx_mpdu_get_addr3_5018, 1410 hal_rx_mpdu_get_addr4_5018, 1411 hal_rx_get_mpdu_sequence_control_valid_5018, 1412 hal_rx_is_unicast_5018, 1413 hal_rx_tid_get_5018, 1414 hal_rx_hw_desc_get_ppduid_get_5018, 1415 hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018, 1416 hal_rx_msdu_end_sa_sw_peer_id_get_5018, 1417 hal_rx_msdu0_buffer_addr_lsb_5018, 1418 hal_rx_msdu_desc_info_ptr_get_5018, 1419 hal_ent_mpdu_desc_info_5018, 1420 hal_dst_mpdu_desc_info_5018, 1421 hal_rx_get_fc_valid_5018, 1422 hal_rx_get_to_ds_flag_5018, 1423 hal_rx_get_mac_addr2_valid_5018, 1424 hal_rx_get_filter_category_5018, 1425 hal_rx_get_ppdu_id_5018, 1426 hal_reo_config_5018, 1427 hal_rx_msdu_flow_idx_get_5018, 1428 hal_rx_msdu_flow_idx_invalid_5018, 1429 hal_rx_msdu_flow_idx_timeout_5018, 1430 hal_rx_msdu_fse_metadata_get_5018, 1431 hal_rx_msdu_cce_metadata_get_5018, 1432 hal_rx_msdu_get_flow_params_5018, 1433 hal_rx_tlv_get_tcp_chksum_5018, 1434 hal_rx_get_rx_sequence_5018, 1435 NULL, 1436 NULL, 1437 }; 1438 1439 struct hal_hw_srng_config hw_srng_table_5018[] = { 1440 /* TODO: max_rings can populated by querying HW capabilities */ 1441 { /* REO_DST */ 1442 .start_ring_id = HAL_SRNG_REO2SW1, 1443 .max_rings = 4, 1444 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1445 .lmac_ring = FALSE, 1446 .ring_dir = HAL_SRNG_DST_RING, 1447 .reg_start = { 1448 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1449 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1450 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1451 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1452 }, 1453 .reg_size = { 1454 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1455 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1456 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1457 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1458 }, 1459 .max_size = 1460 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1461 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1462 }, 1463 { /* REO_EXCEPTION */ 1464 /* Designating REO2TCL ring as exception ring. This ring is 1465 * similar to other REO2SW rings though it is named as REO2TCL. 1466 * Any of theREO2SW rings can be used as exception ring. 1467 */ 1468 .start_ring_id = HAL_SRNG_REO2TCL, 1469 .max_rings = 1, 1470 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1471 .lmac_ring = FALSE, 1472 .ring_dir = HAL_SRNG_DST_RING, 1473 .reg_start = { 1474 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1475 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1476 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1477 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1478 }, 1479 /* Single ring - provide ring size if multiple rings of this 1480 * type are supported 1481 */ 1482 .reg_size = {}, 1483 .max_size = 1484 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1485 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1486 }, 1487 { /* REO_REINJECT */ 1488 .start_ring_id = HAL_SRNG_SW2REO, 1489 .max_rings = 1, 1490 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1491 .lmac_ring = FALSE, 1492 .ring_dir = HAL_SRNG_SRC_RING, 1493 .reg_start = { 1494 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1495 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1496 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1497 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1498 }, 1499 /* Single ring - provide ring size if multiple rings of this 1500 * type are supported 1501 */ 1502 .reg_size = {}, 1503 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1504 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1505 }, 1506 { /* REO_CMD */ 1507 .start_ring_id = HAL_SRNG_REO_CMD, 1508 .max_rings = 1, 1509 .entry_size = (sizeof(struct tlv_32_hdr) + 1510 sizeof(struct reo_get_queue_stats)) >> 2, 1511 .lmac_ring = FALSE, 1512 .ring_dir = HAL_SRNG_SRC_RING, 1513 .reg_start = { 1514 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1515 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1516 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1517 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1518 }, 1519 /* Single ring - provide ring size if multiple rings of this 1520 * type are supported 1521 */ 1522 .reg_size = {}, 1523 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1524 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1525 }, 1526 { /* REO_STATUS */ 1527 .start_ring_id = HAL_SRNG_REO_STATUS, 1528 .max_rings = 1, 1529 .entry_size = (sizeof(struct tlv_32_hdr) + 1530 sizeof(struct reo_get_queue_stats_status)) >> 2, 1531 .lmac_ring = FALSE, 1532 .ring_dir = HAL_SRNG_DST_RING, 1533 .reg_start = { 1534 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1535 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1536 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1537 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1538 }, 1539 /* Single ring - provide ring size if multiple rings of this 1540 * type are supported 1541 */ 1542 .reg_size = {}, 1543 .max_size = 1544 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1545 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1546 }, 1547 { /* TCL_DATA */ 1548 .start_ring_id = HAL_SRNG_SW2TCL1, 1549 .max_rings = 3, 1550 .entry_size = (sizeof(struct tlv_32_hdr) + 1551 sizeof(struct tcl_data_cmd)) >> 2, 1552 .lmac_ring = FALSE, 1553 .ring_dir = HAL_SRNG_SRC_RING, 1554 .reg_start = { 1555 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1556 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1557 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1558 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1559 }, 1560 .reg_size = { 1561 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1562 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1563 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1564 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1565 }, 1566 .max_size = 1567 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1568 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1569 }, 1570 { /* TCL_CMD */ 1571 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1572 .max_rings = 1, 1573 .entry_size = (sizeof(struct tlv_32_hdr) + 1574 sizeof(struct tcl_gse_cmd)) >> 2, 1575 .lmac_ring = FALSE, 1576 .ring_dir = HAL_SRNG_SRC_RING, 1577 .reg_start = { 1578 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 1579 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1580 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 1581 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1582 }, 1583 /* Single ring - provide ring size if multiple rings of this 1584 * type are supported 1585 */ 1586 .reg_size = {}, 1587 .max_size = 1588 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 1589 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 1590 }, 1591 { /* TCL_STATUS */ 1592 .start_ring_id = HAL_SRNG_TCL_STATUS, 1593 .max_rings = 1, 1594 .entry_size = (sizeof(struct tlv_32_hdr) + 1595 sizeof(struct tcl_status_ring)) >> 2, 1596 .lmac_ring = FALSE, 1597 .ring_dir = HAL_SRNG_DST_RING, 1598 .reg_start = { 1599 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1600 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1601 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1602 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1603 }, 1604 /* Single ring - provide ring size if multiple rings of this 1605 * type are supported 1606 */ 1607 .reg_size = {}, 1608 .max_size = 1609 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1610 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1611 }, 1612 { /* CE_SRC */ 1613 .start_ring_id = HAL_SRNG_CE_0_SRC, 1614 .max_rings = 12, 1615 .entry_size = sizeof(struct ce_src_desc) >> 2, 1616 .lmac_ring = FALSE, 1617 .ring_dir = HAL_SRNG_SRC_RING, 1618 .reg_start = { 1619 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1620 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1621 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1622 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1623 }, 1624 .reg_size = { 1625 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1626 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1627 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1628 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1629 }, 1630 .max_size = 1631 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1632 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1633 }, 1634 { /* CE_DST */ 1635 .start_ring_id = HAL_SRNG_CE_0_DST, 1636 .max_rings = 12, 1637 .entry_size = 8 >> 2, 1638 /*TODO: entry_size above should actually be 1639 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1640 * of struct ce_dst_desc in HW header files 1641 */ 1642 .lmac_ring = FALSE, 1643 .ring_dir = HAL_SRNG_SRC_RING, 1644 .reg_start = { 1645 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1646 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1647 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1648 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1649 }, 1650 .reg_size = { 1651 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1652 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1653 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1654 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1655 }, 1656 .max_size = 1657 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1658 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1659 }, 1660 { /* CE_DST_STATUS */ 1661 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1662 .max_rings = 12, 1663 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1664 .lmac_ring = FALSE, 1665 .ring_dir = HAL_SRNG_DST_RING, 1666 .reg_start = { 1667 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1668 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1669 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1670 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1671 }, 1672 /* TODO: check destination status ring registers */ 1673 .reg_size = { 1674 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1675 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1676 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1677 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1678 }, 1679 .max_size = 1680 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1681 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1682 }, 1683 { /* WBM_IDLE_LINK */ 1684 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1685 .max_rings = 1, 1686 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1687 .lmac_ring = FALSE, 1688 .ring_dir = HAL_SRNG_SRC_RING, 1689 .reg_start = { 1690 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1691 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1692 }, 1693 /* Single ring - provide ring size if multiple rings of this 1694 * type are supported 1695 */ 1696 .reg_size = {}, 1697 .max_size = 1698 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1699 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1700 }, 1701 { /* SW2WBM_RELEASE */ 1702 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1703 .max_rings = 1, 1704 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1705 .lmac_ring = FALSE, 1706 .ring_dir = HAL_SRNG_SRC_RING, 1707 .reg_start = { 1708 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1709 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1710 }, 1711 /* Single ring - provide ring size if multiple rings of this 1712 * type are supported 1713 */ 1714 .reg_size = {}, 1715 .max_size = 1716 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1717 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1718 }, 1719 { /* WBM2SW_RELEASE */ 1720 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1721 .max_rings = 4, 1722 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1723 .lmac_ring = FALSE, 1724 .ring_dir = HAL_SRNG_DST_RING, 1725 .reg_start = { 1726 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1727 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1728 }, 1729 .reg_size = { 1730 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1731 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1732 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1733 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1734 }, 1735 .max_size = 1736 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1737 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1738 }, 1739 { /* RXDMA_BUF */ 1740 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1741 #ifdef IPA_OFFLOAD 1742 .max_rings = 3, 1743 #else 1744 .max_rings = 2, 1745 #endif 1746 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1747 .lmac_ring = TRUE, 1748 .ring_dir = HAL_SRNG_SRC_RING, 1749 /* reg_start is not set because LMAC rings are not accessed 1750 * from host 1751 */ 1752 .reg_start = {}, 1753 .reg_size = {}, 1754 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1755 }, 1756 { /* RXDMA_DST */ 1757 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1758 .max_rings = 1, 1759 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1760 .lmac_ring = TRUE, 1761 .ring_dir = HAL_SRNG_DST_RING, 1762 /* reg_start is not set because LMAC rings are not accessed 1763 * from host 1764 */ 1765 .reg_start = {}, 1766 .reg_size = {}, 1767 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1768 }, 1769 { /* RXDMA_MONITOR_BUF */ 1770 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1771 .max_rings = 1, 1772 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1773 .lmac_ring = TRUE, 1774 .ring_dir = HAL_SRNG_SRC_RING, 1775 /* reg_start is not set because LMAC rings are not accessed 1776 * from host 1777 */ 1778 .reg_start = {}, 1779 .reg_size = {}, 1780 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1781 }, 1782 { /* RXDMA_MONITOR_STATUS */ 1783 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1784 .max_rings = 1, 1785 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1786 .lmac_ring = TRUE, 1787 .ring_dir = HAL_SRNG_SRC_RING, 1788 /* reg_start is not set because LMAC rings are not accessed 1789 * from host 1790 */ 1791 .reg_start = {}, 1792 .reg_size = {}, 1793 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1794 }, 1795 { /* RXDMA_MONITOR_DST */ 1796 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1797 .max_rings = 1, 1798 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1799 .lmac_ring = TRUE, 1800 .ring_dir = HAL_SRNG_DST_RING, 1801 /* reg_start is not set because LMAC rings are not accessed 1802 * from host 1803 */ 1804 .reg_start = {}, 1805 .reg_size = {}, 1806 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1807 }, 1808 { /* RXDMA_MONITOR_DESC */ 1809 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1810 .max_rings = 1, 1811 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1812 .lmac_ring = TRUE, 1813 .ring_dir = HAL_SRNG_SRC_RING, 1814 /* reg_start is not set because LMAC rings are not accessed 1815 * from host 1816 */ 1817 .reg_start = {}, 1818 .reg_size = {}, 1819 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1820 }, 1821 { /* DIR_BUF_RX_DMA_SRC */ 1822 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1823 /* one ring for spectral and one ring for cfr */ 1824 .max_rings = 2, 1825 .entry_size = 2, 1826 .lmac_ring = TRUE, 1827 .ring_dir = HAL_SRNG_SRC_RING, 1828 /* reg_start is not set because LMAC rings are not accessed 1829 * from host 1830 */ 1831 .reg_start = {}, 1832 .reg_size = {}, 1833 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1834 }, 1835 #ifdef WLAN_FEATURE_CIF_CFR 1836 { /* WIFI_POS_SRC */ 1837 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1838 .max_rings = 1, 1839 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1840 .lmac_ring = TRUE, 1841 .ring_dir = HAL_SRNG_SRC_RING, 1842 /* reg_start is not set because LMAC rings are not accessed 1843 * from host 1844 */ 1845 .reg_start = {}, 1846 .reg_size = {}, 1847 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1848 }, 1849 #endif 1850 }; 1851 1852 int32_t hal_hw_reg_offset_qca5018[] = { 1853 /* dst */ 1854 REG_OFFSET(DST, HP), 1855 REG_OFFSET(DST, TP), 1856 REG_OFFSET(DST, ID), 1857 REG_OFFSET(DST, MISC), 1858 REG_OFFSET(DST, HP_ADDR_LSB), 1859 REG_OFFSET(DST, HP_ADDR_MSB), 1860 REG_OFFSET(DST, MSI1_BASE_LSB), 1861 REG_OFFSET(DST, MSI1_BASE_MSB), 1862 REG_OFFSET(DST, MSI1_DATA), 1863 REG_OFFSET(DST, BASE_LSB), 1864 REG_OFFSET(DST, BASE_MSB), 1865 REG_OFFSET(DST, PRODUCER_INT_SETUP), 1866 /* src */ 1867 REG_OFFSET(SRC, HP), 1868 REG_OFFSET(SRC, TP), 1869 REG_OFFSET(SRC, ID), 1870 REG_OFFSET(SRC, MISC), 1871 REG_OFFSET(SRC, TP_ADDR_LSB), 1872 REG_OFFSET(SRC, TP_ADDR_MSB), 1873 REG_OFFSET(SRC, MSI1_BASE_LSB), 1874 REG_OFFSET(SRC, MSI1_BASE_MSB), 1875 REG_OFFSET(SRC, MSI1_DATA), 1876 REG_OFFSET(SRC, BASE_LSB), 1877 REG_OFFSET(SRC, BASE_MSB), 1878 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 1879 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 1880 }; 1881 1882 /** 1883 * hal_qca5018_attach()- Attach 5018 target specific hal_soc ops, 1884 * offset and srng table 1885 * Return: void 1886 */ 1887 void hal_qca5018_attach(struct hal_soc *hal_soc) 1888 { 1889 hal_soc->hw_srng_table = hw_srng_table_5018; 1890 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca5018; 1891 hal_soc->ops = &qca5018_hal_hw_txrx_ops; 1892 if (hal_soc->static_window_map) 1893 hal_write_window_register(hal_soc); 1894 } 1895