1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 #include "hal_flow.h" 25 #include "rx_flow_search_entry.h" 26 #include "hal_rx_flow_info.h" 27 28 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 29 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 30 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 31 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 33 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 34 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 35 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 36 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 37 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 38 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 39 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 40 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 41 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 42 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 43 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 44 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 45 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 52 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 53 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 54 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 55 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 56 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 57 RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 58 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 59 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 60 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 61 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 62 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 64 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 65 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 66 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 67 STATUS_HEADER_REO_STATUS_NUMBER 68 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 69 STATUS_HEADER_TIMESTAMP 70 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 71 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 72 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 73 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 74 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 75 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 76 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 77 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 78 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 79 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 80 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 81 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 82 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 83 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 84 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 85 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 86 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 87 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 88 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 89 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 90 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 91 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 92 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 93 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 94 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 95 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 96 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 97 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 98 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 99 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 100 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 101 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 103 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 104 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 105 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 106 107 #define CE_WINDOW_ADDRESS_5018 \ 108 ((WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 109 110 #define UMAC_WINDOW_ADDRESS_5018 \ 111 ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 112 113 #define WINDOW_CONFIGURATION_VALUE_5018 \ 114 ((CE_WINDOW_ADDRESS_5018 << 6) |\ 115 (UMAC_WINDOW_ADDRESS_5018 << 12) | \ 116 WINDOW_ENABLE_BIT) 117 118 #define HOST_CE_MASK_VALUE 0xFF000000 119 120 #include <hal_5018_tx.h> 121 #include <hal_5018_rx.h> 122 #include <hal_generic_api.h> 123 #include <hal_wbm.h> 124 125 /** 126 * hal_rx_msdu_start_nss_get_5018(): API to get the NSS 127 * Interval from rx_msdu_start 128 * 129 * @buf: pointer to the start of RX PKT TLV header 130 * Return: uint32_t(nss) 131 */ 132 static uint32_t hal_rx_msdu_start_nss_get_5018(uint8_t *buf) 133 { 134 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 135 struct rx_msdu_start *msdu_start = 136 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 137 uint8_t mimo_ss_bitmap; 138 139 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 140 141 return qdf_get_hweight8(mimo_ss_bitmap); 142 } 143 144 /** 145 * hal_rx_mon_hw_desc_get_mpdu_status_5018(): Retrieve MPDU status 146 * 147 * @ hw_desc_addr: Start address of Rx HW TLVs 148 * @ rs: Status for monitor mode 149 * 150 * Return: void 151 */ 152 static void hal_rx_mon_hw_desc_get_mpdu_status_5018(void *hw_desc_addr, 153 struct mon_rx_status *rs) 154 { 155 struct rx_msdu_start *rx_msdu_start; 156 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 157 uint32_t reg_value; 158 const uint32_t sgi_hw_to_cdp[] = { 159 CDP_SGI_0_8_US, 160 CDP_SGI_0_4_US, 161 CDP_SGI_1_6_US, 162 CDP_SGI_3_2_US, 163 }; 164 165 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 166 167 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 168 169 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 170 RX_MSDU_START_5, USER_RSSI); 171 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 172 173 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 174 rs->sgi = sgi_hw_to_cdp[reg_value]; 175 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 176 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 177 /* TODO: rs->beamformed should be set for SU beamforming also */ 178 } 179 180 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 181 /** 182 * hal_get_link_desc_size_5018(): API to get the link desc size 183 * 184 * Return: uint32_t 185 */ 186 static uint32_t hal_get_link_desc_size_5018(void) 187 { 188 return LINK_DESC_SIZE; 189 } 190 191 /** 192 * hal_rx_get_tlv_5018(): API to get the tlv 193 * 194 * @rx_tlv: TLV data extracted from the rx packet 195 * Return: uint8_t 196 */ 197 static uint8_t hal_rx_get_tlv_5018(void *rx_tlv) 198 { 199 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 200 } 201 202 /** 203 * hal_rx_mpdu_start_tlv_tag_valid_5018 () - API to check if RX_MPDU_START 204 * tlv tag is valid 205 * 206 *@rx_tlv_hdr: start address of rx_pkt_tlvs 207 * 208 * Return: true if RX_MPDU_START is valied, else false. 209 */ 210 uint8_t hal_rx_mpdu_start_tlv_tag_valid_5018(void *rx_tlv_hdr) 211 { 212 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 213 uint32_t tlv_tag; 214 215 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 216 217 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 218 } 219 220 /** 221 * hal_rx_wbm_err_msdu_continuation_get_5018 () - API to check if WBM 222 * msdu continuation bit is set 223 * 224 *@wbm_desc: wbm release ring descriptor 225 * 226 * Return: true if msdu continuation bit is set. 227 */ 228 uint8_t hal_rx_wbm_err_msdu_continuation_get_5018(void *wbm_desc) 229 { 230 uint32_t comp_desc = 231 *(uint32_t *)(((uint8_t *)wbm_desc) + 232 WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET); 233 234 return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >> 235 WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB; 236 } 237 238 static 239 void hal_compute_reo_remap_ix2_ix3_5018(uint32_t *ring, uint32_t num_rings, 240 uint32_t *remap1, uint32_t *remap2) 241 { 242 switch (num_rings) { 243 case 1: 244 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 245 HAL_REO_REMAP_IX2(ring[0], 17) | 246 HAL_REO_REMAP_IX2(ring[0], 18) | 247 HAL_REO_REMAP_IX2(ring[0], 19) | 248 HAL_REO_REMAP_IX2(ring[0], 20) | 249 HAL_REO_REMAP_IX2(ring[0], 21) | 250 HAL_REO_REMAP_IX2(ring[0], 22) | 251 HAL_REO_REMAP_IX2(ring[0], 23); 252 253 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 254 HAL_REO_REMAP_IX3(ring[0], 25) | 255 HAL_REO_REMAP_IX3(ring[0], 26) | 256 HAL_REO_REMAP_IX3(ring[0], 27) | 257 HAL_REO_REMAP_IX3(ring[0], 28) | 258 HAL_REO_REMAP_IX3(ring[0], 29) | 259 HAL_REO_REMAP_IX3(ring[0], 30) | 260 HAL_REO_REMAP_IX3(ring[0], 31); 261 break; 262 case 2: 263 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 264 HAL_REO_REMAP_IX2(ring[0], 17) | 265 HAL_REO_REMAP_IX2(ring[1], 18) | 266 HAL_REO_REMAP_IX2(ring[1], 19) | 267 HAL_REO_REMAP_IX2(ring[0], 20) | 268 HAL_REO_REMAP_IX2(ring[0], 21) | 269 HAL_REO_REMAP_IX2(ring[1], 22) | 270 HAL_REO_REMAP_IX2(ring[1], 23); 271 272 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 273 HAL_REO_REMAP_IX3(ring[0], 25) | 274 HAL_REO_REMAP_IX3(ring[1], 26) | 275 HAL_REO_REMAP_IX3(ring[1], 27) | 276 HAL_REO_REMAP_IX3(ring[0], 28) | 277 HAL_REO_REMAP_IX3(ring[0], 29) | 278 HAL_REO_REMAP_IX3(ring[1], 30) | 279 HAL_REO_REMAP_IX3(ring[1], 31); 280 break; 281 case 3: 282 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 283 HAL_REO_REMAP_IX2(ring[1], 17) | 284 HAL_REO_REMAP_IX2(ring[2], 18) | 285 HAL_REO_REMAP_IX2(ring[0], 19) | 286 HAL_REO_REMAP_IX2(ring[1], 20) | 287 HAL_REO_REMAP_IX2(ring[2], 21) | 288 HAL_REO_REMAP_IX2(ring[0], 22) | 289 HAL_REO_REMAP_IX2(ring[1], 23); 290 291 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 292 HAL_REO_REMAP_IX3(ring[0], 25) | 293 HAL_REO_REMAP_IX3(ring[1], 26) | 294 HAL_REO_REMAP_IX3(ring[2], 27) | 295 HAL_REO_REMAP_IX3(ring[0], 28) | 296 HAL_REO_REMAP_IX3(ring[1], 29) | 297 HAL_REO_REMAP_IX3(ring[2], 30) | 298 HAL_REO_REMAP_IX3(ring[0], 31); 299 break; 300 case 4: 301 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 302 HAL_REO_REMAP_IX2(ring[1], 17) | 303 HAL_REO_REMAP_IX2(ring[2], 18) | 304 HAL_REO_REMAP_IX2(ring[3], 19) | 305 HAL_REO_REMAP_IX2(ring[0], 20) | 306 HAL_REO_REMAP_IX2(ring[1], 21) | 307 HAL_REO_REMAP_IX2(ring[2], 22) | 308 HAL_REO_REMAP_IX2(ring[3], 23); 309 310 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 311 HAL_REO_REMAP_IX3(ring[1], 25) | 312 HAL_REO_REMAP_IX3(ring[2], 26) | 313 HAL_REO_REMAP_IX3(ring[3], 27) | 314 HAL_REO_REMAP_IX3(ring[0], 28) | 315 HAL_REO_REMAP_IX3(ring[1], 29) | 316 HAL_REO_REMAP_IX3(ring[2], 30) | 317 HAL_REO_REMAP_IX3(ring[3], 31); 318 break; 319 } 320 } 321 322 /** 323 * hal_rx_proc_phyrx_other_receive_info_tlv_5018(): API to get tlv info 324 * 325 * Return: uint32_t 326 */ 327 static inline 328 void hal_rx_proc_phyrx_other_receive_info_tlv_5018(void *rx_tlv_hdr, 329 void *ppdu_info_hdl) 330 { 331 } 332 333 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 334 static inline 335 void hal_rx_get_bb_info_5018(void *rx_tlv, 336 void *ppdu_info_hdl) 337 { 338 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 339 340 ppdu_info->cfr_info.bb_captured_channel = 341 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); 342 343 ppdu_info->cfr_info.bb_captured_timeout = 344 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); 345 346 ppdu_info->cfr_info.bb_captured_reason = 347 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); 348 } 349 350 static inline 351 void hal_rx_get_rtt_info_5018(void *rx_tlv, 352 void *ppdu_info_hdl) 353 { 354 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 355 356 ppdu_info->cfr_info.rx_location_info_valid = 357 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, 358 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 359 360 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 361 HAL_RX_GET(rx_tlv, 362 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 363 RTT_CHE_BUFFER_POINTER_LOW32); 364 365 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 366 HAL_RX_GET(rx_tlv, 367 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 368 RTT_CHE_BUFFER_POINTER_HIGH8); 369 370 ppdu_info->cfr_info.chan_capture_status = 371 HAL_RX_GET(rx_tlv, 372 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 373 RESERVED_8); 374 } 375 #endif 376 377 /** 378 * hal_rx_dump_msdu_start_tlv_5018() : dump RX msdu_start TLV in structured 379 * human readable format. 380 * @ msdu_start: pointer the msdu_start TLV in pkt. 381 * @ dbg_level: log level. 382 * 383 * Return: void 384 */ 385 static void hal_rx_dump_msdu_start_tlv_5018(void *msdustart, 386 uint8_t dbg_level) 387 { 388 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 389 390 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 391 "rx_msdu_start tlv - " 392 "rxpcu_mpdu_filter_in_category: %d " 393 "sw_frame_group_id: %d " 394 "phy_ppdu_id: %d " 395 "msdu_length: %d " 396 "ipsec_esp: %d " 397 "l3_offset: %d " 398 "ipsec_ah: %d " 399 "l4_offset: %d " 400 "msdu_number: %d " 401 "decap_format: %d " 402 "ipv4_proto: %d " 403 "ipv6_proto: %d " 404 "tcp_proto: %d " 405 "udp_proto: %d " 406 "ip_frag: %d " 407 "tcp_only_ack: %d " 408 "da_is_bcast_mcast: %d " 409 "ip4_protocol_ip6_next_header: %d " 410 "toeplitz_hash_2_or_4: %d " 411 "flow_id_toeplitz: %d " 412 "user_rssi: %d " 413 "pkt_type: %d " 414 "stbc: %d " 415 "sgi: %d " 416 "rate_mcs: %d " 417 "receive_bandwidth: %d " 418 "reception_type: %d " 419 "ppdu_start_timestamp: %d " 420 "sw_phy_meta_data: %d ", 421 msdu_start->rxpcu_mpdu_filter_in_category, 422 msdu_start->sw_frame_group_id, 423 msdu_start->phy_ppdu_id, 424 msdu_start->msdu_length, 425 msdu_start->ipsec_esp, 426 msdu_start->l3_offset, 427 msdu_start->ipsec_ah, 428 msdu_start->l4_offset, 429 msdu_start->msdu_number, 430 msdu_start->decap_format, 431 msdu_start->ipv4_proto, 432 msdu_start->ipv6_proto, 433 msdu_start->tcp_proto, 434 msdu_start->udp_proto, 435 msdu_start->ip_frag, 436 msdu_start->tcp_only_ack, 437 msdu_start->da_is_bcast_mcast, 438 msdu_start->ip4_protocol_ip6_next_header, 439 msdu_start->toeplitz_hash_2_or_4, 440 msdu_start->flow_id_toeplitz, 441 msdu_start->user_rssi, 442 msdu_start->pkt_type, 443 msdu_start->stbc, 444 msdu_start->sgi, 445 msdu_start->rate_mcs, 446 msdu_start->receive_bandwidth, 447 msdu_start->reception_type, 448 msdu_start->ppdu_start_timestamp, 449 msdu_start->sw_phy_meta_data); 450 } 451 452 /** 453 * hal_rx_dump_msdu_end_tlv_5018: dump RX msdu_end TLV in structured 454 * human readable format. 455 * @ msdu_end: pointer the msdu_end TLV in pkt. 456 * @ dbg_level: log level. 457 * 458 * Return: void 459 */ 460 static void hal_rx_dump_msdu_end_tlv_5018(void *msduend, 461 uint8_t dbg_level) 462 { 463 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 464 465 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 466 "rx_msdu_end tlv - " 467 "rxpcu_mpdu_filter_in_category: %d " 468 "sw_frame_group_id: %d " 469 "phy_ppdu_id: %d " 470 "ip_hdr_chksum: %d " 471 "reported_mpdu_length: %d " 472 "key_id_octet: %d " 473 "cce_super_rule: %d " 474 "cce_classify_not_done_truncat: %d " 475 "cce_classify_not_done_cce_dis: %d " 476 "rule_indication_31_0: %d " 477 "rule_indication_63_32: %d " 478 "da_offset: %d " 479 "sa_offset: %d " 480 "da_offset_valid: %d " 481 "sa_offset_valid: %d " 482 "ipv6_options_crc: %d " 483 "tcp_seq_number: %d " 484 "tcp_ack_number: %d " 485 "tcp_flag: %d " 486 "lro_eligible: %d " 487 "window_size: %d " 488 "tcp_udp_chksum: %d " 489 "sa_idx_timeout: %d " 490 "da_idx_timeout: %d " 491 "msdu_limit_error: %d " 492 "flow_idx_timeout: %d " 493 "flow_idx_invalid: %d " 494 "wifi_parser_error: %d " 495 "amsdu_parser_error: %d " 496 "sa_is_valid: %d " 497 "da_is_valid: %d " 498 "da_is_mcbc: %d " 499 "l3_header_padding: %d " 500 "first_msdu: %d " 501 "last_msdu: %d " 502 "sa_idx: %d " 503 "msdu_drop: %d " 504 "reo_destination_indication: %d " 505 "flow_idx: %d " 506 "fse_metadata: %d " 507 "cce_metadata: %d " 508 "sa_sw_peer_id: %d ", 509 msdu_end->rxpcu_mpdu_filter_in_category, 510 msdu_end->sw_frame_group_id, 511 msdu_end->phy_ppdu_id, 512 msdu_end->ip_hdr_chksum, 513 msdu_end->reported_mpdu_length, 514 msdu_end->key_id_octet, 515 msdu_end->cce_super_rule, 516 msdu_end->cce_classify_not_done_truncate, 517 msdu_end->cce_classify_not_done_cce_dis, 518 msdu_end->rule_indication_31_0, 519 msdu_end->rule_indication_63_32, 520 msdu_end->da_offset, 521 msdu_end->sa_offset, 522 msdu_end->da_offset_valid, 523 msdu_end->sa_offset_valid, 524 msdu_end->ipv6_options_crc, 525 msdu_end->tcp_seq_number, 526 msdu_end->tcp_ack_number, 527 msdu_end->tcp_flag, 528 msdu_end->lro_eligible, 529 msdu_end->window_size, 530 msdu_end->tcp_udp_chksum, 531 msdu_end->sa_idx_timeout, 532 msdu_end->da_idx_timeout, 533 msdu_end->msdu_limit_error, 534 msdu_end->flow_idx_timeout, 535 msdu_end->flow_idx_invalid, 536 msdu_end->wifi_parser_error, 537 msdu_end->amsdu_parser_error, 538 msdu_end->sa_is_valid, 539 msdu_end->da_is_valid, 540 msdu_end->da_is_mcbc, 541 msdu_end->l3_header_padding, 542 msdu_end->first_msdu, 543 msdu_end->last_msdu, 544 msdu_end->sa_idx, 545 msdu_end->msdu_drop, 546 msdu_end->reo_destination_indication, 547 msdu_end->flow_idx, 548 msdu_end->fse_metadata, 549 msdu_end->cce_metadata, 550 msdu_end->sa_sw_peer_id); 551 } 552 553 /** 554 * hal_rx_mpdu_start_tid_get_5018(): API to get tid 555 * from rx_msdu_start 556 * 557 * @buf: pointer to the start of RX PKT TLV header 558 * Return: uint32_t(tid value) 559 */ 560 static uint32_t hal_rx_mpdu_start_tid_get_5018(uint8_t *buf) 561 { 562 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 563 struct rx_mpdu_start *mpdu_start = 564 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 565 uint32_t tid; 566 567 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 568 569 return tid; 570 } 571 572 /** 573 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 574 * Interval from rx_msdu_start 575 * 576 * @buf: pointer to the start of RX PKT TLV header 577 * Return: uint32_t(reception_type) 578 */ 579 static uint32_t hal_rx_msdu_start_reception_type_get_5018(uint8_t *buf) 580 { 581 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 582 struct rx_msdu_start *msdu_start = 583 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 584 uint32_t reception_type; 585 586 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 587 588 return reception_type; 589 } 590 591 /** 592 * hal_rx_msdu_end_da_idx_get_5018: API to get da_idx 593 * from rx_msdu_end TLV 594 * 595 * @ buf: pointer to the start of RX PKT TLV headers 596 * Return: da index 597 */ 598 static uint16_t hal_rx_msdu_end_da_idx_get_5018(uint8_t *buf) 599 { 600 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 601 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 602 uint16_t da_idx; 603 604 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 605 606 return da_idx; 607 } 608 609 /** 610 * hal_rx_get_rx_fragment_number_5018(): Function to retrieve rx fragment number 611 * 612 * @nbuf: Network buffer 613 * Returns: rx fragment number 614 */ 615 static 616 uint8_t hal_rx_get_rx_fragment_number_5018(uint8_t *buf) 617 { 618 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 619 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 620 621 /* Return first 4 bits as fragment number */ 622 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 623 DOT11_SEQ_FRAG_MASK); 624 } 625 626 /** 627 * hal_rx_msdu_end_da_is_mcbc_get_5018(): API to check if pkt is MCBC 628 * from rx_msdu_end TLV 629 * 630 * @ buf: pointer to the start of RX PKT TLV headers 631 * Return: da_is_mcbc 632 */ 633 static uint8_t 634 hal_rx_msdu_end_da_is_mcbc_get_5018(uint8_t *buf) 635 { 636 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 637 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 638 639 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 640 } 641 642 /** 643 * hal_rx_msdu_end_sa_is_valid_get_5018(): API to get_5018 the 644 * sa_is_valid bit from rx_msdu_end TLV 645 * 646 * @ buf: pointer to the start of RX PKT TLV headers 647 * Return: sa_is_valid bit 648 */ 649 static uint8_t 650 hal_rx_msdu_end_sa_is_valid_get_5018(uint8_t *buf) 651 { 652 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 653 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 654 uint8_t sa_is_valid; 655 656 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 657 658 return sa_is_valid; 659 } 660 661 /** 662 * hal_rx_msdu_end_sa_idx_get_5018(): API to get_5018 the 663 * sa_idx from rx_msdu_end TLV 664 * 665 * @ buf: pointer to the start of RX PKT TLV headers 666 * Return: sa_idx (SA AST index) 667 */ 668 static uint16_t hal_rx_msdu_end_sa_idx_get_5018(uint8_t *buf) 669 { 670 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 671 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 672 uint16_t sa_idx; 673 674 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 675 676 return sa_idx; 677 } 678 679 /** 680 * hal_rx_desc_is_first_msdu_5018() - Check if first msdu 681 * 682 * @hal_soc_hdl: hal_soc handle 683 * @hw_desc_addr: hardware descriptor address 684 * 685 * Return: 0 - success/ non-zero failure 686 */ 687 static uint32_t hal_rx_desc_is_first_msdu_5018(void *hw_desc_addr) 688 { 689 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 690 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 691 692 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 693 } 694 695 /** 696 * hal_rx_msdu_end_l3_hdr_padding_get_5018(): API to get_5018 the 697 * l3_header padding from rx_msdu_end TLV 698 * 699 * @ buf: pointer to the start of RX PKT TLV headers 700 * Return: number of l3 header padding bytes 701 */ 702 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_5018(uint8_t *buf) 703 { 704 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 705 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 706 uint32_t l3_header_padding; 707 708 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 709 710 return l3_header_padding; 711 } 712 713 /** 714 * @ hal_rx_encryption_info_valid_5018: Returns encryption type. 715 * 716 * @ buf: rx_tlv_hdr of the received packet 717 * @ Return: encryption type 718 */ 719 inline uint32_t hal_rx_encryption_info_valid_5018(uint8_t *buf) 720 { 721 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 722 struct rx_mpdu_start *mpdu_start = 723 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 724 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 725 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 726 727 return encryption_info; 728 } 729 730 /* 731 * @ hal_rx_print_pn_5018: Prints the PN of rx packet. 732 * 733 * @ buf: rx_tlv_hdr of the received packet 734 * @ Return: void 735 */ 736 static void hal_rx_print_pn_5018(uint8_t *buf) 737 { 738 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 739 struct rx_mpdu_start *mpdu_start = 740 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 741 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 742 743 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 744 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 745 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 746 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 747 748 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 749 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 750 } 751 752 /** 753 * hal_rx_msdu_end_first_msdu_get_5018: API to get first msdu status 754 * from rx_msdu_end TLV 755 * 756 * @ buf: pointer to the start of RX PKT TLV headers 757 * Return: first_msdu 758 */ 759 static uint8_t hal_rx_msdu_end_first_msdu_get_5018(uint8_t *buf) 760 { 761 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 762 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 763 uint8_t first_msdu; 764 765 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 766 767 return first_msdu; 768 } 769 770 /** 771 * hal_rx_msdu_end_da_is_valid_get_5018: API to check if da is valid 772 * from rx_msdu_end TLV 773 * 774 * @ buf: pointer to the start of RX PKT TLV headers 775 * Return: da_is_valid 776 */ 777 static uint8_t hal_rx_msdu_end_da_is_valid_get_5018(uint8_t *buf) 778 { 779 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 780 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 781 uint8_t da_is_valid; 782 783 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 784 785 return da_is_valid; 786 } 787 788 /** 789 * hal_rx_msdu_end_last_msdu_get_5018: API to get last msdu status 790 * from rx_msdu_end TLV 791 * 792 * @ buf: pointer to the start of RX PKT TLV headers 793 * Return: last_msdu 794 */ 795 static uint8_t hal_rx_msdu_end_last_msdu_get_5018(uint8_t *buf) 796 { 797 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 798 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 799 uint8_t last_msdu; 800 801 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 802 803 return last_msdu; 804 } 805 806 /* 807 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 808 * 809 * @nbuf: Network buffer 810 * Returns: value of mpdu 4th address valid field 811 */ 812 inline bool hal_rx_get_mpdu_mac_ad4_valid_5018(uint8_t *buf) 813 { 814 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 815 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 816 bool ad4_valid = 0; 817 818 ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info); 819 820 return ad4_valid; 821 } 822 823 /** 824 * hal_rx_mpdu_start_sw_peer_id_get_5018: Retrieve sw peer_id 825 * @buf: network buffer 826 * 827 * Return: sw peer_id 828 */ 829 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_5018(uint8_t *buf) 830 { 831 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 832 struct rx_mpdu_start *mpdu_start = 833 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 834 835 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 836 &mpdu_start->rx_mpdu_info_details); 837 } 838 839 /* 840 * hal_rx_mpdu_get_to_ds_5018(): API to get the tods info 841 * from rx_mpdu_start 842 * 843 * @buf: pointer to the start of RX PKT TLV header 844 * Return: uint32_t(to_ds) 845 */ 846 static uint32_t hal_rx_mpdu_get_to_ds_5018(uint8_t *buf) 847 { 848 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 849 struct rx_mpdu_start *mpdu_start = 850 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 851 852 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 853 854 return HAL_RX_MPDU_GET_TODS(mpdu_info); 855 } 856 857 /* 858 * hal_rx_mpdu_get_fr_ds_5018(): API to get the from ds info 859 * from rx_mpdu_start 860 * 861 * @buf: pointer to the start of RX PKT TLV header 862 * Return: uint32_t(fr_ds) 863 */ 864 static uint32_t hal_rx_mpdu_get_fr_ds_5018(uint8_t *buf) 865 { 866 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 867 struct rx_mpdu_start *mpdu_start = 868 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 869 870 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 871 872 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 873 } 874 875 /* 876 * hal_rx_get_mpdu_frame_control_valid_5018(): Retrieves mpdu 877 * frame control valid 878 * 879 * @nbuf: Network buffer 880 * Returns: value of frame control valid field 881 */ 882 static uint8_t hal_rx_get_mpdu_frame_control_valid_5018(uint8_t *buf) 883 { 884 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 885 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 886 887 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 888 } 889 890 /* 891 * hal_rx_mpdu_get_addr1_5018(): API to check get address1 of the mpdu 892 * 893 * @buf: pointer to the start of RX PKT TLV headera 894 * @mac_addr: pointer to mac address 895 * Return: success/failure 896 */ 897 static QDF_STATUS hal_rx_mpdu_get_addr1_5018(uint8_t *buf, 898 uint8_t *mac_addr) 899 { 900 struct __attribute__((__packed__)) hal_addr1 { 901 uint32_t ad1_31_0; 902 uint16_t ad1_47_32; 903 }; 904 905 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 906 struct rx_mpdu_start *mpdu_start = 907 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 908 909 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 910 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 911 uint32_t mac_addr_ad1_valid; 912 913 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 914 915 if (mac_addr_ad1_valid) { 916 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 917 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 918 return QDF_STATUS_SUCCESS; 919 } 920 921 return QDF_STATUS_E_FAILURE; 922 } 923 924 /* 925 * hal_rx_mpdu_get_addr2_5018(): API to check get address2 of the mpdu 926 * in the packet 927 * 928 * @buf: pointer to the start of RX PKT TLV header 929 * @mac_addr: pointer to mac address 930 * Return: success/failure 931 */ 932 static QDF_STATUS hal_rx_mpdu_get_addr2_5018(uint8_t *buf, uint8_t *mac_addr) 933 { 934 struct __attribute__((__packed__)) hal_addr2 { 935 uint16_t ad2_15_0; 936 uint32_t ad2_47_16; 937 }; 938 939 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 940 struct rx_mpdu_start *mpdu_start = 941 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 942 943 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 944 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 945 uint32_t mac_addr_ad2_valid; 946 947 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 948 949 if (mac_addr_ad2_valid) { 950 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 951 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 952 return QDF_STATUS_SUCCESS; 953 } 954 955 return QDF_STATUS_E_FAILURE; 956 } 957 958 /* 959 * hal_rx_mpdu_get_addr3_5018(): API to get address3 of the mpdu 960 * in the packet 961 * 962 * @buf: pointer to the start of RX PKT TLV header 963 * @mac_addr: pointer to mac address 964 * Return: success/failure 965 */ 966 static QDF_STATUS hal_rx_mpdu_get_addr3_5018(uint8_t *buf, uint8_t *mac_addr) 967 { 968 struct __attribute__((__packed__)) hal_addr3 { 969 uint32_t ad3_31_0; 970 uint16_t ad3_47_32; 971 }; 972 973 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 974 struct rx_mpdu_start *mpdu_start = 975 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 976 977 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 978 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 979 uint32_t mac_addr_ad3_valid; 980 981 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 982 983 if (mac_addr_ad3_valid) { 984 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 985 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 986 return QDF_STATUS_SUCCESS; 987 } 988 989 return QDF_STATUS_E_FAILURE; 990 } 991 992 /* 993 * hal_rx_mpdu_get_addr4_5018(): API to get address4 of the mpdu 994 * in the packet 995 * 996 * @buf: pointer to the start of RX PKT TLV header 997 * @mac_addr: pointer to mac address 998 * Return: success/failure 999 */ 1000 static QDF_STATUS hal_rx_mpdu_get_addr4_5018(uint8_t *buf, uint8_t *mac_addr) 1001 { 1002 struct __attribute__((__packed__)) hal_addr4 { 1003 uint32_t ad4_31_0; 1004 uint16_t ad4_47_32; 1005 }; 1006 1007 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1008 struct rx_mpdu_start *mpdu_start = 1009 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1010 1011 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1012 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 1013 uint32_t mac_addr_ad4_valid; 1014 1015 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 1016 1017 if (mac_addr_ad4_valid) { 1018 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 1019 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 1020 return QDF_STATUS_SUCCESS; 1021 } 1022 1023 return QDF_STATUS_E_FAILURE; 1024 } 1025 1026 /* 1027 * hal_rx_get_mpdu_sequence_control_valid_5018(): Get mpdu 1028 * sequence control valid 1029 * 1030 * @nbuf: Network buffer 1031 * Returns: value of sequence control valid field 1032 */ 1033 static uint8_t hal_rx_get_mpdu_sequence_control_valid_5018(uint8_t *buf) 1034 { 1035 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1036 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1037 1038 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 1039 } 1040 1041 /** 1042 * hal_rx_is_unicast_5018: check packet is unicast frame or not. 1043 * 1044 * @ buf: pointer to rx pkt TLV. 1045 * 1046 * Return: true on unicast. 1047 */ 1048 static bool hal_rx_is_unicast_5018(uint8_t *buf) 1049 { 1050 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1051 struct rx_mpdu_start *mpdu_start = 1052 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1053 uint32_t grp_id; 1054 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1055 1056 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1057 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 1058 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 1059 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 1060 1061 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 1062 } 1063 1064 /** 1065 * hal_rx_tid_get_5018: get tid based on qos control valid. 1066 * @hal_soc_hdl: hal soc handle 1067 * @buf: pointer to rx pkt TLV. 1068 * 1069 * Return: tid 1070 */ 1071 static uint32_t hal_rx_tid_get_5018(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1072 { 1073 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1074 struct rx_mpdu_start *mpdu_start = 1075 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1076 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1077 uint8_t qos_control_valid = 1078 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1079 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 1080 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 1081 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 1082 1083 if (qos_control_valid) 1084 return hal_rx_mpdu_start_tid_get_5018(buf); 1085 1086 return HAL_RX_NON_QOS_TID; 1087 } 1088 1089 /** 1090 * hal_rx_hw_desc_get_ppduid_get_5018(): retrieve ppdu id 1091 * @rx_tlv_hdr: rx tlv header 1092 * @rxdma_dst_ring_desc: rxdma HW descriptor 1093 * 1094 * Return: ppdu id 1095 */ 1096 static uint32_t hal_rx_hw_desc_get_ppduid_get_5018(void *rx_tlv_hdr, 1097 void *rxdma_dst_ring_desc) 1098 { 1099 struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc; 1100 1101 return HAL_RX_REO_ENT_PHY_PPDU_ID_GET(reo_ent); 1102 } 1103 1104 /** 1105 * hal_reo_status_get_header_5018 - Process reo desc info 1106 * @d - Pointer to reo descriptior 1107 * @b - tlv type info 1108 * @h1 - Pointer to hal_reo_status_header where info to be stored 1109 * 1110 * Return - none. 1111 * 1112 */ 1113 static void hal_reo_status_get_header_5018(uint32_t *d, int b, void *h1) 1114 { 1115 uint32_t val1 = 0; 1116 struct hal_reo_status_header *h = 1117 (struct hal_reo_status_header *)h1; 1118 1119 switch (b) { 1120 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1121 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1122 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1123 break; 1124 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1125 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1126 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1127 break; 1128 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1129 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1130 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1131 break; 1132 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1133 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1134 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1135 break; 1136 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1137 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1138 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1139 break; 1140 case HAL_REO_DESC_THRES_STATUS_TLV: 1141 val1 = 1142 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1143 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1144 break; 1145 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1146 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1147 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1148 break; 1149 default: 1150 qdf_nofl_err("ERROR: Unknown tlv\n"); 1151 break; 1152 } 1153 h->cmd_num = 1154 HAL_GET_FIELD( 1155 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1156 val1); 1157 h->exec_time = 1158 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1159 CMD_EXECUTION_TIME, val1); 1160 h->status = 1161 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1162 REO_CMD_EXECUTION_STATUS, val1); 1163 switch (b) { 1164 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1165 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1166 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1167 break; 1168 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1169 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1170 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1171 break; 1172 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1173 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1174 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1175 break; 1176 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1177 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1178 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1179 break; 1180 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1181 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1182 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1183 break; 1184 case HAL_REO_DESC_THRES_STATUS_TLV: 1185 val1 = 1186 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1187 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1188 break; 1189 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1190 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1191 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1192 break; 1193 default: 1194 qdf_nofl_err("ERROR: Unknown tlv\n"); 1195 break; 1196 } 1197 h->tstamp = 1198 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1199 } 1200 1201 /** 1202 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(): 1203 * Retrieve qos control valid bit from the tlv. 1204 * @buf: pointer to rx pkt TLV. 1205 * 1206 * Return: qos control value. 1207 */ 1208 static inline uint32_t 1209 hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(uint8_t *buf) 1210 { 1211 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1212 struct rx_mpdu_start *mpdu_start = 1213 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1214 1215 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1216 &mpdu_start->rx_mpdu_info_details); 1217 } 1218 1219 /** 1220 * hal_rx_msdu_end_sa_sw_peer_id_get_5018(): API to get the 1221 * sa_sw_peer_id from rx_msdu_end TLV 1222 * @buf: pointer to the start of RX PKT TLV headers 1223 * 1224 * Return: sa_sw_peer_id index 1225 */ 1226 static inline uint32_t 1227 hal_rx_msdu_end_sa_sw_peer_id_get_5018(uint8_t *buf) 1228 { 1229 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1230 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1231 1232 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1233 } 1234 1235 /** 1236 * hal_tx_desc_set_mesh_en_5018 - Set mesh_enable flag in Tx descriptor 1237 * @desc: Handle to Tx Descriptor 1238 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1239 * enabling the interpretation of the 'Mesh Control Present' bit 1240 * (bit 8) of QoS Control (otherwise this bit is ignored), 1241 * For native WiFi frames, this indicates that a 'Mesh Control' field 1242 * is present between the header and the LLC. 1243 * 1244 * Return: void 1245 */ 1246 static inline 1247 void hal_tx_desc_set_mesh_en_5018(void *desc, uint8_t en) 1248 { 1249 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1250 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1251 } 1252 1253 static 1254 void *hal_rx_msdu0_buffer_addr_lsb_5018(void *link_desc_va) 1255 { 1256 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1257 } 1258 1259 static 1260 void *hal_rx_msdu_desc_info_ptr_get_5018(void *msdu0) 1261 { 1262 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1263 } 1264 1265 static 1266 void *hal_ent_mpdu_desc_info_5018(void *ent_ring_desc) 1267 { 1268 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1269 } 1270 1271 static 1272 void *hal_dst_mpdu_desc_info_5018(void *dst_ring_desc) 1273 { 1274 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1275 } 1276 1277 static 1278 uint8_t hal_rx_get_fc_valid_5018(uint8_t *buf) 1279 { 1280 return HAL_RX_GET_FC_VALID(buf); 1281 } 1282 1283 static uint8_t hal_rx_get_to_ds_flag_5018(uint8_t *buf) 1284 { 1285 return HAL_RX_GET_TO_DS_FLAG(buf); 1286 } 1287 1288 static uint8_t hal_rx_get_mac_addr2_valid_5018(uint8_t *buf) 1289 { 1290 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1291 } 1292 1293 static uint8_t hal_rx_get_filter_category_5018(uint8_t *buf) 1294 { 1295 return HAL_RX_GET_FILTER_CATEGORY(buf); 1296 } 1297 1298 static uint32_t 1299 hal_rx_get_ppdu_id_5018(uint8_t *buf) 1300 { 1301 struct rx_mpdu_info *rx_mpdu_info; 1302 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 1303 1304 rx_mpdu_info = 1305 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1306 1307 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 1308 } 1309 1310 /** 1311 * hal_reo_config_5018(): Set reo config parameters 1312 * @soc: hal soc handle 1313 * @reg_val: value to be set 1314 * @reo_params: reo parameters 1315 * 1316 * Return: void 1317 */ 1318 static void 1319 hal_reo_config_5018(struct hal_soc *soc, 1320 uint32_t reg_val, 1321 struct hal_reo_params *reo_params) 1322 { 1323 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1324 } 1325 1326 /** 1327 * hal_rx_msdu_desc_info_get_ptr_5018() - Get msdu desc info ptr 1328 * @msdu_details_ptr - Pointer to msdu_details_ptr 1329 * 1330 * Return - Pointer to rx_msdu_desc_info structure. 1331 * 1332 */ 1333 static void *hal_rx_msdu_desc_info_get_ptr_5018(void *msdu_details_ptr) 1334 { 1335 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1336 } 1337 1338 /** 1339 * hal_rx_link_desc_msdu0_ptr_5018 - Get pointer to rx_msdu details 1340 * @link_desc - Pointer to link desc 1341 * 1342 * Return - Pointer to rx_msdu_details structure 1343 * 1344 */ 1345 static void *hal_rx_link_desc_msdu0_ptr_5018(void *link_desc) 1346 { 1347 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1348 } 1349 1350 /** 1351 * hal_rx_msdu_flow_idx_get_5018: API to get flow index 1352 * from rx_msdu_end TLV 1353 * @buf: pointer to the start of RX PKT TLV headers 1354 * 1355 * Return: flow index value from MSDU END TLV 1356 */ 1357 static inline uint32_t hal_rx_msdu_flow_idx_get_5018(uint8_t *buf) 1358 { 1359 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1360 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1361 1362 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1363 } 1364 1365 /** 1366 * hal_rx_msdu_flow_idx_invalid_5018: API to get flow index invalid 1367 * from rx_msdu_end TLV 1368 * @buf: pointer to the start of RX PKT TLV headers 1369 * 1370 * Return: flow index invalid value from MSDU END TLV 1371 */ 1372 static bool hal_rx_msdu_flow_idx_invalid_5018(uint8_t *buf) 1373 { 1374 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1375 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1376 1377 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1378 } 1379 1380 /** 1381 * hal_rx_msdu_flow_idx_timeout_5018: API to get flow index timeout 1382 * from rx_msdu_end TLV 1383 * @buf: pointer to the start of RX PKT TLV headers 1384 * 1385 * Return: flow index timeout value from MSDU END TLV 1386 */ 1387 static bool hal_rx_msdu_flow_idx_timeout_5018(uint8_t *buf) 1388 { 1389 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1390 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1391 1392 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1393 } 1394 1395 /** 1396 * hal_rx_msdu_fse_metadata_get_5018: API to get FSE metadata 1397 * from rx_msdu_end TLV 1398 * @buf: pointer to the start of RX PKT TLV headers 1399 * 1400 * Return: fse metadata value from MSDU END TLV 1401 */ 1402 static uint32_t hal_rx_msdu_fse_metadata_get_5018(uint8_t *buf) 1403 { 1404 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1405 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1406 1407 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1408 } 1409 1410 /** 1411 * hal_rx_msdu_cce_metadata_get_5018: API to get CCE metadata 1412 * from rx_msdu_end TLV 1413 * @buf: pointer to the start of RX PKT TLV headers 1414 * 1415 * Return: cce_metadata 1416 */ 1417 static uint16_t 1418 hal_rx_msdu_cce_metadata_get_5018(uint8_t *buf) 1419 { 1420 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1421 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1422 1423 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1424 } 1425 1426 /** 1427 * hal_rx_msdu_get_flow_params_5018: API to get flow index, flow index invalid 1428 * and flow index timeout from rx_msdu_end TLV 1429 * @buf: pointer to the start of RX PKT TLV headers 1430 * @flow_invalid: pointer to return value of flow_idx_valid 1431 * @flow_timeout: pointer to return value of flow_idx_timeout 1432 * @flow_index: pointer to return value of flow_idx 1433 * 1434 * Return: none 1435 */ 1436 static inline void 1437 hal_rx_msdu_get_flow_params_5018(uint8_t *buf, 1438 bool *flow_invalid, 1439 bool *flow_timeout, 1440 uint32_t *flow_index) 1441 { 1442 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1443 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1444 1445 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1446 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1447 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1448 } 1449 1450 /** 1451 * hal_rx_tlv_get_tcp_chksum_5018() - API to get tcp checksum 1452 * @buf: rx_tlv_hdr 1453 * 1454 * Return: tcp checksum 1455 */ 1456 static uint16_t 1457 hal_rx_tlv_get_tcp_chksum_5018(uint8_t *buf) 1458 { 1459 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1460 } 1461 1462 /** 1463 * hal_rx_get_rx_sequence_5018(): Function to retrieve rx sequence number 1464 * 1465 * @nbuf: Network buffer 1466 * Returns: rx sequence number 1467 */ 1468 static 1469 uint16_t hal_rx_get_rx_sequence_5018(uint8_t *buf) 1470 { 1471 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1472 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1473 1474 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1475 } 1476 1477 /** 1478 * hal_get_window_address_5018(): Function to get hp/tp address 1479 * @hal_soc: Pointer to hal_soc 1480 * @addr: address offset of register 1481 * 1482 * Return: modified address offset of register 1483 */ 1484 static inline qdf_iomem_t hal_get_window_address_5018(struct hal_soc *hal_soc, 1485 qdf_iomem_t addr) 1486 { 1487 uint32_t offset = addr - hal_soc->dev_base_addr; 1488 qdf_iomem_t new_offset; 1489 1490 /* 1491 * Check if offset lies within CE register range(0x08400000) 1492 * or UMAC/DP register range (0x00A00000). 1493 * If offset lies within CE register range, map it 1494 * into CE region. 1495 */ 1496 if (offset & HOST_CE_MASK_VALUE) { 1497 offset = offset - WFSS_CE_REG_BASE; 1498 new_offset = (hal_soc->dev_base_addr_ce + offset); 1499 1500 return new_offset; 1501 } else { 1502 /* 1503 * If offset lies within DP register range, 1504 * return the address as such 1505 */ 1506 return addr; 1507 } 1508 } 1509 1510 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1511 { 1512 /* Write value into window configuration register */ 1513 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1514 WINDOW_CONFIGURATION_VALUE_5018); 1515 } 1516 1517 /** 1518 * hal_rx_msdu_packet_metadata_get_5018(): API to get the 1519 * msdu information from rx_msdu_end TLV 1520 * 1521 * @ buf: pointer to the start of RX PKT TLV headers 1522 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 1523 */ 1524 static void 1525 hal_rx_msdu_packet_metadata_get_5018(uint8_t *buf, 1526 void *msdu_pkt_metadata) 1527 { 1528 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1529 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1530 struct hal_rx_msdu_metadata *msdu_metadata = 1531 (struct hal_rx_msdu_metadata *)msdu_pkt_metadata; 1532 1533 msdu_metadata->l3_hdr_pad = 1534 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1535 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1536 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 1537 msdu_metadata->sa_sw_peer_id = 1538 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1539 } 1540 1541 /** 1542 * hal_rx_flow_setup_fse_5018() - Setup a flow search entry in HW FST 1543 * @fst: Pointer to the Rx Flow Search Table 1544 * @table_offset: offset into the table where the flow is to be setup 1545 * @flow: Flow Parameters 1546 * 1547 * Return: Success/Failure 1548 */ 1549 static void * 1550 hal_rx_flow_setup_fse_5018(uint8_t *rx_fst, uint32_t table_offset, 1551 uint8_t *rx_flow) 1552 { 1553 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1554 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1555 uint8_t *fse; 1556 bool fse_valid; 1557 1558 if (table_offset >= fst->max_entries) { 1559 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1560 "HAL FSE table offset %u exceeds max entries %u", 1561 table_offset, fst->max_entries); 1562 return NULL; 1563 } 1564 1565 fse = (uint8_t *)fst->base_vaddr + 1566 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1567 1568 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1569 1570 if (fse_valid) { 1571 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1572 "HAL FSE %pK already valid", fse); 1573 return NULL; 1574 } 1575 1576 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1577 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1578 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1579 1580 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1581 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1582 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1583 1584 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1585 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1586 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1587 1588 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1589 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1590 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1591 1592 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1593 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1594 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1595 1596 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1597 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1598 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1599 1600 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1601 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1602 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1603 1604 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1605 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1606 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1607 1608 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1609 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1610 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1611 (flow->tuple_info.dest_port)); 1612 1613 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1614 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1615 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1616 (flow->tuple_info.src_port)); 1617 1618 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1619 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1620 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1621 flow->tuple_info.l4_protocol); 1622 1623 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1624 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1625 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1626 flow->reo_destination_handler); 1627 1628 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1629 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1630 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1631 1632 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1633 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1634 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1635 flow->fse_metadata); 1636 1637 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1638 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1639 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1640 REO_DESTINATION_INDICATION, 1641 flow->reo_destination_indication); 1642 1643 /* Reset all the other fields in FSE */ 1644 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1645 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1646 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1647 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1648 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1649 1650 return fse; 1651 } 1652 1653 struct hal_hw_txrx_ops qca5018_hal_hw_txrx_ops = { 1654 1655 /* init and setup */ 1656 hal_srng_dst_hw_init_generic, 1657 hal_srng_src_hw_init_generic, 1658 hal_get_hw_hptp_generic, 1659 hal_reo_setup_generic, 1660 hal_setup_link_idle_list_generic, 1661 hal_get_window_address_5018, 1662 NULL, 1663 1664 /* tx */ 1665 hal_tx_desc_set_dscp_tid_table_id_5018, 1666 hal_tx_set_dscp_tid_map_5018, 1667 hal_tx_update_dscp_tid_5018, 1668 hal_tx_desc_set_lmac_id_5018, 1669 hal_tx_desc_set_buf_addr_generic, 1670 hal_tx_desc_set_search_type_generic, 1671 hal_tx_desc_set_search_index_generic, 1672 hal_tx_desc_set_cache_set_num_generic, 1673 hal_tx_comp_get_status_generic, 1674 hal_tx_comp_get_release_reason_generic, 1675 hal_get_wbm_internal_error_generic, 1676 hal_tx_desc_set_mesh_en_5018, 1677 hal_tx_init_cmd_credit_ring_5018, 1678 1679 /* rx */ 1680 hal_rx_msdu_start_nss_get_5018, 1681 hal_rx_mon_hw_desc_get_mpdu_status_5018, 1682 hal_rx_get_tlv_5018, 1683 hal_rx_proc_phyrx_other_receive_info_tlv_5018, 1684 hal_rx_dump_msdu_start_tlv_5018, 1685 hal_rx_dump_msdu_end_tlv_5018, 1686 hal_get_link_desc_size_5018, 1687 hal_rx_mpdu_start_tid_get_5018, 1688 hal_rx_msdu_start_reception_type_get_5018, 1689 hal_rx_msdu_end_da_idx_get_5018, 1690 hal_rx_msdu_desc_info_get_ptr_5018, 1691 hal_rx_link_desc_msdu0_ptr_5018, 1692 hal_reo_status_get_header_5018, 1693 hal_rx_status_get_tlv_info_generic, 1694 hal_rx_wbm_err_info_get_generic, 1695 hal_rx_dump_mpdu_start_tlv_generic, 1696 1697 hal_tx_set_pcp_tid_map_generic, 1698 hal_tx_update_pcp_tid_generic, 1699 hal_tx_update_tidmap_prty_generic, 1700 hal_rx_get_rx_fragment_number_5018, 1701 hal_rx_msdu_end_da_is_mcbc_get_5018, 1702 hal_rx_msdu_end_sa_is_valid_get_5018, 1703 hal_rx_msdu_end_sa_idx_get_5018, 1704 hal_rx_desc_is_first_msdu_5018, 1705 hal_rx_msdu_end_l3_hdr_padding_get_5018, 1706 hal_rx_encryption_info_valid_5018, 1707 hal_rx_print_pn_5018, 1708 hal_rx_msdu_end_first_msdu_get_5018, 1709 hal_rx_msdu_end_da_is_valid_get_5018, 1710 hal_rx_msdu_end_last_msdu_get_5018, 1711 hal_rx_get_mpdu_mac_ad4_valid_5018, 1712 hal_rx_mpdu_start_sw_peer_id_get_5018, 1713 hal_rx_mpdu_get_to_ds_5018, 1714 hal_rx_mpdu_get_fr_ds_5018, 1715 hal_rx_get_mpdu_frame_control_valid_5018, 1716 hal_rx_mpdu_get_addr1_5018, 1717 hal_rx_mpdu_get_addr2_5018, 1718 hal_rx_mpdu_get_addr3_5018, 1719 hal_rx_mpdu_get_addr4_5018, 1720 hal_rx_get_mpdu_sequence_control_valid_5018, 1721 hal_rx_is_unicast_5018, 1722 hal_rx_tid_get_5018, 1723 hal_rx_hw_desc_get_ppduid_get_5018, 1724 hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018, 1725 hal_rx_msdu_end_sa_sw_peer_id_get_5018, 1726 hal_rx_msdu0_buffer_addr_lsb_5018, 1727 hal_rx_msdu_desc_info_ptr_get_5018, 1728 hal_ent_mpdu_desc_info_5018, 1729 hal_dst_mpdu_desc_info_5018, 1730 hal_rx_get_fc_valid_5018, 1731 hal_rx_get_to_ds_flag_5018, 1732 hal_rx_get_mac_addr2_valid_5018, 1733 hal_rx_get_filter_category_5018, 1734 hal_rx_get_ppdu_id_5018, 1735 hal_reo_config_5018, 1736 hal_rx_msdu_flow_idx_get_5018, 1737 hal_rx_msdu_flow_idx_invalid_5018, 1738 hal_rx_msdu_flow_idx_timeout_5018, 1739 hal_rx_msdu_fse_metadata_get_5018, 1740 hal_rx_msdu_cce_metadata_get_5018, 1741 hal_rx_msdu_get_flow_params_5018, 1742 hal_rx_tlv_get_tcp_chksum_5018, 1743 hal_rx_get_rx_sequence_5018, 1744 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 1745 hal_rx_get_bb_info_5018, 1746 hal_rx_get_rtt_info_5018, 1747 #else 1748 NULL, 1749 NULL, 1750 #endif 1751 /* rx - msdu fast path info fields */ 1752 hal_rx_msdu_packet_metadata_get_5018, 1753 NULL, 1754 NULL, 1755 NULL, 1756 NULL, 1757 NULL, 1758 NULL, 1759 hal_rx_mpdu_start_tlv_tag_valid_5018, 1760 NULL, 1761 hal_rx_wbm_err_msdu_continuation_get_5018, 1762 1763 /* rx - TLV struct offsets */ 1764 hal_rx_msdu_end_offset_get_generic, 1765 hal_rx_attn_offset_get_generic, 1766 hal_rx_msdu_start_offset_get_generic, 1767 hal_rx_mpdu_start_offset_get_generic, 1768 hal_rx_mpdu_end_offset_get_generic, 1769 hal_rx_flow_setup_fse_5018, 1770 hal_compute_reo_remap_ix2_ix3_5018, 1771 NULL, 1772 NULL, 1773 NULL, 1774 NULL 1775 }; 1776 1777 struct hal_hw_srng_config hw_srng_table_5018[] = { 1778 /* TODO: max_rings can populated by querying HW capabilities */ 1779 { /* REO_DST */ 1780 .start_ring_id = HAL_SRNG_REO2SW1, 1781 .max_rings = 4, 1782 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1783 .lmac_ring = FALSE, 1784 .ring_dir = HAL_SRNG_DST_RING, 1785 .reg_start = { 1786 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1787 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1788 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1789 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1790 }, 1791 .reg_size = { 1792 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1793 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1794 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1795 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1796 }, 1797 .max_size = 1798 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1799 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1800 }, 1801 { /* REO_EXCEPTION */ 1802 /* Designating REO2TCL ring as exception ring. This ring is 1803 * similar to other REO2SW rings though it is named as REO2TCL. 1804 * Any of theREO2SW rings can be used as exception ring. 1805 */ 1806 .start_ring_id = HAL_SRNG_REO2TCL, 1807 .max_rings = 1, 1808 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1809 .lmac_ring = FALSE, 1810 .ring_dir = HAL_SRNG_DST_RING, 1811 .reg_start = { 1812 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1813 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1814 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1815 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1816 }, 1817 /* Single ring - provide ring size if multiple rings of this 1818 * type are supported 1819 */ 1820 .reg_size = {}, 1821 .max_size = 1822 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1823 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1824 }, 1825 { /* REO_REINJECT */ 1826 .start_ring_id = HAL_SRNG_SW2REO, 1827 .max_rings = 1, 1828 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1829 .lmac_ring = FALSE, 1830 .ring_dir = HAL_SRNG_SRC_RING, 1831 .reg_start = { 1832 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1833 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1834 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1835 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1836 }, 1837 /* Single ring - provide ring size if multiple rings of this 1838 * type are supported 1839 */ 1840 .reg_size = {}, 1841 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1842 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1843 }, 1844 { /* REO_CMD */ 1845 .start_ring_id = HAL_SRNG_REO_CMD, 1846 .max_rings = 1, 1847 .entry_size = (sizeof(struct tlv_32_hdr) + 1848 sizeof(struct reo_get_queue_stats)) >> 2, 1849 .lmac_ring = FALSE, 1850 .ring_dir = HAL_SRNG_SRC_RING, 1851 .reg_start = { 1852 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1853 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1854 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1855 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1856 }, 1857 /* Single ring - provide ring size if multiple rings of this 1858 * type are supported 1859 */ 1860 .reg_size = {}, 1861 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1862 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1863 }, 1864 { /* REO_STATUS */ 1865 .start_ring_id = HAL_SRNG_REO_STATUS, 1866 .max_rings = 1, 1867 .entry_size = (sizeof(struct tlv_32_hdr) + 1868 sizeof(struct reo_get_queue_stats_status)) >> 2, 1869 .lmac_ring = FALSE, 1870 .ring_dir = HAL_SRNG_DST_RING, 1871 .reg_start = { 1872 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1873 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1874 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1875 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1876 }, 1877 /* Single ring - provide ring size if multiple rings of this 1878 * type are supported 1879 */ 1880 .reg_size = {}, 1881 .max_size = 1882 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1883 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1884 }, 1885 { /* TCL_DATA */ 1886 .start_ring_id = HAL_SRNG_SW2TCL1, 1887 .max_rings = 3, 1888 .entry_size = (sizeof(struct tlv_32_hdr) + 1889 sizeof(struct tcl_data_cmd)) >> 2, 1890 .lmac_ring = FALSE, 1891 .ring_dir = HAL_SRNG_SRC_RING, 1892 .reg_start = { 1893 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1894 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1895 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1896 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1897 }, 1898 .reg_size = { 1899 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1900 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1901 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1902 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1903 }, 1904 .max_size = 1905 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1906 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1907 }, 1908 { /* TCL_CMD */ 1909 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1910 .max_rings = 1, 1911 .entry_size = (sizeof(struct tlv_32_hdr) + 1912 sizeof(struct tcl_data_cmd)) >> 2, 1913 .lmac_ring = FALSE, 1914 .ring_dir = HAL_SRNG_SRC_RING, 1915 .reg_start = { 1916 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 1917 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1918 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 1919 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1920 }, 1921 /* Single ring - provide ring size if multiple rings of this 1922 * type are supported 1923 */ 1924 .reg_size = {}, 1925 .max_size = 1926 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 1927 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 1928 }, 1929 { /* TCL_STATUS */ 1930 .start_ring_id = HAL_SRNG_TCL_STATUS, 1931 .max_rings = 1, 1932 .entry_size = (sizeof(struct tlv_32_hdr) + 1933 sizeof(struct tcl_status_ring)) >> 2, 1934 .lmac_ring = FALSE, 1935 .ring_dir = HAL_SRNG_DST_RING, 1936 .reg_start = { 1937 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1938 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1939 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1940 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1941 }, 1942 /* Single ring - provide ring size if multiple rings of this 1943 * type are supported 1944 */ 1945 .reg_size = {}, 1946 .max_size = 1947 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1948 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1949 }, 1950 { /* CE_SRC */ 1951 .start_ring_id = HAL_SRNG_CE_0_SRC, 1952 .max_rings = 12, 1953 .entry_size = sizeof(struct ce_src_desc) >> 2, 1954 .lmac_ring = FALSE, 1955 .ring_dir = HAL_SRNG_SRC_RING, 1956 .reg_start = { 1957 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1958 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1959 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1960 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1961 }, 1962 .reg_size = { 1963 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1964 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1965 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1966 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1967 }, 1968 .max_size = 1969 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1970 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1971 }, 1972 { /* CE_DST */ 1973 .start_ring_id = HAL_SRNG_CE_0_DST, 1974 .max_rings = 12, 1975 .entry_size = 8 >> 2, 1976 /*TODO: entry_size above should actually be 1977 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1978 * of struct ce_dst_desc in HW header files 1979 */ 1980 .lmac_ring = FALSE, 1981 .ring_dir = HAL_SRNG_SRC_RING, 1982 .reg_start = { 1983 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1984 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1985 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1986 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1987 }, 1988 .reg_size = { 1989 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1990 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1991 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1992 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1993 }, 1994 .max_size = 1995 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1996 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1997 }, 1998 { /* CE_DST_STATUS */ 1999 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2000 .max_rings = 12, 2001 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2002 .lmac_ring = FALSE, 2003 .ring_dir = HAL_SRNG_DST_RING, 2004 .reg_start = { 2005 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2006 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2007 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2008 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2009 }, 2010 /* TODO: check destination status ring registers */ 2011 .reg_size = { 2012 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2013 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2014 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2015 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2016 }, 2017 .max_size = 2018 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2019 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2020 }, 2021 { /* WBM_IDLE_LINK */ 2022 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2023 .max_rings = 1, 2024 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2025 .lmac_ring = FALSE, 2026 .ring_dir = HAL_SRNG_SRC_RING, 2027 .reg_start = { 2028 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2029 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2030 }, 2031 /* Single ring - provide ring size if multiple rings of this 2032 * type are supported 2033 */ 2034 .reg_size = {}, 2035 .max_size = 2036 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2037 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2038 }, 2039 { /* SW2WBM_RELEASE */ 2040 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2041 .max_rings = 1, 2042 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2043 .lmac_ring = FALSE, 2044 .ring_dir = HAL_SRNG_SRC_RING, 2045 .reg_start = { 2046 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2047 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2048 }, 2049 /* Single ring - provide ring size if multiple rings of this 2050 * type are supported 2051 */ 2052 .reg_size = {}, 2053 .max_size = 2054 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2055 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2056 }, 2057 { /* WBM2SW_RELEASE */ 2058 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2059 .max_rings = 4, 2060 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2061 .lmac_ring = FALSE, 2062 .ring_dir = HAL_SRNG_DST_RING, 2063 .reg_start = { 2064 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2065 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2066 }, 2067 .reg_size = { 2068 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2069 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2070 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2071 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2072 }, 2073 .max_size = 2074 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2075 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2076 }, 2077 { /* RXDMA_BUF */ 2078 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2079 #ifdef IPA_OFFLOAD 2080 .max_rings = 3, 2081 #else 2082 .max_rings = 2, 2083 #endif 2084 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2085 .lmac_ring = TRUE, 2086 .ring_dir = HAL_SRNG_SRC_RING, 2087 /* reg_start is not set because LMAC rings are not accessed 2088 * from host 2089 */ 2090 .reg_start = {}, 2091 .reg_size = {}, 2092 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2093 }, 2094 { /* RXDMA_DST */ 2095 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2096 .max_rings = 1, 2097 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2098 .lmac_ring = TRUE, 2099 .ring_dir = HAL_SRNG_DST_RING, 2100 /* reg_start is not set because LMAC rings are not accessed 2101 * from host 2102 */ 2103 .reg_start = {}, 2104 .reg_size = {}, 2105 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2106 }, 2107 { /* RXDMA_MONITOR_BUF */ 2108 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2109 .max_rings = 1, 2110 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2111 .lmac_ring = TRUE, 2112 .ring_dir = HAL_SRNG_SRC_RING, 2113 /* reg_start is not set because LMAC rings are not accessed 2114 * from host 2115 */ 2116 .reg_start = {}, 2117 .reg_size = {}, 2118 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2119 }, 2120 { /* RXDMA_MONITOR_STATUS */ 2121 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2122 .max_rings = 1, 2123 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2124 .lmac_ring = TRUE, 2125 .ring_dir = HAL_SRNG_SRC_RING, 2126 /* reg_start is not set because LMAC rings are not accessed 2127 * from host 2128 */ 2129 .reg_start = {}, 2130 .reg_size = {}, 2131 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2132 }, 2133 { /* RXDMA_MONITOR_DST */ 2134 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2135 .max_rings = 1, 2136 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2137 .lmac_ring = TRUE, 2138 .ring_dir = HAL_SRNG_DST_RING, 2139 /* reg_start is not set because LMAC rings are not accessed 2140 * from host 2141 */ 2142 .reg_start = {}, 2143 .reg_size = {}, 2144 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2145 }, 2146 { /* RXDMA_MONITOR_DESC */ 2147 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2148 .max_rings = 1, 2149 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2150 .lmac_ring = TRUE, 2151 .ring_dir = HAL_SRNG_SRC_RING, 2152 /* reg_start is not set because LMAC rings are not accessed 2153 * from host 2154 */ 2155 .reg_start = {}, 2156 .reg_size = {}, 2157 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2158 }, 2159 { /* DIR_BUF_RX_DMA_SRC */ 2160 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2161 /* one ring for spectral and one ring for cfr */ 2162 .max_rings = 2, 2163 .entry_size = 2, 2164 .lmac_ring = TRUE, 2165 .ring_dir = HAL_SRNG_SRC_RING, 2166 /* reg_start is not set because LMAC rings are not accessed 2167 * from host 2168 */ 2169 .reg_start = {}, 2170 .reg_size = {}, 2171 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2172 }, 2173 #ifdef WLAN_FEATURE_CIF_CFR 2174 { /* WIFI_POS_SRC */ 2175 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2176 .max_rings = 1, 2177 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2178 .lmac_ring = TRUE, 2179 .ring_dir = HAL_SRNG_SRC_RING, 2180 /* reg_start is not set because LMAC rings are not accessed 2181 * from host 2182 */ 2183 .reg_start = {}, 2184 .reg_size = {}, 2185 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2186 }, 2187 #endif 2188 }; 2189 2190 int32_t hal_hw_reg_offset_qca5018[] = { 2191 /* dst */ 2192 REG_OFFSET(DST, HP), 2193 REG_OFFSET(DST, TP), 2194 REG_OFFSET(DST, ID), 2195 REG_OFFSET(DST, MISC), 2196 REG_OFFSET(DST, HP_ADDR_LSB), 2197 REG_OFFSET(DST, HP_ADDR_MSB), 2198 REG_OFFSET(DST, MSI1_BASE_LSB), 2199 REG_OFFSET(DST, MSI1_BASE_MSB), 2200 REG_OFFSET(DST, MSI1_DATA), 2201 REG_OFFSET(DST, BASE_LSB), 2202 REG_OFFSET(DST, BASE_MSB), 2203 REG_OFFSET(DST, PRODUCER_INT_SETUP), 2204 /* src */ 2205 REG_OFFSET(SRC, HP), 2206 REG_OFFSET(SRC, TP), 2207 REG_OFFSET(SRC, ID), 2208 REG_OFFSET(SRC, MISC), 2209 REG_OFFSET(SRC, TP_ADDR_LSB), 2210 REG_OFFSET(SRC, TP_ADDR_MSB), 2211 REG_OFFSET(SRC, MSI1_BASE_LSB), 2212 REG_OFFSET(SRC, MSI1_BASE_MSB), 2213 REG_OFFSET(SRC, MSI1_DATA), 2214 REG_OFFSET(SRC, BASE_LSB), 2215 REG_OFFSET(SRC, BASE_MSB), 2216 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 2217 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 2218 }; 2219 2220 /** 2221 * hal_qca5018_attach()- Attach 5018 target specific hal_soc ops, 2222 * offset and srng table 2223 * Return: void 2224 */ 2225 void hal_qca5018_attach(struct hal_soc *hal_soc) 2226 { 2227 hal_soc->hw_srng_table = hw_srng_table_5018; 2228 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca5018; 2229 hal_soc->ops = &qca5018_hal_hw_txrx_ops; 2230 } 2231