1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "hal_li_hw_headers.h" 20 #include "hal_internal.h" 21 #include "hal_api.h" 22 #include "target_type.h" 23 #include "wcss_version.h" 24 #include "qdf_module.h" 25 #include "hal_flow.h" 26 #include "rx_flow_search_entry.h" 27 #include "hal_rx_flow_info.h" 28 29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 30 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 32 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 34 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 35 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \ 36 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 37 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \ 38 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 39 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \ 40 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 41 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 42 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 43 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 44 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 45 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 46 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 47 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 48 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 59 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 60 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 61 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 62 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 63 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 64 RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 65 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 66 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 67 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 68 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 69 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 71 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 72 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 73 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 74 STATUS_HEADER_REO_STATUS_NUMBER 75 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 76 STATUS_HEADER_TIMESTAMP 77 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 78 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 79 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 80 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 81 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 82 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 83 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 84 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 85 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 86 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 87 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 88 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 90 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 92 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 94 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 95 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 96 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 97 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 98 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 99 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 100 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 101 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 102 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 103 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 104 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 105 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 106 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 107 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 108 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 109 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 110 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 112 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 113 114 #define CE_WINDOW_ADDRESS_5018 \ 115 ((WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 116 117 #define UMAC_WINDOW_ADDRESS_5018 \ 118 ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 119 120 #define WINDOW_CONFIGURATION_VALUE_5018 \ 121 ((CE_WINDOW_ADDRESS_5018 << 6) |\ 122 (UMAC_WINDOW_ADDRESS_5018 << 12) | \ 123 WINDOW_ENABLE_BIT) 124 125 #define HOST_CE_MASK_VALUE 0xFF000000 126 127 #include "hal_5018_tx.h" 128 #include "hal_5018_rx.h" 129 #include <hal_generic_api.h> 130 #include "hal_li_rx.h" 131 #include "hal_li_api.h" 132 #include "hal_li_generic_api.h" 133 134 /** 135 * hal_rx_msdu_start_nss_get_5018(): API to get the NSS 136 * Interval from rx_msdu_start 137 * 138 * @buf: pointer to the start of RX PKT TLV header 139 * Return: uint32_t(nss) 140 */ 141 static uint32_t hal_rx_msdu_start_nss_get_5018(uint8_t *buf) 142 { 143 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 144 struct rx_msdu_start *msdu_start = 145 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 146 uint8_t mimo_ss_bitmap; 147 148 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 149 150 return qdf_get_hweight8(mimo_ss_bitmap); 151 } 152 153 /** 154 * hal_rx_msdu_start_get_len_5018(): API to get the MSDU length 155 * from rx_msdu_start TLV 156 * 157 * @ buf: pointer to the start of RX PKT TLV headers 158 * Return: (uint32_t)msdu length 159 */ 160 static uint32_t hal_rx_msdu_start_get_len_5018(uint8_t *buf) 161 { 162 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 163 struct rx_msdu_start *msdu_start = 164 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 165 uint32_t msdu_len; 166 167 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 168 169 return msdu_len; 170 } 171 172 /** 173 * hal_rx_mon_hw_desc_get_mpdu_status_5018(): Retrieve MPDU status 174 * 175 * @ hw_desc_addr: Start address of Rx HW TLVs 176 * @ rs: Status for monitor mode 177 * 178 * Return: void 179 */ 180 static void hal_rx_mon_hw_desc_get_mpdu_status_5018(void *hw_desc_addr, 181 struct mon_rx_status *rs) 182 { 183 struct rx_msdu_start *rx_msdu_start; 184 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 185 uint32_t reg_value; 186 const uint32_t sgi_hw_to_cdp[] = { 187 CDP_SGI_0_8_US, 188 CDP_SGI_0_4_US, 189 CDP_SGI_1_6_US, 190 CDP_SGI_3_2_US, 191 }; 192 193 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 194 195 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 196 197 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 198 RX_MSDU_START_5, USER_RSSI); 199 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 200 201 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 202 rs->sgi = sgi_hw_to_cdp[reg_value]; 203 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 204 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 205 /* TODO: rs->beamformed should be set for SU beamforming also */ 206 } 207 208 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 209 /** 210 * hal_get_link_desc_size_5018(): API to get the link desc size 211 * 212 * Return: uint32_t 213 */ 214 static uint32_t hal_get_link_desc_size_5018(void) 215 { 216 return LINK_DESC_SIZE; 217 } 218 219 /** 220 * hal_rx_get_tlv_5018(): API to get the tlv 221 * 222 * @rx_tlv: TLV data extracted from the rx packet 223 * Return: uint8_t 224 */ 225 static uint8_t hal_rx_get_tlv_5018(void *rx_tlv) 226 { 227 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 228 } 229 230 /** 231 * hal_rx_mpdu_start_tlv_tag_valid_5018 () - API to check if RX_MPDU_START 232 * tlv tag is valid 233 * 234 *@rx_tlv_hdr: start address of rx_pkt_tlvs 235 * 236 * Return: true if RX_MPDU_START is valied, else false. 237 */ 238 uint8_t hal_rx_mpdu_start_tlv_tag_valid_5018(void *rx_tlv_hdr) 239 { 240 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 241 uint32_t tlv_tag; 242 243 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 244 245 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 246 } 247 248 /** 249 * hal_rx_wbm_err_msdu_continuation_get_5018 () - API to check if WBM 250 * msdu continuation bit is set 251 * 252 *@wbm_desc: wbm release ring descriptor 253 * 254 * Return: true if msdu continuation bit is set. 255 */ 256 uint8_t hal_rx_wbm_err_msdu_continuation_get_5018(void *wbm_desc) 257 { 258 uint32_t comp_desc = 259 *(uint32_t *)(((uint8_t *)wbm_desc) + 260 WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET); 261 262 return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >> 263 WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB; 264 } 265 266 static 267 void hal_compute_reo_remap_ix2_ix3_5018(uint32_t *ring, uint32_t num_rings, 268 uint32_t *remap1, uint32_t *remap2) 269 { 270 switch (num_rings) { 271 case 1: 272 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 273 HAL_REO_REMAP_IX2(ring[0], 17) | 274 HAL_REO_REMAP_IX2(ring[0], 18) | 275 HAL_REO_REMAP_IX2(ring[0], 19) | 276 HAL_REO_REMAP_IX2(ring[0], 20) | 277 HAL_REO_REMAP_IX2(ring[0], 21) | 278 HAL_REO_REMAP_IX2(ring[0], 22) | 279 HAL_REO_REMAP_IX2(ring[0], 23); 280 281 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 282 HAL_REO_REMAP_IX3(ring[0], 25) | 283 HAL_REO_REMAP_IX3(ring[0], 26) | 284 HAL_REO_REMAP_IX3(ring[0], 27) | 285 HAL_REO_REMAP_IX3(ring[0], 28) | 286 HAL_REO_REMAP_IX3(ring[0], 29) | 287 HAL_REO_REMAP_IX3(ring[0], 30) | 288 HAL_REO_REMAP_IX3(ring[0], 31); 289 break; 290 case 2: 291 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 292 HAL_REO_REMAP_IX2(ring[0], 17) | 293 HAL_REO_REMAP_IX2(ring[1], 18) | 294 HAL_REO_REMAP_IX2(ring[1], 19) | 295 HAL_REO_REMAP_IX2(ring[0], 20) | 296 HAL_REO_REMAP_IX2(ring[0], 21) | 297 HAL_REO_REMAP_IX2(ring[1], 22) | 298 HAL_REO_REMAP_IX2(ring[1], 23); 299 300 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 301 HAL_REO_REMAP_IX3(ring[0], 25) | 302 HAL_REO_REMAP_IX3(ring[1], 26) | 303 HAL_REO_REMAP_IX3(ring[1], 27) | 304 HAL_REO_REMAP_IX3(ring[0], 28) | 305 HAL_REO_REMAP_IX3(ring[0], 29) | 306 HAL_REO_REMAP_IX3(ring[1], 30) | 307 HAL_REO_REMAP_IX3(ring[1], 31); 308 break; 309 case 3: 310 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 311 HAL_REO_REMAP_IX2(ring[1], 17) | 312 HAL_REO_REMAP_IX2(ring[2], 18) | 313 HAL_REO_REMAP_IX2(ring[0], 19) | 314 HAL_REO_REMAP_IX2(ring[1], 20) | 315 HAL_REO_REMAP_IX2(ring[2], 21) | 316 HAL_REO_REMAP_IX2(ring[0], 22) | 317 HAL_REO_REMAP_IX2(ring[1], 23); 318 319 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 320 HAL_REO_REMAP_IX3(ring[0], 25) | 321 HAL_REO_REMAP_IX3(ring[1], 26) | 322 HAL_REO_REMAP_IX3(ring[2], 27) | 323 HAL_REO_REMAP_IX3(ring[0], 28) | 324 HAL_REO_REMAP_IX3(ring[1], 29) | 325 HAL_REO_REMAP_IX3(ring[2], 30) | 326 HAL_REO_REMAP_IX3(ring[0], 31); 327 break; 328 case 4: 329 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 330 HAL_REO_REMAP_IX2(ring[1], 17) | 331 HAL_REO_REMAP_IX2(ring[2], 18) | 332 HAL_REO_REMAP_IX2(ring[3], 19) | 333 HAL_REO_REMAP_IX2(ring[0], 20) | 334 HAL_REO_REMAP_IX2(ring[1], 21) | 335 HAL_REO_REMAP_IX2(ring[2], 22) | 336 HAL_REO_REMAP_IX2(ring[3], 23); 337 338 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 339 HAL_REO_REMAP_IX3(ring[1], 25) | 340 HAL_REO_REMAP_IX3(ring[2], 26) | 341 HAL_REO_REMAP_IX3(ring[3], 27) | 342 HAL_REO_REMAP_IX3(ring[0], 28) | 343 HAL_REO_REMAP_IX3(ring[1], 29) | 344 HAL_REO_REMAP_IX3(ring[2], 30) | 345 HAL_REO_REMAP_IX3(ring[3], 31); 346 break; 347 } 348 } 349 350 /** 351 * hal_rx_proc_phyrx_other_receive_info_tlv_5018(): API to get tlv info 352 * 353 * Return: uint32_t 354 */ 355 static inline 356 void hal_rx_proc_phyrx_other_receive_info_tlv_5018(void *rx_tlv_hdr, 357 void *ppdu_info_hdl) 358 { 359 } 360 361 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 362 static inline 363 void hal_rx_get_bb_info_5018(void *rx_tlv, 364 void *ppdu_info_hdl) 365 { 366 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 367 368 ppdu_info->cfr_info.bb_captured_channel = 369 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); 370 371 ppdu_info->cfr_info.bb_captured_timeout = 372 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); 373 374 ppdu_info->cfr_info.bb_captured_reason = 375 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); 376 } 377 378 static inline 379 void hal_rx_get_rtt_info_5018(void *rx_tlv, 380 void *ppdu_info_hdl) 381 { 382 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 383 384 ppdu_info->cfr_info.rx_location_info_valid = 385 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, 386 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 387 388 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 389 HAL_RX_GET(rx_tlv, 390 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 391 RTT_CHE_BUFFER_POINTER_LOW32); 392 393 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 394 HAL_RX_GET(rx_tlv, 395 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 396 RTT_CHE_BUFFER_POINTER_HIGH8); 397 398 ppdu_info->cfr_info.chan_capture_status = 399 HAL_RX_GET(rx_tlv, 400 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 401 RESERVED_8); 402 } 403 #endif 404 405 /** 406 * hal_rx_dump_msdu_start_tlv_5018() : dump RX msdu_start TLV in structured 407 * human readable format. 408 * @ msdu_start: pointer the msdu_start TLV in pkt. 409 * @ dbg_level: log level. 410 * 411 * Return: void 412 */ 413 static void hal_rx_dump_msdu_start_tlv_5018(void *msdustart, 414 uint8_t dbg_level) 415 { 416 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 417 418 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 419 "rx_msdu_start tlv - " 420 "rxpcu_mpdu_filter_in_category: %d " 421 "sw_frame_group_id: %d " 422 "phy_ppdu_id: %d " 423 "msdu_length: %d " 424 "ipsec_esp: %d " 425 "l3_offset: %d " 426 "ipsec_ah: %d " 427 "l4_offset: %d " 428 "msdu_number: %d " 429 "decap_format: %d " 430 "ipv4_proto: %d " 431 "ipv6_proto: %d " 432 "tcp_proto: %d " 433 "udp_proto: %d " 434 "ip_frag: %d " 435 "tcp_only_ack: %d " 436 "da_is_bcast_mcast: %d " 437 "ip4_protocol_ip6_next_header: %d " 438 "toeplitz_hash_2_or_4: %d " 439 "flow_id_toeplitz: %d " 440 "user_rssi: %d " 441 "pkt_type: %d " 442 "stbc: %d " 443 "sgi: %d " 444 "rate_mcs: %d " 445 "receive_bandwidth: %d " 446 "reception_type: %d " 447 "ppdu_start_timestamp: %d " 448 "sw_phy_meta_data: %d ", 449 msdu_start->rxpcu_mpdu_filter_in_category, 450 msdu_start->sw_frame_group_id, 451 msdu_start->phy_ppdu_id, 452 msdu_start->msdu_length, 453 msdu_start->ipsec_esp, 454 msdu_start->l3_offset, 455 msdu_start->ipsec_ah, 456 msdu_start->l4_offset, 457 msdu_start->msdu_number, 458 msdu_start->decap_format, 459 msdu_start->ipv4_proto, 460 msdu_start->ipv6_proto, 461 msdu_start->tcp_proto, 462 msdu_start->udp_proto, 463 msdu_start->ip_frag, 464 msdu_start->tcp_only_ack, 465 msdu_start->da_is_bcast_mcast, 466 msdu_start->ip4_protocol_ip6_next_header, 467 msdu_start->toeplitz_hash_2_or_4, 468 msdu_start->flow_id_toeplitz, 469 msdu_start->user_rssi, 470 msdu_start->pkt_type, 471 msdu_start->stbc, 472 msdu_start->sgi, 473 msdu_start->rate_mcs, 474 msdu_start->receive_bandwidth, 475 msdu_start->reception_type, 476 msdu_start->ppdu_start_timestamp, 477 msdu_start->sw_phy_meta_data); 478 } 479 480 /** 481 * hal_rx_dump_msdu_end_tlv_5018: dump RX msdu_end TLV in structured 482 * human readable format. 483 * @ msdu_end: pointer the msdu_end TLV in pkt. 484 * @ dbg_level: log level. 485 * 486 * Return: void 487 */ 488 static void hal_rx_dump_msdu_end_tlv_5018(void *msduend, 489 uint8_t dbg_level) 490 { 491 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 492 493 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 494 "rx_msdu_end tlv - " 495 "rxpcu_mpdu_filter_in_category: %d " 496 "sw_frame_group_id: %d " 497 "phy_ppdu_id: %d " 498 "ip_hdr_chksum: %d " 499 "reported_mpdu_length: %d " 500 "key_id_octet: %d " 501 "cce_super_rule: %d " 502 "cce_classify_not_done_truncat: %d " 503 "cce_classify_not_done_cce_dis: %d " 504 "rule_indication_31_0: %d " 505 "rule_indication_63_32: %d " 506 "da_offset: %d " 507 "sa_offset: %d " 508 "da_offset_valid: %d " 509 "sa_offset_valid: %d " 510 "ipv6_options_crc: %d " 511 "tcp_seq_number: %d " 512 "tcp_ack_number: %d " 513 "tcp_flag: %d " 514 "lro_eligible: %d " 515 "window_size: %d " 516 "tcp_udp_chksum: %d " 517 "sa_idx_timeout: %d " 518 "da_idx_timeout: %d " 519 "msdu_limit_error: %d " 520 "flow_idx_timeout: %d " 521 "flow_idx_invalid: %d " 522 "wifi_parser_error: %d " 523 "amsdu_parser_error: %d " 524 "sa_is_valid: %d " 525 "da_is_valid: %d " 526 "da_is_mcbc: %d " 527 "l3_header_padding: %d " 528 "first_msdu: %d " 529 "last_msdu: %d " 530 "sa_idx: %d " 531 "msdu_drop: %d " 532 "reo_destination_indication: %d " 533 "flow_idx: %d " 534 "fse_metadata: %d " 535 "cce_metadata: %d " 536 "sa_sw_peer_id: %d ", 537 msdu_end->rxpcu_mpdu_filter_in_category, 538 msdu_end->sw_frame_group_id, 539 msdu_end->phy_ppdu_id, 540 msdu_end->ip_hdr_chksum, 541 msdu_end->reported_mpdu_length, 542 msdu_end->key_id_octet, 543 msdu_end->cce_super_rule, 544 msdu_end->cce_classify_not_done_truncate, 545 msdu_end->cce_classify_not_done_cce_dis, 546 msdu_end->rule_indication_31_0, 547 msdu_end->rule_indication_63_32, 548 msdu_end->da_offset, 549 msdu_end->sa_offset, 550 msdu_end->da_offset_valid, 551 msdu_end->sa_offset_valid, 552 msdu_end->ipv6_options_crc, 553 msdu_end->tcp_seq_number, 554 msdu_end->tcp_ack_number, 555 msdu_end->tcp_flag, 556 msdu_end->lro_eligible, 557 msdu_end->window_size, 558 msdu_end->tcp_udp_chksum, 559 msdu_end->sa_idx_timeout, 560 msdu_end->da_idx_timeout, 561 msdu_end->msdu_limit_error, 562 msdu_end->flow_idx_timeout, 563 msdu_end->flow_idx_invalid, 564 msdu_end->wifi_parser_error, 565 msdu_end->amsdu_parser_error, 566 msdu_end->sa_is_valid, 567 msdu_end->da_is_valid, 568 msdu_end->da_is_mcbc, 569 msdu_end->l3_header_padding, 570 msdu_end->first_msdu, 571 msdu_end->last_msdu, 572 msdu_end->sa_idx, 573 msdu_end->msdu_drop, 574 msdu_end->reo_destination_indication, 575 msdu_end->flow_idx, 576 msdu_end->fse_metadata, 577 msdu_end->cce_metadata, 578 msdu_end->sa_sw_peer_id); 579 } 580 581 /** 582 * hal_rx_mpdu_start_tid_get_5018(): API to get tid 583 * from rx_msdu_start 584 * 585 * @buf: pointer to the start of RX PKT TLV header 586 * Return: uint32_t(tid value) 587 */ 588 static uint32_t hal_rx_mpdu_start_tid_get_5018(uint8_t *buf) 589 { 590 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 591 struct rx_mpdu_start *mpdu_start = 592 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 593 uint32_t tid; 594 595 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 596 597 return tid; 598 } 599 600 /** 601 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 602 * Interval from rx_msdu_start 603 * 604 * @buf: pointer to the start of RX PKT TLV header 605 * Return: uint32_t(reception_type) 606 */ 607 static uint32_t hal_rx_msdu_start_reception_type_get_5018(uint8_t *buf) 608 { 609 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 610 struct rx_msdu_start *msdu_start = 611 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 612 uint32_t reception_type; 613 614 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 615 616 return reception_type; 617 } 618 619 /** 620 * hal_rx_msdu_end_da_idx_get_5018: API to get da_idx 621 * from rx_msdu_end TLV 622 * 623 * @ buf: pointer to the start of RX PKT TLV headers 624 * Return: da index 625 */ 626 static uint16_t hal_rx_msdu_end_da_idx_get_5018(uint8_t *buf) 627 { 628 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 629 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 630 uint16_t da_idx; 631 632 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 633 634 return da_idx; 635 } 636 637 /** 638 * hal_rx_get_rx_fragment_number_5018(): Function to retrieve rx fragment number 639 * 640 * @nbuf: Network buffer 641 * Returns: rx fragment number 642 */ 643 static 644 uint8_t hal_rx_get_rx_fragment_number_5018(uint8_t *buf) 645 { 646 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 647 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 648 649 /* Return first 4 bits as fragment number */ 650 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 651 DOT11_SEQ_FRAG_MASK); 652 } 653 654 /** 655 * hal_rx_msdu_end_da_is_mcbc_get_5018(): API to check if pkt is MCBC 656 * from rx_msdu_end TLV 657 * 658 * @ buf: pointer to the start of RX PKT TLV headers 659 * Return: da_is_mcbc 660 */ 661 static uint8_t 662 hal_rx_msdu_end_da_is_mcbc_get_5018(uint8_t *buf) 663 { 664 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 665 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 666 667 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 668 } 669 670 /** 671 * hal_rx_msdu_end_sa_is_valid_get_5018(): API to get_5018 the 672 * sa_is_valid bit from rx_msdu_end TLV 673 * 674 * @ buf: pointer to the start of RX PKT TLV headers 675 * Return: sa_is_valid bit 676 */ 677 static uint8_t 678 hal_rx_msdu_end_sa_is_valid_get_5018(uint8_t *buf) 679 { 680 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 681 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 682 uint8_t sa_is_valid; 683 684 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 685 686 return sa_is_valid; 687 } 688 689 /** 690 * hal_rx_msdu_end_sa_idx_get_5018(): API to get_5018 the 691 * sa_idx from rx_msdu_end TLV 692 * 693 * @ buf: pointer to the start of RX PKT TLV headers 694 * Return: sa_idx (SA AST index) 695 */ 696 static uint16_t hal_rx_msdu_end_sa_idx_get_5018(uint8_t *buf) 697 { 698 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 699 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 700 uint16_t sa_idx; 701 702 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 703 704 return sa_idx; 705 } 706 707 /** 708 * hal_rx_desc_is_first_msdu_5018() - Check if first msdu 709 * 710 * @hal_soc_hdl: hal_soc handle 711 * @hw_desc_addr: hardware descriptor address 712 * 713 * Return: 0 - success/ non-zero failure 714 */ 715 static uint32_t hal_rx_desc_is_first_msdu_5018(void *hw_desc_addr) 716 { 717 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 718 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 719 720 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 721 } 722 723 /** 724 * hal_rx_msdu_end_l3_hdr_padding_get_5018(): API to get_5018 the 725 * l3_header padding from rx_msdu_end TLV 726 * 727 * @ buf: pointer to the start of RX PKT TLV headers 728 * Return: number of l3 header padding bytes 729 */ 730 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_5018(uint8_t *buf) 731 { 732 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 733 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 734 uint32_t l3_header_padding; 735 736 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 737 738 return l3_header_padding; 739 } 740 741 /** 742 * @ hal_rx_encryption_info_valid_5018: Returns encryption type. 743 * 744 * @ buf: rx_tlv_hdr of the received packet 745 * @ Return: encryption type 746 */ 747 inline uint32_t hal_rx_encryption_info_valid_5018(uint8_t *buf) 748 { 749 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 750 struct rx_mpdu_start *mpdu_start = 751 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 752 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 753 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 754 755 return encryption_info; 756 } 757 758 /* 759 * @ hal_rx_print_pn_5018: Prints the PN of rx packet. 760 * 761 * @ buf: rx_tlv_hdr of the received packet 762 * @ Return: void 763 */ 764 static void hal_rx_print_pn_5018(uint8_t *buf) 765 { 766 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 767 struct rx_mpdu_start *mpdu_start = 768 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 769 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 770 771 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 772 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 773 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 774 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 775 776 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 777 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 778 } 779 780 /** 781 * hal_rx_msdu_end_first_msdu_get_5018: API to get first msdu status 782 * from rx_msdu_end TLV 783 * 784 * @ buf: pointer to the start of RX PKT TLV headers 785 * Return: first_msdu 786 */ 787 static uint8_t hal_rx_msdu_end_first_msdu_get_5018(uint8_t *buf) 788 { 789 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 790 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 791 uint8_t first_msdu; 792 793 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 794 795 return first_msdu; 796 } 797 798 /** 799 * hal_rx_msdu_end_da_is_valid_get_5018: API to check if da is valid 800 * from rx_msdu_end TLV 801 * 802 * @ buf: pointer to the start of RX PKT TLV headers 803 * Return: da_is_valid 804 */ 805 static uint8_t hal_rx_msdu_end_da_is_valid_get_5018(uint8_t *buf) 806 { 807 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 808 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 809 uint8_t da_is_valid; 810 811 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 812 813 return da_is_valid; 814 } 815 816 /** 817 * hal_rx_msdu_end_last_msdu_get_5018: API to get last msdu status 818 * from rx_msdu_end TLV 819 * 820 * @ buf: pointer to the start of RX PKT TLV headers 821 * Return: last_msdu 822 */ 823 static uint8_t hal_rx_msdu_end_last_msdu_get_5018(uint8_t *buf) 824 { 825 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 826 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 827 uint8_t last_msdu; 828 829 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 830 831 return last_msdu; 832 } 833 834 /* 835 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 836 * 837 * @nbuf: Network buffer 838 * Returns: value of mpdu 4th address valid field 839 */ 840 inline bool hal_rx_get_mpdu_mac_ad4_valid_5018(uint8_t *buf) 841 { 842 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 843 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 844 bool ad4_valid = 0; 845 846 ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info); 847 848 return ad4_valid; 849 } 850 851 /** 852 * hal_rx_mpdu_start_sw_peer_id_get_5018: Retrieve sw peer_id 853 * @buf: network buffer 854 * 855 * Return: sw peer_id 856 */ 857 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_5018(uint8_t *buf) 858 { 859 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 860 struct rx_mpdu_start *mpdu_start = 861 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 862 863 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 864 &mpdu_start->rx_mpdu_info_details); 865 } 866 867 /* 868 * hal_rx_mpdu_get_to_ds_5018(): API to get the tods info 869 * from rx_mpdu_start 870 * 871 * @buf: pointer to the start of RX PKT TLV header 872 * Return: uint32_t(to_ds) 873 */ 874 static uint32_t hal_rx_mpdu_get_to_ds_5018(uint8_t *buf) 875 { 876 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 877 struct rx_mpdu_start *mpdu_start = 878 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 879 880 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 881 882 return HAL_RX_MPDU_GET_TODS(mpdu_info); 883 } 884 885 /* 886 * hal_rx_mpdu_get_fr_ds_5018(): API to get the from ds info 887 * from rx_mpdu_start 888 * 889 * @buf: pointer to the start of RX PKT TLV header 890 * Return: uint32_t(fr_ds) 891 */ 892 static uint32_t hal_rx_mpdu_get_fr_ds_5018(uint8_t *buf) 893 { 894 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 895 struct rx_mpdu_start *mpdu_start = 896 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 897 898 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 899 900 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 901 } 902 903 /* 904 * hal_rx_get_mpdu_frame_control_valid_5018(): Retrieves mpdu 905 * frame control valid 906 * 907 * @nbuf: Network buffer 908 * Returns: value of frame control valid field 909 */ 910 static uint8_t hal_rx_get_mpdu_frame_control_valid_5018(uint8_t *buf) 911 { 912 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 913 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 914 915 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 916 } 917 918 /** 919 * hal_rx_get_mpdu_frame_control_field_5018(): Function to 920 * retrieve frame control field 921 * 922 * @nbuf: Network buffer 923 * Returns: value of frame control field 924 */ 925 static uint16_t hal_rx_get_mpdu_frame_control_field_5018(uint8_t *buf) 926 { 927 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 928 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 929 uint16_t frame_ctrl = 0; 930 931 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 932 933 return frame_ctrl; 934 } 935 936 /* 937 * hal_rx_mpdu_get_addr1_5018(): API to check get address1 of the mpdu 938 * 939 * @buf: pointer to the start of RX PKT TLV headera 940 * @mac_addr: pointer to mac address 941 * Return: success/failure 942 */ 943 static QDF_STATUS hal_rx_mpdu_get_addr1_5018(uint8_t *buf, 944 uint8_t *mac_addr) 945 { 946 struct __attribute__((__packed__)) hal_addr1 { 947 uint32_t ad1_31_0; 948 uint16_t ad1_47_32; 949 }; 950 951 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 952 struct rx_mpdu_start *mpdu_start = 953 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 954 955 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 956 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 957 uint32_t mac_addr_ad1_valid; 958 959 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 960 961 if (mac_addr_ad1_valid) { 962 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 963 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 964 return QDF_STATUS_SUCCESS; 965 } 966 967 return QDF_STATUS_E_FAILURE; 968 } 969 970 /* 971 * hal_rx_mpdu_get_addr2_5018(): API to check get address2 of the mpdu 972 * in the packet 973 * 974 * @buf: pointer to the start of RX PKT TLV header 975 * @mac_addr: pointer to mac address 976 * Return: success/failure 977 */ 978 static QDF_STATUS hal_rx_mpdu_get_addr2_5018(uint8_t *buf, uint8_t *mac_addr) 979 { 980 struct __attribute__((__packed__)) hal_addr2 { 981 uint16_t ad2_15_0; 982 uint32_t ad2_47_16; 983 }; 984 985 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 986 struct rx_mpdu_start *mpdu_start = 987 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 988 989 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 990 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 991 uint32_t mac_addr_ad2_valid; 992 993 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 994 995 if (mac_addr_ad2_valid) { 996 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 997 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 998 return QDF_STATUS_SUCCESS; 999 } 1000 1001 return QDF_STATUS_E_FAILURE; 1002 } 1003 1004 /* 1005 * hal_rx_mpdu_get_addr3_5018(): API to get address3 of the mpdu 1006 * in the packet 1007 * 1008 * @buf: pointer to the start of RX PKT TLV header 1009 * @mac_addr: pointer to mac address 1010 * Return: success/failure 1011 */ 1012 static QDF_STATUS hal_rx_mpdu_get_addr3_5018(uint8_t *buf, uint8_t *mac_addr) 1013 { 1014 struct __attribute__((__packed__)) hal_addr3 { 1015 uint32_t ad3_31_0; 1016 uint16_t ad3_47_32; 1017 }; 1018 1019 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1020 struct rx_mpdu_start *mpdu_start = 1021 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1022 1023 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1024 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 1025 uint32_t mac_addr_ad3_valid; 1026 1027 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 1028 1029 if (mac_addr_ad3_valid) { 1030 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 1031 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 1032 return QDF_STATUS_SUCCESS; 1033 } 1034 1035 return QDF_STATUS_E_FAILURE; 1036 } 1037 1038 /* 1039 * hal_rx_mpdu_get_addr4_5018(): API to get address4 of the mpdu 1040 * in the packet 1041 * 1042 * @buf: pointer to the start of RX PKT TLV header 1043 * @mac_addr: pointer to mac address 1044 * Return: success/failure 1045 */ 1046 static QDF_STATUS hal_rx_mpdu_get_addr4_5018(uint8_t *buf, uint8_t *mac_addr) 1047 { 1048 struct __attribute__((__packed__)) hal_addr4 { 1049 uint32_t ad4_31_0; 1050 uint16_t ad4_47_32; 1051 }; 1052 1053 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1054 struct rx_mpdu_start *mpdu_start = 1055 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1056 1057 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1058 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 1059 uint32_t mac_addr_ad4_valid; 1060 1061 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 1062 1063 if (mac_addr_ad4_valid) { 1064 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 1065 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 1066 return QDF_STATUS_SUCCESS; 1067 } 1068 1069 return QDF_STATUS_E_FAILURE; 1070 } 1071 1072 /* 1073 * hal_rx_get_mpdu_sequence_control_valid_5018(): Get mpdu 1074 * sequence control valid 1075 * 1076 * @nbuf: Network buffer 1077 * Returns: value of sequence control valid field 1078 */ 1079 static uint8_t hal_rx_get_mpdu_sequence_control_valid_5018(uint8_t *buf) 1080 { 1081 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1082 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1083 1084 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 1085 } 1086 1087 /** 1088 * hal_rx_is_unicast_5018: check packet is unicast frame or not. 1089 * 1090 * @ buf: pointer to rx pkt TLV. 1091 * 1092 * Return: true on unicast. 1093 */ 1094 static bool hal_rx_is_unicast_5018(uint8_t *buf) 1095 { 1096 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1097 struct rx_mpdu_start *mpdu_start = 1098 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1099 uint32_t grp_id; 1100 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1101 1102 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1103 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 1104 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 1105 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 1106 1107 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 1108 } 1109 1110 /** 1111 * hal_rx_tid_get_5018: get tid based on qos control valid. 1112 * @hal_soc_hdl: hal soc handle 1113 * @buf: pointer to rx pkt TLV. 1114 * 1115 * Return: tid 1116 */ 1117 static uint32_t hal_rx_tid_get_5018(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1118 { 1119 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1120 struct rx_mpdu_start *mpdu_start = 1121 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1122 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1123 uint8_t qos_control_valid = 1124 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1125 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 1126 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 1127 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 1128 1129 if (qos_control_valid) 1130 return hal_rx_mpdu_start_tid_get_5018(buf); 1131 1132 return HAL_RX_NON_QOS_TID; 1133 } 1134 1135 /** 1136 * hal_rx_hw_desc_get_ppduid_get_5018(): retrieve ppdu id 1137 * @rx_tlv_hdr: rx tlv header 1138 * @rxdma_dst_ring_desc: rxdma HW descriptor 1139 * 1140 * Return: ppdu id 1141 */ 1142 static uint32_t hal_rx_hw_desc_get_ppduid_get_5018(void *rx_tlv_hdr, 1143 void *rxdma_dst_ring_desc) 1144 { 1145 struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc; 1146 1147 return HAL_RX_REO_ENT_PHY_PPDU_ID_GET(reo_ent); 1148 } 1149 1150 /** 1151 * hal_reo_status_get_header_5018 - Process reo desc info 1152 * @ring_desc: REO status ring descriptor 1153 * @b - tlv type info 1154 * @h1 - Pointer to hal_reo_status_header where info to be stored 1155 * 1156 * Return - none. 1157 * 1158 */ 1159 static void hal_reo_status_get_header_5018(hal_ring_desc_t ring_desc, int b, 1160 void *h1) 1161 { 1162 uint32_t *d = (uint32_t *)ring_desc; 1163 uint32_t val1 = 0; 1164 struct hal_reo_status_header *h = 1165 (struct hal_reo_status_header *)h1; 1166 1167 /* Offsets of descriptor fields defined in HW headers start 1168 * from the field after TLV header 1169 */ 1170 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 1171 1172 switch (b) { 1173 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1174 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1175 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1176 break; 1177 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1178 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1179 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1180 break; 1181 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1182 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1183 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1184 break; 1185 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1186 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1187 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1188 break; 1189 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1190 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1191 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1192 break; 1193 case HAL_REO_DESC_THRES_STATUS_TLV: 1194 val1 = 1195 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1196 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1197 break; 1198 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1199 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1200 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1201 break; 1202 default: 1203 qdf_nofl_err("ERROR: Unknown tlv\n"); 1204 break; 1205 } 1206 h->cmd_num = 1207 HAL_GET_FIELD( 1208 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1209 val1); 1210 h->exec_time = 1211 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1212 CMD_EXECUTION_TIME, val1); 1213 h->status = 1214 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1215 REO_CMD_EXECUTION_STATUS, val1); 1216 switch (b) { 1217 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1218 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1219 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1220 break; 1221 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1222 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1223 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1224 break; 1225 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1226 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1227 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1228 break; 1229 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1230 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1231 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1232 break; 1233 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1234 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1235 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1236 break; 1237 case HAL_REO_DESC_THRES_STATUS_TLV: 1238 val1 = 1239 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1240 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1241 break; 1242 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1243 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1244 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1245 break; 1246 default: 1247 qdf_nofl_err("ERROR: Unknown tlv\n"); 1248 break; 1249 } 1250 h->tstamp = 1251 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1252 } 1253 1254 /** 1255 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(): 1256 * Retrieve qos control valid bit from the tlv. 1257 * @buf: pointer to rx pkt TLV. 1258 * 1259 * Return: qos control value. 1260 */ 1261 static inline uint32_t 1262 hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(uint8_t *buf) 1263 { 1264 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1265 struct rx_mpdu_start *mpdu_start = 1266 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1267 1268 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1269 &mpdu_start->rx_mpdu_info_details); 1270 } 1271 1272 /** 1273 * hal_rx_msdu_end_sa_sw_peer_id_get_5018(): API to get the 1274 * sa_sw_peer_id from rx_msdu_end TLV 1275 * @buf: pointer to the start of RX PKT TLV headers 1276 * 1277 * Return: sa_sw_peer_id index 1278 */ 1279 static inline uint32_t 1280 hal_rx_msdu_end_sa_sw_peer_id_get_5018(uint8_t *buf) 1281 { 1282 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1283 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1284 1285 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1286 } 1287 1288 /** 1289 * hal_tx_desc_set_mesh_en_5018 - Set mesh_enable flag in Tx descriptor 1290 * @desc: Handle to Tx Descriptor 1291 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1292 * enabling the interpretation of the 'Mesh Control Present' bit 1293 * (bit 8) of QoS Control (otherwise this bit is ignored), 1294 * For native WiFi frames, this indicates that a 'Mesh Control' field 1295 * is present between the header and the LLC. 1296 * 1297 * Return: void 1298 */ 1299 static inline 1300 void hal_tx_desc_set_mesh_en_5018(void *desc, uint8_t en) 1301 { 1302 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1303 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1304 } 1305 1306 static 1307 void *hal_rx_msdu0_buffer_addr_lsb_5018(void *link_desc_va) 1308 { 1309 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1310 } 1311 1312 static 1313 void *hal_rx_msdu_desc_info_ptr_get_5018(void *msdu0) 1314 { 1315 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1316 } 1317 1318 static 1319 void *hal_ent_mpdu_desc_info_5018(void *ent_ring_desc) 1320 { 1321 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1322 } 1323 1324 static 1325 void *hal_dst_mpdu_desc_info_5018(void *dst_ring_desc) 1326 { 1327 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1328 } 1329 1330 static 1331 uint8_t hal_rx_get_fc_valid_5018(uint8_t *buf) 1332 { 1333 return HAL_RX_GET_FC_VALID(buf); 1334 } 1335 1336 static uint8_t hal_rx_get_to_ds_flag_5018(uint8_t *buf) 1337 { 1338 return HAL_RX_GET_TO_DS_FLAG(buf); 1339 } 1340 1341 static uint8_t hal_rx_get_mac_addr2_valid_5018(uint8_t *buf) 1342 { 1343 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1344 } 1345 1346 static uint8_t hal_rx_get_filter_category_5018(uint8_t *buf) 1347 { 1348 return HAL_RX_GET_FILTER_CATEGORY(buf); 1349 } 1350 1351 static uint32_t 1352 hal_rx_get_ppdu_id_5018(uint8_t *buf) 1353 { 1354 struct rx_mpdu_info *rx_mpdu_info; 1355 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 1356 1357 rx_mpdu_info = 1358 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1359 1360 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 1361 } 1362 1363 /** 1364 * hal_reo_config_5018(): Set reo config parameters 1365 * @soc: hal soc handle 1366 * @reg_val: value to be set 1367 * @reo_params: reo parameters 1368 * 1369 * Return: void 1370 */ 1371 static void 1372 hal_reo_config_5018(struct hal_soc *soc, 1373 uint32_t reg_val, 1374 struct hal_reo_params *reo_params) 1375 { 1376 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1377 } 1378 1379 /** 1380 * hal_rx_msdu_desc_info_get_ptr_5018() - Get msdu desc info ptr 1381 * @msdu_details_ptr - Pointer to msdu_details_ptr 1382 * 1383 * Return - Pointer to rx_msdu_desc_info structure. 1384 * 1385 */ 1386 static void *hal_rx_msdu_desc_info_get_ptr_5018(void *msdu_details_ptr) 1387 { 1388 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1389 } 1390 1391 /** 1392 * hal_rx_link_desc_msdu0_ptr_5018 - Get pointer to rx_msdu details 1393 * @link_desc - Pointer to link desc 1394 * 1395 * Return - Pointer to rx_msdu_details structure 1396 * 1397 */ 1398 static void *hal_rx_link_desc_msdu0_ptr_5018(void *link_desc) 1399 { 1400 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1401 } 1402 1403 /** 1404 * hal_rx_msdu_flow_idx_get_5018: API to get flow index 1405 * from rx_msdu_end TLV 1406 * @buf: pointer to the start of RX PKT TLV headers 1407 * 1408 * Return: flow index value from MSDU END TLV 1409 */ 1410 static inline uint32_t hal_rx_msdu_flow_idx_get_5018(uint8_t *buf) 1411 { 1412 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1413 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1414 1415 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1416 } 1417 1418 /** 1419 * hal_rx_msdu_flow_idx_invalid_5018: API to get flow index invalid 1420 * from rx_msdu_end TLV 1421 * @buf: pointer to the start of RX PKT TLV headers 1422 * 1423 * Return: flow index invalid value from MSDU END TLV 1424 */ 1425 static bool hal_rx_msdu_flow_idx_invalid_5018(uint8_t *buf) 1426 { 1427 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1428 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1429 1430 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1431 } 1432 1433 /** 1434 * hal_rx_msdu_flow_idx_timeout_5018: API to get flow index timeout 1435 * from rx_msdu_end TLV 1436 * @buf: pointer to the start of RX PKT TLV headers 1437 * 1438 * Return: flow index timeout value from MSDU END TLV 1439 */ 1440 static bool hal_rx_msdu_flow_idx_timeout_5018(uint8_t *buf) 1441 { 1442 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1443 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1444 1445 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1446 } 1447 1448 /** 1449 * hal_rx_msdu_fse_metadata_get_5018: API to get FSE metadata 1450 * from rx_msdu_end TLV 1451 * @buf: pointer to the start of RX PKT TLV headers 1452 * 1453 * Return: fse metadata value from MSDU END TLV 1454 */ 1455 static uint32_t hal_rx_msdu_fse_metadata_get_5018(uint8_t *buf) 1456 { 1457 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1458 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1459 1460 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1461 } 1462 1463 /** 1464 * hal_rx_msdu_cce_metadata_get_5018: API to get CCE metadata 1465 * from rx_msdu_end TLV 1466 * @buf: pointer to the start of RX PKT TLV headers 1467 * 1468 * Return: cce_metadata 1469 */ 1470 static uint16_t 1471 hal_rx_msdu_cce_metadata_get_5018(uint8_t *buf) 1472 { 1473 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1474 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1475 1476 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1477 } 1478 1479 /** 1480 * hal_rx_msdu_get_flow_params_5018: API to get flow index, flow index invalid 1481 * and flow index timeout from rx_msdu_end TLV 1482 * @buf: pointer to the start of RX PKT TLV headers 1483 * @flow_invalid: pointer to return value of flow_idx_valid 1484 * @flow_timeout: pointer to return value of flow_idx_timeout 1485 * @flow_index: pointer to return value of flow_idx 1486 * 1487 * Return: none 1488 */ 1489 static inline void 1490 hal_rx_msdu_get_flow_params_5018(uint8_t *buf, 1491 bool *flow_invalid, 1492 bool *flow_timeout, 1493 uint32_t *flow_index) 1494 { 1495 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1496 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1497 1498 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1499 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1500 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1501 } 1502 1503 /** 1504 * hal_rx_tlv_get_tcp_chksum_5018() - API to get tcp checksum 1505 * @buf: rx_tlv_hdr 1506 * 1507 * Return: tcp checksum 1508 */ 1509 static uint16_t 1510 hal_rx_tlv_get_tcp_chksum_5018(uint8_t *buf) 1511 { 1512 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1513 } 1514 1515 /** 1516 * hal_rx_get_rx_sequence_5018(): Function to retrieve rx sequence number 1517 * 1518 * @nbuf: Network buffer 1519 * Returns: rx sequence number 1520 */ 1521 static 1522 uint16_t hal_rx_get_rx_sequence_5018(uint8_t *buf) 1523 { 1524 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1525 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1526 1527 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1528 } 1529 1530 /** 1531 * hal_get_window_address_5018(): Function to get hp/tp address 1532 * @hal_soc: Pointer to hal_soc 1533 * @addr: address offset of register 1534 * 1535 * Return: modified address offset of register 1536 */ 1537 static inline qdf_iomem_t hal_get_window_address_5018(struct hal_soc *hal_soc, 1538 qdf_iomem_t addr) 1539 { 1540 uint32_t offset = addr - hal_soc->dev_base_addr; 1541 qdf_iomem_t new_offset; 1542 1543 /* 1544 * Check if offset lies within CE register range(0x08400000) 1545 * or UMAC/DP register range (0x00A00000). 1546 * If offset lies within CE register range, map it 1547 * into CE region. 1548 */ 1549 if (offset & HOST_CE_MASK_VALUE) { 1550 offset = offset - WFSS_CE_REG_BASE; 1551 new_offset = (hal_soc->dev_base_addr_ce + offset); 1552 1553 return new_offset; 1554 } else { 1555 /* 1556 * If offset lies within DP register range, 1557 * return the address as such 1558 */ 1559 return addr; 1560 } 1561 } 1562 1563 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1564 { 1565 /* Write value into window configuration register */ 1566 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1567 WINDOW_CONFIGURATION_VALUE_5018); 1568 } 1569 1570 /** 1571 * hal_rx_msdu_packet_metadata_get_5018(): API to get the 1572 * msdu information from rx_msdu_end TLV 1573 * 1574 * @ buf: pointer to the start of RX PKT TLV headers 1575 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 1576 */ 1577 static void 1578 hal_rx_msdu_packet_metadata_get_5018(uint8_t *buf, 1579 void *msdu_pkt_metadata) 1580 { 1581 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1582 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1583 struct hal_rx_msdu_metadata *msdu_metadata = 1584 (struct hal_rx_msdu_metadata *)msdu_pkt_metadata; 1585 1586 msdu_metadata->l3_hdr_pad = 1587 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1588 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1589 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 1590 msdu_metadata->sa_sw_peer_id = 1591 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1592 } 1593 1594 /** 1595 * hal_rx_flow_setup_fse_5018() - Setup a flow search entry in HW FST 1596 * @fst: Pointer to the Rx Flow Search Table 1597 * @table_offset: offset into the table where the flow is to be setup 1598 * @flow: Flow Parameters 1599 * 1600 * Return: Success/Failure 1601 */ 1602 static void * 1603 hal_rx_flow_setup_fse_5018(uint8_t *rx_fst, uint32_t table_offset, 1604 uint8_t *rx_flow) 1605 { 1606 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1607 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1608 uint8_t *fse; 1609 bool fse_valid; 1610 1611 if (table_offset >= fst->max_entries) { 1612 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1613 "HAL FSE table offset %u exceeds max entries %u", 1614 table_offset, fst->max_entries); 1615 return NULL; 1616 } 1617 1618 fse = (uint8_t *)fst->base_vaddr + 1619 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1620 1621 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1622 1623 if (fse_valid) { 1624 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1625 "HAL FSE %pK already valid", fse); 1626 return NULL; 1627 } 1628 1629 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1630 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1631 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1632 1633 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1634 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1635 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1636 1637 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1638 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1639 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1640 1641 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1642 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1643 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1644 1645 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1646 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1647 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1648 1649 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1650 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1651 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1652 1653 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1654 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1655 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1656 1657 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1658 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1659 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1660 1661 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1662 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1663 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1664 (flow->tuple_info.dest_port)); 1665 1666 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1667 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1668 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1669 (flow->tuple_info.src_port)); 1670 1671 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1672 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1673 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1674 flow->tuple_info.l4_protocol); 1675 1676 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1677 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1678 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1679 flow->reo_destination_handler); 1680 1681 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1682 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1683 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1684 1685 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1686 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1687 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1688 flow->fse_metadata); 1689 1690 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1691 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1692 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1693 REO_DESTINATION_INDICATION, 1694 flow->reo_destination_indication); 1695 1696 /* Reset all the other fields in FSE */ 1697 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1698 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1699 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1700 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1701 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1702 1703 return fse; 1704 } 1705 1706 static void hal_hw_txrx_ops_attach_qca5018(struct hal_soc *hal_soc) 1707 { 1708 /* init and setup */ 1709 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1710 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1711 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1712 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1713 hal_soc->ops->hal_get_window_address = hal_get_window_address_5018; 1714 1715 /* tx */ 1716 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1717 hal_tx_desc_set_dscp_tid_table_id_5018; 1718 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5018; 1719 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5018; 1720 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_5018; 1721 hal_soc->ops->hal_tx_desc_set_buf_addr = 1722 hal_tx_desc_set_buf_addr_generic_li; 1723 hal_soc->ops->hal_tx_desc_set_search_type = 1724 hal_tx_desc_set_search_type_generic_li; 1725 hal_soc->ops->hal_tx_desc_set_search_index = 1726 hal_tx_desc_set_search_index_generic_li; 1727 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1728 hal_tx_desc_set_cache_set_num_generic_li; 1729 hal_soc->ops->hal_tx_comp_get_status = 1730 hal_tx_comp_get_status_generic_li; 1731 hal_soc->ops->hal_tx_comp_get_release_reason = 1732 hal_tx_comp_get_release_reason_generic_li; 1733 hal_soc->ops->hal_get_wbm_internal_error = 1734 hal_get_wbm_internal_error_generic_li; 1735 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_5018; 1736 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1737 hal_tx_init_cmd_credit_ring_5018; 1738 1739 /* rx */ 1740 hal_soc->ops->hal_rx_msdu_start_nss_get = 1741 hal_rx_msdu_start_nss_get_5018; 1742 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1743 hal_rx_mon_hw_desc_get_mpdu_status_5018; 1744 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5018; 1745 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1746 hal_rx_proc_phyrx_other_receive_info_tlv_5018; 1747 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1748 hal_rx_dump_msdu_start_tlv_5018; 1749 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5018; 1750 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5018; 1751 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1752 hal_rx_mpdu_start_tid_get_5018; 1753 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1754 hal_rx_msdu_start_reception_type_get_5018; 1755 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1756 hal_rx_msdu_end_da_idx_get_5018; 1757 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1758 hal_rx_msdu_desc_info_get_ptr_5018; 1759 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1760 hal_rx_link_desc_msdu0_ptr_5018; 1761 hal_soc->ops->hal_reo_status_get_header = 1762 hal_reo_status_get_header_5018; 1763 hal_soc->ops->hal_rx_status_get_tlv_info = 1764 hal_rx_status_get_tlv_info_generic_li; 1765 hal_soc->ops->hal_rx_wbm_err_info_get = 1766 hal_rx_wbm_err_info_get_generic_li; 1767 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1768 hal_rx_dump_mpdu_start_tlv_generic_li; 1769 1770 hal_soc->ops->hal_tx_set_pcp_tid_map = 1771 hal_tx_set_pcp_tid_map_generic_li; 1772 hal_soc->ops->hal_tx_update_pcp_tid_map = 1773 hal_tx_update_pcp_tid_generic_li; 1774 hal_soc->ops->hal_tx_set_tidmap_prty = 1775 hal_tx_update_tidmap_prty_generic_li; 1776 hal_soc->ops->hal_rx_get_rx_fragment_number = 1777 hal_rx_get_rx_fragment_number_5018; 1778 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1779 hal_rx_msdu_end_da_is_mcbc_get_5018; 1780 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1781 hal_rx_msdu_end_sa_is_valid_get_5018; 1782 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1783 hal_rx_msdu_end_sa_idx_get_5018; 1784 hal_soc->ops->hal_rx_desc_is_first_msdu = 1785 hal_rx_desc_is_first_msdu_5018; 1786 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1787 hal_rx_msdu_end_l3_hdr_padding_get_5018; 1788 hal_soc->ops->hal_rx_encryption_info_valid = 1789 hal_rx_encryption_info_valid_5018; 1790 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_5018; 1791 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1792 hal_rx_msdu_end_first_msdu_get_5018; 1793 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1794 hal_rx_msdu_end_da_is_valid_get_5018; 1795 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1796 hal_rx_msdu_end_last_msdu_get_5018; 1797 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1798 hal_rx_get_mpdu_mac_ad4_valid_5018; 1799 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1800 hal_rx_mpdu_start_sw_peer_id_get_5018; 1801 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1802 hal_rx_mpdu_peer_meta_data_get_li; 1803 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_5018; 1804 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_5018; 1805 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1806 hal_rx_get_mpdu_frame_control_valid_5018; 1807 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1808 hal_rx_get_mpdu_frame_control_field_5018; 1809 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_5018; 1810 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_5018; 1811 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_5018; 1812 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_5018; 1813 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1814 hal_rx_get_mpdu_sequence_control_valid_5018; 1815 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_5018; 1816 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_5018; 1817 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1818 hal_rx_hw_desc_get_ppduid_get_5018; 1819 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1820 hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018; 1821 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1822 hal_rx_msdu_end_sa_sw_peer_id_get_5018; 1823 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1824 hal_rx_msdu0_buffer_addr_lsb_5018; 1825 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1826 hal_rx_msdu_desc_info_ptr_get_5018; 1827 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5018; 1828 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5018; 1829 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_5018; 1830 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_5018; 1831 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1832 hal_rx_get_mac_addr2_valid_5018; 1833 hal_soc->ops->hal_rx_get_filter_category = 1834 hal_rx_get_filter_category_5018; 1835 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_5018; 1836 hal_soc->ops->hal_reo_config = hal_reo_config_5018; 1837 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_5018; 1838 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1839 hal_rx_msdu_flow_idx_invalid_5018; 1840 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1841 hal_rx_msdu_flow_idx_timeout_5018; 1842 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1843 hal_rx_msdu_fse_metadata_get_5018; 1844 hal_soc->ops->hal_rx_msdu_cce_match_get = 1845 hal_rx_msdu_cce_match_get_li; 1846 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1847 hal_rx_msdu_cce_metadata_get_5018; 1848 hal_soc->ops->hal_rx_msdu_get_flow_params = 1849 hal_rx_msdu_get_flow_params_5018; 1850 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1851 hal_rx_tlv_get_tcp_chksum_5018; 1852 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_5018; 1853 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 1854 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5018; 1855 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5018; 1856 #endif 1857 /* rx - msdu fast path info fields */ 1858 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1859 hal_rx_msdu_packet_metadata_get_5018; 1860 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1861 hal_rx_mpdu_start_tlv_tag_valid_5018; 1862 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1863 hal_rx_wbm_err_msdu_continuation_get_5018; 1864 1865 /* rx - TLV struct offsets */ 1866 hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic; 1867 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1868 hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic; 1869 hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic; 1870 hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic; 1871 #ifndef NO_RX_PKT_HDR_TLV 1872 hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic; 1873 #endif 1874 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5018; 1875 hal_soc->ops->hal_rx_flow_get_tuple_info = 1876 hal_rx_flow_get_tuple_info_li; 1877 hal_soc->ops->hal_rx_flow_delete_entry = 1878 hal_rx_flow_delete_entry_li; 1879 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; 1880 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_5018; 1881 hal_soc->ops->hal_setup_link_idle_list = 1882 hal_setup_link_idle_list_generic_li; 1883 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1884 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1885 hal_rx_msdu_start_get_len_5018; 1886 }; 1887 1888 struct hal_hw_srng_config hw_srng_table_5018[] = { 1889 /* TODO: max_rings can populated by querying HW capabilities */ 1890 { /* REO_DST */ 1891 .start_ring_id = HAL_SRNG_REO2SW1, 1892 .max_rings = 4, 1893 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1894 .lmac_ring = FALSE, 1895 .ring_dir = HAL_SRNG_DST_RING, 1896 .reg_start = { 1897 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1898 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1899 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1900 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1901 }, 1902 .reg_size = { 1903 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1904 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1905 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1906 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1907 }, 1908 .max_size = 1909 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1910 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1911 }, 1912 { /* REO_EXCEPTION */ 1913 /* Designating REO2TCL ring as exception ring. This ring is 1914 * similar to other REO2SW rings though it is named as REO2TCL. 1915 * Any of theREO2SW rings can be used as exception ring. 1916 */ 1917 .start_ring_id = HAL_SRNG_REO2TCL, 1918 .max_rings = 1, 1919 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1920 .lmac_ring = FALSE, 1921 .ring_dir = HAL_SRNG_DST_RING, 1922 .reg_start = { 1923 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1924 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1925 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1926 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1927 }, 1928 /* Single ring - provide ring size if multiple rings of this 1929 * type are supported 1930 */ 1931 .reg_size = {}, 1932 .max_size = 1933 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1934 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1935 }, 1936 { /* REO_REINJECT */ 1937 .start_ring_id = HAL_SRNG_SW2REO, 1938 .max_rings = 1, 1939 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1940 .lmac_ring = FALSE, 1941 .ring_dir = HAL_SRNG_SRC_RING, 1942 .reg_start = { 1943 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1944 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1945 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1946 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1947 }, 1948 /* Single ring - provide ring size if multiple rings of this 1949 * type are supported 1950 */ 1951 .reg_size = {}, 1952 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1953 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1954 }, 1955 { /* REO_CMD */ 1956 .start_ring_id = HAL_SRNG_REO_CMD, 1957 .max_rings = 1, 1958 .entry_size = (sizeof(struct tlv_32_hdr) + 1959 sizeof(struct reo_get_queue_stats)) >> 2, 1960 .lmac_ring = FALSE, 1961 .ring_dir = HAL_SRNG_SRC_RING, 1962 .reg_start = { 1963 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1964 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1965 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1966 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1967 }, 1968 /* Single ring - provide ring size if multiple rings of this 1969 * type are supported 1970 */ 1971 .reg_size = {}, 1972 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1973 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1974 }, 1975 { /* REO_STATUS */ 1976 .start_ring_id = HAL_SRNG_REO_STATUS, 1977 .max_rings = 1, 1978 .entry_size = (sizeof(struct tlv_32_hdr) + 1979 sizeof(struct reo_get_queue_stats_status)) >> 2, 1980 .lmac_ring = FALSE, 1981 .ring_dir = HAL_SRNG_DST_RING, 1982 .reg_start = { 1983 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1984 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1985 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1986 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1987 }, 1988 /* Single ring - provide ring size if multiple rings of this 1989 * type are supported 1990 */ 1991 .reg_size = {}, 1992 .max_size = 1993 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1994 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1995 }, 1996 { /* TCL_DATA */ 1997 .start_ring_id = HAL_SRNG_SW2TCL1, 1998 .max_rings = 3, 1999 .entry_size = (sizeof(struct tlv_32_hdr) + 2000 sizeof(struct tcl_data_cmd)) >> 2, 2001 .lmac_ring = FALSE, 2002 .ring_dir = HAL_SRNG_SRC_RING, 2003 .reg_start = { 2004 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2005 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2006 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2007 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2008 }, 2009 .reg_size = { 2010 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2011 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2012 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2013 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2014 }, 2015 .max_size = 2016 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2017 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2018 }, 2019 { /* TCL_CMD */ 2020 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2021 .max_rings = 1, 2022 .entry_size = (sizeof(struct tlv_32_hdr) + 2023 sizeof(struct tcl_data_cmd)) >> 2, 2024 .lmac_ring = FALSE, 2025 .ring_dir = HAL_SRNG_SRC_RING, 2026 .reg_start = { 2027 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2028 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2029 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2030 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2031 }, 2032 /* Single ring - provide ring size if multiple rings of this 2033 * type are supported 2034 */ 2035 .reg_size = {}, 2036 .max_size = 2037 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2038 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2039 }, 2040 { /* TCL_STATUS */ 2041 .start_ring_id = HAL_SRNG_TCL_STATUS, 2042 .max_rings = 1, 2043 .entry_size = (sizeof(struct tlv_32_hdr) + 2044 sizeof(struct tcl_status_ring)) >> 2, 2045 .lmac_ring = FALSE, 2046 .ring_dir = HAL_SRNG_DST_RING, 2047 .reg_start = { 2048 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2049 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2050 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2051 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2052 }, 2053 /* Single ring - provide ring size if multiple rings of this 2054 * type are supported 2055 */ 2056 .reg_size = {}, 2057 .max_size = 2058 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2059 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2060 }, 2061 { /* CE_SRC */ 2062 .start_ring_id = HAL_SRNG_CE_0_SRC, 2063 .max_rings = 12, 2064 .entry_size = sizeof(struct ce_src_desc) >> 2, 2065 .lmac_ring = FALSE, 2066 .ring_dir = HAL_SRNG_SRC_RING, 2067 .reg_start = { 2068 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2069 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2070 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2071 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2072 }, 2073 .reg_size = { 2074 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2075 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2076 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2077 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2078 }, 2079 .max_size = 2080 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2081 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2082 }, 2083 { /* CE_DST */ 2084 .start_ring_id = HAL_SRNG_CE_0_DST, 2085 .max_rings = 12, 2086 .entry_size = 8 >> 2, 2087 /*TODO: entry_size above should actually be 2088 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2089 * of struct ce_dst_desc in HW header files 2090 */ 2091 .lmac_ring = FALSE, 2092 .ring_dir = HAL_SRNG_SRC_RING, 2093 .reg_start = { 2094 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2095 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2096 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2097 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2098 }, 2099 .reg_size = { 2100 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2101 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2102 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2103 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2104 }, 2105 .max_size = 2106 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2107 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2108 }, 2109 { /* CE_DST_STATUS */ 2110 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2111 .max_rings = 12, 2112 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2113 .lmac_ring = FALSE, 2114 .ring_dir = HAL_SRNG_DST_RING, 2115 .reg_start = { 2116 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2117 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2118 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2119 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2120 }, 2121 /* TODO: check destination status ring registers */ 2122 .reg_size = { 2123 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2124 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2125 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2126 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2127 }, 2128 .max_size = 2129 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2130 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2131 }, 2132 { /* WBM_IDLE_LINK */ 2133 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2134 .max_rings = 1, 2135 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2136 .lmac_ring = FALSE, 2137 .ring_dir = HAL_SRNG_SRC_RING, 2138 .reg_start = { 2139 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2140 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2141 }, 2142 /* Single ring - provide ring size if multiple rings of this 2143 * type are supported 2144 */ 2145 .reg_size = {}, 2146 .max_size = 2147 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2148 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2149 }, 2150 { /* SW2WBM_RELEASE */ 2151 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2152 .max_rings = 1, 2153 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2154 .lmac_ring = FALSE, 2155 .ring_dir = HAL_SRNG_SRC_RING, 2156 .reg_start = { 2157 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2158 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2159 }, 2160 /* Single ring - provide ring size if multiple rings of this 2161 * type are supported 2162 */ 2163 .reg_size = {}, 2164 .max_size = 2165 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2166 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2167 }, 2168 { /* WBM2SW_RELEASE */ 2169 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2170 .max_rings = 5, 2171 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2172 .lmac_ring = FALSE, 2173 .ring_dir = HAL_SRNG_DST_RING, 2174 .reg_start = { 2175 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2176 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2177 }, 2178 .reg_size = { 2179 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2180 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2181 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2182 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2183 }, 2184 .max_size = 2185 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2186 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2187 }, 2188 { /* RXDMA_BUF */ 2189 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2190 #ifdef IPA_OFFLOAD 2191 .max_rings = 3, 2192 #else 2193 .max_rings = 2, 2194 #endif 2195 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2196 .lmac_ring = TRUE, 2197 .ring_dir = HAL_SRNG_SRC_RING, 2198 /* reg_start is not set because LMAC rings are not accessed 2199 * from host 2200 */ 2201 .reg_start = {}, 2202 .reg_size = {}, 2203 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2204 }, 2205 { /* RXDMA_DST */ 2206 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2207 .max_rings = 1, 2208 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2209 .lmac_ring = TRUE, 2210 .ring_dir = HAL_SRNG_DST_RING, 2211 /* reg_start is not set because LMAC rings are not accessed 2212 * from host 2213 */ 2214 .reg_start = {}, 2215 .reg_size = {}, 2216 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2217 }, 2218 { /* RXDMA_MONITOR_BUF */ 2219 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2220 .max_rings = 1, 2221 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2222 .lmac_ring = TRUE, 2223 .ring_dir = HAL_SRNG_SRC_RING, 2224 /* reg_start is not set because LMAC rings are not accessed 2225 * from host 2226 */ 2227 .reg_start = {}, 2228 .reg_size = {}, 2229 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2230 }, 2231 { /* RXDMA_MONITOR_STATUS */ 2232 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2233 .max_rings = 1, 2234 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2235 .lmac_ring = TRUE, 2236 .ring_dir = HAL_SRNG_SRC_RING, 2237 /* reg_start is not set because LMAC rings are not accessed 2238 * from host 2239 */ 2240 .reg_start = {}, 2241 .reg_size = {}, 2242 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2243 }, 2244 { /* RXDMA_MONITOR_DST */ 2245 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2246 .max_rings = 1, 2247 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2248 .lmac_ring = TRUE, 2249 .ring_dir = HAL_SRNG_DST_RING, 2250 /* reg_start is not set because LMAC rings are not accessed 2251 * from host 2252 */ 2253 .reg_start = {}, 2254 .reg_size = {}, 2255 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2256 }, 2257 { /* RXDMA_MONITOR_DESC */ 2258 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2259 .max_rings = 1, 2260 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2261 .lmac_ring = TRUE, 2262 .ring_dir = HAL_SRNG_SRC_RING, 2263 /* reg_start is not set because LMAC rings are not accessed 2264 * from host 2265 */ 2266 .reg_start = {}, 2267 .reg_size = {}, 2268 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2269 }, 2270 { /* DIR_BUF_RX_DMA_SRC */ 2271 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2272 /* one ring for spectral and one ring for cfr */ 2273 .max_rings = 2, 2274 .entry_size = 2, 2275 .lmac_ring = TRUE, 2276 .ring_dir = HAL_SRNG_SRC_RING, 2277 /* reg_start is not set because LMAC rings are not accessed 2278 * from host 2279 */ 2280 .reg_start = {}, 2281 .reg_size = {}, 2282 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2283 }, 2284 #ifdef WLAN_FEATURE_CIF_CFR 2285 { /* WIFI_POS_SRC */ 2286 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2287 .max_rings = 1, 2288 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2289 .lmac_ring = TRUE, 2290 .ring_dir = HAL_SRNG_SRC_RING, 2291 /* reg_start is not set because LMAC rings are not accessed 2292 * from host 2293 */ 2294 .reg_start = {}, 2295 .reg_size = {}, 2296 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2297 }, 2298 #endif 2299 { /* REO2PPE */ 0}, 2300 { /* PPE2TCL */ 0}, 2301 { /* PPE_RELEASE */ 0}, 2302 { /* TX_MONITOR_BUF */ 0}, 2303 { /* TX_MONITOR_DST */ 0}, 2304 { /* SW2RXDMA_NEW */ 0}, 2305 }; 2306 2307 /** 2308 * hal_qca5018_attach()- Attach 5018 target specific hal_soc ops, 2309 * offset and srng table 2310 * Return: void 2311 */ 2312 void hal_qca5018_attach(struct hal_soc *hal_soc) 2313 { 2314 hal_soc->hw_srng_table = hw_srng_table_5018; 2315 2316 hal_srng_hw_reg_offset_init_generic(hal_soc); 2317 hal_hw_txrx_default_ops_attach_li(hal_soc); 2318 hal_hw_txrx_ops_attach_qca5018(hal_soc); 2319 } 2320