1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 #include "hal_flow.h" 25 #include "rx_flow_search_entry.h" 26 #include "hal_rx_flow_info.h" 27 28 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 29 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 30 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 31 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 33 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 34 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 35 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 36 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 37 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 38 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 39 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 40 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 41 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 42 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 43 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 44 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 45 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 52 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 53 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 54 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 55 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 56 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 57 RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 58 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 59 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 60 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 61 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 62 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 64 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 65 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 66 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 67 STATUS_HEADER_REO_STATUS_NUMBER 68 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 69 STATUS_HEADER_TIMESTAMP 70 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 71 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 72 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 73 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 74 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 75 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 76 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 77 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 78 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 79 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 80 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 81 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 82 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 83 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 84 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 85 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 86 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 87 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 88 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 89 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 90 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 91 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 92 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 93 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 94 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 95 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 96 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 97 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 98 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 99 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 100 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 101 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 103 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 104 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 105 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 106 107 #define CE_WINDOW_ADDRESS_5018 \ 108 ((WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 109 110 #define UMAC_WINDOW_ADDRESS_5018 \ 111 ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 112 113 #define WINDOW_CONFIGURATION_VALUE_5018 \ 114 ((CE_WINDOW_ADDRESS_5018 << 6) |\ 115 (UMAC_WINDOW_ADDRESS_5018 << 12) | \ 116 WINDOW_ENABLE_BIT) 117 118 #define HOST_CE_MASK_VALUE 0xFF000000 119 120 #include <hal_5018_tx.h> 121 #include <hal_5018_rx.h> 122 #include <hal_generic_api.h> 123 #include <hal_wbm.h> 124 125 /** 126 * hal_rx_msdu_start_nss_get_5018(): API to get the NSS 127 * Interval from rx_msdu_start 128 * 129 * @buf: pointer to the start of RX PKT TLV header 130 * Return: uint32_t(nss) 131 */ 132 static uint32_t hal_rx_msdu_start_nss_get_5018(uint8_t *buf) 133 { 134 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 135 struct rx_msdu_start *msdu_start = 136 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 137 uint8_t mimo_ss_bitmap; 138 139 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 140 141 return qdf_get_hweight8(mimo_ss_bitmap); 142 } 143 144 /** 145 * hal_rx_mon_hw_desc_get_mpdu_status_5018(): Retrieve MPDU status 146 * 147 * @ hw_desc_addr: Start address of Rx HW TLVs 148 * @ rs: Status for monitor mode 149 * 150 * Return: void 151 */ 152 static void hal_rx_mon_hw_desc_get_mpdu_status_5018(void *hw_desc_addr, 153 struct mon_rx_status *rs) 154 { 155 struct rx_msdu_start *rx_msdu_start; 156 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 157 uint32_t reg_value; 158 const uint32_t sgi_hw_to_cdp[] = { 159 CDP_SGI_0_8_US, 160 CDP_SGI_0_4_US, 161 CDP_SGI_1_6_US, 162 CDP_SGI_3_2_US, 163 }; 164 165 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 166 167 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 168 169 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 170 RX_MSDU_START_5, USER_RSSI); 171 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 172 173 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 174 rs->sgi = sgi_hw_to_cdp[reg_value]; 175 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 176 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 177 /* TODO: rs->beamformed should be set for SU beamforming also */ 178 } 179 180 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 181 /** 182 * hal_get_link_desc_size_5018(): API to get the link desc size 183 * 184 * Return: uint32_t 185 */ 186 static uint32_t hal_get_link_desc_size_5018(void) 187 { 188 return LINK_DESC_SIZE; 189 } 190 191 /** 192 * hal_rx_get_tlv_5018(): API to get the tlv 193 * 194 * @rx_tlv: TLV data extracted from the rx packet 195 * Return: uint8_t 196 */ 197 static uint8_t hal_rx_get_tlv_5018(void *rx_tlv) 198 { 199 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 200 } 201 202 /** 203 * hal_rx_mpdu_start_tlv_tag_valid_5018 () - API to check if RX_MPDU_START 204 * tlv tag is valid 205 * 206 *@rx_tlv_hdr: start address of rx_pkt_tlvs 207 * 208 * Return: true if RX_MPDU_START is valied, else false. 209 */ 210 uint8_t hal_rx_mpdu_start_tlv_tag_valid_5018(void *rx_tlv_hdr) 211 { 212 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 213 uint32_t tlv_tag; 214 215 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 216 217 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 218 } 219 220 static 221 void hal_compute_reo_remap_ix2_ix3_5018(uint32_t *ring, uint32_t num_rings, 222 uint32_t *remap1, uint32_t *remap2) 223 { 224 switch (num_rings) { 225 case 3: 226 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 227 HAL_REO_REMAP_IX2(ring[1], 17) | 228 HAL_REO_REMAP_IX2(ring[2], 18) | 229 HAL_REO_REMAP_IX2(ring[0], 19) | 230 HAL_REO_REMAP_IX2(ring[1], 20) | 231 HAL_REO_REMAP_IX2(ring[2], 21) | 232 HAL_REO_REMAP_IX2(ring[0], 22) | 233 HAL_REO_REMAP_IX2(ring[1], 23); 234 235 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 236 HAL_REO_REMAP_IX3(ring[0], 25) | 237 HAL_REO_REMAP_IX3(ring[1], 26) | 238 HAL_REO_REMAP_IX3(ring[2], 27) | 239 HAL_REO_REMAP_IX3(ring[0], 28) | 240 HAL_REO_REMAP_IX3(ring[1], 29) | 241 HAL_REO_REMAP_IX3(ring[2], 30) | 242 HAL_REO_REMAP_IX3(ring[0], 31); 243 break; 244 case 4: 245 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 246 HAL_REO_REMAP_IX2(ring[1], 17) | 247 HAL_REO_REMAP_IX2(ring[2], 18) | 248 HAL_REO_REMAP_IX2(ring[3], 19) | 249 HAL_REO_REMAP_IX2(ring[0], 20) | 250 HAL_REO_REMAP_IX2(ring[1], 21) | 251 HAL_REO_REMAP_IX2(ring[2], 22) | 252 HAL_REO_REMAP_IX2(ring[3], 23); 253 254 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 255 HAL_REO_REMAP_IX3(ring[1], 25) | 256 HAL_REO_REMAP_IX3(ring[2], 26) | 257 HAL_REO_REMAP_IX3(ring[3], 27) | 258 HAL_REO_REMAP_IX3(ring[0], 28) | 259 HAL_REO_REMAP_IX3(ring[1], 29) | 260 HAL_REO_REMAP_IX3(ring[2], 30) | 261 HAL_REO_REMAP_IX3(ring[3], 31); 262 break; 263 } 264 } 265 266 /** 267 * hal_rx_proc_phyrx_other_receive_info_tlv_5018(): API to get tlv info 268 * 269 * Return: uint32_t 270 */ 271 static inline 272 void hal_rx_proc_phyrx_other_receive_info_tlv_5018(void *rx_tlv_hdr, 273 void *ppdu_info_hdl) 274 { 275 } 276 277 /** 278 * hal_rx_dump_msdu_start_tlv_5018() : dump RX msdu_start TLV in structured 279 * human readable format. 280 * @ msdu_start: pointer the msdu_start TLV in pkt. 281 * @ dbg_level: log level. 282 * 283 * Return: void 284 */ 285 static void hal_rx_dump_msdu_start_tlv_5018(void *msdustart, 286 uint8_t dbg_level) 287 { 288 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 289 290 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 291 "rx_msdu_start tlv - " 292 "rxpcu_mpdu_filter_in_category: %d " 293 "sw_frame_group_id: %d " 294 "phy_ppdu_id: %d " 295 "msdu_length: %d " 296 "ipsec_esp: %d " 297 "l3_offset: %d " 298 "ipsec_ah: %d " 299 "l4_offset: %d " 300 "msdu_number: %d " 301 "decap_format: %d " 302 "ipv4_proto: %d " 303 "ipv6_proto: %d " 304 "tcp_proto: %d " 305 "udp_proto: %d " 306 "ip_frag: %d " 307 "tcp_only_ack: %d " 308 "da_is_bcast_mcast: %d " 309 "ip4_protocol_ip6_next_header: %d " 310 "toeplitz_hash_2_or_4: %d " 311 "flow_id_toeplitz: %d " 312 "user_rssi: %d " 313 "pkt_type: %d " 314 "stbc: %d " 315 "sgi: %d " 316 "rate_mcs: %d " 317 "receive_bandwidth: %d " 318 "reception_type: %d " 319 "ppdu_start_timestamp: %d " 320 "sw_phy_meta_data: %d ", 321 msdu_start->rxpcu_mpdu_filter_in_category, 322 msdu_start->sw_frame_group_id, 323 msdu_start->phy_ppdu_id, 324 msdu_start->msdu_length, 325 msdu_start->ipsec_esp, 326 msdu_start->l3_offset, 327 msdu_start->ipsec_ah, 328 msdu_start->l4_offset, 329 msdu_start->msdu_number, 330 msdu_start->decap_format, 331 msdu_start->ipv4_proto, 332 msdu_start->ipv6_proto, 333 msdu_start->tcp_proto, 334 msdu_start->udp_proto, 335 msdu_start->ip_frag, 336 msdu_start->tcp_only_ack, 337 msdu_start->da_is_bcast_mcast, 338 msdu_start->ip4_protocol_ip6_next_header, 339 msdu_start->toeplitz_hash_2_or_4, 340 msdu_start->flow_id_toeplitz, 341 msdu_start->user_rssi, 342 msdu_start->pkt_type, 343 msdu_start->stbc, 344 msdu_start->sgi, 345 msdu_start->rate_mcs, 346 msdu_start->receive_bandwidth, 347 msdu_start->reception_type, 348 msdu_start->ppdu_start_timestamp, 349 msdu_start->sw_phy_meta_data); 350 } 351 352 /** 353 * hal_rx_dump_msdu_end_tlv_5018: dump RX msdu_end TLV in structured 354 * human readable format. 355 * @ msdu_end: pointer the msdu_end TLV in pkt. 356 * @ dbg_level: log level. 357 * 358 * Return: void 359 */ 360 static void hal_rx_dump_msdu_end_tlv_5018(void *msduend, 361 uint8_t dbg_level) 362 { 363 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 364 365 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 366 "rx_msdu_end tlv - " 367 "rxpcu_mpdu_filter_in_category: %d " 368 "sw_frame_group_id: %d " 369 "phy_ppdu_id: %d " 370 "ip_hdr_chksum: %d " 371 "reported_mpdu_length: %d " 372 "key_id_octet: %d " 373 "cce_super_rule: %d " 374 "cce_classify_not_done_truncat: %d " 375 "cce_classify_not_done_cce_dis: %d " 376 "rule_indication_31_0: %d " 377 "rule_indication_63_32: %d " 378 "da_offset: %d " 379 "sa_offset: %d " 380 "da_offset_valid: %d " 381 "sa_offset_valid: %d " 382 "ipv6_options_crc: %d " 383 "tcp_seq_number: %d " 384 "tcp_ack_number: %d " 385 "tcp_flag: %d " 386 "lro_eligible: %d " 387 "window_size: %d " 388 "tcp_udp_chksum: %d " 389 "sa_idx_timeout: %d " 390 "da_idx_timeout: %d " 391 "msdu_limit_error: %d " 392 "flow_idx_timeout: %d " 393 "flow_idx_invalid: %d " 394 "wifi_parser_error: %d " 395 "amsdu_parser_error: %d " 396 "sa_is_valid: %d " 397 "da_is_valid: %d " 398 "da_is_mcbc: %d " 399 "l3_header_padding: %d " 400 "first_msdu: %d " 401 "last_msdu: %d " 402 "sa_idx: %d " 403 "msdu_drop: %d " 404 "reo_destination_indication: %d " 405 "flow_idx: %d " 406 "fse_metadata: %d " 407 "cce_metadata: %d " 408 "sa_sw_peer_id: %d ", 409 msdu_end->rxpcu_mpdu_filter_in_category, 410 msdu_end->sw_frame_group_id, 411 msdu_end->phy_ppdu_id, 412 msdu_end->ip_hdr_chksum, 413 msdu_end->reported_mpdu_length, 414 msdu_end->key_id_octet, 415 msdu_end->cce_super_rule, 416 msdu_end->cce_classify_not_done_truncate, 417 msdu_end->cce_classify_not_done_cce_dis, 418 msdu_end->rule_indication_31_0, 419 msdu_end->rule_indication_63_32, 420 msdu_end->da_offset, 421 msdu_end->sa_offset, 422 msdu_end->da_offset_valid, 423 msdu_end->sa_offset_valid, 424 msdu_end->ipv6_options_crc, 425 msdu_end->tcp_seq_number, 426 msdu_end->tcp_ack_number, 427 msdu_end->tcp_flag, 428 msdu_end->lro_eligible, 429 msdu_end->window_size, 430 msdu_end->tcp_udp_chksum, 431 msdu_end->sa_idx_timeout, 432 msdu_end->da_idx_timeout, 433 msdu_end->msdu_limit_error, 434 msdu_end->flow_idx_timeout, 435 msdu_end->flow_idx_invalid, 436 msdu_end->wifi_parser_error, 437 msdu_end->amsdu_parser_error, 438 msdu_end->sa_is_valid, 439 msdu_end->da_is_valid, 440 msdu_end->da_is_mcbc, 441 msdu_end->l3_header_padding, 442 msdu_end->first_msdu, 443 msdu_end->last_msdu, 444 msdu_end->sa_idx, 445 msdu_end->msdu_drop, 446 msdu_end->reo_destination_indication, 447 msdu_end->flow_idx, 448 msdu_end->fse_metadata, 449 msdu_end->cce_metadata, 450 msdu_end->sa_sw_peer_id); 451 } 452 453 /** 454 * hal_rx_mpdu_start_tid_get_5018(): API to get tid 455 * from rx_msdu_start 456 * 457 * @buf: pointer to the start of RX PKT TLV header 458 * Return: uint32_t(tid value) 459 */ 460 static uint32_t hal_rx_mpdu_start_tid_get_5018(uint8_t *buf) 461 { 462 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 463 struct rx_mpdu_start *mpdu_start = 464 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 465 uint32_t tid; 466 467 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 468 469 return tid; 470 } 471 472 /** 473 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 474 * Interval from rx_msdu_start 475 * 476 * @buf: pointer to the start of RX PKT TLV header 477 * Return: uint32_t(reception_type) 478 */ 479 static uint32_t hal_rx_msdu_start_reception_type_get_5018(uint8_t *buf) 480 { 481 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 482 struct rx_msdu_start *msdu_start = 483 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 484 uint32_t reception_type; 485 486 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 487 488 return reception_type; 489 } 490 491 /** 492 * hal_rx_msdu_end_da_idx_get_5018: API to get da_idx 493 * from rx_msdu_end TLV 494 * 495 * @ buf: pointer to the start of RX PKT TLV headers 496 * Return: da index 497 */ 498 static uint16_t hal_rx_msdu_end_da_idx_get_5018(uint8_t *buf) 499 { 500 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 501 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 502 uint16_t da_idx; 503 504 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 505 506 return da_idx; 507 } 508 509 /** 510 * hal_rx_get_rx_fragment_number_5018(): Function to retrieve rx fragment number 511 * 512 * @nbuf: Network buffer 513 * Returns: rx fragment number 514 */ 515 static 516 uint8_t hal_rx_get_rx_fragment_number_5018(uint8_t *buf) 517 { 518 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 519 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 520 521 /* Return first 4 bits as fragment number */ 522 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 523 DOT11_SEQ_FRAG_MASK); 524 } 525 526 /** 527 * hal_rx_msdu_end_da_is_mcbc_get_5018(): API to check if pkt is MCBC 528 * from rx_msdu_end TLV 529 * 530 * @ buf: pointer to the start of RX PKT TLV headers 531 * Return: da_is_mcbc 532 */ 533 static uint8_t 534 hal_rx_msdu_end_da_is_mcbc_get_5018(uint8_t *buf) 535 { 536 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 537 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 538 539 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 540 } 541 542 /** 543 * hal_rx_msdu_end_sa_is_valid_get_5018(): API to get_5018 the 544 * sa_is_valid bit from rx_msdu_end TLV 545 * 546 * @ buf: pointer to the start of RX PKT TLV headers 547 * Return: sa_is_valid bit 548 */ 549 static uint8_t 550 hal_rx_msdu_end_sa_is_valid_get_5018(uint8_t *buf) 551 { 552 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 553 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 554 uint8_t sa_is_valid; 555 556 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 557 558 return sa_is_valid; 559 } 560 561 /** 562 * hal_rx_msdu_end_sa_idx_get_5018(): API to get_5018 the 563 * sa_idx from rx_msdu_end TLV 564 * 565 * @ buf: pointer to the start of RX PKT TLV headers 566 * Return: sa_idx (SA AST index) 567 */ 568 static uint16_t hal_rx_msdu_end_sa_idx_get_5018(uint8_t *buf) 569 { 570 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 571 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 572 uint16_t sa_idx; 573 574 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 575 576 return sa_idx; 577 } 578 579 /** 580 * hal_rx_desc_is_first_msdu_5018() - Check if first msdu 581 * 582 * @hal_soc_hdl: hal_soc handle 583 * @hw_desc_addr: hardware descriptor address 584 * 585 * Return: 0 - success/ non-zero failure 586 */ 587 static uint32_t hal_rx_desc_is_first_msdu_5018(void *hw_desc_addr) 588 { 589 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 590 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 591 592 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 593 } 594 595 /** 596 * hal_rx_msdu_end_l3_hdr_padding_get_5018(): API to get_5018 the 597 * l3_header padding from rx_msdu_end TLV 598 * 599 * @ buf: pointer to the start of RX PKT TLV headers 600 * Return: number of l3 header padding bytes 601 */ 602 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_5018(uint8_t *buf) 603 { 604 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 605 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 606 uint32_t l3_header_padding; 607 608 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 609 610 return l3_header_padding; 611 } 612 613 /** 614 * @ hal_rx_encryption_info_valid_5018: Returns encryption type. 615 * 616 * @ buf: rx_tlv_hdr of the received packet 617 * @ Return: encryption type 618 */ 619 inline uint32_t hal_rx_encryption_info_valid_5018(uint8_t *buf) 620 { 621 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 622 struct rx_mpdu_start *mpdu_start = 623 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 624 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 625 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 626 627 return encryption_info; 628 } 629 630 /* 631 * @ hal_rx_print_pn_5018: Prints the PN of rx packet. 632 * 633 * @ buf: rx_tlv_hdr of the received packet 634 * @ Return: void 635 */ 636 static void hal_rx_print_pn_5018(uint8_t *buf) 637 { 638 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 639 struct rx_mpdu_start *mpdu_start = 640 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 641 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 642 643 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 644 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 645 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 646 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 647 648 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 649 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 650 } 651 652 /** 653 * hal_rx_msdu_end_first_msdu_get_5018: API to get first msdu status 654 * from rx_msdu_end TLV 655 * 656 * @ buf: pointer to the start of RX PKT TLV headers 657 * Return: first_msdu 658 */ 659 static uint8_t hal_rx_msdu_end_first_msdu_get_5018(uint8_t *buf) 660 { 661 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 662 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 663 uint8_t first_msdu; 664 665 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 666 667 return first_msdu; 668 } 669 670 /** 671 * hal_rx_msdu_end_da_is_valid_get_5018: API to check if da is valid 672 * from rx_msdu_end TLV 673 * 674 * @ buf: pointer to the start of RX PKT TLV headers 675 * Return: da_is_valid 676 */ 677 static uint8_t hal_rx_msdu_end_da_is_valid_get_5018(uint8_t *buf) 678 { 679 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 680 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 681 uint8_t da_is_valid; 682 683 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 684 685 return da_is_valid; 686 } 687 688 /** 689 * hal_rx_msdu_end_last_msdu_get_5018: API to get last msdu status 690 * from rx_msdu_end TLV 691 * 692 * @ buf: pointer to the start of RX PKT TLV headers 693 * Return: last_msdu 694 */ 695 static uint8_t hal_rx_msdu_end_last_msdu_get_5018(uint8_t *buf) 696 { 697 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 698 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 699 uint8_t last_msdu; 700 701 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 702 703 return last_msdu; 704 } 705 706 /* 707 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 708 * 709 * @nbuf: Network buffer 710 * Returns: value of mpdu 4th address valid field 711 */ 712 inline bool hal_rx_get_mpdu_mac_ad4_valid_5018(uint8_t *buf) 713 { 714 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 715 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 716 bool ad4_valid = 0; 717 718 ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info); 719 720 return ad4_valid; 721 } 722 723 /** 724 * hal_rx_mpdu_start_sw_peer_id_get_5018: Retrieve sw peer_id 725 * @buf: network buffer 726 * 727 * Return: sw peer_id 728 */ 729 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_5018(uint8_t *buf) 730 { 731 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 732 struct rx_mpdu_start *mpdu_start = 733 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 734 735 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 736 &mpdu_start->rx_mpdu_info_details); 737 } 738 739 /* 740 * hal_rx_mpdu_get_to_ds_5018(): API to get the tods info 741 * from rx_mpdu_start 742 * 743 * @buf: pointer to the start of RX PKT TLV header 744 * Return: uint32_t(to_ds) 745 */ 746 static uint32_t hal_rx_mpdu_get_to_ds_5018(uint8_t *buf) 747 { 748 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 749 struct rx_mpdu_start *mpdu_start = 750 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 751 752 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 753 754 return HAL_RX_MPDU_GET_TODS(mpdu_info); 755 } 756 757 /* 758 * hal_rx_mpdu_get_fr_ds_5018(): API to get the from ds info 759 * from rx_mpdu_start 760 * 761 * @buf: pointer to the start of RX PKT TLV header 762 * Return: uint32_t(fr_ds) 763 */ 764 static uint32_t hal_rx_mpdu_get_fr_ds_5018(uint8_t *buf) 765 { 766 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 767 struct rx_mpdu_start *mpdu_start = 768 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 769 770 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 771 772 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 773 } 774 775 /* 776 * hal_rx_get_mpdu_frame_control_valid_5018(): Retrieves mpdu 777 * frame control valid 778 * 779 * @nbuf: Network buffer 780 * Returns: value of frame control valid field 781 */ 782 static uint8_t hal_rx_get_mpdu_frame_control_valid_5018(uint8_t *buf) 783 { 784 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 785 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 786 787 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 788 } 789 790 /* 791 * hal_rx_mpdu_get_addr1_5018(): API to check get address1 of the mpdu 792 * 793 * @buf: pointer to the start of RX PKT TLV headera 794 * @mac_addr: pointer to mac address 795 * Return: success/failure 796 */ 797 static QDF_STATUS hal_rx_mpdu_get_addr1_5018(uint8_t *buf, 798 uint8_t *mac_addr) 799 { 800 struct __attribute__((__packed__)) hal_addr1 { 801 uint32_t ad1_31_0; 802 uint16_t ad1_47_32; 803 }; 804 805 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 806 struct rx_mpdu_start *mpdu_start = 807 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 808 809 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 810 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 811 uint32_t mac_addr_ad1_valid; 812 813 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 814 815 if (mac_addr_ad1_valid) { 816 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 817 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 818 return QDF_STATUS_SUCCESS; 819 } 820 821 return QDF_STATUS_E_FAILURE; 822 } 823 824 /* 825 * hal_rx_mpdu_get_addr2_5018(): API to check get address2 of the mpdu 826 * in the packet 827 * 828 * @buf: pointer to the start of RX PKT TLV header 829 * @mac_addr: pointer to mac address 830 * Return: success/failure 831 */ 832 static QDF_STATUS hal_rx_mpdu_get_addr2_5018(uint8_t *buf, uint8_t *mac_addr) 833 { 834 struct __attribute__((__packed__)) hal_addr2 { 835 uint16_t ad2_15_0; 836 uint32_t ad2_47_16; 837 }; 838 839 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 840 struct rx_mpdu_start *mpdu_start = 841 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 842 843 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 844 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 845 uint32_t mac_addr_ad2_valid; 846 847 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 848 849 if (mac_addr_ad2_valid) { 850 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 851 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 852 return QDF_STATUS_SUCCESS; 853 } 854 855 return QDF_STATUS_E_FAILURE; 856 } 857 858 /* 859 * hal_rx_mpdu_get_addr3_5018(): API to get address3 of the mpdu 860 * in the packet 861 * 862 * @buf: pointer to the start of RX PKT TLV header 863 * @mac_addr: pointer to mac address 864 * Return: success/failure 865 */ 866 static QDF_STATUS hal_rx_mpdu_get_addr3_5018(uint8_t *buf, uint8_t *mac_addr) 867 { 868 struct __attribute__((__packed__)) hal_addr3 { 869 uint32_t ad3_31_0; 870 uint16_t ad3_47_32; 871 }; 872 873 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 874 struct rx_mpdu_start *mpdu_start = 875 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 876 877 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 878 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 879 uint32_t mac_addr_ad3_valid; 880 881 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 882 883 if (mac_addr_ad3_valid) { 884 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 885 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 886 return QDF_STATUS_SUCCESS; 887 } 888 889 return QDF_STATUS_E_FAILURE; 890 } 891 892 /* 893 * hal_rx_mpdu_get_addr4_5018(): API to get address4 of the mpdu 894 * in the packet 895 * 896 * @buf: pointer to the start of RX PKT TLV header 897 * @mac_addr: pointer to mac address 898 * Return: success/failure 899 */ 900 static QDF_STATUS hal_rx_mpdu_get_addr4_5018(uint8_t *buf, uint8_t *mac_addr) 901 { 902 struct __attribute__((__packed__)) hal_addr4 { 903 uint32_t ad4_31_0; 904 uint16_t ad4_47_32; 905 }; 906 907 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 908 struct rx_mpdu_start *mpdu_start = 909 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 910 911 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 912 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 913 uint32_t mac_addr_ad4_valid; 914 915 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 916 917 if (mac_addr_ad4_valid) { 918 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 919 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 920 return QDF_STATUS_SUCCESS; 921 } 922 923 return QDF_STATUS_E_FAILURE; 924 } 925 926 /* 927 * hal_rx_get_mpdu_sequence_control_valid_5018(): Get mpdu 928 * sequence control valid 929 * 930 * @nbuf: Network buffer 931 * Returns: value of sequence control valid field 932 */ 933 static uint8_t hal_rx_get_mpdu_sequence_control_valid_5018(uint8_t *buf) 934 { 935 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 936 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 937 938 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 939 } 940 941 /** 942 * hal_rx_is_unicast_5018: check packet is unicast frame or not. 943 * 944 * @ buf: pointer to rx pkt TLV. 945 * 946 * Return: true on unicast. 947 */ 948 static bool hal_rx_is_unicast_5018(uint8_t *buf) 949 { 950 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 951 struct rx_mpdu_start *mpdu_start = 952 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 953 uint32_t grp_id; 954 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 955 956 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 957 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 958 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 959 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 960 961 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 962 } 963 964 /** 965 * hal_rx_tid_get_5018: get tid based on qos control valid. 966 * @hal_soc_hdl: hal soc handle 967 * @buf: pointer to rx pkt TLV. 968 * 969 * Return: tid 970 */ 971 static uint32_t hal_rx_tid_get_5018(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 972 { 973 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 974 struct rx_mpdu_start *mpdu_start = 975 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 976 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 977 uint8_t qos_control_valid = 978 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 979 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 980 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 981 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 982 983 if (qos_control_valid) 984 return hal_rx_mpdu_start_tid_get_5018(buf); 985 986 return HAL_RX_NON_QOS_TID; 987 } 988 989 /** 990 * hal_rx_hw_desc_get_ppduid_get_5018(): retrieve ppdu id 991 * @rx_tlv_hdr: rx tlv header 992 * @rxdma_dst_ring_desc: rxdma HW descriptor 993 * 994 * Return: ppdu id 995 */ 996 static uint32_t hal_rx_hw_desc_get_ppduid_get_5018(void *rx_tlv_hdr, 997 void *rxdma_dst_ring_desc) 998 { 999 struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc; 1000 1001 return HAL_RX_REO_ENT_PHY_PPDU_ID_GET(reo_ent); 1002 } 1003 1004 /** 1005 * hal_reo_status_get_header_5018 - Process reo desc info 1006 * @d - Pointer to reo descriptior 1007 * @b - tlv type info 1008 * @h1 - Pointer to hal_reo_status_header where info to be stored 1009 * 1010 * Return - none. 1011 * 1012 */ 1013 static void hal_reo_status_get_header_5018(uint32_t *d, int b, void *h1) 1014 { 1015 uint32_t val1 = 0; 1016 struct hal_reo_status_header *h = 1017 (struct hal_reo_status_header *)h1; 1018 1019 switch (b) { 1020 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1021 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1022 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1023 break; 1024 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1025 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1026 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1027 break; 1028 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1029 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1030 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1031 break; 1032 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1033 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1034 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1035 break; 1036 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1037 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1038 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1039 break; 1040 case HAL_REO_DESC_THRES_STATUS_TLV: 1041 val1 = 1042 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1043 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1044 break; 1045 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1046 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1047 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1048 break; 1049 default: 1050 qdf_nofl_err("ERROR: Unknown tlv\n"); 1051 break; 1052 } 1053 h->cmd_num = 1054 HAL_GET_FIELD( 1055 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1056 val1); 1057 h->exec_time = 1058 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1059 CMD_EXECUTION_TIME, val1); 1060 h->status = 1061 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1062 REO_CMD_EXECUTION_STATUS, val1); 1063 switch (b) { 1064 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1065 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1066 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1067 break; 1068 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1069 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1070 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1071 break; 1072 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1073 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1074 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1075 break; 1076 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1077 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1078 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1079 break; 1080 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1081 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1082 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1083 break; 1084 case HAL_REO_DESC_THRES_STATUS_TLV: 1085 val1 = 1086 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1087 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1088 break; 1089 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1090 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1091 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1092 break; 1093 default: 1094 qdf_nofl_err("ERROR: Unknown tlv\n"); 1095 break; 1096 } 1097 h->tstamp = 1098 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1099 } 1100 1101 /** 1102 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(): 1103 * Retrieve qos control valid bit from the tlv. 1104 * @buf: pointer to rx pkt TLV. 1105 * 1106 * Return: qos control value. 1107 */ 1108 static inline uint32_t 1109 hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(uint8_t *buf) 1110 { 1111 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1112 struct rx_mpdu_start *mpdu_start = 1113 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1114 1115 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1116 &mpdu_start->rx_mpdu_info_details); 1117 } 1118 1119 /** 1120 * hal_rx_msdu_end_sa_sw_peer_id_get_5018(): API to get the 1121 * sa_sw_peer_id from rx_msdu_end TLV 1122 * @buf: pointer to the start of RX PKT TLV headers 1123 * 1124 * Return: sa_sw_peer_id index 1125 */ 1126 static inline uint32_t 1127 hal_rx_msdu_end_sa_sw_peer_id_get_5018(uint8_t *buf) 1128 { 1129 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1130 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1131 1132 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1133 } 1134 1135 /** 1136 * hal_tx_desc_set_mesh_en_5018 - Set mesh_enable flag in Tx descriptor 1137 * @desc: Handle to Tx Descriptor 1138 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1139 * enabling the interpretation of the 'Mesh Control Present' bit 1140 * (bit 8) of QoS Control (otherwise this bit is ignored), 1141 * For native WiFi frames, this indicates that a 'Mesh Control' field 1142 * is present between the header and the LLC. 1143 * 1144 * Return: void 1145 */ 1146 static inline 1147 void hal_tx_desc_set_mesh_en_5018(void *desc, uint8_t en) 1148 { 1149 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1150 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1151 } 1152 1153 static 1154 void *hal_rx_msdu0_buffer_addr_lsb_5018(void *link_desc_va) 1155 { 1156 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1157 } 1158 1159 static 1160 void *hal_rx_msdu_desc_info_ptr_get_5018(void *msdu0) 1161 { 1162 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1163 } 1164 1165 static 1166 void *hal_ent_mpdu_desc_info_5018(void *ent_ring_desc) 1167 { 1168 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1169 } 1170 1171 static 1172 void *hal_dst_mpdu_desc_info_5018(void *dst_ring_desc) 1173 { 1174 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1175 } 1176 1177 static 1178 uint8_t hal_rx_get_fc_valid_5018(uint8_t *buf) 1179 { 1180 return HAL_RX_GET_FC_VALID(buf); 1181 } 1182 1183 static uint8_t hal_rx_get_to_ds_flag_5018(uint8_t *buf) 1184 { 1185 return HAL_RX_GET_TO_DS_FLAG(buf); 1186 } 1187 1188 static uint8_t hal_rx_get_mac_addr2_valid_5018(uint8_t *buf) 1189 { 1190 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1191 } 1192 1193 static uint8_t hal_rx_get_filter_category_5018(uint8_t *buf) 1194 { 1195 return HAL_RX_GET_FILTER_CATEGORY(buf); 1196 } 1197 1198 static uint32_t 1199 hal_rx_get_ppdu_id_5018(uint8_t *buf) 1200 { 1201 struct rx_mpdu_info *rx_mpdu_info; 1202 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 1203 1204 rx_mpdu_info = 1205 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1206 1207 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 1208 } 1209 1210 /** 1211 * hal_reo_config_5018(): Set reo config parameters 1212 * @soc: hal soc handle 1213 * @reg_val: value to be set 1214 * @reo_params: reo parameters 1215 * 1216 * Return: void 1217 */ 1218 static void 1219 hal_reo_config_5018(struct hal_soc *soc, 1220 uint32_t reg_val, 1221 struct hal_reo_params *reo_params) 1222 { 1223 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1224 } 1225 1226 /** 1227 * hal_rx_msdu_desc_info_get_ptr_5018() - Get msdu desc info ptr 1228 * @msdu_details_ptr - Pointer to msdu_details_ptr 1229 * 1230 * Return - Pointer to rx_msdu_desc_info structure. 1231 * 1232 */ 1233 static void *hal_rx_msdu_desc_info_get_ptr_5018(void *msdu_details_ptr) 1234 { 1235 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1236 } 1237 1238 /** 1239 * hal_rx_link_desc_msdu0_ptr_5018 - Get pointer to rx_msdu details 1240 * @link_desc - Pointer to link desc 1241 * 1242 * Return - Pointer to rx_msdu_details structure 1243 * 1244 */ 1245 static void *hal_rx_link_desc_msdu0_ptr_5018(void *link_desc) 1246 { 1247 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1248 } 1249 1250 /** 1251 * hal_rx_msdu_flow_idx_get_5018: API to get flow index 1252 * from rx_msdu_end TLV 1253 * @buf: pointer to the start of RX PKT TLV headers 1254 * 1255 * Return: flow index value from MSDU END TLV 1256 */ 1257 static inline uint32_t hal_rx_msdu_flow_idx_get_5018(uint8_t *buf) 1258 { 1259 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1260 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1261 1262 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1263 } 1264 1265 /** 1266 * hal_rx_msdu_flow_idx_invalid_5018: API to get flow index invalid 1267 * from rx_msdu_end TLV 1268 * @buf: pointer to the start of RX PKT TLV headers 1269 * 1270 * Return: flow index invalid value from MSDU END TLV 1271 */ 1272 static bool hal_rx_msdu_flow_idx_invalid_5018(uint8_t *buf) 1273 { 1274 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1275 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1276 1277 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1278 } 1279 1280 /** 1281 * hal_rx_msdu_flow_idx_timeout_5018: API to get flow index timeout 1282 * from rx_msdu_end TLV 1283 * @buf: pointer to the start of RX PKT TLV headers 1284 * 1285 * Return: flow index timeout value from MSDU END TLV 1286 */ 1287 static bool hal_rx_msdu_flow_idx_timeout_5018(uint8_t *buf) 1288 { 1289 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1290 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1291 1292 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1293 } 1294 1295 /** 1296 * hal_rx_msdu_fse_metadata_get_5018: API to get FSE metadata 1297 * from rx_msdu_end TLV 1298 * @buf: pointer to the start of RX PKT TLV headers 1299 * 1300 * Return: fse metadata value from MSDU END TLV 1301 */ 1302 static uint32_t hal_rx_msdu_fse_metadata_get_5018(uint8_t *buf) 1303 { 1304 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1305 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1306 1307 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1308 } 1309 1310 /** 1311 * hal_rx_msdu_cce_metadata_get_5018: API to get CCE metadata 1312 * from rx_msdu_end TLV 1313 * @buf: pointer to the start of RX PKT TLV headers 1314 * 1315 * Return: cce_metadata 1316 */ 1317 static uint16_t 1318 hal_rx_msdu_cce_metadata_get_5018(uint8_t *buf) 1319 { 1320 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1321 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1322 1323 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1324 } 1325 1326 /** 1327 * hal_rx_msdu_get_flow_params_5018: API to get flow index, flow index invalid 1328 * and flow index timeout from rx_msdu_end TLV 1329 * @buf: pointer to the start of RX PKT TLV headers 1330 * @flow_invalid: pointer to return value of flow_idx_valid 1331 * @flow_timeout: pointer to return value of flow_idx_timeout 1332 * @flow_index: pointer to return value of flow_idx 1333 * 1334 * Return: none 1335 */ 1336 static inline void 1337 hal_rx_msdu_get_flow_params_5018(uint8_t *buf, 1338 bool *flow_invalid, 1339 bool *flow_timeout, 1340 uint32_t *flow_index) 1341 { 1342 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1343 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1344 1345 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1346 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1347 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1348 } 1349 1350 /** 1351 * hal_rx_tlv_get_tcp_chksum_5018() - API to get tcp checksum 1352 * @buf: rx_tlv_hdr 1353 * 1354 * Return: tcp checksum 1355 */ 1356 static uint16_t 1357 hal_rx_tlv_get_tcp_chksum_5018(uint8_t *buf) 1358 { 1359 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1360 } 1361 1362 /** 1363 * hal_rx_get_rx_sequence_5018(): Function to retrieve rx sequence number 1364 * 1365 * @nbuf: Network buffer 1366 * Returns: rx sequence number 1367 */ 1368 static 1369 uint16_t hal_rx_get_rx_sequence_5018(uint8_t *buf) 1370 { 1371 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1372 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1373 1374 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1375 } 1376 1377 /** 1378 * hal_get_window_address_5018(): Function to get hp/tp address 1379 * @hal_soc: Pointer to hal_soc 1380 * @addr: address offset of register 1381 * 1382 * Return: modified address offset of register 1383 */ 1384 static inline qdf_iomem_t hal_get_window_address_5018(struct hal_soc *hal_soc, 1385 qdf_iomem_t addr) 1386 { 1387 uint32_t offset = addr - hal_soc->dev_base_addr; 1388 qdf_iomem_t new_offset; 1389 1390 /* 1391 * Check if offset lies within CE register range(0x08400000) 1392 * or UMAC/DP register range (0x00A00000). 1393 * If offset lies within CE register range, map it 1394 * into CE region. 1395 */ 1396 if (offset & HOST_CE_MASK_VALUE) { 1397 offset = offset - WFSS_CE_REG_BASE; 1398 new_offset = (hal_soc->dev_base_addr_ce + offset); 1399 1400 return new_offset; 1401 } else { 1402 /* 1403 * If offset lies within DP register range, 1404 * return the address as such 1405 */ 1406 return addr; 1407 } 1408 } 1409 1410 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1411 { 1412 /* Write value into window configuration register */ 1413 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1414 WINDOW_CONFIGURATION_VALUE_5018); 1415 } 1416 1417 /** 1418 * hal_rx_msdu_packet_metadata_get_5018(): API to get the 1419 * msdu information from rx_msdu_end TLV 1420 * 1421 * @ buf: pointer to the start of RX PKT TLV headers 1422 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 1423 */ 1424 static void 1425 hal_rx_msdu_packet_metadata_get_5018(uint8_t *buf, 1426 void *msdu_pkt_metadata) 1427 { 1428 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1429 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1430 struct hal_rx_msdu_metadata *msdu_metadata = 1431 (struct hal_rx_msdu_metadata *)msdu_pkt_metadata; 1432 1433 msdu_metadata->l3_hdr_pad = 1434 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1435 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1436 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 1437 msdu_metadata->sa_sw_peer_id = 1438 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1439 } 1440 1441 /** 1442 * hal_rx_flow_setup_fse_5018() - Setup a flow search entry in HW FST 1443 * @fst: Pointer to the Rx Flow Search Table 1444 * @table_offset: offset into the table where the flow is to be setup 1445 * @flow: Flow Parameters 1446 * 1447 * Return: Success/Failure 1448 */ 1449 static void * 1450 hal_rx_flow_setup_fse_5018(uint8_t *rx_fst, uint32_t table_offset, 1451 uint8_t *rx_flow) 1452 { 1453 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1454 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1455 uint8_t *fse; 1456 bool fse_valid; 1457 1458 if (table_offset >= fst->max_entries) { 1459 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1460 "HAL FSE table offset %u exceeds max entries %u", 1461 table_offset, fst->max_entries); 1462 return NULL; 1463 } 1464 1465 fse = (uint8_t *)fst->base_vaddr + 1466 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1467 1468 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1469 1470 if (fse_valid) { 1471 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1472 "HAL FSE %pK already valid", fse); 1473 return NULL; 1474 } 1475 1476 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1477 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1478 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1479 1480 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1481 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1482 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1483 1484 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1485 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1486 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1487 1488 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1489 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1490 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1491 1492 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1493 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1494 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1495 1496 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1497 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1498 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1499 1500 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1501 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1502 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1503 1504 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1505 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1506 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1507 1508 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1509 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1510 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1511 (flow->tuple_info.dest_port)); 1512 1513 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1514 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1515 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1516 (flow->tuple_info.src_port)); 1517 1518 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1519 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1520 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1521 flow->tuple_info.l4_protocol); 1522 1523 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1524 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1525 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1526 flow->reo_destination_handler); 1527 1528 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1529 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1530 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1531 1532 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1533 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1534 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1535 flow->fse_metadata); 1536 1537 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1538 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1539 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1540 REO_DESTINATION_INDICATION, 1541 flow->reo_destination_indication); 1542 1543 /* Reset all the other fields in FSE */ 1544 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1545 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1546 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1547 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1548 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1549 1550 return fse; 1551 } 1552 1553 struct hal_hw_txrx_ops qca5018_hal_hw_txrx_ops = { 1554 1555 /* init and setup */ 1556 hal_srng_dst_hw_init_generic, 1557 hal_srng_src_hw_init_generic, 1558 hal_get_hw_hptp_generic, 1559 hal_reo_setup_generic, 1560 hal_setup_link_idle_list_generic, 1561 hal_get_window_address_5018, 1562 NULL, 1563 1564 /* tx */ 1565 hal_tx_desc_set_dscp_tid_table_id_5018, 1566 hal_tx_set_dscp_tid_map_5018, 1567 hal_tx_update_dscp_tid_5018, 1568 hal_tx_desc_set_lmac_id_5018, 1569 hal_tx_desc_set_buf_addr_generic, 1570 hal_tx_desc_set_search_type_generic, 1571 hal_tx_desc_set_search_index_generic, 1572 hal_tx_desc_set_cache_set_num_generic, 1573 hal_tx_comp_get_status_generic, 1574 hal_tx_comp_get_release_reason_generic, 1575 hal_get_wbm_internal_error_generic, 1576 hal_tx_desc_set_mesh_en_5018, 1577 hal_tx_init_cmd_credit_ring_5018, 1578 1579 /* rx */ 1580 hal_rx_msdu_start_nss_get_5018, 1581 hal_rx_mon_hw_desc_get_mpdu_status_5018, 1582 hal_rx_get_tlv_5018, 1583 hal_rx_proc_phyrx_other_receive_info_tlv_5018, 1584 hal_rx_dump_msdu_start_tlv_5018, 1585 hal_rx_dump_msdu_end_tlv_5018, 1586 hal_get_link_desc_size_5018, 1587 hal_rx_mpdu_start_tid_get_5018, 1588 hal_rx_msdu_start_reception_type_get_5018, 1589 hal_rx_msdu_end_da_idx_get_5018, 1590 hal_rx_msdu_desc_info_get_ptr_5018, 1591 hal_rx_link_desc_msdu0_ptr_5018, 1592 hal_reo_status_get_header_5018, 1593 hal_rx_status_get_tlv_info_generic, 1594 hal_rx_wbm_err_info_get_generic, 1595 hal_rx_dump_mpdu_start_tlv_generic, 1596 1597 hal_tx_set_pcp_tid_map_generic, 1598 hal_tx_update_pcp_tid_generic, 1599 hal_tx_update_tidmap_prty_generic, 1600 hal_rx_get_rx_fragment_number_5018, 1601 hal_rx_msdu_end_da_is_mcbc_get_5018, 1602 hal_rx_msdu_end_sa_is_valid_get_5018, 1603 hal_rx_msdu_end_sa_idx_get_5018, 1604 hal_rx_desc_is_first_msdu_5018, 1605 hal_rx_msdu_end_l3_hdr_padding_get_5018, 1606 hal_rx_encryption_info_valid_5018, 1607 hal_rx_print_pn_5018, 1608 hal_rx_msdu_end_first_msdu_get_5018, 1609 hal_rx_msdu_end_da_is_valid_get_5018, 1610 hal_rx_msdu_end_last_msdu_get_5018, 1611 hal_rx_get_mpdu_mac_ad4_valid_5018, 1612 hal_rx_mpdu_start_sw_peer_id_get_5018, 1613 hal_rx_mpdu_get_to_ds_5018, 1614 hal_rx_mpdu_get_fr_ds_5018, 1615 hal_rx_get_mpdu_frame_control_valid_5018, 1616 hal_rx_mpdu_get_addr1_5018, 1617 hal_rx_mpdu_get_addr2_5018, 1618 hal_rx_mpdu_get_addr3_5018, 1619 hal_rx_mpdu_get_addr4_5018, 1620 hal_rx_get_mpdu_sequence_control_valid_5018, 1621 hal_rx_is_unicast_5018, 1622 hal_rx_tid_get_5018, 1623 hal_rx_hw_desc_get_ppduid_get_5018, 1624 hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018, 1625 hal_rx_msdu_end_sa_sw_peer_id_get_5018, 1626 hal_rx_msdu0_buffer_addr_lsb_5018, 1627 hal_rx_msdu_desc_info_ptr_get_5018, 1628 hal_ent_mpdu_desc_info_5018, 1629 hal_dst_mpdu_desc_info_5018, 1630 hal_rx_get_fc_valid_5018, 1631 hal_rx_get_to_ds_flag_5018, 1632 hal_rx_get_mac_addr2_valid_5018, 1633 hal_rx_get_filter_category_5018, 1634 hal_rx_get_ppdu_id_5018, 1635 hal_reo_config_5018, 1636 hal_rx_msdu_flow_idx_get_5018, 1637 hal_rx_msdu_flow_idx_invalid_5018, 1638 hal_rx_msdu_flow_idx_timeout_5018, 1639 hal_rx_msdu_fse_metadata_get_5018, 1640 hal_rx_msdu_cce_metadata_get_5018, 1641 hal_rx_msdu_get_flow_params_5018, 1642 hal_rx_tlv_get_tcp_chksum_5018, 1643 hal_rx_get_rx_sequence_5018, 1644 NULL, 1645 NULL, 1646 /* rx - msdu fast path info fields */ 1647 hal_rx_msdu_packet_metadata_get_5018, 1648 NULL, 1649 NULL, 1650 NULL, 1651 NULL, 1652 NULL, 1653 NULL, 1654 hal_rx_mpdu_start_tlv_tag_valid_5018, 1655 NULL, 1656 NULL, 1657 1658 /* rx - TLV struct offsets */ 1659 hal_rx_msdu_end_offset_get_generic, 1660 hal_rx_attn_offset_get_generic, 1661 hal_rx_msdu_start_offset_get_generic, 1662 hal_rx_mpdu_start_offset_get_generic, 1663 hal_rx_mpdu_end_offset_get_generic, 1664 hal_rx_flow_setup_fse_5018, 1665 hal_compute_reo_remap_ix2_ix3_5018 1666 }; 1667 1668 struct hal_hw_srng_config hw_srng_table_5018[] = { 1669 /* TODO: max_rings can populated by querying HW capabilities */ 1670 { /* REO_DST */ 1671 .start_ring_id = HAL_SRNG_REO2SW1, 1672 .max_rings = 4, 1673 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1674 .lmac_ring = FALSE, 1675 .ring_dir = HAL_SRNG_DST_RING, 1676 .reg_start = { 1677 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1678 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1679 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1680 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1681 }, 1682 .reg_size = { 1683 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1684 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1685 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1686 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1687 }, 1688 .max_size = 1689 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1690 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1691 }, 1692 { /* REO_EXCEPTION */ 1693 /* Designating REO2TCL ring as exception ring. This ring is 1694 * similar to other REO2SW rings though it is named as REO2TCL. 1695 * Any of theREO2SW rings can be used as exception ring. 1696 */ 1697 .start_ring_id = HAL_SRNG_REO2TCL, 1698 .max_rings = 1, 1699 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1700 .lmac_ring = FALSE, 1701 .ring_dir = HAL_SRNG_DST_RING, 1702 .reg_start = { 1703 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1704 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1705 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1706 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1707 }, 1708 /* Single ring - provide ring size if multiple rings of this 1709 * type are supported 1710 */ 1711 .reg_size = {}, 1712 .max_size = 1713 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1714 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1715 }, 1716 { /* REO_REINJECT */ 1717 .start_ring_id = HAL_SRNG_SW2REO, 1718 .max_rings = 1, 1719 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1720 .lmac_ring = FALSE, 1721 .ring_dir = HAL_SRNG_SRC_RING, 1722 .reg_start = { 1723 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1724 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1725 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1726 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1727 }, 1728 /* Single ring - provide ring size if multiple rings of this 1729 * type are supported 1730 */ 1731 .reg_size = {}, 1732 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1733 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1734 }, 1735 { /* REO_CMD */ 1736 .start_ring_id = HAL_SRNG_REO_CMD, 1737 .max_rings = 1, 1738 .entry_size = (sizeof(struct tlv_32_hdr) + 1739 sizeof(struct reo_get_queue_stats)) >> 2, 1740 .lmac_ring = FALSE, 1741 .ring_dir = HAL_SRNG_SRC_RING, 1742 .reg_start = { 1743 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1744 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1745 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1746 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1747 }, 1748 /* Single ring - provide ring size if multiple rings of this 1749 * type are supported 1750 */ 1751 .reg_size = {}, 1752 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1753 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1754 }, 1755 { /* REO_STATUS */ 1756 .start_ring_id = HAL_SRNG_REO_STATUS, 1757 .max_rings = 1, 1758 .entry_size = (sizeof(struct tlv_32_hdr) + 1759 sizeof(struct reo_get_queue_stats_status)) >> 2, 1760 .lmac_ring = FALSE, 1761 .ring_dir = HAL_SRNG_DST_RING, 1762 .reg_start = { 1763 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1764 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1765 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1766 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1767 }, 1768 /* Single ring - provide ring size if multiple rings of this 1769 * type are supported 1770 */ 1771 .reg_size = {}, 1772 .max_size = 1773 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1774 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1775 }, 1776 { /* TCL_DATA */ 1777 .start_ring_id = HAL_SRNG_SW2TCL1, 1778 .max_rings = 3, 1779 .entry_size = (sizeof(struct tlv_32_hdr) + 1780 sizeof(struct tcl_data_cmd)) >> 2, 1781 .lmac_ring = FALSE, 1782 .ring_dir = HAL_SRNG_SRC_RING, 1783 .reg_start = { 1784 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1785 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1786 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1787 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1788 }, 1789 .reg_size = { 1790 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1791 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1792 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1793 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1794 }, 1795 .max_size = 1796 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1797 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1798 }, 1799 { /* TCL_CMD */ 1800 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1801 .max_rings = 1, 1802 .entry_size = (sizeof(struct tlv_32_hdr) + 1803 sizeof(struct tcl_data_cmd)) >> 2, 1804 .lmac_ring = FALSE, 1805 .ring_dir = HAL_SRNG_SRC_RING, 1806 .reg_start = { 1807 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 1808 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1809 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 1810 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1811 }, 1812 /* Single ring - provide ring size if multiple rings of this 1813 * type are supported 1814 */ 1815 .reg_size = {}, 1816 .max_size = 1817 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 1818 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 1819 }, 1820 { /* TCL_STATUS */ 1821 .start_ring_id = HAL_SRNG_TCL_STATUS, 1822 .max_rings = 1, 1823 .entry_size = (sizeof(struct tlv_32_hdr) + 1824 sizeof(struct tcl_status_ring)) >> 2, 1825 .lmac_ring = FALSE, 1826 .ring_dir = HAL_SRNG_DST_RING, 1827 .reg_start = { 1828 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1829 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1830 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1831 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1832 }, 1833 /* Single ring - provide ring size if multiple rings of this 1834 * type are supported 1835 */ 1836 .reg_size = {}, 1837 .max_size = 1838 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1839 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1840 }, 1841 { /* CE_SRC */ 1842 .start_ring_id = HAL_SRNG_CE_0_SRC, 1843 .max_rings = 12, 1844 .entry_size = sizeof(struct ce_src_desc) >> 2, 1845 .lmac_ring = FALSE, 1846 .ring_dir = HAL_SRNG_SRC_RING, 1847 .reg_start = { 1848 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1849 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1850 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1851 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1852 }, 1853 .reg_size = { 1854 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1855 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1856 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1857 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1858 }, 1859 .max_size = 1860 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1861 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1862 }, 1863 { /* CE_DST */ 1864 .start_ring_id = HAL_SRNG_CE_0_DST, 1865 .max_rings = 12, 1866 .entry_size = 8 >> 2, 1867 /*TODO: entry_size above should actually be 1868 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1869 * of struct ce_dst_desc in HW header files 1870 */ 1871 .lmac_ring = FALSE, 1872 .ring_dir = HAL_SRNG_SRC_RING, 1873 .reg_start = { 1874 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1875 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1876 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1877 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1878 }, 1879 .reg_size = { 1880 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1881 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1882 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1883 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1884 }, 1885 .max_size = 1886 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1887 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1888 }, 1889 { /* CE_DST_STATUS */ 1890 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1891 .max_rings = 12, 1892 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1893 .lmac_ring = FALSE, 1894 .ring_dir = HAL_SRNG_DST_RING, 1895 .reg_start = { 1896 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1897 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1898 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1899 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1900 }, 1901 /* TODO: check destination status ring registers */ 1902 .reg_size = { 1903 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1904 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1905 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1906 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1907 }, 1908 .max_size = 1909 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1910 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1911 }, 1912 { /* WBM_IDLE_LINK */ 1913 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1914 .max_rings = 1, 1915 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1916 .lmac_ring = FALSE, 1917 .ring_dir = HAL_SRNG_SRC_RING, 1918 .reg_start = { 1919 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1920 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1921 }, 1922 /* Single ring - provide ring size if multiple rings of this 1923 * type are supported 1924 */ 1925 .reg_size = {}, 1926 .max_size = 1927 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1928 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1929 }, 1930 { /* SW2WBM_RELEASE */ 1931 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1932 .max_rings = 1, 1933 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1934 .lmac_ring = FALSE, 1935 .ring_dir = HAL_SRNG_SRC_RING, 1936 .reg_start = { 1937 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1938 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1939 }, 1940 /* Single ring - provide ring size if multiple rings of this 1941 * type are supported 1942 */ 1943 .reg_size = {}, 1944 .max_size = 1945 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1946 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1947 }, 1948 { /* WBM2SW_RELEASE */ 1949 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1950 .max_rings = 4, 1951 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1952 .lmac_ring = FALSE, 1953 .ring_dir = HAL_SRNG_DST_RING, 1954 .reg_start = { 1955 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1956 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1957 }, 1958 .reg_size = { 1959 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1960 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1961 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1962 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1963 }, 1964 .max_size = 1965 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1966 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1967 }, 1968 { /* RXDMA_BUF */ 1969 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1970 #ifdef IPA_OFFLOAD 1971 .max_rings = 3, 1972 #else 1973 .max_rings = 2, 1974 #endif 1975 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1976 .lmac_ring = TRUE, 1977 .ring_dir = HAL_SRNG_SRC_RING, 1978 /* reg_start is not set because LMAC rings are not accessed 1979 * from host 1980 */ 1981 .reg_start = {}, 1982 .reg_size = {}, 1983 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1984 }, 1985 { /* RXDMA_DST */ 1986 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1987 .max_rings = 1, 1988 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1989 .lmac_ring = TRUE, 1990 .ring_dir = HAL_SRNG_DST_RING, 1991 /* reg_start is not set because LMAC rings are not accessed 1992 * from host 1993 */ 1994 .reg_start = {}, 1995 .reg_size = {}, 1996 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1997 }, 1998 { /* RXDMA_MONITOR_BUF */ 1999 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2000 .max_rings = 1, 2001 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2002 .lmac_ring = TRUE, 2003 .ring_dir = HAL_SRNG_SRC_RING, 2004 /* reg_start is not set because LMAC rings are not accessed 2005 * from host 2006 */ 2007 .reg_start = {}, 2008 .reg_size = {}, 2009 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2010 }, 2011 { /* RXDMA_MONITOR_STATUS */ 2012 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2013 .max_rings = 1, 2014 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2015 .lmac_ring = TRUE, 2016 .ring_dir = HAL_SRNG_SRC_RING, 2017 /* reg_start is not set because LMAC rings are not accessed 2018 * from host 2019 */ 2020 .reg_start = {}, 2021 .reg_size = {}, 2022 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2023 }, 2024 { /* RXDMA_MONITOR_DST */ 2025 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2026 .max_rings = 1, 2027 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2028 .lmac_ring = TRUE, 2029 .ring_dir = HAL_SRNG_DST_RING, 2030 /* reg_start is not set because LMAC rings are not accessed 2031 * from host 2032 */ 2033 .reg_start = {}, 2034 .reg_size = {}, 2035 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2036 }, 2037 { /* RXDMA_MONITOR_DESC */ 2038 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2039 .max_rings = 1, 2040 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2041 .lmac_ring = TRUE, 2042 .ring_dir = HAL_SRNG_SRC_RING, 2043 /* reg_start is not set because LMAC rings are not accessed 2044 * from host 2045 */ 2046 .reg_start = {}, 2047 .reg_size = {}, 2048 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2049 }, 2050 { /* DIR_BUF_RX_DMA_SRC */ 2051 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2052 /* one ring for spectral and one ring for cfr */ 2053 .max_rings = 2, 2054 .entry_size = 2, 2055 .lmac_ring = TRUE, 2056 .ring_dir = HAL_SRNG_SRC_RING, 2057 /* reg_start is not set because LMAC rings are not accessed 2058 * from host 2059 */ 2060 .reg_start = {}, 2061 .reg_size = {}, 2062 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2063 }, 2064 #ifdef WLAN_FEATURE_CIF_CFR 2065 { /* WIFI_POS_SRC */ 2066 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2067 .max_rings = 1, 2068 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2069 .lmac_ring = TRUE, 2070 .ring_dir = HAL_SRNG_SRC_RING, 2071 /* reg_start is not set because LMAC rings are not accessed 2072 * from host 2073 */ 2074 .reg_start = {}, 2075 .reg_size = {}, 2076 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2077 }, 2078 #endif 2079 }; 2080 2081 int32_t hal_hw_reg_offset_qca5018[] = { 2082 /* dst */ 2083 REG_OFFSET(DST, HP), 2084 REG_OFFSET(DST, TP), 2085 REG_OFFSET(DST, ID), 2086 REG_OFFSET(DST, MISC), 2087 REG_OFFSET(DST, HP_ADDR_LSB), 2088 REG_OFFSET(DST, HP_ADDR_MSB), 2089 REG_OFFSET(DST, MSI1_BASE_LSB), 2090 REG_OFFSET(DST, MSI1_BASE_MSB), 2091 REG_OFFSET(DST, MSI1_DATA), 2092 REG_OFFSET(DST, BASE_LSB), 2093 REG_OFFSET(DST, BASE_MSB), 2094 REG_OFFSET(DST, PRODUCER_INT_SETUP), 2095 /* src */ 2096 REG_OFFSET(SRC, HP), 2097 REG_OFFSET(SRC, TP), 2098 REG_OFFSET(SRC, ID), 2099 REG_OFFSET(SRC, MISC), 2100 REG_OFFSET(SRC, TP_ADDR_LSB), 2101 REG_OFFSET(SRC, TP_ADDR_MSB), 2102 REG_OFFSET(SRC, MSI1_BASE_LSB), 2103 REG_OFFSET(SRC, MSI1_BASE_MSB), 2104 REG_OFFSET(SRC, MSI1_DATA), 2105 REG_OFFSET(SRC, BASE_LSB), 2106 REG_OFFSET(SRC, BASE_MSB), 2107 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 2108 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 2109 }; 2110 2111 /** 2112 * hal_qca5018_attach()- Attach 5018 target specific hal_soc ops, 2113 * offset and srng table 2114 * Return: void 2115 */ 2116 void hal_qca5018_attach(struct hal_soc *hal_soc) 2117 { 2118 hal_soc->hw_srng_table = hw_srng_table_5018; 2119 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca5018; 2120 hal_soc->ops = &qca5018_hal_hw_txrx_ops; 2121 } 2122