1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "hal_li_hw_headers.h" 20 #include "hal_internal.h" 21 #include "hal_api.h" 22 #include "target_type.h" 23 #include "wcss_version.h" 24 #include "qdf_module.h" 25 #include "hal_flow.h" 26 #include "rx_flow_search_entry.h" 27 #include "hal_rx_flow_info.h" 28 29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 30 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 32 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 34 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 35 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \ 36 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 37 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \ 38 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 39 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \ 40 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 41 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 42 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 43 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 44 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 45 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 46 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 47 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 48 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 59 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 60 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 61 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 62 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 63 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 64 RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 65 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 66 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 67 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 68 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 69 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 71 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 72 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 73 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 74 STATUS_HEADER_REO_STATUS_NUMBER 75 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 76 STATUS_HEADER_TIMESTAMP 77 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 78 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 79 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 80 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 81 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 82 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 83 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 84 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 85 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 86 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 87 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 88 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 90 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 92 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 94 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 95 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 96 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 97 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 98 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 99 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 100 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 101 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 102 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 103 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 104 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 105 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 106 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 107 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 108 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 109 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 110 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 112 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 113 114 #define CE_WINDOW_ADDRESS_5018 \ 115 ((WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 116 117 #define UMAC_WINDOW_ADDRESS_5018 \ 118 ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 119 120 #define WINDOW_CONFIGURATION_VALUE_5018 \ 121 ((CE_WINDOW_ADDRESS_5018 << 6) |\ 122 (UMAC_WINDOW_ADDRESS_5018 << 12) | \ 123 WINDOW_ENABLE_BIT) 124 125 #define HOST_CE_MASK_VALUE 0xFF000000 126 127 #include "hal_5018_tx.h" 128 #include "hal_5018_rx.h" 129 #include <hal_generic_api.h> 130 #include "hal_li_rx.h" 131 #include "hal_li_api.h" 132 #include "hal_li_generic_api.h" 133 134 /** 135 * hal_rx_msdu_start_nss_get_5018() - API to get the NSS 136 * Interval from rx_msdu_start 137 * @buf: pointer to the start of RX PKT TLV header 138 * 139 * Return: uint32_t(nss) 140 */ 141 static uint32_t hal_rx_msdu_start_nss_get_5018(uint8_t *buf) 142 { 143 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 144 struct rx_msdu_start *msdu_start = 145 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 146 uint8_t mimo_ss_bitmap; 147 148 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 149 150 return qdf_get_hweight8(mimo_ss_bitmap); 151 } 152 153 /** 154 * hal_rx_msdu_start_get_len_5018() - API to get the MSDU length 155 * from rx_msdu_start TLV 156 * @buf: pointer to the start of RX PKT TLV headers 157 * 158 * Return: (uint32_t)msdu length 159 */ 160 static uint32_t hal_rx_msdu_start_get_len_5018(uint8_t *buf) 161 { 162 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 163 struct rx_msdu_start *msdu_start = 164 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 165 uint32_t msdu_len; 166 167 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 168 169 return msdu_len; 170 } 171 172 /** 173 * hal_rx_mon_hw_desc_get_mpdu_status_5018() - Retrieve MPDU status 174 * 175 * @hw_desc_addr: Start address of Rx HW TLVs 176 * @rs: Status for monitor mode 177 * 178 * Return: void 179 */ 180 static void hal_rx_mon_hw_desc_get_mpdu_status_5018(void *hw_desc_addr, 181 struct mon_rx_status *rs) 182 { 183 struct rx_msdu_start *rx_msdu_start; 184 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 185 uint32_t reg_value; 186 const uint32_t sgi_hw_to_cdp[] = { 187 CDP_SGI_0_8_US, 188 CDP_SGI_0_4_US, 189 CDP_SGI_1_6_US, 190 CDP_SGI_3_2_US, 191 }; 192 193 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 194 195 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 196 197 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 198 RX_MSDU_START_5, USER_RSSI); 199 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 200 201 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 202 rs->sgi = sgi_hw_to_cdp[reg_value]; 203 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 204 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 205 /* TODO: rs->beamformed should be set for SU beamforming also */ 206 } 207 208 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 209 /** 210 * hal_get_link_desc_size_5018() - API to get the link desc size 211 * 212 * Return: uint32_t 213 */ 214 static uint32_t hal_get_link_desc_size_5018(void) 215 { 216 return LINK_DESC_SIZE; 217 } 218 219 /** 220 * hal_rx_get_tlv_5018() - API to get the tlv 221 * @rx_tlv: TLV data extracted from the rx packet 222 * 223 * Return: uint8_t 224 */ 225 static uint8_t hal_rx_get_tlv_5018(void *rx_tlv) 226 { 227 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 228 } 229 230 /** 231 * hal_rx_mpdu_start_tlv_tag_valid_5018() - API to check if RX_MPDU_START 232 * tlv tag is valid 233 * 234 * @rx_tlv_hdr: start address of rx_pkt_tlvs 235 * 236 * Return: true if RX_MPDU_START is valid, else false. 237 */ 238 uint8_t hal_rx_mpdu_start_tlv_tag_valid_5018(void *rx_tlv_hdr) 239 { 240 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 241 uint32_t tlv_tag; 242 243 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 244 245 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 246 } 247 248 /** 249 * hal_rx_wbm_err_msdu_continuation_get_5018() - API to check if WBM 250 * msdu continuation bit is set 251 * 252 * @wbm_desc: wbm release ring descriptor 253 * 254 * Return: true if msdu continuation bit is set. 255 */ 256 uint8_t hal_rx_wbm_err_msdu_continuation_get_5018(void *wbm_desc) 257 { 258 uint32_t comp_desc = 259 *(uint32_t *)(((uint8_t *)wbm_desc) + 260 WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET); 261 262 return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >> 263 WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB; 264 } 265 266 static 267 void hal_compute_reo_remap_ix2_ix3_5018(uint32_t *ring, uint32_t num_rings, 268 uint32_t *remap1, uint32_t *remap2) 269 { 270 switch (num_rings) { 271 case 1: 272 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 273 HAL_REO_REMAP_IX2(ring[0], 17) | 274 HAL_REO_REMAP_IX2(ring[0], 18) | 275 HAL_REO_REMAP_IX2(ring[0], 19) | 276 HAL_REO_REMAP_IX2(ring[0], 20) | 277 HAL_REO_REMAP_IX2(ring[0], 21) | 278 HAL_REO_REMAP_IX2(ring[0], 22) | 279 HAL_REO_REMAP_IX2(ring[0], 23); 280 281 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 282 HAL_REO_REMAP_IX3(ring[0], 25) | 283 HAL_REO_REMAP_IX3(ring[0], 26) | 284 HAL_REO_REMAP_IX3(ring[0], 27) | 285 HAL_REO_REMAP_IX3(ring[0], 28) | 286 HAL_REO_REMAP_IX3(ring[0], 29) | 287 HAL_REO_REMAP_IX3(ring[0], 30) | 288 HAL_REO_REMAP_IX3(ring[0], 31); 289 break; 290 case 2: 291 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 292 HAL_REO_REMAP_IX2(ring[0], 17) | 293 HAL_REO_REMAP_IX2(ring[1], 18) | 294 HAL_REO_REMAP_IX2(ring[1], 19) | 295 HAL_REO_REMAP_IX2(ring[0], 20) | 296 HAL_REO_REMAP_IX2(ring[0], 21) | 297 HAL_REO_REMAP_IX2(ring[1], 22) | 298 HAL_REO_REMAP_IX2(ring[1], 23); 299 300 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 301 HAL_REO_REMAP_IX3(ring[0], 25) | 302 HAL_REO_REMAP_IX3(ring[1], 26) | 303 HAL_REO_REMAP_IX3(ring[1], 27) | 304 HAL_REO_REMAP_IX3(ring[0], 28) | 305 HAL_REO_REMAP_IX3(ring[0], 29) | 306 HAL_REO_REMAP_IX3(ring[1], 30) | 307 HAL_REO_REMAP_IX3(ring[1], 31); 308 break; 309 case 3: 310 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 311 HAL_REO_REMAP_IX2(ring[1], 17) | 312 HAL_REO_REMAP_IX2(ring[2], 18) | 313 HAL_REO_REMAP_IX2(ring[0], 19) | 314 HAL_REO_REMAP_IX2(ring[1], 20) | 315 HAL_REO_REMAP_IX2(ring[2], 21) | 316 HAL_REO_REMAP_IX2(ring[0], 22) | 317 HAL_REO_REMAP_IX2(ring[1], 23); 318 319 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 320 HAL_REO_REMAP_IX3(ring[0], 25) | 321 HAL_REO_REMAP_IX3(ring[1], 26) | 322 HAL_REO_REMAP_IX3(ring[2], 27) | 323 HAL_REO_REMAP_IX3(ring[0], 28) | 324 HAL_REO_REMAP_IX3(ring[1], 29) | 325 HAL_REO_REMAP_IX3(ring[2], 30) | 326 HAL_REO_REMAP_IX3(ring[0], 31); 327 break; 328 case 4: 329 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 330 HAL_REO_REMAP_IX2(ring[1], 17) | 331 HAL_REO_REMAP_IX2(ring[2], 18) | 332 HAL_REO_REMAP_IX2(ring[3], 19) | 333 HAL_REO_REMAP_IX2(ring[0], 20) | 334 HAL_REO_REMAP_IX2(ring[1], 21) | 335 HAL_REO_REMAP_IX2(ring[2], 22) | 336 HAL_REO_REMAP_IX2(ring[3], 23); 337 338 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 339 HAL_REO_REMAP_IX3(ring[1], 25) | 340 HAL_REO_REMAP_IX3(ring[2], 26) | 341 HAL_REO_REMAP_IX3(ring[3], 27) | 342 HAL_REO_REMAP_IX3(ring[0], 28) | 343 HAL_REO_REMAP_IX3(ring[1], 29) | 344 HAL_REO_REMAP_IX3(ring[2], 30) | 345 HAL_REO_REMAP_IX3(ring[3], 31); 346 break; 347 } 348 } 349 350 /** 351 * hal_rx_proc_phyrx_other_receive_info_tlv_5018() - API to get tlv info 352 * @rx_tlv_hdr: start address of rx_pkt_tlvs 353 * @ppdu_info_hdl: PPDU info handle to fill 354 * 355 * Return: uint32_t 356 */ 357 static inline 358 void hal_rx_proc_phyrx_other_receive_info_tlv_5018(void *rx_tlv_hdr, 359 void *ppdu_info_hdl) 360 { 361 } 362 363 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 364 static inline 365 void hal_rx_get_bb_info_5018(void *rx_tlv, 366 void *ppdu_info_hdl) 367 { 368 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 369 370 ppdu_info->cfr_info.bb_captured_channel = 371 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); 372 373 ppdu_info->cfr_info.bb_captured_timeout = 374 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); 375 376 ppdu_info->cfr_info.bb_captured_reason = 377 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); 378 } 379 380 static inline 381 void hal_rx_get_rtt_info_5018(void *rx_tlv, 382 void *ppdu_info_hdl) 383 { 384 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 385 386 ppdu_info->cfr_info.rx_location_info_valid = 387 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, 388 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 389 390 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 391 HAL_RX_GET(rx_tlv, 392 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 393 RTT_CHE_BUFFER_POINTER_LOW32); 394 395 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 396 HAL_RX_GET(rx_tlv, 397 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 398 RTT_CHE_BUFFER_POINTER_HIGH8); 399 400 ppdu_info->cfr_info.chan_capture_status = 401 HAL_RX_GET(rx_tlv, 402 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 403 RESERVED_8); 404 } 405 #endif 406 407 /** 408 * hal_rx_dump_msdu_start_tlv_5018() - dump RX msdu_start TLV in structured 409 * human readable format. 410 * @msdustart: pointer the msdu_start TLV in pkt. 411 * @dbg_level: log level. 412 * 413 * Return: void 414 */ 415 static void hal_rx_dump_msdu_start_tlv_5018(void *msdustart, 416 uint8_t dbg_level) 417 { 418 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 419 420 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 421 "rx_msdu_start tlv - " 422 "rxpcu_mpdu_filter_in_category: %d " 423 "sw_frame_group_id: %d " 424 "phy_ppdu_id: %d " 425 "msdu_length: %d " 426 "ipsec_esp: %d " 427 "l3_offset: %d " 428 "ipsec_ah: %d " 429 "l4_offset: %d " 430 "msdu_number: %d " 431 "decap_format: %d " 432 "ipv4_proto: %d " 433 "ipv6_proto: %d " 434 "tcp_proto: %d " 435 "udp_proto: %d " 436 "ip_frag: %d " 437 "tcp_only_ack: %d " 438 "da_is_bcast_mcast: %d " 439 "ip4_protocol_ip6_next_header: %d " 440 "toeplitz_hash_2_or_4: %d " 441 "flow_id_toeplitz: %d " 442 "user_rssi: %d " 443 "pkt_type: %d " 444 "stbc: %d " 445 "sgi: %d " 446 "rate_mcs: %d " 447 "receive_bandwidth: %d " 448 "reception_type: %d " 449 "ppdu_start_timestamp: %d " 450 "sw_phy_meta_data: %d ", 451 msdu_start->rxpcu_mpdu_filter_in_category, 452 msdu_start->sw_frame_group_id, 453 msdu_start->phy_ppdu_id, 454 msdu_start->msdu_length, 455 msdu_start->ipsec_esp, 456 msdu_start->l3_offset, 457 msdu_start->ipsec_ah, 458 msdu_start->l4_offset, 459 msdu_start->msdu_number, 460 msdu_start->decap_format, 461 msdu_start->ipv4_proto, 462 msdu_start->ipv6_proto, 463 msdu_start->tcp_proto, 464 msdu_start->udp_proto, 465 msdu_start->ip_frag, 466 msdu_start->tcp_only_ack, 467 msdu_start->da_is_bcast_mcast, 468 msdu_start->ip4_protocol_ip6_next_header, 469 msdu_start->toeplitz_hash_2_or_4, 470 msdu_start->flow_id_toeplitz, 471 msdu_start->user_rssi, 472 msdu_start->pkt_type, 473 msdu_start->stbc, 474 msdu_start->sgi, 475 msdu_start->rate_mcs, 476 msdu_start->receive_bandwidth, 477 msdu_start->reception_type, 478 msdu_start->ppdu_start_timestamp, 479 msdu_start->sw_phy_meta_data); 480 } 481 482 /** 483 * hal_rx_dump_msdu_end_tlv_5018() - dump RX msdu_end TLV in structured 484 * human readable format. 485 * @msduend: pointer the msdu_end TLV in pkt. 486 * @dbg_level: log level. 487 * 488 * Return: void 489 */ 490 static void hal_rx_dump_msdu_end_tlv_5018(void *msduend, 491 uint8_t dbg_level) 492 { 493 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 494 495 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 496 "rx_msdu_end tlv - " 497 "rxpcu_mpdu_filter_in_category: %d " 498 "sw_frame_group_id: %d " 499 "phy_ppdu_id: %d " 500 "ip_hdr_chksum: %d " 501 "reported_mpdu_length: %d " 502 "key_id_octet: %d " 503 "cce_super_rule: %d " 504 "cce_classify_not_done_truncat: %d " 505 "cce_classify_not_done_cce_dis: %d " 506 "rule_indication_31_0: %d " 507 "rule_indication_63_32: %d " 508 "da_offset: %d " 509 "sa_offset: %d " 510 "da_offset_valid: %d " 511 "sa_offset_valid: %d " 512 "ipv6_options_crc: %d " 513 "tcp_seq_number: %d " 514 "tcp_ack_number: %d " 515 "tcp_flag: %d " 516 "lro_eligible: %d " 517 "window_size: %d " 518 "tcp_udp_chksum: %d " 519 "sa_idx_timeout: %d " 520 "da_idx_timeout: %d " 521 "msdu_limit_error: %d " 522 "flow_idx_timeout: %d " 523 "flow_idx_invalid: %d " 524 "wifi_parser_error: %d " 525 "amsdu_parser_error: %d " 526 "sa_is_valid: %d " 527 "da_is_valid: %d " 528 "da_is_mcbc: %d " 529 "l3_header_padding: %d " 530 "first_msdu: %d " 531 "last_msdu: %d " 532 "sa_idx: %d " 533 "msdu_drop: %d " 534 "reo_destination_indication: %d " 535 "flow_idx: %d " 536 "fse_metadata: %d " 537 "cce_metadata: %d " 538 "sa_sw_peer_id: %d ", 539 msdu_end->rxpcu_mpdu_filter_in_category, 540 msdu_end->sw_frame_group_id, 541 msdu_end->phy_ppdu_id, 542 msdu_end->ip_hdr_chksum, 543 msdu_end->reported_mpdu_length, 544 msdu_end->key_id_octet, 545 msdu_end->cce_super_rule, 546 msdu_end->cce_classify_not_done_truncate, 547 msdu_end->cce_classify_not_done_cce_dis, 548 msdu_end->rule_indication_31_0, 549 msdu_end->rule_indication_63_32, 550 msdu_end->da_offset, 551 msdu_end->sa_offset, 552 msdu_end->da_offset_valid, 553 msdu_end->sa_offset_valid, 554 msdu_end->ipv6_options_crc, 555 msdu_end->tcp_seq_number, 556 msdu_end->tcp_ack_number, 557 msdu_end->tcp_flag, 558 msdu_end->lro_eligible, 559 msdu_end->window_size, 560 msdu_end->tcp_udp_chksum, 561 msdu_end->sa_idx_timeout, 562 msdu_end->da_idx_timeout, 563 msdu_end->msdu_limit_error, 564 msdu_end->flow_idx_timeout, 565 msdu_end->flow_idx_invalid, 566 msdu_end->wifi_parser_error, 567 msdu_end->amsdu_parser_error, 568 msdu_end->sa_is_valid, 569 msdu_end->da_is_valid, 570 msdu_end->da_is_mcbc, 571 msdu_end->l3_header_padding, 572 msdu_end->first_msdu, 573 msdu_end->last_msdu, 574 msdu_end->sa_idx, 575 msdu_end->msdu_drop, 576 msdu_end->reo_destination_indication, 577 msdu_end->flow_idx, 578 msdu_end->fse_metadata, 579 msdu_end->cce_metadata, 580 msdu_end->sa_sw_peer_id); 581 } 582 583 /** 584 * hal_rx_mpdu_start_tid_get_5018() - API to get tid from rx_msdu_start 585 * @buf: pointer to the start of RX PKT TLV header 586 * 587 * Return: uint32_t(tid value) 588 */ 589 static uint32_t hal_rx_mpdu_start_tid_get_5018(uint8_t *buf) 590 { 591 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 592 struct rx_mpdu_start *mpdu_start = 593 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 594 uint32_t tid; 595 596 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 597 598 return tid; 599 } 600 601 /** 602 * hal_rx_msdu_start_reception_type_get_5018() - API to get the reception type 603 * Interval from rx_msdu_start 604 * @buf: pointer to the start of RX PKT TLV header 605 * 606 * Return: uint32_t(reception_type) 607 */ 608 static uint32_t hal_rx_msdu_start_reception_type_get_5018(uint8_t *buf) 609 { 610 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 611 struct rx_msdu_start *msdu_start = 612 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 613 uint32_t reception_type; 614 615 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 616 617 return reception_type; 618 } 619 620 /** 621 * hal_rx_msdu_end_da_idx_get_5018() - API to get da_idx from rx_msdu_end TLV 622 * @buf: pointer to the start of RX PKT TLV headers 623 * 624 * Return: da index 625 */ 626 static uint16_t hal_rx_msdu_end_da_idx_get_5018(uint8_t *buf) 627 { 628 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 629 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 630 uint16_t da_idx; 631 632 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 633 634 return da_idx; 635 } 636 637 /** 638 * hal_rx_get_rx_fragment_number_5018() - API to retrieve rx fragment number 639 * @buf: Network buffer 640 * 641 * Return: rx fragment number 642 */ 643 static 644 uint8_t hal_rx_get_rx_fragment_number_5018(uint8_t *buf) 645 { 646 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 647 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 648 649 /* Return first 4 bits as fragment number */ 650 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 651 DOT11_SEQ_FRAG_MASK); 652 } 653 654 /** 655 * hal_rx_msdu_end_da_is_mcbc_get_5018() - API to check if pkt is MCBC 656 * from rx_msdu_end TLV 657 * @buf: pointer to the start of RX PKT TLV headers 658 * 659 * Return: da_is_mcbc 660 */ 661 static uint8_t 662 hal_rx_msdu_end_da_is_mcbc_get_5018(uint8_t *buf) 663 { 664 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 665 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 666 667 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 668 } 669 670 /** 671 * hal_rx_msdu_end_sa_is_valid_get_5018() - API to get_5018 the sa_is_valid 672 * bit from rx_msdu_end TLV 673 * @buf: pointer to the start of RX PKT TLV headers 674 * 675 * Return: sa_is_valid bit 676 */ 677 static uint8_t 678 hal_rx_msdu_end_sa_is_valid_get_5018(uint8_t *buf) 679 { 680 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 681 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 682 uint8_t sa_is_valid; 683 684 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 685 686 return sa_is_valid; 687 } 688 689 /** 690 * hal_rx_msdu_end_sa_idx_get_5018() - API to get_5018 the sa_idx from 691 * rx_msdu_end TLV 692 * @buf: pointer to the start of RX PKT TLV headers 693 * 694 * Return: sa_idx (SA AST index) 695 */ 696 static uint16_t hal_rx_msdu_end_sa_idx_get_5018(uint8_t *buf) 697 { 698 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 699 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 700 uint16_t sa_idx; 701 702 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 703 704 return sa_idx; 705 } 706 707 /** 708 * hal_rx_desc_is_first_msdu_5018() - Check if first msdu 709 * @hw_desc_addr: hardware descriptor address 710 * 711 * Return: 0 - success/ non-zero failure 712 */ 713 static uint32_t hal_rx_desc_is_first_msdu_5018(void *hw_desc_addr) 714 { 715 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 716 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 717 718 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 719 } 720 721 /** 722 * hal_rx_msdu_end_l3_hdr_padding_get_5018() - API to get_5018 the 723 * l3_header padding from 724 * rx_msdu_end TLV 725 * @buf: pointer to the start of RX PKT TLV headers 726 * 727 * Return: number of l3 header padding bytes 728 */ 729 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_5018(uint8_t *buf) 730 { 731 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 732 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 733 uint32_t l3_header_padding; 734 735 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 736 737 return l3_header_padding; 738 } 739 740 /** 741 * hal_rx_encryption_info_valid_5018() - Returns encryption type. 742 * @buf: rx_tlv_hdr of the received packet 743 * 744 * Return: encryption type 745 */ 746 inline uint32_t hal_rx_encryption_info_valid_5018(uint8_t *buf) 747 { 748 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 749 struct rx_mpdu_start *mpdu_start = 750 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 751 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 752 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 753 754 return encryption_info; 755 } 756 757 /** 758 * hal_rx_print_pn_5018() - Prints the PN of rx packet. 759 * @buf: rx_tlv_hdr of the received packet 760 * 761 * Return: void 762 */ 763 static void hal_rx_print_pn_5018(uint8_t *buf) 764 { 765 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 766 struct rx_mpdu_start *mpdu_start = 767 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 768 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 769 770 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 771 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 772 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 773 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 774 775 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x", 776 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 777 } 778 779 /** 780 * hal_rx_msdu_end_first_msdu_get_5018() - API to get first msdu status 781 * from rx_msdu_end TLV 782 * @buf: pointer to the start of RX PKT TLV headers 783 * 784 * Return: first_msdu 785 */ 786 static uint8_t hal_rx_msdu_end_first_msdu_get_5018(uint8_t *buf) 787 { 788 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 789 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 790 uint8_t first_msdu; 791 792 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 793 794 return first_msdu; 795 } 796 797 /** 798 * hal_rx_msdu_end_da_is_valid_get_5018() - API to check if da is valid 799 * from rx_msdu_end TLV 800 * @buf: pointer to the start of RX PKT TLV headers 801 * 802 * Return: da_is_valid 803 */ 804 static uint8_t hal_rx_msdu_end_da_is_valid_get_5018(uint8_t *buf) 805 { 806 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 807 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 808 uint8_t da_is_valid; 809 810 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 811 812 return da_is_valid; 813 } 814 815 /** 816 * hal_rx_msdu_end_last_msdu_get_5018() - API to get last msdu status 817 * from rx_msdu_end TLV 818 * @buf: pointer to the start of RX PKT TLV headers 819 * 820 * Return: last_msdu 821 */ 822 static uint8_t hal_rx_msdu_end_last_msdu_get_5018(uint8_t *buf) 823 { 824 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 825 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 826 uint8_t last_msdu; 827 828 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 829 830 return last_msdu; 831 } 832 833 /** 834 * hal_rx_get_mpdu_mac_ad4_valid_5018() - Retrieves if mpdu 4th addr is valid 835 * @buf: Network buffer 836 * 837 * Return: value of mpdu 4th address valid field 838 */ 839 inline bool hal_rx_get_mpdu_mac_ad4_valid_5018(uint8_t *buf) 840 { 841 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 842 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 843 bool ad4_valid = 0; 844 845 ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info); 846 847 return ad4_valid; 848 } 849 850 /** 851 * hal_rx_mpdu_start_sw_peer_id_get_5018() - Retrieve sw peer_id 852 * @buf: network buffer 853 * 854 * Return: sw peer_id 855 */ 856 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_5018(uint8_t *buf) 857 { 858 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 859 struct rx_mpdu_start *mpdu_start = 860 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 861 862 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 863 &mpdu_start->rx_mpdu_info_details); 864 } 865 866 /** 867 * hal_rx_mpdu_get_to_ds_5018() - API to get the tods info from 868 * rx_mpdu_start 869 * @buf: pointer to the start of RX PKT TLV header 870 * 871 * Return: uint32_t(to_ds) 872 */ 873 static uint32_t hal_rx_mpdu_get_to_ds_5018(uint8_t *buf) 874 { 875 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 876 struct rx_mpdu_start *mpdu_start = 877 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 878 879 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 880 881 return HAL_RX_MPDU_GET_TODS(mpdu_info); 882 } 883 884 /** 885 * hal_rx_mpdu_get_fr_ds_5018() - API to get the from ds info from 886 * rx_mpdu_start 887 * @buf: pointer to the start of RX PKT TLV header 888 * 889 * Return: uint32_t(fr_ds) 890 */ 891 static uint32_t hal_rx_mpdu_get_fr_ds_5018(uint8_t *buf) 892 { 893 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 894 struct rx_mpdu_start *mpdu_start = 895 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 896 897 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 898 899 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 900 } 901 902 /** 903 * hal_rx_get_mpdu_frame_control_valid_5018() - Retrieves mpdu frame 904 * control valid 905 * @buf: Network buffer 906 * 907 * Return: value of frame control valid field 908 */ 909 static uint8_t hal_rx_get_mpdu_frame_control_valid_5018(uint8_t *buf) 910 { 911 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 912 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 913 914 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 915 } 916 917 /** 918 * hal_rx_get_mpdu_frame_control_field_5018() - Function to retrieve 919 * frame control field 920 * @buf: Network buffer 921 * 922 * Return: value of frame control field 923 */ 924 static uint16_t hal_rx_get_mpdu_frame_control_field_5018(uint8_t *buf) 925 { 926 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 927 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 928 uint16_t frame_ctrl = 0; 929 930 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 931 932 return frame_ctrl; 933 } 934 935 /** 936 * hal_rx_mpdu_get_addr1_5018() - API to check get address1 of the mpdu 937 * @buf: pointer to the start of RX PKT TLV headera 938 * @mac_addr: pointer to mac address 939 * 940 * Return: success/failure 941 */ 942 static QDF_STATUS hal_rx_mpdu_get_addr1_5018(uint8_t *buf, 943 uint8_t *mac_addr) 944 { 945 struct __attribute__((__packed__)) hal_addr1 { 946 uint32_t ad1_31_0; 947 uint16_t ad1_47_32; 948 }; 949 950 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 951 struct rx_mpdu_start *mpdu_start = 952 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 953 954 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 955 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 956 uint32_t mac_addr_ad1_valid; 957 958 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 959 960 if (mac_addr_ad1_valid) { 961 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 962 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 963 return QDF_STATUS_SUCCESS; 964 } 965 966 return QDF_STATUS_E_FAILURE; 967 } 968 969 /** 970 * hal_rx_mpdu_get_addr2_5018() - API to check get address2 of the mpdu 971 * in the packet 972 * @buf: pointer to the start of RX PKT TLV header 973 * @mac_addr: pointer to mac address 974 * 975 * Return: success/failure 976 */ 977 static QDF_STATUS hal_rx_mpdu_get_addr2_5018(uint8_t *buf, uint8_t *mac_addr) 978 { 979 struct __attribute__((__packed__)) hal_addr2 { 980 uint16_t ad2_15_0; 981 uint32_t ad2_47_16; 982 }; 983 984 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 985 struct rx_mpdu_start *mpdu_start = 986 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 987 988 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 989 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 990 uint32_t mac_addr_ad2_valid; 991 992 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 993 994 if (mac_addr_ad2_valid) { 995 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 996 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 997 return QDF_STATUS_SUCCESS; 998 } 999 1000 return QDF_STATUS_E_FAILURE; 1001 } 1002 1003 /** 1004 * hal_rx_mpdu_get_addr3_5018() - API to get address3 of the mpdu 1005 * in the packet 1006 * @buf: pointer to the start of RX PKT TLV header 1007 * @mac_addr: pointer to mac address 1008 * 1009 * Return: success/failure 1010 */ 1011 static QDF_STATUS hal_rx_mpdu_get_addr3_5018(uint8_t *buf, uint8_t *mac_addr) 1012 { 1013 struct __attribute__((__packed__)) hal_addr3 { 1014 uint32_t ad3_31_0; 1015 uint16_t ad3_47_32; 1016 }; 1017 1018 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1019 struct rx_mpdu_start *mpdu_start = 1020 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1021 1022 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1023 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 1024 uint32_t mac_addr_ad3_valid; 1025 1026 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 1027 1028 if (mac_addr_ad3_valid) { 1029 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 1030 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 1031 return QDF_STATUS_SUCCESS; 1032 } 1033 1034 return QDF_STATUS_E_FAILURE; 1035 } 1036 1037 /** 1038 * hal_rx_mpdu_get_addr4_5018() - API to get address4 of the mpdu 1039 * in the packet 1040 * @buf: pointer to the start of RX PKT TLV header 1041 * @mac_addr: pointer to mac address 1042 * 1043 * Return: success/failure 1044 */ 1045 static QDF_STATUS hal_rx_mpdu_get_addr4_5018(uint8_t *buf, uint8_t *mac_addr) 1046 { 1047 struct __attribute__((__packed__)) hal_addr4 { 1048 uint32_t ad4_31_0; 1049 uint16_t ad4_47_32; 1050 }; 1051 1052 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1053 struct rx_mpdu_start *mpdu_start = 1054 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1055 1056 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1057 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 1058 uint32_t mac_addr_ad4_valid; 1059 1060 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 1061 1062 if (mac_addr_ad4_valid) { 1063 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 1064 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 1065 return QDF_STATUS_SUCCESS; 1066 } 1067 1068 return QDF_STATUS_E_FAILURE; 1069 } 1070 1071 /** 1072 * hal_rx_get_mpdu_sequence_control_valid_5018() - Get mpdu sequence 1073 * control valid 1074 * @buf: Network buffer 1075 * 1076 * Return: value of sequence control valid field 1077 */ 1078 static uint8_t hal_rx_get_mpdu_sequence_control_valid_5018(uint8_t *buf) 1079 { 1080 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1081 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1082 1083 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 1084 } 1085 1086 /** 1087 * hal_rx_is_unicast_5018() - check packet is unicast frame or not. 1088 * @buf: pointer to rx pkt TLV. 1089 * 1090 * Return: true on unicast. 1091 */ 1092 static bool hal_rx_is_unicast_5018(uint8_t *buf) 1093 { 1094 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1095 struct rx_mpdu_start *mpdu_start = 1096 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1097 uint32_t grp_id; 1098 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1099 1100 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1101 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 1102 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 1103 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 1104 1105 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 1106 } 1107 1108 /** 1109 * hal_rx_tid_get_5018() - get tid based on qos control valid. 1110 * @hal_soc_hdl: hal soc handle 1111 * @buf: pointer to rx pkt TLV. 1112 * 1113 * Return: tid 1114 */ 1115 static uint32_t hal_rx_tid_get_5018(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1116 { 1117 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1118 struct rx_mpdu_start *mpdu_start = 1119 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1120 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1121 uint8_t qos_control_valid = 1122 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1123 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 1124 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 1125 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 1126 1127 if (qos_control_valid) 1128 return hal_rx_mpdu_start_tid_get_5018(buf); 1129 1130 return HAL_RX_NON_QOS_TID; 1131 } 1132 1133 /** 1134 * hal_rx_hw_desc_get_ppduid_get_5018() - retrieve ppdu id 1135 * @rx_tlv_hdr: rx tlv header 1136 * @rxdma_dst_ring_desc: rxdma HW descriptor 1137 * 1138 * Return: ppdu id 1139 */ 1140 static uint32_t hal_rx_hw_desc_get_ppduid_get_5018(void *rx_tlv_hdr, 1141 void *rxdma_dst_ring_desc) 1142 { 1143 struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc; 1144 1145 return HAL_RX_REO_ENT_PHY_PPDU_ID_GET(reo_ent); 1146 } 1147 1148 /** 1149 * hal_reo_status_get_header_5018() - Process reo desc info 1150 * @ring_desc: REO status ring descriptor 1151 * @b: tlv type info 1152 * @h1: Pointer to hal_reo_status_header where info to be stored 1153 * 1154 * Return - none. 1155 * 1156 */ 1157 static void hal_reo_status_get_header_5018(hal_ring_desc_t ring_desc, int b, 1158 void *h1) 1159 { 1160 uint32_t *d = (uint32_t *)ring_desc; 1161 uint32_t val1 = 0; 1162 struct hal_reo_status_header *h = 1163 (struct hal_reo_status_header *)h1; 1164 1165 /* Offsets of descriptor fields defined in HW headers start 1166 * from the field after TLV header 1167 */ 1168 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 1169 1170 switch (b) { 1171 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1172 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1173 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1174 break; 1175 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1176 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1177 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1178 break; 1179 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1180 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1181 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1182 break; 1183 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1184 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1185 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1186 break; 1187 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1188 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1189 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1190 break; 1191 case HAL_REO_DESC_THRES_STATUS_TLV: 1192 val1 = 1193 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1194 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1195 break; 1196 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1197 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1198 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1199 break; 1200 default: 1201 qdf_nofl_err("ERROR: Unknown tlv\n"); 1202 break; 1203 } 1204 h->cmd_num = 1205 HAL_GET_FIELD( 1206 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1207 val1); 1208 h->exec_time = 1209 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1210 CMD_EXECUTION_TIME, val1); 1211 h->status = 1212 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1213 REO_CMD_EXECUTION_STATUS, val1); 1214 switch (b) { 1215 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1216 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1217 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1218 break; 1219 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1220 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1221 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1222 break; 1223 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1224 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1225 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1226 break; 1227 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1228 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1229 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1230 break; 1231 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1232 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1233 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1234 break; 1235 case HAL_REO_DESC_THRES_STATUS_TLV: 1236 val1 = 1237 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1238 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1239 break; 1240 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1241 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1242 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1243 break; 1244 default: 1245 qdf_nofl_err("ERROR: Unknown tlv\n"); 1246 break; 1247 } 1248 h->tstamp = 1249 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1250 } 1251 1252 /** 1253 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(): 1254 * Retrieve qos control valid bit from the tlv. 1255 * @buf: pointer to rx pkt TLV. 1256 * 1257 * Return: qos control value. 1258 */ 1259 static inline uint32_t 1260 hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(uint8_t *buf) 1261 { 1262 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1263 struct rx_mpdu_start *mpdu_start = 1264 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1265 1266 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1267 &mpdu_start->rx_mpdu_info_details); 1268 } 1269 1270 /** 1271 * hal_rx_msdu_end_sa_sw_peer_id_get_5018() - API to get the 1272 * sa_sw_peer_id from rx_msdu_end TLV 1273 * @buf: pointer to the start of RX PKT TLV headers 1274 * 1275 * Return: sa_sw_peer_id index 1276 */ 1277 static inline uint32_t 1278 hal_rx_msdu_end_sa_sw_peer_id_get_5018(uint8_t *buf) 1279 { 1280 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1281 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1282 1283 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1284 } 1285 1286 /** 1287 * hal_tx_desc_set_mesh_en_5018() - Set mesh_enable flag in Tx descriptor 1288 * @desc: Handle to Tx Descriptor 1289 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1290 * enabling the interpretation of the 'Mesh Control Present' bit 1291 * (bit 8) of QoS Control (otherwise this bit is ignored), 1292 * For native WiFi frames, this indicates that a 'Mesh Control' field 1293 * is present between the header and the LLC. 1294 * 1295 * Return: void 1296 */ 1297 static inline 1298 void hal_tx_desc_set_mesh_en_5018(void *desc, uint8_t en) 1299 { 1300 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1301 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1302 } 1303 1304 static 1305 void *hal_rx_msdu0_buffer_addr_lsb_5018(void *link_desc_va) 1306 { 1307 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1308 } 1309 1310 static 1311 void *hal_rx_msdu_desc_info_ptr_get_5018(void *msdu0) 1312 { 1313 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1314 } 1315 1316 static 1317 void *hal_ent_mpdu_desc_info_5018(void *ent_ring_desc) 1318 { 1319 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1320 } 1321 1322 static 1323 void *hal_dst_mpdu_desc_info_5018(void *dst_ring_desc) 1324 { 1325 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1326 } 1327 1328 static 1329 uint8_t hal_rx_get_fc_valid_5018(uint8_t *buf) 1330 { 1331 return HAL_RX_GET_FC_VALID(buf); 1332 } 1333 1334 static uint8_t hal_rx_get_to_ds_flag_5018(uint8_t *buf) 1335 { 1336 return HAL_RX_GET_TO_DS_FLAG(buf); 1337 } 1338 1339 static uint8_t hal_rx_get_mac_addr2_valid_5018(uint8_t *buf) 1340 { 1341 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1342 } 1343 1344 static uint8_t hal_rx_get_filter_category_5018(uint8_t *buf) 1345 { 1346 return HAL_RX_GET_FILTER_CATEGORY(buf); 1347 } 1348 1349 static uint32_t 1350 hal_rx_get_ppdu_id_5018(uint8_t *buf) 1351 { 1352 struct rx_mpdu_info *rx_mpdu_info; 1353 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 1354 1355 rx_mpdu_info = 1356 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1357 1358 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 1359 } 1360 1361 /** 1362 * hal_reo_config_5018() - Set reo config parameters 1363 * @soc: hal soc handle 1364 * @reg_val: value to be set 1365 * @reo_params: reo parameters 1366 * 1367 * Return: void 1368 */ 1369 static void 1370 hal_reo_config_5018(struct hal_soc *soc, 1371 uint32_t reg_val, 1372 struct hal_reo_params *reo_params) 1373 { 1374 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1375 } 1376 1377 /** 1378 * hal_rx_msdu_desc_info_get_ptr_5018() - Get msdu desc info ptr 1379 * @msdu_details_ptr: Pointer to msdu_details_ptr 1380 * 1381 * Return - Pointer to rx_msdu_desc_info structure. 1382 * 1383 */ 1384 static void *hal_rx_msdu_desc_info_get_ptr_5018(void *msdu_details_ptr) 1385 { 1386 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1387 } 1388 1389 /** 1390 * hal_rx_link_desc_msdu0_ptr_5018 - Get pointer to rx_msdu details 1391 * @link_desc: Pointer to link desc 1392 * 1393 * Return - Pointer to rx_msdu_details structure 1394 * 1395 */ 1396 static void *hal_rx_link_desc_msdu0_ptr_5018(void *link_desc) 1397 { 1398 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1399 } 1400 1401 /** 1402 * hal_rx_msdu_flow_idx_get_5018() - API to get flow index from 1403 * rx_msdu_end TLV 1404 * @buf: pointer to the start of RX PKT TLV headers 1405 * 1406 * Return: flow index value from MSDU END TLV 1407 */ 1408 static inline uint32_t hal_rx_msdu_flow_idx_get_5018(uint8_t *buf) 1409 { 1410 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1411 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1412 1413 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1414 } 1415 1416 /** 1417 * hal_rx_msdu_flow_idx_invalid_5018() - API to get flow index invalid 1418 * from rx_msdu_end TLV 1419 * @buf: pointer to the start of RX PKT TLV headers 1420 * 1421 * Return: flow index invalid value from MSDU END TLV 1422 */ 1423 static bool hal_rx_msdu_flow_idx_invalid_5018(uint8_t *buf) 1424 { 1425 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1426 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1427 1428 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1429 } 1430 1431 /** 1432 * hal_rx_msdu_flow_idx_timeout_5018() - API to get flow index timeout 1433 * from rx_msdu_end TLV 1434 * @buf: pointer to the start of RX PKT TLV headers 1435 * 1436 * Return: flow index timeout value from MSDU END TLV 1437 */ 1438 static bool hal_rx_msdu_flow_idx_timeout_5018(uint8_t *buf) 1439 { 1440 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1441 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1442 1443 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1444 } 1445 1446 /** 1447 * hal_rx_msdu_fse_metadata_get_5018() - API to get FSE metadata 1448 * from rx_msdu_end TLV 1449 * @buf: pointer to the start of RX PKT TLV headers 1450 * 1451 * Return: fse metadata value from MSDU END TLV 1452 */ 1453 static uint32_t hal_rx_msdu_fse_metadata_get_5018(uint8_t *buf) 1454 { 1455 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1456 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1457 1458 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1459 } 1460 1461 /** 1462 * hal_rx_msdu_cce_metadata_get_5018() - API to get CCE metadata 1463 * from rx_msdu_end TLV 1464 * @buf: pointer to the start of RX PKT TLV headers 1465 * 1466 * Return: cce_metadata 1467 */ 1468 static uint16_t 1469 hal_rx_msdu_cce_metadata_get_5018(uint8_t *buf) 1470 { 1471 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1472 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1473 1474 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1475 } 1476 1477 /** 1478 * hal_rx_msdu_get_flow_params_5018() - API to get flow index, flow index 1479 * invalid and flow index timeout from 1480 * rx_msdu_end TLV 1481 * @buf: pointer to the start of RX PKT TLV headers 1482 * @flow_invalid: pointer to return value of flow_idx_valid 1483 * @flow_timeout: pointer to return value of flow_idx_timeout 1484 * @flow_index: pointer to return value of flow_idx 1485 * 1486 * Return: none 1487 */ 1488 static inline void 1489 hal_rx_msdu_get_flow_params_5018(uint8_t *buf, 1490 bool *flow_invalid, 1491 bool *flow_timeout, 1492 uint32_t *flow_index) 1493 { 1494 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1495 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1496 1497 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1498 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1499 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1500 } 1501 1502 /** 1503 * hal_rx_tlv_get_tcp_chksum_5018() - API to get tcp checksum 1504 * @buf: rx_tlv_hdr 1505 * 1506 * Return: tcp checksum 1507 */ 1508 static uint16_t 1509 hal_rx_tlv_get_tcp_chksum_5018(uint8_t *buf) 1510 { 1511 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1512 } 1513 1514 /** 1515 * hal_rx_get_rx_sequence_5018() - Function to retrieve rx sequence number 1516 * @buf: Network buffer 1517 * 1518 * Return: rx sequence number 1519 */ 1520 static 1521 uint16_t hal_rx_get_rx_sequence_5018(uint8_t *buf) 1522 { 1523 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1524 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1525 1526 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1527 } 1528 1529 /** 1530 * hal_get_window_address_5018() - Function to get hp/tp address 1531 * @hal_soc: Pointer to hal_soc 1532 * @addr: address offset of register 1533 * 1534 * Return: modified address offset of register 1535 */ 1536 static inline qdf_iomem_t hal_get_window_address_5018(struct hal_soc *hal_soc, 1537 qdf_iomem_t addr) 1538 { 1539 uint32_t offset = addr - hal_soc->dev_base_addr; 1540 qdf_iomem_t new_offset; 1541 1542 /* 1543 * Check if offset lies within CE register range(0x08400000) 1544 * or UMAC/DP register range (0x00A00000). 1545 * If offset lies within CE register range, map it 1546 * into CE region. 1547 */ 1548 if (offset & HOST_CE_MASK_VALUE) { 1549 offset = offset - WFSS_CE_REG_BASE; 1550 new_offset = (hal_soc->dev_base_addr_ce + offset); 1551 1552 return new_offset; 1553 } else { 1554 /* 1555 * If offset lies within DP register range, 1556 * return the address as such 1557 */ 1558 return addr; 1559 } 1560 } 1561 1562 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1563 { 1564 /* Write value into window configuration register */ 1565 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1566 WINDOW_CONFIGURATION_VALUE_5018); 1567 } 1568 1569 /** 1570 * hal_rx_msdu_packet_metadata_get_5018() - API to get the msdu 1571 * information from rx_msdu_end TLV 1572 * @buf: pointer to the start of RX PKT TLV headers 1573 * @msdu_pkt_metadata: pointer to the msdu info structure 1574 */ 1575 static void 1576 hal_rx_msdu_packet_metadata_get_5018(uint8_t *buf, 1577 void *msdu_pkt_metadata) 1578 { 1579 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1580 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1581 struct hal_rx_msdu_metadata *msdu_metadata = 1582 (struct hal_rx_msdu_metadata *)msdu_pkt_metadata; 1583 1584 msdu_metadata->l3_hdr_pad = 1585 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1586 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1587 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 1588 msdu_metadata->sa_sw_peer_id = 1589 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1590 } 1591 1592 /** 1593 * hal_rx_flow_setup_fse_5018() - Setup a flow search entry in HW FST 1594 * @rx_fst: Pointer to the Rx Flow Search Table 1595 * @table_offset: offset into the table where the flow is to be setup 1596 * @rx_flow: Flow Parameters 1597 * 1598 * Return: Success/Failure 1599 */ 1600 static void * 1601 hal_rx_flow_setup_fse_5018(uint8_t *rx_fst, uint32_t table_offset, 1602 uint8_t *rx_flow) 1603 { 1604 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1605 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1606 uint8_t *fse; 1607 bool fse_valid; 1608 1609 if (table_offset >= fst->max_entries) { 1610 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1611 "HAL FSE table offset %u exceeds max entries %u", 1612 table_offset, fst->max_entries); 1613 return NULL; 1614 } 1615 1616 fse = (uint8_t *)fst->base_vaddr + 1617 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1618 1619 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1620 1621 if (fse_valid) { 1622 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1623 "HAL FSE %pK already valid", fse); 1624 return NULL; 1625 } 1626 1627 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1628 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1629 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1630 1631 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1632 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1633 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1634 1635 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1636 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1637 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1638 1639 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1640 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1641 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1642 1643 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1644 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1645 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1646 1647 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1648 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1649 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1650 1651 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1652 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1653 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1654 1655 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1656 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1657 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1658 1659 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1660 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1661 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1662 (flow->tuple_info.dest_port)); 1663 1664 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1665 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1666 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1667 (flow->tuple_info.src_port)); 1668 1669 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1670 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1671 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1672 flow->tuple_info.l4_protocol); 1673 1674 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1675 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1676 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1677 flow->reo_destination_handler); 1678 1679 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1680 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1681 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1682 1683 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1684 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1685 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1686 flow->fse_metadata); 1687 1688 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1689 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1690 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1691 REO_DESTINATION_INDICATION, 1692 flow->reo_destination_indication); 1693 1694 /* Reset all the other fields in FSE */ 1695 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1696 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1697 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1698 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1699 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1700 1701 return fse; 1702 } 1703 1704 static void hal_hw_txrx_ops_attach_qca5018(struct hal_soc *hal_soc) 1705 { 1706 /* init and setup */ 1707 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1708 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1709 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1710 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1711 hal_soc->ops->hal_get_window_address = hal_get_window_address_5018; 1712 1713 /* tx */ 1714 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1715 hal_tx_desc_set_dscp_tid_table_id_5018; 1716 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5018; 1717 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5018; 1718 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_5018; 1719 hal_soc->ops->hal_tx_desc_set_buf_addr = 1720 hal_tx_desc_set_buf_addr_generic_li; 1721 hal_soc->ops->hal_tx_desc_set_search_type = 1722 hal_tx_desc_set_search_type_generic_li; 1723 hal_soc->ops->hal_tx_desc_set_search_index = 1724 hal_tx_desc_set_search_index_generic_li; 1725 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1726 hal_tx_desc_set_cache_set_num_generic_li; 1727 hal_soc->ops->hal_tx_comp_get_status = 1728 hal_tx_comp_get_status_generic_li; 1729 hal_soc->ops->hal_tx_comp_get_release_reason = 1730 hal_tx_comp_get_release_reason_generic_li; 1731 hal_soc->ops->hal_get_wbm_internal_error = 1732 hal_get_wbm_internal_error_generic_li; 1733 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_5018; 1734 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1735 hal_tx_init_cmd_credit_ring_5018; 1736 1737 /* rx */ 1738 hal_soc->ops->hal_rx_msdu_start_nss_get = 1739 hal_rx_msdu_start_nss_get_5018; 1740 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1741 hal_rx_mon_hw_desc_get_mpdu_status_5018; 1742 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5018; 1743 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1744 hal_rx_proc_phyrx_other_receive_info_tlv_5018; 1745 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1746 hal_rx_dump_msdu_start_tlv_5018; 1747 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5018; 1748 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5018; 1749 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1750 hal_rx_mpdu_start_tid_get_5018; 1751 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1752 hal_rx_msdu_start_reception_type_get_5018; 1753 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1754 hal_rx_msdu_end_da_idx_get_5018; 1755 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1756 hal_rx_msdu_desc_info_get_ptr_5018; 1757 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1758 hal_rx_link_desc_msdu0_ptr_5018; 1759 hal_soc->ops->hal_reo_status_get_header = 1760 hal_reo_status_get_header_5018; 1761 hal_soc->ops->hal_rx_status_get_tlv_info = 1762 hal_rx_status_get_tlv_info_generic_li; 1763 hal_soc->ops->hal_rx_wbm_err_info_get = 1764 hal_rx_wbm_err_info_get_generic_li; 1765 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1766 hal_rx_dump_mpdu_start_tlv_generic_li; 1767 1768 hal_soc->ops->hal_tx_set_pcp_tid_map = 1769 hal_tx_set_pcp_tid_map_generic_li; 1770 hal_soc->ops->hal_tx_update_pcp_tid_map = 1771 hal_tx_update_pcp_tid_generic_li; 1772 hal_soc->ops->hal_tx_set_tidmap_prty = 1773 hal_tx_update_tidmap_prty_generic_li; 1774 hal_soc->ops->hal_rx_get_rx_fragment_number = 1775 hal_rx_get_rx_fragment_number_5018; 1776 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1777 hal_rx_msdu_end_da_is_mcbc_get_5018; 1778 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1779 hal_rx_msdu_end_sa_is_valid_get_5018; 1780 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1781 hal_rx_msdu_end_sa_idx_get_5018; 1782 hal_soc->ops->hal_rx_desc_is_first_msdu = 1783 hal_rx_desc_is_first_msdu_5018; 1784 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1785 hal_rx_msdu_end_l3_hdr_padding_get_5018; 1786 hal_soc->ops->hal_rx_encryption_info_valid = 1787 hal_rx_encryption_info_valid_5018; 1788 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_5018; 1789 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1790 hal_rx_msdu_end_first_msdu_get_5018; 1791 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1792 hal_rx_msdu_end_da_is_valid_get_5018; 1793 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1794 hal_rx_msdu_end_last_msdu_get_5018; 1795 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1796 hal_rx_get_mpdu_mac_ad4_valid_5018; 1797 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1798 hal_rx_mpdu_start_sw_peer_id_get_5018; 1799 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1800 hal_rx_mpdu_peer_meta_data_get_li; 1801 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_5018; 1802 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_5018; 1803 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1804 hal_rx_get_mpdu_frame_control_valid_5018; 1805 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1806 hal_rx_get_mpdu_frame_control_field_5018; 1807 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_5018; 1808 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_5018; 1809 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_5018; 1810 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_5018; 1811 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1812 hal_rx_get_mpdu_sequence_control_valid_5018; 1813 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_5018; 1814 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_5018; 1815 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1816 hal_rx_hw_desc_get_ppduid_get_5018; 1817 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1818 hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018; 1819 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1820 hal_rx_msdu_end_sa_sw_peer_id_get_5018; 1821 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1822 hal_rx_msdu0_buffer_addr_lsb_5018; 1823 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1824 hal_rx_msdu_desc_info_ptr_get_5018; 1825 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5018; 1826 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5018; 1827 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_5018; 1828 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_5018; 1829 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1830 hal_rx_get_mac_addr2_valid_5018; 1831 hal_soc->ops->hal_rx_get_filter_category = 1832 hal_rx_get_filter_category_5018; 1833 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_5018; 1834 hal_soc->ops->hal_reo_config = hal_reo_config_5018; 1835 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_5018; 1836 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1837 hal_rx_msdu_flow_idx_invalid_5018; 1838 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1839 hal_rx_msdu_flow_idx_timeout_5018; 1840 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1841 hal_rx_msdu_fse_metadata_get_5018; 1842 hal_soc->ops->hal_rx_msdu_cce_match_get = 1843 hal_rx_msdu_cce_match_get_li; 1844 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1845 hal_rx_msdu_cce_metadata_get_5018; 1846 hal_soc->ops->hal_rx_msdu_get_flow_params = 1847 hal_rx_msdu_get_flow_params_5018; 1848 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1849 hal_rx_tlv_get_tcp_chksum_5018; 1850 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_5018; 1851 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 1852 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5018; 1853 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5018; 1854 #endif 1855 /* rx - msdu fast path info fields */ 1856 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1857 hal_rx_msdu_packet_metadata_get_5018; 1858 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1859 hal_rx_mpdu_start_tlv_tag_valid_5018; 1860 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1861 hal_rx_wbm_err_msdu_continuation_get_5018; 1862 1863 /* rx - TLV struct offsets */ 1864 hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic; 1865 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1866 hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic; 1867 hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic; 1868 hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic; 1869 #ifndef NO_RX_PKT_HDR_TLV 1870 hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic; 1871 #endif 1872 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5018; 1873 hal_soc->ops->hal_rx_flow_get_tuple_info = 1874 hal_rx_flow_get_tuple_info_li; 1875 hal_soc->ops->hal_rx_flow_delete_entry = 1876 hal_rx_flow_delete_entry_li; 1877 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; 1878 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_5018; 1879 hal_soc->ops->hal_setup_link_idle_list = 1880 hal_setup_link_idle_list_generic_li; 1881 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1882 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1883 hal_rx_msdu_start_get_len_5018; 1884 }; 1885 1886 struct hal_hw_srng_config hw_srng_table_5018[] = { 1887 /* TODO: max_rings can populated by querying HW capabilities */ 1888 { /* REO_DST */ 1889 .start_ring_id = HAL_SRNG_REO2SW1, 1890 .max_rings = 4, 1891 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1892 .lmac_ring = FALSE, 1893 .ring_dir = HAL_SRNG_DST_RING, 1894 .reg_start = { 1895 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1896 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1897 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1898 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1899 }, 1900 .reg_size = { 1901 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1902 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1903 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1904 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1905 }, 1906 .max_size = 1907 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1908 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1909 }, 1910 { /* REO_EXCEPTION */ 1911 /* Designating REO2TCL ring as exception ring. This ring is 1912 * similar to other REO2SW rings though it is named as REO2TCL. 1913 * Any of theREO2SW rings can be used as exception ring. 1914 */ 1915 .start_ring_id = HAL_SRNG_REO2TCL, 1916 .max_rings = 1, 1917 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1918 .lmac_ring = FALSE, 1919 .ring_dir = HAL_SRNG_DST_RING, 1920 .reg_start = { 1921 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1922 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1923 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1924 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1925 }, 1926 /* Single ring - provide ring size if multiple rings of this 1927 * type are supported 1928 */ 1929 .reg_size = {}, 1930 .max_size = 1931 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1932 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1933 }, 1934 { /* REO_REINJECT */ 1935 .start_ring_id = HAL_SRNG_SW2REO, 1936 .max_rings = 1, 1937 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1938 .lmac_ring = FALSE, 1939 .ring_dir = HAL_SRNG_SRC_RING, 1940 .reg_start = { 1941 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1942 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1943 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1944 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1945 }, 1946 /* Single ring - provide ring size if multiple rings of this 1947 * type are supported 1948 */ 1949 .reg_size = {}, 1950 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1951 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1952 }, 1953 { /* REO_CMD */ 1954 .start_ring_id = HAL_SRNG_REO_CMD, 1955 .max_rings = 1, 1956 .entry_size = (sizeof(struct tlv_32_hdr) + 1957 sizeof(struct reo_get_queue_stats)) >> 2, 1958 .lmac_ring = FALSE, 1959 .ring_dir = HAL_SRNG_SRC_RING, 1960 .reg_start = { 1961 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1962 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1963 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1964 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1965 }, 1966 /* Single ring - provide ring size if multiple rings of this 1967 * type are supported 1968 */ 1969 .reg_size = {}, 1970 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1971 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1972 }, 1973 { /* REO_STATUS */ 1974 .start_ring_id = HAL_SRNG_REO_STATUS, 1975 .max_rings = 1, 1976 .entry_size = (sizeof(struct tlv_32_hdr) + 1977 sizeof(struct reo_get_queue_stats_status)) >> 2, 1978 .lmac_ring = FALSE, 1979 .ring_dir = HAL_SRNG_DST_RING, 1980 .reg_start = { 1981 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1982 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1983 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1984 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1985 }, 1986 /* Single ring - provide ring size if multiple rings of this 1987 * type are supported 1988 */ 1989 .reg_size = {}, 1990 .max_size = 1991 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1992 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1993 }, 1994 { /* TCL_DATA */ 1995 .start_ring_id = HAL_SRNG_SW2TCL1, 1996 .max_rings = 3, 1997 .entry_size = (sizeof(struct tlv_32_hdr) + 1998 sizeof(struct tcl_data_cmd)) >> 2, 1999 .lmac_ring = FALSE, 2000 .ring_dir = HAL_SRNG_SRC_RING, 2001 .reg_start = { 2002 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2003 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2004 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2005 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2006 }, 2007 .reg_size = { 2008 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2009 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2010 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2011 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2012 }, 2013 .max_size = 2014 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2015 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2016 }, 2017 { /* TCL_CMD */ 2018 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2019 .max_rings = 1, 2020 .entry_size = (sizeof(struct tlv_32_hdr) + 2021 sizeof(struct tcl_data_cmd)) >> 2, 2022 .lmac_ring = FALSE, 2023 .ring_dir = HAL_SRNG_SRC_RING, 2024 .reg_start = { 2025 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2026 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2027 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2028 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2029 }, 2030 /* Single ring - provide ring size if multiple rings of this 2031 * type are supported 2032 */ 2033 .reg_size = {}, 2034 .max_size = 2035 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2036 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2037 }, 2038 { /* TCL_STATUS */ 2039 .start_ring_id = HAL_SRNG_TCL_STATUS, 2040 .max_rings = 1, 2041 .entry_size = (sizeof(struct tlv_32_hdr) + 2042 sizeof(struct tcl_status_ring)) >> 2, 2043 .lmac_ring = FALSE, 2044 .ring_dir = HAL_SRNG_DST_RING, 2045 .reg_start = { 2046 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2047 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2048 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2049 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2050 }, 2051 /* Single ring - provide ring size if multiple rings of this 2052 * type are supported 2053 */ 2054 .reg_size = {}, 2055 .max_size = 2056 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2057 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2058 }, 2059 { /* CE_SRC */ 2060 .start_ring_id = HAL_SRNG_CE_0_SRC, 2061 .max_rings = 12, 2062 .entry_size = sizeof(struct ce_src_desc) >> 2, 2063 .lmac_ring = FALSE, 2064 .ring_dir = HAL_SRNG_SRC_RING, 2065 .reg_start = { 2066 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2067 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2068 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2069 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2070 }, 2071 .reg_size = { 2072 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2073 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2074 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2075 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2076 }, 2077 .max_size = 2078 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2079 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2080 }, 2081 { /* CE_DST */ 2082 .start_ring_id = HAL_SRNG_CE_0_DST, 2083 .max_rings = 12, 2084 .entry_size = 8 >> 2, 2085 /*TODO: entry_size above should actually be 2086 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2087 * of struct ce_dst_desc in HW header files 2088 */ 2089 .lmac_ring = FALSE, 2090 .ring_dir = HAL_SRNG_SRC_RING, 2091 .reg_start = { 2092 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2093 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2094 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2095 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2096 }, 2097 .reg_size = { 2098 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2099 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2100 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2101 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2102 }, 2103 .max_size = 2104 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2105 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2106 }, 2107 { /* CE_DST_STATUS */ 2108 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2109 .max_rings = 12, 2110 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2111 .lmac_ring = FALSE, 2112 .ring_dir = HAL_SRNG_DST_RING, 2113 .reg_start = { 2114 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2115 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2116 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2117 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2118 }, 2119 /* TODO: check destination status ring registers */ 2120 .reg_size = { 2121 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2122 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2123 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2124 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2125 }, 2126 .max_size = 2127 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2128 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2129 }, 2130 { /* WBM_IDLE_LINK */ 2131 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2132 .max_rings = 1, 2133 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2134 .lmac_ring = FALSE, 2135 .ring_dir = HAL_SRNG_SRC_RING, 2136 .reg_start = { 2137 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2138 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2139 }, 2140 /* Single ring - provide ring size if multiple rings of this 2141 * type are supported 2142 */ 2143 .reg_size = {}, 2144 .max_size = 2145 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2146 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2147 }, 2148 { /* SW2WBM_RELEASE */ 2149 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2150 .max_rings = 1, 2151 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2152 .lmac_ring = FALSE, 2153 .ring_dir = HAL_SRNG_SRC_RING, 2154 .reg_start = { 2155 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2156 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2157 }, 2158 /* Single ring - provide ring size if multiple rings of this 2159 * type are supported 2160 */ 2161 .reg_size = {}, 2162 .max_size = 2163 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2164 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2165 }, 2166 { /* WBM2SW_RELEASE */ 2167 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2168 .max_rings = 5, 2169 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2170 .lmac_ring = FALSE, 2171 .ring_dir = HAL_SRNG_DST_RING, 2172 .reg_start = { 2173 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2174 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2175 }, 2176 .reg_size = { 2177 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2178 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2179 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2180 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2181 }, 2182 .max_size = 2183 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2184 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2185 }, 2186 { /* RXDMA_BUF */ 2187 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2188 #ifdef IPA_OFFLOAD 2189 .max_rings = 3, 2190 #else 2191 .max_rings = 2, 2192 #endif 2193 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2194 .lmac_ring = TRUE, 2195 .ring_dir = HAL_SRNG_SRC_RING, 2196 /* reg_start is not set because LMAC rings are not accessed 2197 * from host 2198 */ 2199 .reg_start = {}, 2200 .reg_size = {}, 2201 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2202 }, 2203 { /* RXDMA_DST */ 2204 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2205 .max_rings = 1, 2206 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2207 .lmac_ring = TRUE, 2208 .ring_dir = HAL_SRNG_DST_RING, 2209 /* reg_start is not set because LMAC rings are not accessed 2210 * from host 2211 */ 2212 .reg_start = {}, 2213 .reg_size = {}, 2214 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2215 }, 2216 { /* RXDMA_MONITOR_BUF */ 2217 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2218 .max_rings = 1, 2219 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2220 .lmac_ring = TRUE, 2221 .ring_dir = HAL_SRNG_SRC_RING, 2222 /* reg_start is not set because LMAC rings are not accessed 2223 * from host 2224 */ 2225 .reg_start = {}, 2226 .reg_size = {}, 2227 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2228 }, 2229 { /* RXDMA_MONITOR_STATUS */ 2230 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2231 .max_rings = 1, 2232 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2233 .lmac_ring = TRUE, 2234 .ring_dir = HAL_SRNG_SRC_RING, 2235 /* reg_start is not set because LMAC rings are not accessed 2236 * from host 2237 */ 2238 .reg_start = {}, 2239 .reg_size = {}, 2240 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2241 }, 2242 { /* RXDMA_MONITOR_DST */ 2243 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2244 .max_rings = 1, 2245 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2246 .lmac_ring = TRUE, 2247 .ring_dir = HAL_SRNG_DST_RING, 2248 /* reg_start is not set because LMAC rings are not accessed 2249 * from host 2250 */ 2251 .reg_start = {}, 2252 .reg_size = {}, 2253 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2254 }, 2255 { /* RXDMA_MONITOR_DESC */ 2256 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2257 .max_rings = 1, 2258 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2259 .lmac_ring = TRUE, 2260 .ring_dir = HAL_SRNG_SRC_RING, 2261 /* reg_start is not set because LMAC rings are not accessed 2262 * from host 2263 */ 2264 .reg_start = {}, 2265 .reg_size = {}, 2266 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2267 }, 2268 { /* DIR_BUF_RX_DMA_SRC */ 2269 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2270 /* one ring for spectral and one ring for cfr */ 2271 .max_rings = 2, 2272 .entry_size = 2, 2273 .lmac_ring = TRUE, 2274 .ring_dir = HAL_SRNG_SRC_RING, 2275 /* reg_start is not set because LMAC rings are not accessed 2276 * from host 2277 */ 2278 .reg_start = {}, 2279 .reg_size = {}, 2280 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2281 }, 2282 #ifdef WLAN_FEATURE_CIF_CFR 2283 { /* WIFI_POS_SRC */ 2284 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2285 .max_rings = 1, 2286 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2287 .lmac_ring = TRUE, 2288 .ring_dir = HAL_SRNG_SRC_RING, 2289 /* reg_start is not set because LMAC rings are not accessed 2290 * from host 2291 */ 2292 .reg_start = {}, 2293 .reg_size = {}, 2294 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2295 }, 2296 #endif 2297 { /* REO2PPE */ 0}, 2298 { /* PPE2TCL */ 0}, 2299 { /* PPE_RELEASE */ 0}, 2300 { /* TX_MONITOR_BUF */ 0}, 2301 { /* TX_MONITOR_DST */ 0}, 2302 { /* SW2RXDMA_NEW */ 0}, 2303 }; 2304 2305 /** 2306 * hal_qca5018_attach()- Attach 5018 target specific hal_soc ops, 2307 * offset and srng table 2308 * @hal_soc: hal_soc handle 2309 * 2310 * Return: void 2311 */ 2312 void hal_qca5018_attach(struct hal_soc *hal_soc) 2313 { 2314 hal_soc->hw_srng_table = hw_srng_table_5018; 2315 2316 hal_srng_hw_reg_offset_init_generic(hal_soc); 2317 hal_hw_txrx_default_ops_attach_li(hal_soc); 2318 hal_hw_txrx_ops_attach_qca5018(hal_soc); 2319 } 2320