1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 #include "hal_flow.h" 25 #include "rx_flow_search_entry.h" 26 #include "hal_rx_flow_info.h" 27 28 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 29 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 30 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 31 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 33 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 34 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 35 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 36 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 37 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 38 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 39 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 40 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 41 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 42 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 43 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 44 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 45 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 52 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 53 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 54 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 55 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 56 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 57 RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 58 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 59 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 60 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 61 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 62 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 64 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 65 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 66 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 67 STATUS_HEADER_REO_STATUS_NUMBER 68 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 69 STATUS_HEADER_TIMESTAMP 70 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 71 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 72 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 73 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 74 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 75 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 76 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 77 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 78 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 79 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 80 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 81 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 82 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 83 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 84 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 85 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 86 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 87 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 88 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 89 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 90 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 91 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 92 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 93 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 94 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 95 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 96 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 97 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 98 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 99 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 100 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 101 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 103 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 104 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 105 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 106 107 #define CE_WINDOW_ADDRESS_5018 \ 108 ((WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 109 110 #define UMAC_WINDOW_ADDRESS_5018 \ 111 ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 112 113 #define WINDOW_CONFIGURATION_VALUE_5018 \ 114 ((CE_WINDOW_ADDRESS_5018 << 6) |\ 115 (UMAC_WINDOW_ADDRESS_5018 << 12) | \ 116 WINDOW_ENABLE_BIT) 117 118 #define HOST_CE_MASK_VALUE 0xFF000000 119 120 #include <hal_5018_tx.h> 121 #include <hal_5018_rx.h> 122 #include <hal_generic_api.h> 123 #include <hal_wbm.h> 124 125 /** 126 * hal_rx_msdu_start_nss_get_5018(): API to get the NSS 127 * Interval from rx_msdu_start 128 * 129 * @buf: pointer to the start of RX PKT TLV header 130 * Return: uint32_t(nss) 131 */ 132 static uint32_t hal_rx_msdu_start_nss_get_5018(uint8_t *buf) 133 { 134 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 135 struct rx_msdu_start *msdu_start = 136 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 137 uint8_t mimo_ss_bitmap; 138 139 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 140 141 return qdf_get_hweight8(mimo_ss_bitmap); 142 } 143 144 /** 145 * hal_rx_mon_hw_desc_get_mpdu_status_5018(): Retrieve MPDU status 146 * 147 * @ hw_desc_addr: Start address of Rx HW TLVs 148 * @ rs: Status for monitor mode 149 * 150 * Return: void 151 */ 152 static void hal_rx_mon_hw_desc_get_mpdu_status_5018(void *hw_desc_addr, 153 struct mon_rx_status *rs) 154 { 155 struct rx_msdu_start *rx_msdu_start; 156 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 157 uint32_t reg_value; 158 const uint32_t sgi_hw_to_cdp[] = { 159 CDP_SGI_0_8_US, 160 CDP_SGI_0_4_US, 161 CDP_SGI_1_6_US, 162 CDP_SGI_3_2_US, 163 }; 164 165 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 166 167 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 168 169 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 170 RX_MSDU_START_5, USER_RSSI); 171 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 172 173 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 174 rs->sgi = sgi_hw_to_cdp[reg_value]; 175 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 176 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 177 /* TODO: rs->beamformed should be set for SU beamforming also */ 178 } 179 180 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 181 /** 182 * hal_get_link_desc_size_5018(): API to get the link desc size 183 * 184 * Return: uint32_t 185 */ 186 static uint32_t hal_get_link_desc_size_5018(void) 187 { 188 return LINK_DESC_SIZE; 189 } 190 191 /** 192 * hal_rx_get_tlv_5018(): API to get the tlv 193 * 194 * @rx_tlv: TLV data extracted from the rx packet 195 * Return: uint8_t 196 */ 197 static uint8_t hal_rx_get_tlv_5018(void *rx_tlv) 198 { 199 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 200 } 201 202 /** 203 * hal_rx_mpdu_start_tlv_tag_valid_5018 () - API to check if RX_MPDU_START 204 * tlv tag is valid 205 * 206 *@rx_tlv_hdr: start address of rx_pkt_tlvs 207 * 208 * Return: true if RX_MPDU_START is valied, else false. 209 */ 210 uint8_t hal_rx_mpdu_start_tlv_tag_valid_5018(void *rx_tlv_hdr) 211 { 212 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 213 uint32_t tlv_tag; 214 215 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 216 217 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 218 } 219 220 /** 221 * hal_rx_wbm_err_msdu_continuation_get_5018 () - API to check if WBM 222 * msdu continuation bit is set 223 * 224 *@wbm_desc: wbm release ring descriptor 225 * 226 * Return: true if msdu continuation bit is set. 227 */ 228 uint8_t hal_rx_wbm_err_msdu_continuation_get_5018(void *wbm_desc) 229 { 230 uint32_t comp_desc = 231 *(uint32_t *)(((uint8_t *)wbm_desc) + 232 WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET); 233 234 return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >> 235 WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB; 236 } 237 238 static 239 void hal_compute_reo_remap_ix2_ix3_5018(uint32_t *ring, uint32_t num_rings, 240 uint32_t *remap1, uint32_t *remap2) 241 { 242 switch (num_rings) { 243 case 1: 244 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 245 HAL_REO_REMAP_IX2(ring[0], 17) | 246 HAL_REO_REMAP_IX2(ring[0], 18) | 247 HAL_REO_REMAP_IX2(ring[0], 19) | 248 HAL_REO_REMAP_IX2(ring[0], 20) | 249 HAL_REO_REMAP_IX2(ring[0], 21) | 250 HAL_REO_REMAP_IX2(ring[0], 22) | 251 HAL_REO_REMAP_IX2(ring[0], 23); 252 253 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 254 HAL_REO_REMAP_IX3(ring[0], 25) | 255 HAL_REO_REMAP_IX3(ring[0], 26) | 256 HAL_REO_REMAP_IX3(ring[0], 27) | 257 HAL_REO_REMAP_IX3(ring[0], 28) | 258 HAL_REO_REMAP_IX3(ring[0], 29) | 259 HAL_REO_REMAP_IX3(ring[0], 30) | 260 HAL_REO_REMAP_IX3(ring[0], 31); 261 break; 262 case 2: 263 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 264 HAL_REO_REMAP_IX2(ring[0], 17) | 265 HAL_REO_REMAP_IX2(ring[1], 18) | 266 HAL_REO_REMAP_IX2(ring[1], 19) | 267 HAL_REO_REMAP_IX2(ring[0], 20) | 268 HAL_REO_REMAP_IX2(ring[0], 21) | 269 HAL_REO_REMAP_IX2(ring[1], 22) | 270 HAL_REO_REMAP_IX2(ring[1], 23); 271 272 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 273 HAL_REO_REMAP_IX3(ring[0], 25) | 274 HAL_REO_REMAP_IX3(ring[1], 26) | 275 HAL_REO_REMAP_IX3(ring[1], 27) | 276 HAL_REO_REMAP_IX3(ring[0], 28) | 277 HAL_REO_REMAP_IX3(ring[0], 29) | 278 HAL_REO_REMAP_IX3(ring[1], 30) | 279 HAL_REO_REMAP_IX3(ring[1], 31); 280 break; 281 case 3: 282 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 283 HAL_REO_REMAP_IX2(ring[1], 17) | 284 HAL_REO_REMAP_IX2(ring[2], 18) | 285 HAL_REO_REMAP_IX2(ring[0], 19) | 286 HAL_REO_REMAP_IX2(ring[1], 20) | 287 HAL_REO_REMAP_IX2(ring[2], 21) | 288 HAL_REO_REMAP_IX2(ring[0], 22) | 289 HAL_REO_REMAP_IX2(ring[1], 23); 290 291 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 292 HAL_REO_REMAP_IX3(ring[0], 25) | 293 HAL_REO_REMAP_IX3(ring[1], 26) | 294 HAL_REO_REMAP_IX3(ring[2], 27) | 295 HAL_REO_REMAP_IX3(ring[0], 28) | 296 HAL_REO_REMAP_IX3(ring[1], 29) | 297 HAL_REO_REMAP_IX3(ring[2], 30) | 298 HAL_REO_REMAP_IX3(ring[0], 31); 299 break; 300 case 4: 301 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 302 HAL_REO_REMAP_IX2(ring[1], 17) | 303 HAL_REO_REMAP_IX2(ring[2], 18) | 304 HAL_REO_REMAP_IX2(ring[3], 19) | 305 HAL_REO_REMAP_IX2(ring[0], 20) | 306 HAL_REO_REMAP_IX2(ring[1], 21) | 307 HAL_REO_REMAP_IX2(ring[2], 22) | 308 HAL_REO_REMAP_IX2(ring[3], 23); 309 310 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 311 HAL_REO_REMAP_IX3(ring[1], 25) | 312 HAL_REO_REMAP_IX3(ring[2], 26) | 313 HAL_REO_REMAP_IX3(ring[3], 27) | 314 HAL_REO_REMAP_IX3(ring[0], 28) | 315 HAL_REO_REMAP_IX3(ring[1], 29) | 316 HAL_REO_REMAP_IX3(ring[2], 30) | 317 HAL_REO_REMAP_IX3(ring[3], 31); 318 break; 319 } 320 } 321 322 /** 323 * hal_rx_proc_phyrx_other_receive_info_tlv_5018(): API to get tlv info 324 * 325 * Return: uint32_t 326 */ 327 static inline 328 void hal_rx_proc_phyrx_other_receive_info_tlv_5018(void *rx_tlv_hdr, 329 void *ppdu_info_hdl) 330 { 331 } 332 333 /** 334 * hal_rx_dump_msdu_start_tlv_5018() : dump RX msdu_start TLV in structured 335 * human readable format. 336 * @ msdu_start: pointer the msdu_start TLV in pkt. 337 * @ dbg_level: log level. 338 * 339 * Return: void 340 */ 341 static void hal_rx_dump_msdu_start_tlv_5018(void *msdustart, 342 uint8_t dbg_level) 343 { 344 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 345 346 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 347 "rx_msdu_start tlv - " 348 "rxpcu_mpdu_filter_in_category: %d " 349 "sw_frame_group_id: %d " 350 "phy_ppdu_id: %d " 351 "msdu_length: %d " 352 "ipsec_esp: %d " 353 "l3_offset: %d " 354 "ipsec_ah: %d " 355 "l4_offset: %d " 356 "msdu_number: %d " 357 "decap_format: %d " 358 "ipv4_proto: %d " 359 "ipv6_proto: %d " 360 "tcp_proto: %d " 361 "udp_proto: %d " 362 "ip_frag: %d " 363 "tcp_only_ack: %d " 364 "da_is_bcast_mcast: %d " 365 "ip4_protocol_ip6_next_header: %d " 366 "toeplitz_hash_2_or_4: %d " 367 "flow_id_toeplitz: %d " 368 "user_rssi: %d " 369 "pkt_type: %d " 370 "stbc: %d " 371 "sgi: %d " 372 "rate_mcs: %d " 373 "receive_bandwidth: %d " 374 "reception_type: %d " 375 "ppdu_start_timestamp: %d " 376 "sw_phy_meta_data: %d ", 377 msdu_start->rxpcu_mpdu_filter_in_category, 378 msdu_start->sw_frame_group_id, 379 msdu_start->phy_ppdu_id, 380 msdu_start->msdu_length, 381 msdu_start->ipsec_esp, 382 msdu_start->l3_offset, 383 msdu_start->ipsec_ah, 384 msdu_start->l4_offset, 385 msdu_start->msdu_number, 386 msdu_start->decap_format, 387 msdu_start->ipv4_proto, 388 msdu_start->ipv6_proto, 389 msdu_start->tcp_proto, 390 msdu_start->udp_proto, 391 msdu_start->ip_frag, 392 msdu_start->tcp_only_ack, 393 msdu_start->da_is_bcast_mcast, 394 msdu_start->ip4_protocol_ip6_next_header, 395 msdu_start->toeplitz_hash_2_or_4, 396 msdu_start->flow_id_toeplitz, 397 msdu_start->user_rssi, 398 msdu_start->pkt_type, 399 msdu_start->stbc, 400 msdu_start->sgi, 401 msdu_start->rate_mcs, 402 msdu_start->receive_bandwidth, 403 msdu_start->reception_type, 404 msdu_start->ppdu_start_timestamp, 405 msdu_start->sw_phy_meta_data); 406 } 407 408 /** 409 * hal_rx_dump_msdu_end_tlv_5018: dump RX msdu_end TLV in structured 410 * human readable format. 411 * @ msdu_end: pointer the msdu_end TLV in pkt. 412 * @ dbg_level: log level. 413 * 414 * Return: void 415 */ 416 static void hal_rx_dump_msdu_end_tlv_5018(void *msduend, 417 uint8_t dbg_level) 418 { 419 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 420 421 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 422 "rx_msdu_end tlv - " 423 "rxpcu_mpdu_filter_in_category: %d " 424 "sw_frame_group_id: %d " 425 "phy_ppdu_id: %d " 426 "ip_hdr_chksum: %d " 427 "reported_mpdu_length: %d " 428 "key_id_octet: %d " 429 "cce_super_rule: %d " 430 "cce_classify_not_done_truncat: %d " 431 "cce_classify_not_done_cce_dis: %d " 432 "rule_indication_31_0: %d " 433 "rule_indication_63_32: %d " 434 "da_offset: %d " 435 "sa_offset: %d " 436 "da_offset_valid: %d " 437 "sa_offset_valid: %d " 438 "ipv6_options_crc: %d " 439 "tcp_seq_number: %d " 440 "tcp_ack_number: %d " 441 "tcp_flag: %d " 442 "lro_eligible: %d " 443 "window_size: %d " 444 "tcp_udp_chksum: %d " 445 "sa_idx_timeout: %d " 446 "da_idx_timeout: %d " 447 "msdu_limit_error: %d " 448 "flow_idx_timeout: %d " 449 "flow_idx_invalid: %d " 450 "wifi_parser_error: %d " 451 "amsdu_parser_error: %d " 452 "sa_is_valid: %d " 453 "da_is_valid: %d " 454 "da_is_mcbc: %d " 455 "l3_header_padding: %d " 456 "first_msdu: %d " 457 "last_msdu: %d " 458 "sa_idx: %d " 459 "msdu_drop: %d " 460 "reo_destination_indication: %d " 461 "flow_idx: %d " 462 "fse_metadata: %d " 463 "cce_metadata: %d " 464 "sa_sw_peer_id: %d ", 465 msdu_end->rxpcu_mpdu_filter_in_category, 466 msdu_end->sw_frame_group_id, 467 msdu_end->phy_ppdu_id, 468 msdu_end->ip_hdr_chksum, 469 msdu_end->reported_mpdu_length, 470 msdu_end->key_id_octet, 471 msdu_end->cce_super_rule, 472 msdu_end->cce_classify_not_done_truncate, 473 msdu_end->cce_classify_not_done_cce_dis, 474 msdu_end->rule_indication_31_0, 475 msdu_end->rule_indication_63_32, 476 msdu_end->da_offset, 477 msdu_end->sa_offset, 478 msdu_end->da_offset_valid, 479 msdu_end->sa_offset_valid, 480 msdu_end->ipv6_options_crc, 481 msdu_end->tcp_seq_number, 482 msdu_end->tcp_ack_number, 483 msdu_end->tcp_flag, 484 msdu_end->lro_eligible, 485 msdu_end->window_size, 486 msdu_end->tcp_udp_chksum, 487 msdu_end->sa_idx_timeout, 488 msdu_end->da_idx_timeout, 489 msdu_end->msdu_limit_error, 490 msdu_end->flow_idx_timeout, 491 msdu_end->flow_idx_invalid, 492 msdu_end->wifi_parser_error, 493 msdu_end->amsdu_parser_error, 494 msdu_end->sa_is_valid, 495 msdu_end->da_is_valid, 496 msdu_end->da_is_mcbc, 497 msdu_end->l3_header_padding, 498 msdu_end->first_msdu, 499 msdu_end->last_msdu, 500 msdu_end->sa_idx, 501 msdu_end->msdu_drop, 502 msdu_end->reo_destination_indication, 503 msdu_end->flow_idx, 504 msdu_end->fse_metadata, 505 msdu_end->cce_metadata, 506 msdu_end->sa_sw_peer_id); 507 } 508 509 /** 510 * hal_rx_mpdu_start_tid_get_5018(): API to get tid 511 * from rx_msdu_start 512 * 513 * @buf: pointer to the start of RX PKT TLV header 514 * Return: uint32_t(tid value) 515 */ 516 static uint32_t hal_rx_mpdu_start_tid_get_5018(uint8_t *buf) 517 { 518 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 519 struct rx_mpdu_start *mpdu_start = 520 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 521 uint32_t tid; 522 523 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 524 525 return tid; 526 } 527 528 /** 529 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 530 * Interval from rx_msdu_start 531 * 532 * @buf: pointer to the start of RX PKT TLV header 533 * Return: uint32_t(reception_type) 534 */ 535 static uint32_t hal_rx_msdu_start_reception_type_get_5018(uint8_t *buf) 536 { 537 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 538 struct rx_msdu_start *msdu_start = 539 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 540 uint32_t reception_type; 541 542 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 543 544 return reception_type; 545 } 546 547 /** 548 * hal_rx_msdu_end_da_idx_get_5018: API to get da_idx 549 * from rx_msdu_end TLV 550 * 551 * @ buf: pointer to the start of RX PKT TLV headers 552 * Return: da index 553 */ 554 static uint16_t hal_rx_msdu_end_da_idx_get_5018(uint8_t *buf) 555 { 556 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 557 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 558 uint16_t da_idx; 559 560 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 561 562 return da_idx; 563 } 564 565 /** 566 * hal_rx_get_rx_fragment_number_5018(): Function to retrieve rx fragment number 567 * 568 * @nbuf: Network buffer 569 * Returns: rx fragment number 570 */ 571 static 572 uint8_t hal_rx_get_rx_fragment_number_5018(uint8_t *buf) 573 { 574 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 575 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 576 577 /* Return first 4 bits as fragment number */ 578 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 579 DOT11_SEQ_FRAG_MASK); 580 } 581 582 /** 583 * hal_rx_msdu_end_da_is_mcbc_get_5018(): API to check if pkt is MCBC 584 * from rx_msdu_end TLV 585 * 586 * @ buf: pointer to the start of RX PKT TLV headers 587 * Return: da_is_mcbc 588 */ 589 static uint8_t 590 hal_rx_msdu_end_da_is_mcbc_get_5018(uint8_t *buf) 591 { 592 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 593 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 594 595 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 596 } 597 598 /** 599 * hal_rx_msdu_end_sa_is_valid_get_5018(): API to get_5018 the 600 * sa_is_valid bit from rx_msdu_end TLV 601 * 602 * @ buf: pointer to the start of RX PKT TLV headers 603 * Return: sa_is_valid bit 604 */ 605 static uint8_t 606 hal_rx_msdu_end_sa_is_valid_get_5018(uint8_t *buf) 607 { 608 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 609 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 610 uint8_t sa_is_valid; 611 612 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 613 614 return sa_is_valid; 615 } 616 617 /** 618 * hal_rx_msdu_end_sa_idx_get_5018(): API to get_5018 the 619 * sa_idx from rx_msdu_end TLV 620 * 621 * @ buf: pointer to the start of RX PKT TLV headers 622 * Return: sa_idx (SA AST index) 623 */ 624 static uint16_t hal_rx_msdu_end_sa_idx_get_5018(uint8_t *buf) 625 { 626 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 627 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 628 uint16_t sa_idx; 629 630 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 631 632 return sa_idx; 633 } 634 635 /** 636 * hal_rx_desc_is_first_msdu_5018() - Check if first msdu 637 * 638 * @hal_soc_hdl: hal_soc handle 639 * @hw_desc_addr: hardware descriptor address 640 * 641 * Return: 0 - success/ non-zero failure 642 */ 643 static uint32_t hal_rx_desc_is_first_msdu_5018(void *hw_desc_addr) 644 { 645 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 646 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 647 648 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 649 } 650 651 /** 652 * hal_rx_msdu_end_l3_hdr_padding_get_5018(): API to get_5018 the 653 * l3_header padding from rx_msdu_end TLV 654 * 655 * @ buf: pointer to the start of RX PKT TLV headers 656 * Return: number of l3 header padding bytes 657 */ 658 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_5018(uint8_t *buf) 659 { 660 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 661 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 662 uint32_t l3_header_padding; 663 664 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 665 666 return l3_header_padding; 667 } 668 669 /** 670 * @ hal_rx_encryption_info_valid_5018: Returns encryption type. 671 * 672 * @ buf: rx_tlv_hdr of the received packet 673 * @ Return: encryption type 674 */ 675 inline uint32_t hal_rx_encryption_info_valid_5018(uint8_t *buf) 676 { 677 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 678 struct rx_mpdu_start *mpdu_start = 679 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 680 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 681 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 682 683 return encryption_info; 684 } 685 686 /* 687 * @ hal_rx_print_pn_5018: Prints the PN of rx packet. 688 * 689 * @ buf: rx_tlv_hdr of the received packet 690 * @ Return: void 691 */ 692 static void hal_rx_print_pn_5018(uint8_t *buf) 693 { 694 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 695 struct rx_mpdu_start *mpdu_start = 696 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 697 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 698 699 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 700 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 701 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 702 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 703 704 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 705 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 706 } 707 708 /** 709 * hal_rx_msdu_end_first_msdu_get_5018: API to get first msdu status 710 * from rx_msdu_end TLV 711 * 712 * @ buf: pointer to the start of RX PKT TLV headers 713 * Return: first_msdu 714 */ 715 static uint8_t hal_rx_msdu_end_first_msdu_get_5018(uint8_t *buf) 716 { 717 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 718 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 719 uint8_t first_msdu; 720 721 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 722 723 return first_msdu; 724 } 725 726 /** 727 * hal_rx_msdu_end_da_is_valid_get_5018: API to check if da is valid 728 * from rx_msdu_end TLV 729 * 730 * @ buf: pointer to the start of RX PKT TLV headers 731 * Return: da_is_valid 732 */ 733 static uint8_t hal_rx_msdu_end_da_is_valid_get_5018(uint8_t *buf) 734 { 735 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 736 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 737 uint8_t da_is_valid; 738 739 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 740 741 return da_is_valid; 742 } 743 744 /** 745 * hal_rx_msdu_end_last_msdu_get_5018: API to get last msdu status 746 * from rx_msdu_end TLV 747 * 748 * @ buf: pointer to the start of RX PKT TLV headers 749 * Return: last_msdu 750 */ 751 static uint8_t hal_rx_msdu_end_last_msdu_get_5018(uint8_t *buf) 752 { 753 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 754 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 755 uint8_t last_msdu; 756 757 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 758 759 return last_msdu; 760 } 761 762 /* 763 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 764 * 765 * @nbuf: Network buffer 766 * Returns: value of mpdu 4th address valid field 767 */ 768 inline bool hal_rx_get_mpdu_mac_ad4_valid_5018(uint8_t *buf) 769 { 770 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 771 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 772 bool ad4_valid = 0; 773 774 ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info); 775 776 return ad4_valid; 777 } 778 779 /** 780 * hal_rx_mpdu_start_sw_peer_id_get_5018: Retrieve sw peer_id 781 * @buf: network buffer 782 * 783 * Return: sw peer_id 784 */ 785 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_5018(uint8_t *buf) 786 { 787 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 788 struct rx_mpdu_start *mpdu_start = 789 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 790 791 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 792 &mpdu_start->rx_mpdu_info_details); 793 } 794 795 /* 796 * hal_rx_mpdu_get_to_ds_5018(): API to get the tods info 797 * from rx_mpdu_start 798 * 799 * @buf: pointer to the start of RX PKT TLV header 800 * Return: uint32_t(to_ds) 801 */ 802 static uint32_t hal_rx_mpdu_get_to_ds_5018(uint8_t *buf) 803 { 804 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 805 struct rx_mpdu_start *mpdu_start = 806 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 807 808 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 809 810 return HAL_RX_MPDU_GET_TODS(mpdu_info); 811 } 812 813 /* 814 * hal_rx_mpdu_get_fr_ds_5018(): API to get the from ds info 815 * from rx_mpdu_start 816 * 817 * @buf: pointer to the start of RX PKT TLV header 818 * Return: uint32_t(fr_ds) 819 */ 820 static uint32_t hal_rx_mpdu_get_fr_ds_5018(uint8_t *buf) 821 { 822 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 823 struct rx_mpdu_start *mpdu_start = 824 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 825 826 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 827 828 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 829 } 830 831 /* 832 * hal_rx_get_mpdu_frame_control_valid_5018(): Retrieves mpdu 833 * frame control valid 834 * 835 * @nbuf: Network buffer 836 * Returns: value of frame control valid field 837 */ 838 static uint8_t hal_rx_get_mpdu_frame_control_valid_5018(uint8_t *buf) 839 { 840 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 841 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 842 843 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 844 } 845 846 /* 847 * hal_rx_mpdu_get_addr1_5018(): API to check get address1 of the mpdu 848 * 849 * @buf: pointer to the start of RX PKT TLV headera 850 * @mac_addr: pointer to mac address 851 * Return: success/failure 852 */ 853 static QDF_STATUS hal_rx_mpdu_get_addr1_5018(uint8_t *buf, 854 uint8_t *mac_addr) 855 { 856 struct __attribute__((__packed__)) hal_addr1 { 857 uint32_t ad1_31_0; 858 uint16_t ad1_47_32; 859 }; 860 861 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 862 struct rx_mpdu_start *mpdu_start = 863 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 864 865 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 866 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 867 uint32_t mac_addr_ad1_valid; 868 869 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 870 871 if (mac_addr_ad1_valid) { 872 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 873 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 874 return QDF_STATUS_SUCCESS; 875 } 876 877 return QDF_STATUS_E_FAILURE; 878 } 879 880 /* 881 * hal_rx_mpdu_get_addr2_5018(): API to check get address2 of the mpdu 882 * in the packet 883 * 884 * @buf: pointer to the start of RX PKT TLV header 885 * @mac_addr: pointer to mac address 886 * Return: success/failure 887 */ 888 static QDF_STATUS hal_rx_mpdu_get_addr2_5018(uint8_t *buf, uint8_t *mac_addr) 889 { 890 struct __attribute__((__packed__)) hal_addr2 { 891 uint16_t ad2_15_0; 892 uint32_t ad2_47_16; 893 }; 894 895 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 896 struct rx_mpdu_start *mpdu_start = 897 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 898 899 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 900 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 901 uint32_t mac_addr_ad2_valid; 902 903 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 904 905 if (mac_addr_ad2_valid) { 906 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 907 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 908 return QDF_STATUS_SUCCESS; 909 } 910 911 return QDF_STATUS_E_FAILURE; 912 } 913 914 /* 915 * hal_rx_mpdu_get_addr3_5018(): API to get address3 of the mpdu 916 * in the packet 917 * 918 * @buf: pointer to the start of RX PKT TLV header 919 * @mac_addr: pointer to mac address 920 * Return: success/failure 921 */ 922 static QDF_STATUS hal_rx_mpdu_get_addr3_5018(uint8_t *buf, uint8_t *mac_addr) 923 { 924 struct __attribute__((__packed__)) hal_addr3 { 925 uint32_t ad3_31_0; 926 uint16_t ad3_47_32; 927 }; 928 929 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 930 struct rx_mpdu_start *mpdu_start = 931 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 932 933 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 934 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 935 uint32_t mac_addr_ad3_valid; 936 937 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 938 939 if (mac_addr_ad3_valid) { 940 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 941 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 942 return QDF_STATUS_SUCCESS; 943 } 944 945 return QDF_STATUS_E_FAILURE; 946 } 947 948 /* 949 * hal_rx_mpdu_get_addr4_5018(): API to get address4 of the mpdu 950 * in the packet 951 * 952 * @buf: pointer to the start of RX PKT TLV header 953 * @mac_addr: pointer to mac address 954 * Return: success/failure 955 */ 956 static QDF_STATUS hal_rx_mpdu_get_addr4_5018(uint8_t *buf, uint8_t *mac_addr) 957 { 958 struct __attribute__((__packed__)) hal_addr4 { 959 uint32_t ad4_31_0; 960 uint16_t ad4_47_32; 961 }; 962 963 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 964 struct rx_mpdu_start *mpdu_start = 965 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 966 967 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 968 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 969 uint32_t mac_addr_ad4_valid; 970 971 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 972 973 if (mac_addr_ad4_valid) { 974 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 975 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 976 return QDF_STATUS_SUCCESS; 977 } 978 979 return QDF_STATUS_E_FAILURE; 980 } 981 982 /* 983 * hal_rx_get_mpdu_sequence_control_valid_5018(): Get mpdu 984 * sequence control valid 985 * 986 * @nbuf: Network buffer 987 * Returns: value of sequence control valid field 988 */ 989 static uint8_t hal_rx_get_mpdu_sequence_control_valid_5018(uint8_t *buf) 990 { 991 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 992 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 993 994 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 995 } 996 997 /** 998 * hal_rx_is_unicast_5018: check packet is unicast frame or not. 999 * 1000 * @ buf: pointer to rx pkt TLV. 1001 * 1002 * Return: true on unicast. 1003 */ 1004 static bool hal_rx_is_unicast_5018(uint8_t *buf) 1005 { 1006 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1007 struct rx_mpdu_start *mpdu_start = 1008 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1009 uint32_t grp_id; 1010 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1011 1012 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1013 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 1014 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 1015 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 1016 1017 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 1018 } 1019 1020 /** 1021 * hal_rx_tid_get_5018: get tid based on qos control valid. 1022 * @hal_soc_hdl: hal soc handle 1023 * @buf: pointer to rx pkt TLV. 1024 * 1025 * Return: tid 1026 */ 1027 static uint32_t hal_rx_tid_get_5018(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1028 { 1029 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1030 struct rx_mpdu_start *mpdu_start = 1031 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1032 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1033 uint8_t qos_control_valid = 1034 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1035 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 1036 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 1037 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 1038 1039 if (qos_control_valid) 1040 return hal_rx_mpdu_start_tid_get_5018(buf); 1041 1042 return HAL_RX_NON_QOS_TID; 1043 } 1044 1045 /** 1046 * hal_rx_hw_desc_get_ppduid_get_5018(): retrieve ppdu id 1047 * @rx_tlv_hdr: rx tlv header 1048 * @rxdma_dst_ring_desc: rxdma HW descriptor 1049 * 1050 * Return: ppdu id 1051 */ 1052 static uint32_t hal_rx_hw_desc_get_ppduid_get_5018(void *rx_tlv_hdr, 1053 void *rxdma_dst_ring_desc) 1054 { 1055 struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc; 1056 1057 return HAL_RX_REO_ENT_PHY_PPDU_ID_GET(reo_ent); 1058 } 1059 1060 /** 1061 * hal_reo_status_get_header_5018 - Process reo desc info 1062 * @d - Pointer to reo descriptior 1063 * @b - tlv type info 1064 * @h1 - Pointer to hal_reo_status_header where info to be stored 1065 * 1066 * Return - none. 1067 * 1068 */ 1069 static void hal_reo_status_get_header_5018(uint32_t *d, int b, void *h1) 1070 { 1071 uint32_t val1 = 0; 1072 struct hal_reo_status_header *h = 1073 (struct hal_reo_status_header *)h1; 1074 1075 switch (b) { 1076 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1077 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1078 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1079 break; 1080 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1081 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1082 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1083 break; 1084 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1085 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1086 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1087 break; 1088 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1089 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1090 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1091 break; 1092 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1093 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1094 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1095 break; 1096 case HAL_REO_DESC_THRES_STATUS_TLV: 1097 val1 = 1098 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1099 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1100 break; 1101 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1102 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1103 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1104 break; 1105 default: 1106 qdf_nofl_err("ERROR: Unknown tlv\n"); 1107 break; 1108 } 1109 h->cmd_num = 1110 HAL_GET_FIELD( 1111 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1112 val1); 1113 h->exec_time = 1114 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1115 CMD_EXECUTION_TIME, val1); 1116 h->status = 1117 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1118 REO_CMD_EXECUTION_STATUS, val1); 1119 switch (b) { 1120 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1121 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1122 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1123 break; 1124 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1125 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1126 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1127 break; 1128 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1129 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1130 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1131 break; 1132 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1133 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1134 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1135 break; 1136 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1137 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1138 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1139 break; 1140 case HAL_REO_DESC_THRES_STATUS_TLV: 1141 val1 = 1142 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1143 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1144 break; 1145 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1146 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1147 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1148 break; 1149 default: 1150 qdf_nofl_err("ERROR: Unknown tlv\n"); 1151 break; 1152 } 1153 h->tstamp = 1154 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1155 } 1156 1157 /** 1158 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(): 1159 * Retrieve qos control valid bit from the tlv. 1160 * @buf: pointer to rx pkt TLV. 1161 * 1162 * Return: qos control value. 1163 */ 1164 static inline uint32_t 1165 hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(uint8_t *buf) 1166 { 1167 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1168 struct rx_mpdu_start *mpdu_start = 1169 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1170 1171 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1172 &mpdu_start->rx_mpdu_info_details); 1173 } 1174 1175 /** 1176 * hal_rx_msdu_end_sa_sw_peer_id_get_5018(): API to get the 1177 * sa_sw_peer_id from rx_msdu_end TLV 1178 * @buf: pointer to the start of RX PKT TLV headers 1179 * 1180 * Return: sa_sw_peer_id index 1181 */ 1182 static inline uint32_t 1183 hal_rx_msdu_end_sa_sw_peer_id_get_5018(uint8_t *buf) 1184 { 1185 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1186 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1187 1188 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1189 } 1190 1191 /** 1192 * hal_tx_desc_set_mesh_en_5018 - Set mesh_enable flag in Tx descriptor 1193 * @desc: Handle to Tx Descriptor 1194 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1195 * enabling the interpretation of the 'Mesh Control Present' bit 1196 * (bit 8) of QoS Control (otherwise this bit is ignored), 1197 * For native WiFi frames, this indicates that a 'Mesh Control' field 1198 * is present between the header and the LLC. 1199 * 1200 * Return: void 1201 */ 1202 static inline 1203 void hal_tx_desc_set_mesh_en_5018(void *desc, uint8_t en) 1204 { 1205 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1206 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1207 } 1208 1209 static 1210 void *hal_rx_msdu0_buffer_addr_lsb_5018(void *link_desc_va) 1211 { 1212 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1213 } 1214 1215 static 1216 void *hal_rx_msdu_desc_info_ptr_get_5018(void *msdu0) 1217 { 1218 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1219 } 1220 1221 static 1222 void *hal_ent_mpdu_desc_info_5018(void *ent_ring_desc) 1223 { 1224 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1225 } 1226 1227 static 1228 void *hal_dst_mpdu_desc_info_5018(void *dst_ring_desc) 1229 { 1230 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1231 } 1232 1233 static 1234 uint8_t hal_rx_get_fc_valid_5018(uint8_t *buf) 1235 { 1236 return HAL_RX_GET_FC_VALID(buf); 1237 } 1238 1239 static uint8_t hal_rx_get_to_ds_flag_5018(uint8_t *buf) 1240 { 1241 return HAL_RX_GET_TO_DS_FLAG(buf); 1242 } 1243 1244 static uint8_t hal_rx_get_mac_addr2_valid_5018(uint8_t *buf) 1245 { 1246 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1247 } 1248 1249 static uint8_t hal_rx_get_filter_category_5018(uint8_t *buf) 1250 { 1251 return HAL_RX_GET_FILTER_CATEGORY(buf); 1252 } 1253 1254 static uint32_t 1255 hal_rx_get_ppdu_id_5018(uint8_t *buf) 1256 { 1257 struct rx_mpdu_info *rx_mpdu_info; 1258 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 1259 1260 rx_mpdu_info = 1261 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1262 1263 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 1264 } 1265 1266 /** 1267 * hal_reo_config_5018(): Set reo config parameters 1268 * @soc: hal soc handle 1269 * @reg_val: value to be set 1270 * @reo_params: reo parameters 1271 * 1272 * Return: void 1273 */ 1274 static void 1275 hal_reo_config_5018(struct hal_soc *soc, 1276 uint32_t reg_val, 1277 struct hal_reo_params *reo_params) 1278 { 1279 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1280 } 1281 1282 /** 1283 * hal_rx_msdu_desc_info_get_ptr_5018() - Get msdu desc info ptr 1284 * @msdu_details_ptr - Pointer to msdu_details_ptr 1285 * 1286 * Return - Pointer to rx_msdu_desc_info structure. 1287 * 1288 */ 1289 static void *hal_rx_msdu_desc_info_get_ptr_5018(void *msdu_details_ptr) 1290 { 1291 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1292 } 1293 1294 /** 1295 * hal_rx_link_desc_msdu0_ptr_5018 - Get pointer to rx_msdu details 1296 * @link_desc - Pointer to link desc 1297 * 1298 * Return - Pointer to rx_msdu_details structure 1299 * 1300 */ 1301 static void *hal_rx_link_desc_msdu0_ptr_5018(void *link_desc) 1302 { 1303 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1304 } 1305 1306 /** 1307 * hal_rx_msdu_flow_idx_get_5018: API to get flow index 1308 * from rx_msdu_end TLV 1309 * @buf: pointer to the start of RX PKT TLV headers 1310 * 1311 * Return: flow index value from MSDU END TLV 1312 */ 1313 static inline uint32_t hal_rx_msdu_flow_idx_get_5018(uint8_t *buf) 1314 { 1315 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1316 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1317 1318 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1319 } 1320 1321 /** 1322 * hal_rx_msdu_flow_idx_invalid_5018: API to get flow index invalid 1323 * from rx_msdu_end TLV 1324 * @buf: pointer to the start of RX PKT TLV headers 1325 * 1326 * Return: flow index invalid value from MSDU END TLV 1327 */ 1328 static bool hal_rx_msdu_flow_idx_invalid_5018(uint8_t *buf) 1329 { 1330 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1331 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1332 1333 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1334 } 1335 1336 /** 1337 * hal_rx_msdu_flow_idx_timeout_5018: API to get flow index timeout 1338 * from rx_msdu_end TLV 1339 * @buf: pointer to the start of RX PKT TLV headers 1340 * 1341 * Return: flow index timeout value from MSDU END TLV 1342 */ 1343 static bool hal_rx_msdu_flow_idx_timeout_5018(uint8_t *buf) 1344 { 1345 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1346 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1347 1348 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1349 } 1350 1351 /** 1352 * hal_rx_msdu_fse_metadata_get_5018: API to get FSE metadata 1353 * from rx_msdu_end TLV 1354 * @buf: pointer to the start of RX PKT TLV headers 1355 * 1356 * Return: fse metadata value from MSDU END TLV 1357 */ 1358 static uint32_t hal_rx_msdu_fse_metadata_get_5018(uint8_t *buf) 1359 { 1360 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1361 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1362 1363 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1364 } 1365 1366 /** 1367 * hal_rx_msdu_cce_metadata_get_5018: API to get CCE metadata 1368 * from rx_msdu_end TLV 1369 * @buf: pointer to the start of RX PKT TLV headers 1370 * 1371 * Return: cce_metadata 1372 */ 1373 static uint16_t 1374 hal_rx_msdu_cce_metadata_get_5018(uint8_t *buf) 1375 { 1376 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1377 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1378 1379 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1380 } 1381 1382 /** 1383 * hal_rx_msdu_get_flow_params_5018: API to get flow index, flow index invalid 1384 * and flow index timeout from rx_msdu_end TLV 1385 * @buf: pointer to the start of RX PKT TLV headers 1386 * @flow_invalid: pointer to return value of flow_idx_valid 1387 * @flow_timeout: pointer to return value of flow_idx_timeout 1388 * @flow_index: pointer to return value of flow_idx 1389 * 1390 * Return: none 1391 */ 1392 static inline void 1393 hal_rx_msdu_get_flow_params_5018(uint8_t *buf, 1394 bool *flow_invalid, 1395 bool *flow_timeout, 1396 uint32_t *flow_index) 1397 { 1398 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1399 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1400 1401 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1402 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1403 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1404 } 1405 1406 /** 1407 * hal_rx_tlv_get_tcp_chksum_5018() - API to get tcp checksum 1408 * @buf: rx_tlv_hdr 1409 * 1410 * Return: tcp checksum 1411 */ 1412 static uint16_t 1413 hal_rx_tlv_get_tcp_chksum_5018(uint8_t *buf) 1414 { 1415 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1416 } 1417 1418 /** 1419 * hal_rx_get_rx_sequence_5018(): Function to retrieve rx sequence number 1420 * 1421 * @nbuf: Network buffer 1422 * Returns: rx sequence number 1423 */ 1424 static 1425 uint16_t hal_rx_get_rx_sequence_5018(uint8_t *buf) 1426 { 1427 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1428 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1429 1430 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1431 } 1432 1433 /** 1434 * hal_get_window_address_5018(): Function to get hp/tp address 1435 * @hal_soc: Pointer to hal_soc 1436 * @addr: address offset of register 1437 * 1438 * Return: modified address offset of register 1439 */ 1440 static inline qdf_iomem_t hal_get_window_address_5018(struct hal_soc *hal_soc, 1441 qdf_iomem_t addr) 1442 { 1443 uint32_t offset = addr - hal_soc->dev_base_addr; 1444 qdf_iomem_t new_offset; 1445 1446 /* 1447 * Check if offset lies within CE register range(0x08400000) 1448 * or UMAC/DP register range (0x00A00000). 1449 * If offset lies within CE register range, map it 1450 * into CE region. 1451 */ 1452 if (offset & HOST_CE_MASK_VALUE) { 1453 offset = offset - WFSS_CE_REG_BASE; 1454 new_offset = (hal_soc->dev_base_addr_ce + offset); 1455 1456 return new_offset; 1457 } else { 1458 /* 1459 * If offset lies within DP register range, 1460 * return the address as such 1461 */ 1462 return addr; 1463 } 1464 } 1465 1466 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1467 { 1468 /* Write value into window configuration register */ 1469 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1470 WINDOW_CONFIGURATION_VALUE_5018); 1471 } 1472 1473 /** 1474 * hal_rx_msdu_packet_metadata_get_5018(): API to get the 1475 * msdu information from rx_msdu_end TLV 1476 * 1477 * @ buf: pointer to the start of RX PKT TLV headers 1478 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 1479 */ 1480 static void 1481 hal_rx_msdu_packet_metadata_get_5018(uint8_t *buf, 1482 void *msdu_pkt_metadata) 1483 { 1484 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1485 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1486 struct hal_rx_msdu_metadata *msdu_metadata = 1487 (struct hal_rx_msdu_metadata *)msdu_pkt_metadata; 1488 1489 msdu_metadata->l3_hdr_pad = 1490 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1491 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1492 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 1493 msdu_metadata->sa_sw_peer_id = 1494 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1495 } 1496 1497 /** 1498 * hal_rx_flow_setup_fse_5018() - Setup a flow search entry in HW FST 1499 * @fst: Pointer to the Rx Flow Search Table 1500 * @table_offset: offset into the table where the flow is to be setup 1501 * @flow: Flow Parameters 1502 * 1503 * Return: Success/Failure 1504 */ 1505 static void * 1506 hal_rx_flow_setup_fse_5018(uint8_t *rx_fst, uint32_t table_offset, 1507 uint8_t *rx_flow) 1508 { 1509 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1510 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1511 uint8_t *fse; 1512 bool fse_valid; 1513 1514 if (table_offset >= fst->max_entries) { 1515 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1516 "HAL FSE table offset %u exceeds max entries %u", 1517 table_offset, fst->max_entries); 1518 return NULL; 1519 } 1520 1521 fse = (uint8_t *)fst->base_vaddr + 1522 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1523 1524 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1525 1526 if (fse_valid) { 1527 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1528 "HAL FSE %pK already valid", fse); 1529 return NULL; 1530 } 1531 1532 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1533 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1534 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1535 1536 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1537 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1538 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1539 1540 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1541 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1542 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1543 1544 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1545 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1546 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1547 1548 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1549 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1550 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1551 1552 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1553 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1554 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1555 1556 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1557 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1558 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1559 1560 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1561 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1562 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1563 1564 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1565 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1566 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1567 (flow->tuple_info.dest_port)); 1568 1569 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1570 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1571 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1572 (flow->tuple_info.src_port)); 1573 1574 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1575 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1576 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1577 flow->tuple_info.l4_protocol); 1578 1579 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1580 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1581 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1582 flow->reo_destination_handler); 1583 1584 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1585 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1586 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1587 1588 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1589 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1590 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1591 flow->fse_metadata); 1592 1593 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1594 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1595 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1596 REO_DESTINATION_INDICATION, 1597 flow->reo_destination_indication); 1598 1599 /* Reset all the other fields in FSE */ 1600 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1601 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1602 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1603 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1604 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1605 1606 return fse; 1607 } 1608 1609 struct hal_hw_txrx_ops qca5018_hal_hw_txrx_ops = { 1610 1611 /* init and setup */ 1612 hal_srng_dst_hw_init_generic, 1613 hal_srng_src_hw_init_generic, 1614 hal_get_hw_hptp_generic, 1615 hal_reo_setup_generic, 1616 hal_setup_link_idle_list_generic, 1617 hal_get_window_address_5018, 1618 NULL, 1619 1620 /* tx */ 1621 hal_tx_desc_set_dscp_tid_table_id_5018, 1622 hal_tx_set_dscp_tid_map_5018, 1623 hal_tx_update_dscp_tid_5018, 1624 hal_tx_desc_set_lmac_id_5018, 1625 hal_tx_desc_set_buf_addr_generic, 1626 hal_tx_desc_set_search_type_generic, 1627 hal_tx_desc_set_search_index_generic, 1628 hal_tx_desc_set_cache_set_num_generic, 1629 hal_tx_comp_get_status_generic, 1630 hal_tx_comp_get_release_reason_generic, 1631 hal_get_wbm_internal_error_generic, 1632 hal_tx_desc_set_mesh_en_5018, 1633 hal_tx_init_cmd_credit_ring_5018, 1634 1635 /* rx */ 1636 hal_rx_msdu_start_nss_get_5018, 1637 hal_rx_mon_hw_desc_get_mpdu_status_5018, 1638 hal_rx_get_tlv_5018, 1639 hal_rx_proc_phyrx_other_receive_info_tlv_5018, 1640 hal_rx_dump_msdu_start_tlv_5018, 1641 hal_rx_dump_msdu_end_tlv_5018, 1642 hal_get_link_desc_size_5018, 1643 hal_rx_mpdu_start_tid_get_5018, 1644 hal_rx_msdu_start_reception_type_get_5018, 1645 hal_rx_msdu_end_da_idx_get_5018, 1646 hal_rx_msdu_desc_info_get_ptr_5018, 1647 hal_rx_link_desc_msdu0_ptr_5018, 1648 hal_reo_status_get_header_5018, 1649 hal_rx_status_get_tlv_info_generic, 1650 hal_rx_wbm_err_info_get_generic, 1651 hal_rx_dump_mpdu_start_tlv_generic, 1652 1653 hal_tx_set_pcp_tid_map_generic, 1654 hal_tx_update_pcp_tid_generic, 1655 hal_tx_update_tidmap_prty_generic, 1656 hal_rx_get_rx_fragment_number_5018, 1657 hal_rx_msdu_end_da_is_mcbc_get_5018, 1658 hal_rx_msdu_end_sa_is_valid_get_5018, 1659 hal_rx_msdu_end_sa_idx_get_5018, 1660 hal_rx_desc_is_first_msdu_5018, 1661 hal_rx_msdu_end_l3_hdr_padding_get_5018, 1662 hal_rx_encryption_info_valid_5018, 1663 hal_rx_print_pn_5018, 1664 hal_rx_msdu_end_first_msdu_get_5018, 1665 hal_rx_msdu_end_da_is_valid_get_5018, 1666 hal_rx_msdu_end_last_msdu_get_5018, 1667 hal_rx_get_mpdu_mac_ad4_valid_5018, 1668 hal_rx_mpdu_start_sw_peer_id_get_5018, 1669 hal_rx_mpdu_get_to_ds_5018, 1670 hal_rx_mpdu_get_fr_ds_5018, 1671 hal_rx_get_mpdu_frame_control_valid_5018, 1672 hal_rx_mpdu_get_addr1_5018, 1673 hal_rx_mpdu_get_addr2_5018, 1674 hal_rx_mpdu_get_addr3_5018, 1675 hal_rx_mpdu_get_addr4_5018, 1676 hal_rx_get_mpdu_sequence_control_valid_5018, 1677 hal_rx_is_unicast_5018, 1678 hal_rx_tid_get_5018, 1679 hal_rx_hw_desc_get_ppduid_get_5018, 1680 hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018, 1681 hal_rx_msdu_end_sa_sw_peer_id_get_5018, 1682 hal_rx_msdu0_buffer_addr_lsb_5018, 1683 hal_rx_msdu_desc_info_ptr_get_5018, 1684 hal_ent_mpdu_desc_info_5018, 1685 hal_dst_mpdu_desc_info_5018, 1686 hal_rx_get_fc_valid_5018, 1687 hal_rx_get_to_ds_flag_5018, 1688 hal_rx_get_mac_addr2_valid_5018, 1689 hal_rx_get_filter_category_5018, 1690 hal_rx_get_ppdu_id_5018, 1691 hal_reo_config_5018, 1692 hal_rx_msdu_flow_idx_get_5018, 1693 hal_rx_msdu_flow_idx_invalid_5018, 1694 hal_rx_msdu_flow_idx_timeout_5018, 1695 hal_rx_msdu_fse_metadata_get_5018, 1696 hal_rx_msdu_cce_metadata_get_5018, 1697 hal_rx_msdu_get_flow_params_5018, 1698 hal_rx_tlv_get_tcp_chksum_5018, 1699 hal_rx_get_rx_sequence_5018, 1700 NULL, 1701 NULL, 1702 /* rx - msdu fast path info fields */ 1703 hal_rx_msdu_packet_metadata_get_5018, 1704 NULL, 1705 NULL, 1706 NULL, 1707 NULL, 1708 NULL, 1709 NULL, 1710 hal_rx_mpdu_start_tlv_tag_valid_5018, 1711 NULL, 1712 hal_rx_wbm_err_msdu_continuation_get_5018, 1713 1714 /* rx - TLV struct offsets */ 1715 hal_rx_msdu_end_offset_get_generic, 1716 hal_rx_attn_offset_get_generic, 1717 hal_rx_msdu_start_offset_get_generic, 1718 hal_rx_mpdu_start_offset_get_generic, 1719 hal_rx_mpdu_end_offset_get_generic, 1720 hal_rx_flow_setup_fse_5018, 1721 hal_compute_reo_remap_ix2_ix3_5018 1722 }; 1723 1724 struct hal_hw_srng_config hw_srng_table_5018[] = { 1725 /* TODO: max_rings can populated by querying HW capabilities */ 1726 { /* REO_DST */ 1727 .start_ring_id = HAL_SRNG_REO2SW1, 1728 .max_rings = 4, 1729 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1730 .lmac_ring = FALSE, 1731 .ring_dir = HAL_SRNG_DST_RING, 1732 .reg_start = { 1733 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1734 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1735 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1736 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1737 }, 1738 .reg_size = { 1739 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1740 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1741 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1742 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1743 }, 1744 .max_size = 1745 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1746 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1747 }, 1748 { /* REO_EXCEPTION */ 1749 /* Designating REO2TCL ring as exception ring. This ring is 1750 * similar to other REO2SW rings though it is named as REO2TCL. 1751 * Any of theREO2SW rings can be used as exception ring. 1752 */ 1753 .start_ring_id = HAL_SRNG_REO2TCL, 1754 .max_rings = 1, 1755 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1756 .lmac_ring = FALSE, 1757 .ring_dir = HAL_SRNG_DST_RING, 1758 .reg_start = { 1759 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1760 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1761 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1762 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1763 }, 1764 /* Single ring - provide ring size if multiple rings of this 1765 * type are supported 1766 */ 1767 .reg_size = {}, 1768 .max_size = 1769 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1770 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1771 }, 1772 { /* REO_REINJECT */ 1773 .start_ring_id = HAL_SRNG_SW2REO, 1774 .max_rings = 1, 1775 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1776 .lmac_ring = FALSE, 1777 .ring_dir = HAL_SRNG_SRC_RING, 1778 .reg_start = { 1779 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1780 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1781 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1782 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1783 }, 1784 /* Single ring - provide ring size if multiple rings of this 1785 * type are supported 1786 */ 1787 .reg_size = {}, 1788 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1789 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1790 }, 1791 { /* REO_CMD */ 1792 .start_ring_id = HAL_SRNG_REO_CMD, 1793 .max_rings = 1, 1794 .entry_size = (sizeof(struct tlv_32_hdr) + 1795 sizeof(struct reo_get_queue_stats)) >> 2, 1796 .lmac_ring = FALSE, 1797 .ring_dir = HAL_SRNG_SRC_RING, 1798 .reg_start = { 1799 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1800 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1801 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1802 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1803 }, 1804 /* Single ring - provide ring size if multiple rings of this 1805 * type are supported 1806 */ 1807 .reg_size = {}, 1808 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1809 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1810 }, 1811 { /* REO_STATUS */ 1812 .start_ring_id = HAL_SRNG_REO_STATUS, 1813 .max_rings = 1, 1814 .entry_size = (sizeof(struct tlv_32_hdr) + 1815 sizeof(struct reo_get_queue_stats_status)) >> 2, 1816 .lmac_ring = FALSE, 1817 .ring_dir = HAL_SRNG_DST_RING, 1818 .reg_start = { 1819 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1820 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1821 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1822 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1823 }, 1824 /* Single ring - provide ring size if multiple rings of this 1825 * type are supported 1826 */ 1827 .reg_size = {}, 1828 .max_size = 1829 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1830 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1831 }, 1832 { /* TCL_DATA */ 1833 .start_ring_id = HAL_SRNG_SW2TCL1, 1834 .max_rings = 3, 1835 .entry_size = (sizeof(struct tlv_32_hdr) + 1836 sizeof(struct tcl_data_cmd)) >> 2, 1837 .lmac_ring = FALSE, 1838 .ring_dir = HAL_SRNG_SRC_RING, 1839 .reg_start = { 1840 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1841 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1842 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1843 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1844 }, 1845 .reg_size = { 1846 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1847 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1848 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1849 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1850 }, 1851 .max_size = 1852 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1853 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1854 }, 1855 { /* TCL_CMD */ 1856 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1857 .max_rings = 1, 1858 .entry_size = (sizeof(struct tlv_32_hdr) + 1859 sizeof(struct tcl_data_cmd)) >> 2, 1860 .lmac_ring = FALSE, 1861 .ring_dir = HAL_SRNG_SRC_RING, 1862 .reg_start = { 1863 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 1864 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1865 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 1866 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1867 }, 1868 /* Single ring - provide ring size if multiple rings of this 1869 * type are supported 1870 */ 1871 .reg_size = {}, 1872 .max_size = 1873 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 1874 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 1875 }, 1876 { /* TCL_STATUS */ 1877 .start_ring_id = HAL_SRNG_TCL_STATUS, 1878 .max_rings = 1, 1879 .entry_size = (sizeof(struct tlv_32_hdr) + 1880 sizeof(struct tcl_status_ring)) >> 2, 1881 .lmac_ring = FALSE, 1882 .ring_dir = HAL_SRNG_DST_RING, 1883 .reg_start = { 1884 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1885 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1886 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1887 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1888 }, 1889 /* Single ring - provide ring size if multiple rings of this 1890 * type are supported 1891 */ 1892 .reg_size = {}, 1893 .max_size = 1894 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1895 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1896 }, 1897 { /* CE_SRC */ 1898 .start_ring_id = HAL_SRNG_CE_0_SRC, 1899 .max_rings = 12, 1900 .entry_size = sizeof(struct ce_src_desc) >> 2, 1901 .lmac_ring = FALSE, 1902 .ring_dir = HAL_SRNG_SRC_RING, 1903 .reg_start = { 1904 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1905 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1906 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1907 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1908 }, 1909 .reg_size = { 1910 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1911 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1912 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1913 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1914 }, 1915 .max_size = 1916 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1917 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1918 }, 1919 { /* CE_DST */ 1920 .start_ring_id = HAL_SRNG_CE_0_DST, 1921 .max_rings = 12, 1922 .entry_size = 8 >> 2, 1923 /*TODO: entry_size above should actually be 1924 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1925 * of struct ce_dst_desc in HW header files 1926 */ 1927 .lmac_ring = FALSE, 1928 .ring_dir = HAL_SRNG_SRC_RING, 1929 .reg_start = { 1930 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1931 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1932 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1933 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1934 }, 1935 .reg_size = { 1936 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1937 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1938 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1939 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1940 }, 1941 .max_size = 1942 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1943 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1944 }, 1945 { /* CE_DST_STATUS */ 1946 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1947 .max_rings = 12, 1948 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1949 .lmac_ring = FALSE, 1950 .ring_dir = HAL_SRNG_DST_RING, 1951 .reg_start = { 1952 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1953 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1954 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1955 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1956 }, 1957 /* TODO: check destination status ring registers */ 1958 .reg_size = { 1959 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1960 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1961 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1962 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1963 }, 1964 .max_size = 1965 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1966 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1967 }, 1968 { /* WBM_IDLE_LINK */ 1969 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1970 .max_rings = 1, 1971 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1972 .lmac_ring = FALSE, 1973 .ring_dir = HAL_SRNG_SRC_RING, 1974 .reg_start = { 1975 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1976 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1977 }, 1978 /* Single ring - provide ring size if multiple rings of this 1979 * type are supported 1980 */ 1981 .reg_size = {}, 1982 .max_size = 1983 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1984 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1985 }, 1986 { /* SW2WBM_RELEASE */ 1987 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1988 .max_rings = 1, 1989 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1990 .lmac_ring = FALSE, 1991 .ring_dir = HAL_SRNG_SRC_RING, 1992 .reg_start = { 1993 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1994 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1995 }, 1996 /* Single ring - provide ring size if multiple rings of this 1997 * type are supported 1998 */ 1999 .reg_size = {}, 2000 .max_size = 2001 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2002 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2003 }, 2004 { /* WBM2SW_RELEASE */ 2005 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2006 .max_rings = 4, 2007 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2008 .lmac_ring = FALSE, 2009 .ring_dir = HAL_SRNG_DST_RING, 2010 .reg_start = { 2011 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2012 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2013 }, 2014 .reg_size = { 2015 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2016 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2017 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2018 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2019 }, 2020 .max_size = 2021 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2022 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2023 }, 2024 { /* RXDMA_BUF */ 2025 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2026 #ifdef IPA_OFFLOAD 2027 .max_rings = 3, 2028 #else 2029 .max_rings = 2, 2030 #endif 2031 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2032 .lmac_ring = TRUE, 2033 .ring_dir = HAL_SRNG_SRC_RING, 2034 /* reg_start is not set because LMAC rings are not accessed 2035 * from host 2036 */ 2037 .reg_start = {}, 2038 .reg_size = {}, 2039 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2040 }, 2041 { /* RXDMA_DST */ 2042 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2043 .max_rings = 1, 2044 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2045 .lmac_ring = TRUE, 2046 .ring_dir = HAL_SRNG_DST_RING, 2047 /* reg_start is not set because LMAC rings are not accessed 2048 * from host 2049 */ 2050 .reg_start = {}, 2051 .reg_size = {}, 2052 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2053 }, 2054 { /* RXDMA_MONITOR_BUF */ 2055 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2056 .max_rings = 1, 2057 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2058 .lmac_ring = TRUE, 2059 .ring_dir = HAL_SRNG_SRC_RING, 2060 /* reg_start is not set because LMAC rings are not accessed 2061 * from host 2062 */ 2063 .reg_start = {}, 2064 .reg_size = {}, 2065 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2066 }, 2067 { /* RXDMA_MONITOR_STATUS */ 2068 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2069 .max_rings = 1, 2070 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2071 .lmac_ring = TRUE, 2072 .ring_dir = HAL_SRNG_SRC_RING, 2073 /* reg_start is not set because LMAC rings are not accessed 2074 * from host 2075 */ 2076 .reg_start = {}, 2077 .reg_size = {}, 2078 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2079 }, 2080 { /* RXDMA_MONITOR_DST */ 2081 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2082 .max_rings = 1, 2083 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2084 .lmac_ring = TRUE, 2085 .ring_dir = HAL_SRNG_DST_RING, 2086 /* reg_start is not set because LMAC rings are not accessed 2087 * from host 2088 */ 2089 .reg_start = {}, 2090 .reg_size = {}, 2091 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2092 }, 2093 { /* RXDMA_MONITOR_DESC */ 2094 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2095 .max_rings = 1, 2096 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2097 .lmac_ring = TRUE, 2098 .ring_dir = HAL_SRNG_SRC_RING, 2099 /* reg_start is not set because LMAC rings are not accessed 2100 * from host 2101 */ 2102 .reg_start = {}, 2103 .reg_size = {}, 2104 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2105 }, 2106 { /* DIR_BUF_RX_DMA_SRC */ 2107 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2108 /* one ring for spectral and one ring for cfr */ 2109 .max_rings = 2, 2110 .entry_size = 2, 2111 .lmac_ring = TRUE, 2112 .ring_dir = HAL_SRNG_SRC_RING, 2113 /* reg_start is not set because LMAC rings are not accessed 2114 * from host 2115 */ 2116 .reg_start = {}, 2117 .reg_size = {}, 2118 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2119 }, 2120 #ifdef WLAN_FEATURE_CIF_CFR 2121 { /* WIFI_POS_SRC */ 2122 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2123 .max_rings = 1, 2124 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2125 .lmac_ring = TRUE, 2126 .ring_dir = HAL_SRNG_SRC_RING, 2127 /* reg_start is not set because LMAC rings are not accessed 2128 * from host 2129 */ 2130 .reg_start = {}, 2131 .reg_size = {}, 2132 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2133 }, 2134 #endif 2135 }; 2136 2137 int32_t hal_hw_reg_offset_qca5018[] = { 2138 /* dst */ 2139 REG_OFFSET(DST, HP), 2140 REG_OFFSET(DST, TP), 2141 REG_OFFSET(DST, ID), 2142 REG_OFFSET(DST, MISC), 2143 REG_OFFSET(DST, HP_ADDR_LSB), 2144 REG_OFFSET(DST, HP_ADDR_MSB), 2145 REG_OFFSET(DST, MSI1_BASE_LSB), 2146 REG_OFFSET(DST, MSI1_BASE_MSB), 2147 REG_OFFSET(DST, MSI1_DATA), 2148 REG_OFFSET(DST, BASE_LSB), 2149 REG_OFFSET(DST, BASE_MSB), 2150 REG_OFFSET(DST, PRODUCER_INT_SETUP), 2151 /* src */ 2152 REG_OFFSET(SRC, HP), 2153 REG_OFFSET(SRC, TP), 2154 REG_OFFSET(SRC, ID), 2155 REG_OFFSET(SRC, MISC), 2156 REG_OFFSET(SRC, TP_ADDR_LSB), 2157 REG_OFFSET(SRC, TP_ADDR_MSB), 2158 REG_OFFSET(SRC, MSI1_BASE_LSB), 2159 REG_OFFSET(SRC, MSI1_BASE_MSB), 2160 REG_OFFSET(SRC, MSI1_DATA), 2161 REG_OFFSET(SRC, BASE_LSB), 2162 REG_OFFSET(SRC, BASE_MSB), 2163 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), 2164 REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), 2165 }; 2166 2167 /** 2168 * hal_qca5018_attach()- Attach 5018 target specific hal_soc ops, 2169 * offset and srng table 2170 * Return: void 2171 */ 2172 void hal_qca5018_attach(struct hal_soc *hal_soc) 2173 { 2174 hal_soc->hw_srng_table = hw_srng_table_5018; 2175 hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca5018; 2176 hal_soc->ops = &qca5018_hal_hw_txrx_ops; 2177 } 2178