1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 #include "hal_li_hw_headers.h" 19 #include "hal_internal.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 #include "hal_flow.h" 25 #include "rx_flow_search_entry.h" 26 #include "hal_rx_flow_info.h" 27 28 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 29 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 30 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 31 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 33 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 34 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 35 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 36 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 37 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 38 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 39 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 40 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 41 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 42 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 43 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 44 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 45 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 46 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 47 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 48 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 49 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 50 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 51 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 52 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 53 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 54 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 55 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 56 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 57 RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 58 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 59 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 60 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 61 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 62 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 63 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 64 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 65 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 66 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 67 STATUS_HEADER_REO_STATUS_NUMBER 68 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 69 STATUS_HEADER_TIMESTAMP 70 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 71 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 72 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 73 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 74 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 75 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 76 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 77 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 78 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 79 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 80 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 81 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 82 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 83 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 84 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 85 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 86 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 87 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 88 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 89 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 90 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 91 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 92 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 93 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 94 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 95 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 96 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 97 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 98 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 99 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 100 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 101 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 102 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 103 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 104 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 105 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 106 107 #define CE_WINDOW_ADDRESS_5018 \ 108 ((WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 109 110 #define UMAC_WINDOW_ADDRESS_5018 \ 111 ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 112 113 #define WINDOW_CONFIGURATION_VALUE_5018 \ 114 ((CE_WINDOW_ADDRESS_5018 << 6) |\ 115 (UMAC_WINDOW_ADDRESS_5018 << 12) | \ 116 WINDOW_ENABLE_BIT) 117 118 #define HOST_CE_MASK_VALUE 0xFF000000 119 120 #include "hal_5018_tx.h" 121 #include "hal_5018_rx.h" 122 #include <hal_generic_api.h> 123 #include "hal_li_rx.h" 124 #include "hal_li_api.h" 125 #include "hal_li_generic_api.h" 126 127 /** 128 * hal_rx_msdu_start_nss_get_5018(): API to get the NSS 129 * Interval from rx_msdu_start 130 * 131 * @buf: pointer to the start of RX PKT TLV header 132 * Return: uint32_t(nss) 133 */ 134 static uint32_t hal_rx_msdu_start_nss_get_5018(uint8_t *buf) 135 { 136 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 137 struct rx_msdu_start *msdu_start = 138 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 139 uint8_t mimo_ss_bitmap; 140 141 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 142 143 return qdf_get_hweight8(mimo_ss_bitmap); 144 } 145 146 /** 147 * hal_rx_mon_hw_desc_get_mpdu_status_5018(): Retrieve MPDU status 148 * 149 * @ hw_desc_addr: Start address of Rx HW TLVs 150 * @ rs: Status for monitor mode 151 * 152 * Return: void 153 */ 154 static void hal_rx_mon_hw_desc_get_mpdu_status_5018(void *hw_desc_addr, 155 struct mon_rx_status *rs) 156 { 157 struct rx_msdu_start *rx_msdu_start; 158 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 159 uint32_t reg_value; 160 const uint32_t sgi_hw_to_cdp[] = { 161 CDP_SGI_0_8_US, 162 CDP_SGI_0_4_US, 163 CDP_SGI_1_6_US, 164 CDP_SGI_3_2_US, 165 }; 166 167 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 168 169 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 170 171 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 172 RX_MSDU_START_5, USER_RSSI); 173 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 174 175 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 176 rs->sgi = sgi_hw_to_cdp[reg_value]; 177 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 178 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 179 /* TODO: rs->beamformed should be set for SU beamforming also */ 180 } 181 182 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 183 /** 184 * hal_get_link_desc_size_5018(): API to get the link desc size 185 * 186 * Return: uint32_t 187 */ 188 static uint32_t hal_get_link_desc_size_5018(void) 189 { 190 return LINK_DESC_SIZE; 191 } 192 193 /** 194 * hal_rx_get_tlv_5018(): API to get the tlv 195 * 196 * @rx_tlv: TLV data extracted from the rx packet 197 * Return: uint8_t 198 */ 199 static uint8_t hal_rx_get_tlv_5018(void *rx_tlv) 200 { 201 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 202 } 203 204 /** 205 * hal_rx_mpdu_start_tlv_tag_valid_5018 () - API to check if RX_MPDU_START 206 * tlv tag is valid 207 * 208 *@rx_tlv_hdr: start address of rx_pkt_tlvs 209 * 210 * Return: true if RX_MPDU_START is valied, else false. 211 */ 212 uint8_t hal_rx_mpdu_start_tlv_tag_valid_5018(void *rx_tlv_hdr) 213 { 214 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 215 uint32_t tlv_tag; 216 217 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 218 219 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 220 } 221 222 /** 223 * hal_rx_wbm_err_msdu_continuation_get_5018 () - API to check if WBM 224 * msdu continuation bit is set 225 * 226 *@wbm_desc: wbm release ring descriptor 227 * 228 * Return: true if msdu continuation bit is set. 229 */ 230 uint8_t hal_rx_wbm_err_msdu_continuation_get_5018(void *wbm_desc) 231 { 232 uint32_t comp_desc = 233 *(uint32_t *)(((uint8_t *)wbm_desc) + 234 WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET); 235 236 return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >> 237 WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB; 238 } 239 240 static 241 void hal_compute_reo_remap_ix2_ix3_5018(uint32_t *ring, uint32_t num_rings, 242 uint32_t *remap1, uint32_t *remap2) 243 { 244 switch (num_rings) { 245 case 1: 246 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 247 HAL_REO_REMAP_IX2(ring[0], 17) | 248 HAL_REO_REMAP_IX2(ring[0], 18) | 249 HAL_REO_REMAP_IX2(ring[0], 19) | 250 HAL_REO_REMAP_IX2(ring[0], 20) | 251 HAL_REO_REMAP_IX2(ring[0], 21) | 252 HAL_REO_REMAP_IX2(ring[0], 22) | 253 HAL_REO_REMAP_IX2(ring[0], 23); 254 255 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 256 HAL_REO_REMAP_IX3(ring[0], 25) | 257 HAL_REO_REMAP_IX3(ring[0], 26) | 258 HAL_REO_REMAP_IX3(ring[0], 27) | 259 HAL_REO_REMAP_IX3(ring[0], 28) | 260 HAL_REO_REMAP_IX3(ring[0], 29) | 261 HAL_REO_REMAP_IX3(ring[0], 30) | 262 HAL_REO_REMAP_IX3(ring[0], 31); 263 break; 264 case 2: 265 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 266 HAL_REO_REMAP_IX2(ring[0], 17) | 267 HAL_REO_REMAP_IX2(ring[1], 18) | 268 HAL_REO_REMAP_IX2(ring[1], 19) | 269 HAL_REO_REMAP_IX2(ring[0], 20) | 270 HAL_REO_REMAP_IX2(ring[0], 21) | 271 HAL_REO_REMAP_IX2(ring[1], 22) | 272 HAL_REO_REMAP_IX2(ring[1], 23); 273 274 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 275 HAL_REO_REMAP_IX3(ring[0], 25) | 276 HAL_REO_REMAP_IX3(ring[1], 26) | 277 HAL_REO_REMAP_IX3(ring[1], 27) | 278 HAL_REO_REMAP_IX3(ring[0], 28) | 279 HAL_REO_REMAP_IX3(ring[0], 29) | 280 HAL_REO_REMAP_IX3(ring[1], 30) | 281 HAL_REO_REMAP_IX3(ring[1], 31); 282 break; 283 case 3: 284 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 285 HAL_REO_REMAP_IX2(ring[1], 17) | 286 HAL_REO_REMAP_IX2(ring[2], 18) | 287 HAL_REO_REMAP_IX2(ring[0], 19) | 288 HAL_REO_REMAP_IX2(ring[1], 20) | 289 HAL_REO_REMAP_IX2(ring[2], 21) | 290 HAL_REO_REMAP_IX2(ring[0], 22) | 291 HAL_REO_REMAP_IX2(ring[1], 23); 292 293 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 294 HAL_REO_REMAP_IX3(ring[0], 25) | 295 HAL_REO_REMAP_IX3(ring[1], 26) | 296 HAL_REO_REMAP_IX3(ring[2], 27) | 297 HAL_REO_REMAP_IX3(ring[0], 28) | 298 HAL_REO_REMAP_IX3(ring[1], 29) | 299 HAL_REO_REMAP_IX3(ring[2], 30) | 300 HAL_REO_REMAP_IX3(ring[0], 31); 301 break; 302 case 4: 303 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 304 HAL_REO_REMAP_IX2(ring[1], 17) | 305 HAL_REO_REMAP_IX2(ring[2], 18) | 306 HAL_REO_REMAP_IX2(ring[3], 19) | 307 HAL_REO_REMAP_IX2(ring[0], 20) | 308 HAL_REO_REMAP_IX2(ring[1], 21) | 309 HAL_REO_REMAP_IX2(ring[2], 22) | 310 HAL_REO_REMAP_IX2(ring[3], 23); 311 312 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 313 HAL_REO_REMAP_IX3(ring[1], 25) | 314 HAL_REO_REMAP_IX3(ring[2], 26) | 315 HAL_REO_REMAP_IX3(ring[3], 27) | 316 HAL_REO_REMAP_IX3(ring[0], 28) | 317 HAL_REO_REMAP_IX3(ring[1], 29) | 318 HAL_REO_REMAP_IX3(ring[2], 30) | 319 HAL_REO_REMAP_IX3(ring[3], 31); 320 break; 321 } 322 } 323 324 /** 325 * hal_rx_proc_phyrx_other_receive_info_tlv_5018(): API to get tlv info 326 * 327 * Return: uint32_t 328 */ 329 static inline 330 void hal_rx_proc_phyrx_other_receive_info_tlv_5018(void *rx_tlv_hdr, 331 void *ppdu_info_hdl) 332 { 333 } 334 335 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 336 static inline 337 void hal_rx_get_bb_info_5018(void *rx_tlv, 338 void *ppdu_info_hdl) 339 { 340 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 341 342 ppdu_info->cfr_info.bb_captured_channel = 343 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); 344 345 ppdu_info->cfr_info.bb_captured_timeout = 346 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); 347 348 ppdu_info->cfr_info.bb_captured_reason = 349 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); 350 } 351 352 static inline 353 void hal_rx_get_rtt_info_5018(void *rx_tlv, 354 void *ppdu_info_hdl) 355 { 356 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 357 358 ppdu_info->cfr_info.rx_location_info_valid = 359 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, 360 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 361 362 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 363 HAL_RX_GET(rx_tlv, 364 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 365 RTT_CHE_BUFFER_POINTER_LOW32); 366 367 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 368 HAL_RX_GET(rx_tlv, 369 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 370 RTT_CHE_BUFFER_POINTER_HIGH8); 371 372 ppdu_info->cfr_info.chan_capture_status = 373 HAL_RX_GET(rx_tlv, 374 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 375 RESERVED_8); 376 } 377 #endif 378 379 /** 380 * hal_rx_dump_msdu_start_tlv_5018() : dump RX msdu_start TLV in structured 381 * human readable format. 382 * @ msdu_start: pointer the msdu_start TLV in pkt. 383 * @ dbg_level: log level. 384 * 385 * Return: void 386 */ 387 static void hal_rx_dump_msdu_start_tlv_5018(void *msdustart, 388 uint8_t dbg_level) 389 { 390 struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; 391 392 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 393 "rx_msdu_start tlv - " 394 "rxpcu_mpdu_filter_in_category: %d " 395 "sw_frame_group_id: %d " 396 "phy_ppdu_id: %d " 397 "msdu_length: %d " 398 "ipsec_esp: %d " 399 "l3_offset: %d " 400 "ipsec_ah: %d " 401 "l4_offset: %d " 402 "msdu_number: %d " 403 "decap_format: %d " 404 "ipv4_proto: %d " 405 "ipv6_proto: %d " 406 "tcp_proto: %d " 407 "udp_proto: %d " 408 "ip_frag: %d " 409 "tcp_only_ack: %d " 410 "da_is_bcast_mcast: %d " 411 "ip4_protocol_ip6_next_header: %d " 412 "toeplitz_hash_2_or_4: %d " 413 "flow_id_toeplitz: %d " 414 "user_rssi: %d " 415 "pkt_type: %d " 416 "stbc: %d " 417 "sgi: %d " 418 "rate_mcs: %d " 419 "receive_bandwidth: %d " 420 "reception_type: %d " 421 "ppdu_start_timestamp: %d " 422 "sw_phy_meta_data: %d ", 423 msdu_start->rxpcu_mpdu_filter_in_category, 424 msdu_start->sw_frame_group_id, 425 msdu_start->phy_ppdu_id, 426 msdu_start->msdu_length, 427 msdu_start->ipsec_esp, 428 msdu_start->l3_offset, 429 msdu_start->ipsec_ah, 430 msdu_start->l4_offset, 431 msdu_start->msdu_number, 432 msdu_start->decap_format, 433 msdu_start->ipv4_proto, 434 msdu_start->ipv6_proto, 435 msdu_start->tcp_proto, 436 msdu_start->udp_proto, 437 msdu_start->ip_frag, 438 msdu_start->tcp_only_ack, 439 msdu_start->da_is_bcast_mcast, 440 msdu_start->ip4_protocol_ip6_next_header, 441 msdu_start->toeplitz_hash_2_or_4, 442 msdu_start->flow_id_toeplitz, 443 msdu_start->user_rssi, 444 msdu_start->pkt_type, 445 msdu_start->stbc, 446 msdu_start->sgi, 447 msdu_start->rate_mcs, 448 msdu_start->receive_bandwidth, 449 msdu_start->reception_type, 450 msdu_start->ppdu_start_timestamp, 451 msdu_start->sw_phy_meta_data); 452 } 453 454 /** 455 * hal_rx_dump_msdu_end_tlv_5018: dump RX msdu_end TLV in structured 456 * human readable format. 457 * @ msdu_end: pointer the msdu_end TLV in pkt. 458 * @ dbg_level: log level. 459 * 460 * Return: void 461 */ 462 static void hal_rx_dump_msdu_end_tlv_5018(void *msduend, 463 uint8_t dbg_level) 464 { 465 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 466 467 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 468 "rx_msdu_end tlv - " 469 "rxpcu_mpdu_filter_in_category: %d " 470 "sw_frame_group_id: %d " 471 "phy_ppdu_id: %d " 472 "ip_hdr_chksum: %d " 473 "reported_mpdu_length: %d " 474 "key_id_octet: %d " 475 "cce_super_rule: %d " 476 "cce_classify_not_done_truncat: %d " 477 "cce_classify_not_done_cce_dis: %d " 478 "rule_indication_31_0: %d " 479 "rule_indication_63_32: %d " 480 "da_offset: %d " 481 "sa_offset: %d " 482 "da_offset_valid: %d " 483 "sa_offset_valid: %d " 484 "ipv6_options_crc: %d " 485 "tcp_seq_number: %d " 486 "tcp_ack_number: %d " 487 "tcp_flag: %d " 488 "lro_eligible: %d " 489 "window_size: %d " 490 "tcp_udp_chksum: %d " 491 "sa_idx_timeout: %d " 492 "da_idx_timeout: %d " 493 "msdu_limit_error: %d " 494 "flow_idx_timeout: %d " 495 "flow_idx_invalid: %d " 496 "wifi_parser_error: %d " 497 "amsdu_parser_error: %d " 498 "sa_is_valid: %d " 499 "da_is_valid: %d " 500 "da_is_mcbc: %d " 501 "l3_header_padding: %d " 502 "first_msdu: %d " 503 "last_msdu: %d " 504 "sa_idx: %d " 505 "msdu_drop: %d " 506 "reo_destination_indication: %d " 507 "flow_idx: %d " 508 "fse_metadata: %d " 509 "cce_metadata: %d " 510 "sa_sw_peer_id: %d ", 511 msdu_end->rxpcu_mpdu_filter_in_category, 512 msdu_end->sw_frame_group_id, 513 msdu_end->phy_ppdu_id, 514 msdu_end->ip_hdr_chksum, 515 msdu_end->reported_mpdu_length, 516 msdu_end->key_id_octet, 517 msdu_end->cce_super_rule, 518 msdu_end->cce_classify_not_done_truncate, 519 msdu_end->cce_classify_not_done_cce_dis, 520 msdu_end->rule_indication_31_0, 521 msdu_end->rule_indication_63_32, 522 msdu_end->da_offset, 523 msdu_end->sa_offset, 524 msdu_end->da_offset_valid, 525 msdu_end->sa_offset_valid, 526 msdu_end->ipv6_options_crc, 527 msdu_end->tcp_seq_number, 528 msdu_end->tcp_ack_number, 529 msdu_end->tcp_flag, 530 msdu_end->lro_eligible, 531 msdu_end->window_size, 532 msdu_end->tcp_udp_chksum, 533 msdu_end->sa_idx_timeout, 534 msdu_end->da_idx_timeout, 535 msdu_end->msdu_limit_error, 536 msdu_end->flow_idx_timeout, 537 msdu_end->flow_idx_invalid, 538 msdu_end->wifi_parser_error, 539 msdu_end->amsdu_parser_error, 540 msdu_end->sa_is_valid, 541 msdu_end->da_is_valid, 542 msdu_end->da_is_mcbc, 543 msdu_end->l3_header_padding, 544 msdu_end->first_msdu, 545 msdu_end->last_msdu, 546 msdu_end->sa_idx, 547 msdu_end->msdu_drop, 548 msdu_end->reo_destination_indication, 549 msdu_end->flow_idx, 550 msdu_end->fse_metadata, 551 msdu_end->cce_metadata, 552 msdu_end->sa_sw_peer_id); 553 } 554 555 /** 556 * hal_rx_mpdu_start_tid_get_5018(): API to get tid 557 * from rx_msdu_start 558 * 559 * @buf: pointer to the start of RX PKT TLV header 560 * Return: uint32_t(tid value) 561 */ 562 static uint32_t hal_rx_mpdu_start_tid_get_5018(uint8_t *buf) 563 { 564 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 565 struct rx_mpdu_start *mpdu_start = 566 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 567 uint32_t tid; 568 569 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 570 571 return tid; 572 } 573 574 /** 575 * hal_rx_msdu_start_reception_type_get(): API to get the reception type 576 * Interval from rx_msdu_start 577 * 578 * @buf: pointer to the start of RX PKT TLV header 579 * Return: uint32_t(reception_type) 580 */ 581 static uint32_t hal_rx_msdu_start_reception_type_get_5018(uint8_t *buf) 582 { 583 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 584 struct rx_msdu_start *msdu_start = 585 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 586 uint32_t reception_type; 587 588 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 589 590 return reception_type; 591 } 592 593 /** 594 * hal_rx_msdu_end_da_idx_get_5018: API to get da_idx 595 * from rx_msdu_end TLV 596 * 597 * @ buf: pointer to the start of RX PKT TLV headers 598 * Return: da index 599 */ 600 static uint16_t hal_rx_msdu_end_da_idx_get_5018(uint8_t *buf) 601 { 602 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 603 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 604 uint16_t da_idx; 605 606 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 607 608 return da_idx; 609 } 610 611 /** 612 * hal_rx_get_rx_fragment_number_5018(): Function to retrieve rx fragment number 613 * 614 * @nbuf: Network buffer 615 * Returns: rx fragment number 616 */ 617 static 618 uint8_t hal_rx_get_rx_fragment_number_5018(uint8_t *buf) 619 { 620 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 621 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 622 623 /* Return first 4 bits as fragment number */ 624 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 625 DOT11_SEQ_FRAG_MASK); 626 } 627 628 /** 629 * hal_rx_msdu_end_da_is_mcbc_get_5018(): API to check if pkt is MCBC 630 * from rx_msdu_end TLV 631 * 632 * @ buf: pointer to the start of RX PKT TLV headers 633 * Return: da_is_mcbc 634 */ 635 static uint8_t 636 hal_rx_msdu_end_da_is_mcbc_get_5018(uint8_t *buf) 637 { 638 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 639 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 640 641 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 642 } 643 644 /** 645 * hal_rx_msdu_end_sa_is_valid_get_5018(): API to get_5018 the 646 * sa_is_valid bit from rx_msdu_end TLV 647 * 648 * @ buf: pointer to the start of RX PKT TLV headers 649 * Return: sa_is_valid bit 650 */ 651 static uint8_t 652 hal_rx_msdu_end_sa_is_valid_get_5018(uint8_t *buf) 653 { 654 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 655 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 656 uint8_t sa_is_valid; 657 658 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 659 660 return sa_is_valid; 661 } 662 663 /** 664 * hal_rx_msdu_end_sa_idx_get_5018(): API to get_5018 the 665 * sa_idx from rx_msdu_end TLV 666 * 667 * @ buf: pointer to the start of RX PKT TLV headers 668 * Return: sa_idx (SA AST index) 669 */ 670 static uint16_t hal_rx_msdu_end_sa_idx_get_5018(uint8_t *buf) 671 { 672 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 673 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 674 uint16_t sa_idx; 675 676 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 677 678 return sa_idx; 679 } 680 681 /** 682 * hal_rx_desc_is_first_msdu_5018() - Check if first msdu 683 * 684 * @hal_soc_hdl: hal_soc handle 685 * @hw_desc_addr: hardware descriptor address 686 * 687 * Return: 0 - success/ non-zero failure 688 */ 689 static uint32_t hal_rx_desc_is_first_msdu_5018(void *hw_desc_addr) 690 { 691 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 692 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 693 694 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 695 } 696 697 /** 698 * hal_rx_msdu_end_l3_hdr_padding_get_5018(): API to get_5018 the 699 * l3_header padding from rx_msdu_end TLV 700 * 701 * @ buf: pointer to the start of RX PKT TLV headers 702 * Return: number of l3 header padding bytes 703 */ 704 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_5018(uint8_t *buf) 705 { 706 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 707 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 708 uint32_t l3_header_padding; 709 710 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 711 712 return l3_header_padding; 713 } 714 715 /** 716 * @ hal_rx_encryption_info_valid_5018: Returns encryption type. 717 * 718 * @ buf: rx_tlv_hdr of the received packet 719 * @ Return: encryption type 720 */ 721 inline uint32_t hal_rx_encryption_info_valid_5018(uint8_t *buf) 722 { 723 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 724 struct rx_mpdu_start *mpdu_start = 725 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 726 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 727 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 728 729 return encryption_info; 730 } 731 732 /* 733 * @ hal_rx_print_pn_5018: Prints the PN of rx packet. 734 * 735 * @ buf: rx_tlv_hdr of the received packet 736 * @ Return: void 737 */ 738 static void hal_rx_print_pn_5018(uint8_t *buf) 739 { 740 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 741 struct rx_mpdu_start *mpdu_start = 742 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 743 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 744 745 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 746 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 747 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 748 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 749 750 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", 751 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 752 } 753 754 /** 755 * hal_rx_msdu_end_first_msdu_get_5018: API to get first msdu status 756 * from rx_msdu_end TLV 757 * 758 * @ buf: pointer to the start of RX PKT TLV headers 759 * Return: first_msdu 760 */ 761 static uint8_t hal_rx_msdu_end_first_msdu_get_5018(uint8_t *buf) 762 { 763 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 764 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 765 uint8_t first_msdu; 766 767 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 768 769 return first_msdu; 770 } 771 772 /** 773 * hal_rx_msdu_end_da_is_valid_get_5018: API to check if da is valid 774 * from rx_msdu_end TLV 775 * 776 * @ buf: pointer to the start of RX PKT TLV headers 777 * Return: da_is_valid 778 */ 779 static uint8_t hal_rx_msdu_end_da_is_valid_get_5018(uint8_t *buf) 780 { 781 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 782 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 783 uint8_t da_is_valid; 784 785 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 786 787 return da_is_valid; 788 } 789 790 /** 791 * hal_rx_msdu_end_last_msdu_get_5018: API to get last msdu status 792 * from rx_msdu_end TLV 793 * 794 * @ buf: pointer to the start of RX PKT TLV headers 795 * Return: last_msdu 796 */ 797 static uint8_t hal_rx_msdu_end_last_msdu_get_5018(uint8_t *buf) 798 { 799 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 800 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 801 uint8_t last_msdu; 802 803 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 804 805 return last_msdu; 806 } 807 808 /* 809 * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid 810 * 811 * @nbuf: Network buffer 812 * Returns: value of mpdu 4th address valid field 813 */ 814 inline bool hal_rx_get_mpdu_mac_ad4_valid_5018(uint8_t *buf) 815 { 816 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 817 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 818 bool ad4_valid = 0; 819 820 ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info); 821 822 return ad4_valid; 823 } 824 825 /** 826 * hal_rx_mpdu_start_sw_peer_id_get_5018: Retrieve sw peer_id 827 * @buf: network buffer 828 * 829 * Return: sw peer_id 830 */ 831 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_5018(uint8_t *buf) 832 { 833 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 834 struct rx_mpdu_start *mpdu_start = 835 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 836 837 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 838 &mpdu_start->rx_mpdu_info_details); 839 } 840 841 /* 842 * hal_rx_mpdu_get_to_ds_5018(): API to get the tods info 843 * from rx_mpdu_start 844 * 845 * @buf: pointer to the start of RX PKT TLV header 846 * Return: uint32_t(to_ds) 847 */ 848 static uint32_t hal_rx_mpdu_get_to_ds_5018(uint8_t *buf) 849 { 850 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 851 struct rx_mpdu_start *mpdu_start = 852 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 853 854 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 855 856 return HAL_RX_MPDU_GET_TODS(mpdu_info); 857 } 858 859 /* 860 * hal_rx_mpdu_get_fr_ds_5018(): API to get the from ds info 861 * from rx_mpdu_start 862 * 863 * @buf: pointer to the start of RX PKT TLV header 864 * Return: uint32_t(fr_ds) 865 */ 866 static uint32_t hal_rx_mpdu_get_fr_ds_5018(uint8_t *buf) 867 { 868 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 869 struct rx_mpdu_start *mpdu_start = 870 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 871 872 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 873 874 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 875 } 876 877 /* 878 * hal_rx_get_mpdu_frame_control_valid_5018(): Retrieves mpdu 879 * frame control valid 880 * 881 * @nbuf: Network buffer 882 * Returns: value of frame control valid field 883 */ 884 static uint8_t hal_rx_get_mpdu_frame_control_valid_5018(uint8_t *buf) 885 { 886 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 887 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 888 889 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 890 } 891 892 /* 893 * hal_rx_mpdu_get_addr1_5018(): API to check get address1 of the mpdu 894 * 895 * @buf: pointer to the start of RX PKT TLV headera 896 * @mac_addr: pointer to mac address 897 * Return: success/failure 898 */ 899 static QDF_STATUS hal_rx_mpdu_get_addr1_5018(uint8_t *buf, 900 uint8_t *mac_addr) 901 { 902 struct __attribute__((__packed__)) hal_addr1 { 903 uint32_t ad1_31_0; 904 uint16_t ad1_47_32; 905 }; 906 907 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 908 struct rx_mpdu_start *mpdu_start = 909 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 910 911 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 912 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 913 uint32_t mac_addr_ad1_valid; 914 915 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 916 917 if (mac_addr_ad1_valid) { 918 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 919 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 920 return QDF_STATUS_SUCCESS; 921 } 922 923 return QDF_STATUS_E_FAILURE; 924 } 925 926 /* 927 * hal_rx_mpdu_get_addr2_5018(): API to check get address2 of the mpdu 928 * in the packet 929 * 930 * @buf: pointer to the start of RX PKT TLV header 931 * @mac_addr: pointer to mac address 932 * Return: success/failure 933 */ 934 static QDF_STATUS hal_rx_mpdu_get_addr2_5018(uint8_t *buf, uint8_t *mac_addr) 935 { 936 struct __attribute__((__packed__)) hal_addr2 { 937 uint16_t ad2_15_0; 938 uint32_t ad2_47_16; 939 }; 940 941 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 942 struct rx_mpdu_start *mpdu_start = 943 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 944 945 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 946 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 947 uint32_t mac_addr_ad2_valid; 948 949 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 950 951 if (mac_addr_ad2_valid) { 952 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 953 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 954 return QDF_STATUS_SUCCESS; 955 } 956 957 return QDF_STATUS_E_FAILURE; 958 } 959 960 /* 961 * hal_rx_mpdu_get_addr3_5018(): API to get address3 of the mpdu 962 * in the packet 963 * 964 * @buf: pointer to the start of RX PKT TLV header 965 * @mac_addr: pointer to mac address 966 * Return: success/failure 967 */ 968 static QDF_STATUS hal_rx_mpdu_get_addr3_5018(uint8_t *buf, uint8_t *mac_addr) 969 { 970 struct __attribute__((__packed__)) hal_addr3 { 971 uint32_t ad3_31_0; 972 uint16_t ad3_47_32; 973 }; 974 975 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 976 struct rx_mpdu_start *mpdu_start = 977 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 978 979 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 980 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 981 uint32_t mac_addr_ad3_valid; 982 983 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 984 985 if (mac_addr_ad3_valid) { 986 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 987 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 988 return QDF_STATUS_SUCCESS; 989 } 990 991 return QDF_STATUS_E_FAILURE; 992 } 993 994 /* 995 * hal_rx_mpdu_get_addr4_5018(): API to get address4 of the mpdu 996 * in the packet 997 * 998 * @buf: pointer to the start of RX PKT TLV header 999 * @mac_addr: pointer to mac address 1000 * Return: success/failure 1001 */ 1002 static QDF_STATUS hal_rx_mpdu_get_addr4_5018(uint8_t *buf, uint8_t *mac_addr) 1003 { 1004 struct __attribute__((__packed__)) hal_addr4 { 1005 uint32_t ad4_31_0; 1006 uint16_t ad4_47_32; 1007 }; 1008 1009 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1010 struct rx_mpdu_start *mpdu_start = 1011 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1012 1013 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1014 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 1015 uint32_t mac_addr_ad4_valid; 1016 1017 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 1018 1019 if (mac_addr_ad4_valid) { 1020 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 1021 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 1022 return QDF_STATUS_SUCCESS; 1023 } 1024 1025 return QDF_STATUS_E_FAILURE; 1026 } 1027 1028 /* 1029 * hal_rx_get_mpdu_sequence_control_valid_5018(): Get mpdu 1030 * sequence control valid 1031 * 1032 * @nbuf: Network buffer 1033 * Returns: value of sequence control valid field 1034 */ 1035 static uint8_t hal_rx_get_mpdu_sequence_control_valid_5018(uint8_t *buf) 1036 { 1037 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1038 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1039 1040 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 1041 } 1042 1043 /** 1044 * hal_rx_is_unicast_5018: check packet is unicast frame or not. 1045 * 1046 * @ buf: pointer to rx pkt TLV. 1047 * 1048 * Return: true on unicast. 1049 */ 1050 static bool hal_rx_is_unicast_5018(uint8_t *buf) 1051 { 1052 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1053 struct rx_mpdu_start *mpdu_start = 1054 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1055 uint32_t grp_id; 1056 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1057 1058 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1059 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 1060 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 1061 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 1062 1063 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 1064 } 1065 1066 /** 1067 * hal_rx_tid_get_5018: get tid based on qos control valid. 1068 * @hal_soc_hdl: hal soc handle 1069 * @buf: pointer to rx pkt TLV. 1070 * 1071 * Return: tid 1072 */ 1073 static uint32_t hal_rx_tid_get_5018(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1074 { 1075 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1076 struct rx_mpdu_start *mpdu_start = 1077 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1078 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1079 uint8_t qos_control_valid = 1080 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1081 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 1082 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 1083 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 1084 1085 if (qos_control_valid) 1086 return hal_rx_mpdu_start_tid_get_5018(buf); 1087 1088 return HAL_RX_NON_QOS_TID; 1089 } 1090 1091 /** 1092 * hal_rx_hw_desc_get_ppduid_get_5018(): retrieve ppdu id 1093 * @rx_tlv_hdr: rx tlv header 1094 * @rxdma_dst_ring_desc: rxdma HW descriptor 1095 * 1096 * Return: ppdu id 1097 */ 1098 static uint32_t hal_rx_hw_desc_get_ppduid_get_5018(void *rx_tlv_hdr, 1099 void *rxdma_dst_ring_desc) 1100 { 1101 struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc; 1102 1103 return HAL_RX_REO_ENT_PHY_PPDU_ID_GET(reo_ent); 1104 } 1105 1106 /** 1107 * hal_reo_status_get_header_5018 - Process reo desc info 1108 * @ring_desc: REO status ring descriptor 1109 * @b - tlv type info 1110 * @h1 - Pointer to hal_reo_status_header where info to be stored 1111 * 1112 * Return - none. 1113 * 1114 */ 1115 static void hal_reo_status_get_header_5018(hal_ring_desc_t ring_desc, int b, 1116 void *h1) 1117 { 1118 uint32_t *d = (uint32_t *)ring_desc; 1119 uint32_t val1 = 0; 1120 struct hal_reo_status_header *h = 1121 (struct hal_reo_status_header *)h1; 1122 1123 /* Offsets of descriptor fields defined in HW headers start 1124 * from the field after TLV header 1125 */ 1126 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 1127 1128 switch (b) { 1129 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1130 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1131 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1132 break; 1133 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1134 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1135 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1136 break; 1137 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1138 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1139 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1140 break; 1141 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1142 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1143 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1144 break; 1145 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1146 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1147 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1148 break; 1149 case HAL_REO_DESC_THRES_STATUS_TLV: 1150 val1 = 1151 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1152 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1153 break; 1154 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1155 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1156 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1157 break; 1158 default: 1159 qdf_nofl_err("ERROR: Unknown tlv\n"); 1160 break; 1161 } 1162 h->cmd_num = 1163 HAL_GET_FIELD( 1164 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1165 val1); 1166 h->exec_time = 1167 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1168 CMD_EXECUTION_TIME, val1); 1169 h->status = 1170 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1171 REO_CMD_EXECUTION_STATUS, val1); 1172 switch (b) { 1173 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1174 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1175 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1176 break; 1177 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1178 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1179 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1180 break; 1181 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1182 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1183 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1184 break; 1185 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1186 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1187 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1188 break; 1189 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1190 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1191 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1192 break; 1193 case HAL_REO_DESC_THRES_STATUS_TLV: 1194 val1 = 1195 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1196 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1197 break; 1198 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1199 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1200 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1201 break; 1202 default: 1203 qdf_nofl_err("ERROR: Unknown tlv\n"); 1204 break; 1205 } 1206 h->tstamp = 1207 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1208 } 1209 1210 /** 1211 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(): 1212 * Retrieve qos control valid bit from the tlv. 1213 * @buf: pointer to rx pkt TLV. 1214 * 1215 * Return: qos control value. 1216 */ 1217 static inline uint32_t 1218 hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(uint8_t *buf) 1219 { 1220 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1221 struct rx_mpdu_start *mpdu_start = 1222 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1223 1224 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1225 &mpdu_start->rx_mpdu_info_details); 1226 } 1227 1228 /** 1229 * hal_rx_msdu_end_sa_sw_peer_id_get_5018(): API to get the 1230 * sa_sw_peer_id from rx_msdu_end TLV 1231 * @buf: pointer to the start of RX PKT TLV headers 1232 * 1233 * Return: sa_sw_peer_id index 1234 */ 1235 static inline uint32_t 1236 hal_rx_msdu_end_sa_sw_peer_id_get_5018(uint8_t *buf) 1237 { 1238 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1239 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1240 1241 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1242 } 1243 1244 /** 1245 * hal_tx_desc_set_mesh_en_5018 - Set mesh_enable flag in Tx descriptor 1246 * @desc: Handle to Tx Descriptor 1247 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1248 * enabling the interpretation of the 'Mesh Control Present' bit 1249 * (bit 8) of QoS Control (otherwise this bit is ignored), 1250 * For native WiFi frames, this indicates that a 'Mesh Control' field 1251 * is present between the header and the LLC. 1252 * 1253 * Return: void 1254 */ 1255 static inline 1256 void hal_tx_desc_set_mesh_en_5018(void *desc, uint8_t en) 1257 { 1258 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1259 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1260 } 1261 1262 static 1263 void *hal_rx_msdu0_buffer_addr_lsb_5018(void *link_desc_va) 1264 { 1265 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1266 } 1267 1268 static 1269 void *hal_rx_msdu_desc_info_ptr_get_5018(void *msdu0) 1270 { 1271 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1272 } 1273 1274 static 1275 void *hal_ent_mpdu_desc_info_5018(void *ent_ring_desc) 1276 { 1277 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1278 } 1279 1280 static 1281 void *hal_dst_mpdu_desc_info_5018(void *dst_ring_desc) 1282 { 1283 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1284 } 1285 1286 static 1287 uint8_t hal_rx_get_fc_valid_5018(uint8_t *buf) 1288 { 1289 return HAL_RX_GET_FC_VALID(buf); 1290 } 1291 1292 static uint8_t hal_rx_get_to_ds_flag_5018(uint8_t *buf) 1293 { 1294 return HAL_RX_GET_TO_DS_FLAG(buf); 1295 } 1296 1297 static uint8_t hal_rx_get_mac_addr2_valid_5018(uint8_t *buf) 1298 { 1299 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1300 } 1301 1302 static uint8_t hal_rx_get_filter_category_5018(uint8_t *buf) 1303 { 1304 return HAL_RX_GET_FILTER_CATEGORY(buf); 1305 } 1306 1307 static uint32_t 1308 hal_rx_get_ppdu_id_5018(uint8_t *buf) 1309 { 1310 struct rx_mpdu_info *rx_mpdu_info; 1311 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 1312 1313 rx_mpdu_info = 1314 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1315 1316 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 1317 } 1318 1319 /** 1320 * hal_reo_config_5018(): Set reo config parameters 1321 * @soc: hal soc handle 1322 * @reg_val: value to be set 1323 * @reo_params: reo parameters 1324 * 1325 * Return: void 1326 */ 1327 static void 1328 hal_reo_config_5018(struct hal_soc *soc, 1329 uint32_t reg_val, 1330 struct hal_reo_params *reo_params) 1331 { 1332 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1333 } 1334 1335 /** 1336 * hal_rx_msdu_desc_info_get_ptr_5018() - Get msdu desc info ptr 1337 * @msdu_details_ptr - Pointer to msdu_details_ptr 1338 * 1339 * Return - Pointer to rx_msdu_desc_info structure. 1340 * 1341 */ 1342 static void *hal_rx_msdu_desc_info_get_ptr_5018(void *msdu_details_ptr) 1343 { 1344 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1345 } 1346 1347 /** 1348 * hal_rx_link_desc_msdu0_ptr_5018 - Get pointer to rx_msdu details 1349 * @link_desc - Pointer to link desc 1350 * 1351 * Return - Pointer to rx_msdu_details structure 1352 * 1353 */ 1354 static void *hal_rx_link_desc_msdu0_ptr_5018(void *link_desc) 1355 { 1356 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1357 } 1358 1359 /** 1360 * hal_rx_msdu_flow_idx_get_5018: API to get flow index 1361 * from rx_msdu_end TLV 1362 * @buf: pointer to the start of RX PKT TLV headers 1363 * 1364 * Return: flow index value from MSDU END TLV 1365 */ 1366 static inline uint32_t hal_rx_msdu_flow_idx_get_5018(uint8_t *buf) 1367 { 1368 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1369 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1370 1371 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1372 } 1373 1374 /** 1375 * hal_rx_msdu_flow_idx_invalid_5018: API to get flow index invalid 1376 * from rx_msdu_end TLV 1377 * @buf: pointer to the start of RX PKT TLV headers 1378 * 1379 * Return: flow index invalid value from MSDU END TLV 1380 */ 1381 static bool hal_rx_msdu_flow_idx_invalid_5018(uint8_t *buf) 1382 { 1383 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1384 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1385 1386 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1387 } 1388 1389 /** 1390 * hal_rx_msdu_flow_idx_timeout_5018: API to get flow index timeout 1391 * from rx_msdu_end TLV 1392 * @buf: pointer to the start of RX PKT TLV headers 1393 * 1394 * Return: flow index timeout value from MSDU END TLV 1395 */ 1396 static bool hal_rx_msdu_flow_idx_timeout_5018(uint8_t *buf) 1397 { 1398 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1399 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1400 1401 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1402 } 1403 1404 /** 1405 * hal_rx_msdu_fse_metadata_get_5018: API to get FSE metadata 1406 * from rx_msdu_end TLV 1407 * @buf: pointer to the start of RX PKT TLV headers 1408 * 1409 * Return: fse metadata value from MSDU END TLV 1410 */ 1411 static uint32_t hal_rx_msdu_fse_metadata_get_5018(uint8_t *buf) 1412 { 1413 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1414 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1415 1416 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1417 } 1418 1419 /** 1420 * hal_rx_msdu_cce_metadata_get_5018: API to get CCE metadata 1421 * from rx_msdu_end TLV 1422 * @buf: pointer to the start of RX PKT TLV headers 1423 * 1424 * Return: cce_metadata 1425 */ 1426 static uint16_t 1427 hal_rx_msdu_cce_metadata_get_5018(uint8_t *buf) 1428 { 1429 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1430 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1431 1432 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1433 } 1434 1435 /** 1436 * hal_rx_msdu_get_flow_params_5018: API to get flow index, flow index invalid 1437 * and flow index timeout from rx_msdu_end TLV 1438 * @buf: pointer to the start of RX PKT TLV headers 1439 * @flow_invalid: pointer to return value of flow_idx_valid 1440 * @flow_timeout: pointer to return value of flow_idx_timeout 1441 * @flow_index: pointer to return value of flow_idx 1442 * 1443 * Return: none 1444 */ 1445 static inline void 1446 hal_rx_msdu_get_flow_params_5018(uint8_t *buf, 1447 bool *flow_invalid, 1448 bool *flow_timeout, 1449 uint32_t *flow_index) 1450 { 1451 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1452 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1453 1454 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1455 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1456 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1457 } 1458 1459 /** 1460 * hal_rx_tlv_get_tcp_chksum_5018() - API to get tcp checksum 1461 * @buf: rx_tlv_hdr 1462 * 1463 * Return: tcp checksum 1464 */ 1465 static uint16_t 1466 hal_rx_tlv_get_tcp_chksum_5018(uint8_t *buf) 1467 { 1468 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1469 } 1470 1471 /** 1472 * hal_rx_get_rx_sequence_5018(): Function to retrieve rx sequence number 1473 * 1474 * @nbuf: Network buffer 1475 * Returns: rx sequence number 1476 */ 1477 static 1478 uint16_t hal_rx_get_rx_sequence_5018(uint8_t *buf) 1479 { 1480 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1481 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1482 1483 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1484 } 1485 1486 /** 1487 * hal_get_window_address_5018(): Function to get hp/tp address 1488 * @hal_soc: Pointer to hal_soc 1489 * @addr: address offset of register 1490 * 1491 * Return: modified address offset of register 1492 */ 1493 static inline qdf_iomem_t hal_get_window_address_5018(struct hal_soc *hal_soc, 1494 qdf_iomem_t addr) 1495 { 1496 uint32_t offset = addr - hal_soc->dev_base_addr; 1497 qdf_iomem_t new_offset; 1498 1499 /* 1500 * Check if offset lies within CE register range(0x08400000) 1501 * or UMAC/DP register range (0x00A00000). 1502 * If offset lies within CE register range, map it 1503 * into CE region. 1504 */ 1505 if (offset & HOST_CE_MASK_VALUE) { 1506 offset = offset - WFSS_CE_REG_BASE; 1507 new_offset = (hal_soc->dev_base_addr_ce + offset); 1508 1509 return new_offset; 1510 } else { 1511 /* 1512 * If offset lies within DP register range, 1513 * return the address as such 1514 */ 1515 return addr; 1516 } 1517 } 1518 1519 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1520 { 1521 /* Write value into window configuration register */ 1522 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1523 WINDOW_CONFIGURATION_VALUE_5018); 1524 } 1525 1526 /** 1527 * hal_rx_msdu_packet_metadata_get_5018(): API to get the 1528 * msdu information from rx_msdu_end TLV 1529 * 1530 * @ buf: pointer to the start of RX PKT TLV headers 1531 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 1532 */ 1533 static void 1534 hal_rx_msdu_packet_metadata_get_5018(uint8_t *buf, 1535 void *msdu_pkt_metadata) 1536 { 1537 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1538 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1539 struct hal_rx_msdu_metadata *msdu_metadata = 1540 (struct hal_rx_msdu_metadata *)msdu_pkt_metadata; 1541 1542 msdu_metadata->l3_hdr_pad = 1543 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1544 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1545 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 1546 msdu_metadata->sa_sw_peer_id = 1547 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1548 } 1549 1550 /** 1551 * hal_rx_flow_setup_fse_5018() - Setup a flow search entry in HW FST 1552 * @fst: Pointer to the Rx Flow Search Table 1553 * @table_offset: offset into the table where the flow is to be setup 1554 * @flow: Flow Parameters 1555 * 1556 * Return: Success/Failure 1557 */ 1558 static void * 1559 hal_rx_flow_setup_fse_5018(uint8_t *rx_fst, uint32_t table_offset, 1560 uint8_t *rx_flow) 1561 { 1562 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1563 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1564 uint8_t *fse; 1565 bool fse_valid; 1566 1567 if (table_offset >= fst->max_entries) { 1568 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1569 "HAL FSE table offset %u exceeds max entries %u", 1570 table_offset, fst->max_entries); 1571 return NULL; 1572 } 1573 1574 fse = (uint8_t *)fst->base_vaddr + 1575 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1576 1577 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1578 1579 if (fse_valid) { 1580 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1581 "HAL FSE %pK already valid", fse); 1582 return NULL; 1583 } 1584 1585 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1586 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1587 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1588 1589 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1590 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1591 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1592 1593 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1594 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1595 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1596 1597 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1598 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1599 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1600 1601 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1602 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1603 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1604 1605 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1606 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1607 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1608 1609 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1610 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1611 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1612 1613 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1614 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1615 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1616 1617 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1618 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1619 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1620 (flow->tuple_info.dest_port)); 1621 1622 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1623 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1624 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1625 (flow->tuple_info.src_port)); 1626 1627 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1628 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1629 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1630 flow->tuple_info.l4_protocol); 1631 1632 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1633 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1634 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1635 flow->reo_destination_handler); 1636 1637 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1638 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1639 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1640 1641 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1642 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1643 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1644 flow->fse_metadata); 1645 1646 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1647 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1648 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1649 REO_DESTINATION_INDICATION, 1650 flow->reo_destination_indication); 1651 1652 /* Reset all the other fields in FSE */ 1653 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1654 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1655 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1656 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1657 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1658 1659 return fse; 1660 } 1661 1662 static void hal_hw_txrx_ops_attach_qca5018(struct hal_soc *hal_soc) 1663 { 1664 /* init and setup */ 1665 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1666 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1667 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1668 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1669 hal_soc->ops->hal_get_window_address = hal_get_window_address_5018; 1670 1671 /* tx */ 1672 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1673 hal_tx_desc_set_dscp_tid_table_id_5018; 1674 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5018; 1675 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5018; 1676 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_5018; 1677 hal_soc->ops->hal_tx_desc_set_buf_addr = 1678 hal_tx_desc_set_buf_addr_generic_li; 1679 hal_soc->ops->hal_tx_desc_set_search_type = 1680 hal_tx_desc_set_search_type_generic_li; 1681 hal_soc->ops->hal_tx_desc_set_search_index = 1682 hal_tx_desc_set_search_index_generic_li; 1683 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1684 hal_tx_desc_set_cache_set_num_generic_li; 1685 hal_soc->ops->hal_tx_comp_get_status = 1686 hal_tx_comp_get_status_generic_li; 1687 hal_soc->ops->hal_tx_comp_get_release_reason = 1688 hal_tx_comp_get_release_reason_generic_li; 1689 hal_soc->ops->hal_get_wbm_internal_error = 1690 hal_get_wbm_internal_error_generic_li; 1691 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_5018; 1692 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1693 hal_tx_init_cmd_credit_ring_5018; 1694 1695 /* rx */ 1696 hal_soc->ops->hal_rx_msdu_start_nss_get = 1697 hal_rx_msdu_start_nss_get_5018; 1698 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1699 hal_rx_mon_hw_desc_get_mpdu_status_5018; 1700 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5018; 1701 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1702 hal_rx_proc_phyrx_other_receive_info_tlv_5018; 1703 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1704 hal_rx_dump_msdu_start_tlv_5018; 1705 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5018; 1706 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5018; 1707 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1708 hal_rx_mpdu_start_tid_get_5018; 1709 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1710 hal_rx_msdu_start_reception_type_get_5018; 1711 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1712 hal_rx_msdu_end_da_idx_get_5018; 1713 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1714 hal_rx_msdu_desc_info_get_ptr_5018; 1715 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1716 hal_rx_link_desc_msdu0_ptr_5018; 1717 hal_soc->ops->hal_reo_status_get_header = 1718 hal_reo_status_get_header_5018; 1719 hal_soc->ops->hal_rx_status_get_tlv_info = 1720 hal_rx_status_get_tlv_info_generic_li; 1721 hal_soc->ops->hal_rx_wbm_err_info_get = 1722 hal_rx_wbm_err_info_get_generic_li; 1723 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1724 hal_rx_dump_mpdu_start_tlv_generic_li; 1725 1726 hal_soc->ops->hal_tx_set_pcp_tid_map = 1727 hal_tx_set_pcp_tid_map_generic_li; 1728 hal_soc->ops->hal_tx_update_pcp_tid_map = 1729 hal_tx_update_pcp_tid_generic_li; 1730 hal_soc->ops->hal_tx_set_tidmap_prty = 1731 hal_tx_update_tidmap_prty_generic_li; 1732 hal_soc->ops->hal_rx_get_rx_fragment_number = 1733 hal_rx_get_rx_fragment_number_5018; 1734 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1735 hal_rx_msdu_end_da_is_mcbc_get_5018; 1736 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1737 hal_rx_msdu_end_sa_is_valid_get_5018; 1738 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1739 hal_rx_msdu_end_sa_idx_get_5018; 1740 hal_soc->ops->hal_rx_desc_is_first_msdu = 1741 hal_rx_desc_is_first_msdu_5018; 1742 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1743 hal_rx_msdu_end_l3_hdr_padding_get_5018; 1744 hal_soc->ops->hal_rx_encryption_info_valid = 1745 hal_rx_encryption_info_valid_5018; 1746 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_5018; 1747 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1748 hal_rx_msdu_end_first_msdu_get_5018; 1749 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1750 hal_rx_msdu_end_da_is_valid_get_5018; 1751 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1752 hal_rx_msdu_end_last_msdu_get_5018; 1753 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1754 hal_rx_get_mpdu_mac_ad4_valid_5018; 1755 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1756 hal_rx_mpdu_start_sw_peer_id_get_5018; 1757 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_5018; 1758 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_5018; 1759 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1760 hal_rx_get_mpdu_frame_control_valid_5018; 1761 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_5018; 1762 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_5018; 1763 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_5018; 1764 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_5018; 1765 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1766 hal_rx_get_mpdu_sequence_control_valid_5018; 1767 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_5018; 1768 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_5018; 1769 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1770 hal_rx_hw_desc_get_ppduid_get_5018; 1771 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1772 hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018; 1773 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1774 hal_rx_msdu_end_sa_sw_peer_id_get_5018; 1775 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1776 hal_rx_msdu0_buffer_addr_lsb_5018; 1777 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1778 hal_rx_msdu_desc_info_ptr_get_5018; 1779 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5018; 1780 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5018; 1781 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_5018; 1782 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_5018; 1783 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1784 hal_rx_get_mac_addr2_valid_5018; 1785 hal_soc->ops->hal_rx_get_filter_category = 1786 hal_rx_get_filter_category_5018; 1787 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_5018; 1788 hal_soc->ops->hal_reo_config = hal_reo_config_5018; 1789 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_5018; 1790 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1791 hal_rx_msdu_flow_idx_invalid_5018; 1792 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1793 hal_rx_msdu_flow_idx_timeout_5018; 1794 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1795 hal_rx_msdu_fse_metadata_get_5018; 1796 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1797 hal_rx_msdu_cce_metadata_get_5018; 1798 hal_soc->ops->hal_rx_msdu_get_flow_params = 1799 hal_rx_msdu_get_flow_params_5018; 1800 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1801 hal_rx_tlv_get_tcp_chksum_5018; 1802 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_5018; 1803 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 1804 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5018; 1805 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5018; 1806 #endif 1807 /* rx - msdu fast path info fields */ 1808 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1809 hal_rx_msdu_packet_metadata_get_5018; 1810 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1811 hal_rx_mpdu_start_tlv_tag_valid_5018; 1812 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1813 hal_rx_wbm_err_msdu_continuation_get_5018; 1814 1815 /* rx - TLV struct offsets */ 1816 hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic; 1817 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1818 hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic; 1819 hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic; 1820 hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic; 1821 #ifndef NO_RX_PKT_HDR_TLV 1822 hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic; 1823 #endif 1824 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5018; 1825 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_5018; 1826 hal_soc->ops->hal_setup_link_idle_list = 1827 hal_setup_link_idle_list_generic_li; 1828 }; 1829 1830 struct hal_hw_srng_config hw_srng_table_5018[] = { 1831 /* TODO: max_rings can populated by querying HW capabilities */ 1832 { /* REO_DST */ 1833 .start_ring_id = HAL_SRNG_REO2SW1, 1834 .max_rings = 4, 1835 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1836 .lmac_ring = FALSE, 1837 .ring_dir = HAL_SRNG_DST_RING, 1838 .reg_start = { 1839 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1840 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1841 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1842 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1843 }, 1844 .reg_size = { 1845 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1846 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1847 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1848 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1849 }, 1850 .max_size = 1851 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1852 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1853 }, 1854 { /* REO_EXCEPTION */ 1855 /* Designating REO2TCL ring as exception ring. This ring is 1856 * similar to other REO2SW rings though it is named as REO2TCL. 1857 * Any of theREO2SW rings can be used as exception ring. 1858 */ 1859 .start_ring_id = HAL_SRNG_REO2TCL, 1860 .max_rings = 1, 1861 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1862 .lmac_ring = FALSE, 1863 .ring_dir = HAL_SRNG_DST_RING, 1864 .reg_start = { 1865 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1866 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1867 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1868 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1869 }, 1870 /* Single ring - provide ring size if multiple rings of this 1871 * type are supported 1872 */ 1873 .reg_size = {}, 1874 .max_size = 1875 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1876 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1877 }, 1878 { /* REO_REINJECT */ 1879 .start_ring_id = HAL_SRNG_SW2REO, 1880 .max_rings = 1, 1881 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1882 .lmac_ring = FALSE, 1883 .ring_dir = HAL_SRNG_SRC_RING, 1884 .reg_start = { 1885 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1886 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1887 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1888 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1889 }, 1890 /* Single ring - provide ring size if multiple rings of this 1891 * type are supported 1892 */ 1893 .reg_size = {}, 1894 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1895 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1896 }, 1897 { /* REO_CMD */ 1898 .start_ring_id = HAL_SRNG_REO_CMD, 1899 .max_rings = 1, 1900 .entry_size = (sizeof(struct tlv_32_hdr) + 1901 sizeof(struct reo_get_queue_stats)) >> 2, 1902 .lmac_ring = FALSE, 1903 .ring_dir = HAL_SRNG_SRC_RING, 1904 .reg_start = { 1905 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1906 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1907 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1908 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1909 }, 1910 /* Single ring - provide ring size if multiple rings of this 1911 * type are supported 1912 */ 1913 .reg_size = {}, 1914 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1915 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1916 }, 1917 { /* REO_STATUS */ 1918 .start_ring_id = HAL_SRNG_REO_STATUS, 1919 .max_rings = 1, 1920 .entry_size = (sizeof(struct tlv_32_hdr) + 1921 sizeof(struct reo_get_queue_stats_status)) >> 2, 1922 .lmac_ring = FALSE, 1923 .ring_dir = HAL_SRNG_DST_RING, 1924 .reg_start = { 1925 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1926 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1927 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1928 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1929 }, 1930 /* Single ring - provide ring size if multiple rings of this 1931 * type are supported 1932 */ 1933 .reg_size = {}, 1934 .max_size = 1935 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1936 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1937 }, 1938 { /* TCL_DATA */ 1939 .start_ring_id = HAL_SRNG_SW2TCL1, 1940 .max_rings = 3, 1941 .entry_size = (sizeof(struct tlv_32_hdr) + 1942 sizeof(struct tcl_data_cmd)) >> 2, 1943 .lmac_ring = FALSE, 1944 .ring_dir = HAL_SRNG_SRC_RING, 1945 .reg_start = { 1946 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1947 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1948 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1949 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1950 }, 1951 .reg_size = { 1952 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1953 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1954 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1955 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1956 }, 1957 .max_size = 1958 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1959 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1960 }, 1961 { /* TCL_CMD */ 1962 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1963 .max_rings = 1, 1964 .entry_size = (sizeof(struct tlv_32_hdr) + 1965 sizeof(struct tcl_data_cmd)) >> 2, 1966 .lmac_ring = FALSE, 1967 .ring_dir = HAL_SRNG_SRC_RING, 1968 .reg_start = { 1969 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 1970 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1971 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 1972 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1973 }, 1974 /* Single ring - provide ring size if multiple rings of this 1975 * type are supported 1976 */ 1977 .reg_size = {}, 1978 .max_size = 1979 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 1980 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 1981 }, 1982 { /* TCL_STATUS */ 1983 .start_ring_id = HAL_SRNG_TCL_STATUS, 1984 .max_rings = 1, 1985 .entry_size = (sizeof(struct tlv_32_hdr) + 1986 sizeof(struct tcl_status_ring)) >> 2, 1987 .lmac_ring = FALSE, 1988 .ring_dir = HAL_SRNG_DST_RING, 1989 .reg_start = { 1990 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1991 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1992 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1993 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1994 }, 1995 /* Single ring - provide ring size if multiple rings of this 1996 * type are supported 1997 */ 1998 .reg_size = {}, 1999 .max_size = 2000 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2001 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2002 }, 2003 { /* CE_SRC */ 2004 .start_ring_id = HAL_SRNG_CE_0_SRC, 2005 .max_rings = 12, 2006 .entry_size = sizeof(struct ce_src_desc) >> 2, 2007 .lmac_ring = FALSE, 2008 .ring_dir = HAL_SRNG_SRC_RING, 2009 .reg_start = { 2010 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2011 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2012 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2013 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2014 }, 2015 .reg_size = { 2016 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2017 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2018 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2019 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2020 }, 2021 .max_size = 2022 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2023 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2024 }, 2025 { /* CE_DST */ 2026 .start_ring_id = HAL_SRNG_CE_0_DST, 2027 .max_rings = 12, 2028 .entry_size = 8 >> 2, 2029 /*TODO: entry_size above should actually be 2030 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2031 * of struct ce_dst_desc in HW header files 2032 */ 2033 .lmac_ring = FALSE, 2034 .ring_dir = HAL_SRNG_SRC_RING, 2035 .reg_start = { 2036 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2037 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2038 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2039 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2040 }, 2041 .reg_size = { 2042 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2043 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2044 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2045 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2046 }, 2047 .max_size = 2048 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2049 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2050 }, 2051 { /* CE_DST_STATUS */ 2052 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2053 .max_rings = 12, 2054 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2055 .lmac_ring = FALSE, 2056 .ring_dir = HAL_SRNG_DST_RING, 2057 .reg_start = { 2058 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2059 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2060 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2061 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2062 }, 2063 /* TODO: check destination status ring registers */ 2064 .reg_size = { 2065 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2066 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2067 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2068 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2069 }, 2070 .max_size = 2071 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2072 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2073 }, 2074 { /* WBM_IDLE_LINK */ 2075 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2076 .max_rings = 1, 2077 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2078 .lmac_ring = FALSE, 2079 .ring_dir = HAL_SRNG_SRC_RING, 2080 .reg_start = { 2081 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2082 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2083 }, 2084 /* Single ring - provide ring size if multiple rings of this 2085 * type are supported 2086 */ 2087 .reg_size = {}, 2088 .max_size = 2089 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2090 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2091 }, 2092 { /* SW2WBM_RELEASE */ 2093 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2094 .max_rings = 1, 2095 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2096 .lmac_ring = FALSE, 2097 .ring_dir = HAL_SRNG_SRC_RING, 2098 .reg_start = { 2099 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2100 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2101 }, 2102 /* Single ring - provide ring size if multiple rings of this 2103 * type are supported 2104 */ 2105 .reg_size = {}, 2106 .max_size = 2107 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2108 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2109 }, 2110 { /* WBM2SW_RELEASE */ 2111 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2112 .max_rings = 4, 2113 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2114 .lmac_ring = FALSE, 2115 .ring_dir = HAL_SRNG_DST_RING, 2116 .reg_start = { 2117 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2118 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2119 }, 2120 .reg_size = { 2121 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2122 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2123 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2124 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2125 }, 2126 .max_size = 2127 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2128 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2129 }, 2130 { /* RXDMA_BUF */ 2131 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2132 #ifdef IPA_OFFLOAD 2133 .max_rings = 3, 2134 #else 2135 .max_rings = 2, 2136 #endif 2137 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2138 .lmac_ring = TRUE, 2139 .ring_dir = HAL_SRNG_SRC_RING, 2140 /* reg_start is not set because LMAC rings are not accessed 2141 * from host 2142 */ 2143 .reg_start = {}, 2144 .reg_size = {}, 2145 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2146 }, 2147 { /* RXDMA_DST */ 2148 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2149 .max_rings = 1, 2150 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2151 .lmac_ring = TRUE, 2152 .ring_dir = HAL_SRNG_DST_RING, 2153 /* reg_start is not set because LMAC rings are not accessed 2154 * from host 2155 */ 2156 .reg_start = {}, 2157 .reg_size = {}, 2158 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2159 }, 2160 { /* RXDMA_MONITOR_BUF */ 2161 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2162 .max_rings = 1, 2163 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2164 .lmac_ring = TRUE, 2165 .ring_dir = HAL_SRNG_SRC_RING, 2166 /* reg_start is not set because LMAC rings are not accessed 2167 * from host 2168 */ 2169 .reg_start = {}, 2170 .reg_size = {}, 2171 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2172 }, 2173 { /* RXDMA_MONITOR_STATUS */ 2174 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2175 .max_rings = 1, 2176 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2177 .lmac_ring = TRUE, 2178 .ring_dir = HAL_SRNG_SRC_RING, 2179 /* reg_start is not set because LMAC rings are not accessed 2180 * from host 2181 */ 2182 .reg_start = {}, 2183 .reg_size = {}, 2184 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2185 }, 2186 { /* RXDMA_MONITOR_DST */ 2187 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2188 .max_rings = 1, 2189 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2190 .lmac_ring = TRUE, 2191 .ring_dir = HAL_SRNG_DST_RING, 2192 /* reg_start is not set because LMAC rings are not accessed 2193 * from host 2194 */ 2195 .reg_start = {}, 2196 .reg_size = {}, 2197 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2198 }, 2199 { /* RXDMA_MONITOR_DESC */ 2200 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2201 .max_rings = 1, 2202 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2203 .lmac_ring = TRUE, 2204 .ring_dir = HAL_SRNG_SRC_RING, 2205 /* reg_start is not set because LMAC rings are not accessed 2206 * from host 2207 */ 2208 .reg_start = {}, 2209 .reg_size = {}, 2210 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2211 }, 2212 { /* DIR_BUF_RX_DMA_SRC */ 2213 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2214 /* one ring for spectral and one ring for cfr */ 2215 .max_rings = 2, 2216 .entry_size = 2, 2217 .lmac_ring = TRUE, 2218 .ring_dir = HAL_SRNG_SRC_RING, 2219 /* reg_start is not set because LMAC rings are not accessed 2220 * from host 2221 */ 2222 .reg_start = {}, 2223 .reg_size = {}, 2224 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2225 }, 2226 #ifdef WLAN_FEATURE_CIF_CFR 2227 { /* WIFI_POS_SRC */ 2228 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2229 .max_rings = 1, 2230 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2231 .lmac_ring = TRUE, 2232 .ring_dir = HAL_SRNG_SRC_RING, 2233 /* reg_start is not set because LMAC rings are not accessed 2234 * from host 2235 */ 2236 .reg_start = {}, 2237 .reg_size = {}, 2238 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2239 }, 2240 #endif 2241 { /* REO2PPE */ 0}, 2242 { /* PPE2TCL */ 0}, 2243 { /* PPE_RELEASE */ 0}, 2244 { /* TX_MONITOR_BUF */ 0}, 2245 { /* TX_MONITOR_DST */ 0}, 2246 { /* SW2RXDMA_NEW */ 0}, 2247 }; 2248 2249 /** 2250 * hal_qca5018_attach()- Attach 5018 target specific hal_soc ops, 2251 * offset and srng table 2252 * Return: void 2253 */ 2254 void hal_qca5018_attach(struct hal_soc *hal_soc) 2255 { 2256 hal_soc->hw_srng_table = hw_srng_table_5018; 2257 2258 hal_srng_hw_reg_offset_init_generic(hal_soc); 2259 hal_hw_txrx_default_ops_attach_li(hal_soc); 2260 hal_hw_txrx_ops_attach_qca5018(hal_soc); 2261 } 2262