1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_LI_TX_H_ 20 #define _HAL_LI_TX_H_ 21 22 enum hal_li_tx_ret_buf_manager { 23 HAL_LI_WBM_SW0_BM_ID = 3, 24 HAL_LI_WBM_SW1_BM_ID = 4, 25 HAL_LI_WBM_SW2_BM_ID = 5, 26 HAL_LI_WBM_SW3_BM_ID = 6, 27 #ifdef IPA_WDI3_TX_TWO_PIPES 28 HAL_LI_WBM_SW4_BM_ID = 7, 29 #endif 30 }; 31 32 /*--------------------------------------------------------------------------- 33 * Function declarations and documentation 34 * --------------------------------------------------------------------------- 35 */ 36 37 /*--------------------------------------------------------------------------- 38 * TCL Descriptor accessor APIs 39 * --------------------------------------------------------------------------- 40 */ 41 42 /** 43 * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor 44 * @desc: Handle to Tx Descriptor 45 * @data_length: MSDU length in case of direct descriptor. 46 * Length of link extension descriptor in case of Link extension 47 * descriptor.Includes the length of Metadata 48 * Return: None 49 */ 50 static inline void hal_tx_desc_set_buf_length(void *desc, 51 uint16_t data_length) 52 { 53 HAL_SET_FLD(desc, TCL_DATA_CMD_3, DATA_LENGTH) |= 54 HAL_TX_SM(TCL_DATA_CMD_3, DATA_LENGTH, data_length); 55 } 56 57 /** 58 * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor 59 * @desc: Handle to Tx Descriptor 60 * @offset: Packet offset from Metadata in case of direct buffer descriptor. 61 * 62 * Return: void 63 */ 64 static inline void hal_tx_desc_set_buf_offset(void *desc, 65 uint8_t offset) 66 { 67 HAL_SET_FLD(desc, TCL_DATA_CMD_3, PACKET_OFFSET) |= 68 HAL_TX_SM(TCL_DATA_CMD_3, PACKET_OFFSET, offset); 69 } 70 71 /** 72 * hal_tx_desc_set_encap_type - Set encapsulation type in Tx Descriptor 73 * @desc: Handle to Tx Descriptor 74 * @encap_type: Encapsulation that HW will perform 75 * 76 * Return: void 77 * 78 */ 79 static inline void hal_tx_desc_set_encap_type(void *desc, 80 enum hal_tx_encap_type encap_type) 81 { 82 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCAP_TYPE) |= 83 HAL_TX_SM(TCL_DATA_CMD_2, ENCAP_TYPE, encap_type); 84 } 85 86 /** 87 * hal_tx_desc_set_encrypt_type - Sets the Encrypt Type in Tx Descriptor 88 * @desc: Handle to Tx Descriptor 89 * @type: Encrypt Type 90 * 91 * Return: void 92 */ 93 static inline void hal_tx_desc_set_encrypt_type(void *desc, 94 enum hal_tx_encrypt_type type) 95 { 96 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCRYPT_TYPE) |= 97 HAL_TX_SM(TCL_DATA_CMD_2, ENCRYPT_TYPE, type); 98 } 99 100 /** 101 * hal_tx_desc_set_addr_search_flags - Enable AddrX and AddrY search flags 102 * @desc: Handle to Tx Descriptor 103 * @flags: Bit 0 - AddrY search enable, Bit 1 - AddrX search enable 104 * 105 * Return: void 106 */ 107 static inline void hal_tx_desc_set_addr_search_flags(void *desc, 108 uint8_t flags) 109 { 110 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRX_EN) |= 111 HAL_TX_SM(TCL_DATA_CMD_2, ADDRX_EN, (flags & 0x1)); 112 113 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRY_EN) |= 114 HAL_TX_SM(TCL_DATA_CMD_2, ADDRY_EN, (flags >> 1)); 115 } 116 117 /** 118 * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags 119 * Tx Descriptor for MSDU_buffer type 120 * @desc: Handle to Tx Descriptor 121 * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits) 122 * 123 * Return: void 124 */ 125 static inline void hal_tx_desc_set_l4_checksum_en(void *desc, 126 uint8_t en) 127 { 128 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 129 (HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV4_CHECKSUM_EN, en) | 130 HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV6_CHECKSUM_EN, en) | 131 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV4_CHECKSUM_EN, en) | 132 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV6_CHECKSUM_EN, en)); 133 } 134 135 /** 136 * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in 137 * Tx Descriptor for MSDU_buffer type 138 * @desc: Handle to Tx Descriptor 139 * @checksum_en_flags: ipv4 checksum enable flags 140 * 141 * Return: void 142 */ 143 static inline void hal_tx_desc_set_l3_checksum_en(void *desc, 144 uint8_t en) 145 { 146 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 147 HAL_TX_SM(TCL_DATA_CMD_3, IPV4_CHECKSUM_EN, en); 148 } 149 150 /** 151 * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor 152 * @desc:Handle to Tx Descriptor 153 * @metadata: Metadata to be sent to Firmware 154 * 155 * Return: void 156 */ 157 static inline void hal_tx_desc_set_fw_metadata(void *desc, 158 uint16_t metadata) 159 { 160 HAL_SET_FLD(desc, TCL_DATA_CMD_2, TCL_CMD_NUMBER) |= 161 HAL_TX_SM(TCL_DATA_CMD_2, TCL_CMD_NUMBER, metadata); 162 } 163 164 /** 165 * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor. 166 * @desc:Handle to Tx Descriptor 167 * @to_fw: if set, Forward packet to FW along with classification result 168 * 169 * Return: void 170 */ 171 static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw) 172 { 173 HAL_SET_FLD(desc, TCL_DATA_CMD_3, TO_FW) |= 174 HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw); 175 } 176 177 /** 178 * hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor 179 * @hal_soc_hdl: hal soc handle 180 * @desc: Handle to Tx Descriptor 181 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 182 * enabling the interpretation of the 'Mesh Control Present' bit 183 * (bit 8) of QoS Control (otherwise this bit is ignored), 184 * For native WiFi frames, this indicates that a 'Mesh Control' field 185 * is present between the header and the LLC. 186 * 187 * Return: void 188 */ 189 static inline void hal_tx_desc_set_mesh_en(hal_soc_handle_t hal_soc_hdl, 190 void *desc, uint8_t en) 191 { 192 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 193 194 hal_soc->ops->hal_tx_desc_set_mesh_en(desc, en); 195 } 196 197 /** 198 * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in 199 * frame) to be used for Tx Frame 200 * @desc: Handle to Tx Descriptor 201 * @hlos_tid: HLOS TID 202 * 203 * Return: void 204 */ 205 static inline void hal_tx_desc_set_hlos_tid(void *desc, 206 uint8_t hlos_tid) 207 { 208 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID) |= 209 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID, hlos_tid); 210 211 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |= 212 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1); 213 } 214 215 /** 216 * hal_tx_desc_set_dscp_tid_table_id() - Sets DSCP to TID conversion table ID 217 * @hal_soc: Handle to HAL SoC structure 218 * @desc: Handle to Tx Descriptor 219 * @id: DSCP to tid conversion table to be used for this frame 220 * 221 * Return: void 222 */ 223 static inline 224 void hal_tx_desc_set_dscp_tid_table_id(hal_soc_handle_t hal_soc_hdl, 225 void *desc, uint8_t id) 226 { 227 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 228 229 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id(desc, id); 230 } 231 232 /** 233 * hal_tx_desc_sync - Commit the descriptor to Hardware 234 * @hal_tx_des_cached: Cached descriptor that software maintains 235 * @hw_desc: Hardware descriptor to be updated 236 */ 237 static inline void hal_tx_desc_sync(void *hal_tx_desc_cached, 238 void *hw_desc) 239 { 240 qdf_mem_copy((hw_desc + sizeof(struct tlv_32_hdr)), 241 hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES); 242 } 243 244 /*--------------------------------------------------------------------------- 245 * WBM Descriptor accessor APIs for Tx completions 246 *--------------------------------------------------------------------------- 247 */ 248 249 /** 250 * hal_tx_get_wbm_sw0_bm_id() - Get the BM ID for first tx completion ring 251 * 252 * Return: BM ID for first tx completion ring 253 */ 254 static inline uint32_t hal_tx_get_wbm_sw0_bm_id(void) 255 { 256 return HAL_LI_WBM_SW0_BM_ID; 257 } 258 259 /** 260 * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor 261 * @hal_desc: completion ring descriptor pointer 262 * 263 * This function will tx descriptor id, cookie, within hardware completion 264 * descriptor 265 * 266 * Return: cookie 267 */ 268 static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc) 269 { 270 uint32_t comp_desc = 271 *(uint32_t *)(((uint8_t *)hal_desc) + 272 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET); 273 274 /* Cookie is placed on 2nd word */ 275 return (comp_desc & BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) >> 276 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB; 277 } 278 279 /** 280 * hal_tx_comp_get_paddr() - Get paddr within comp descriptor 281 * @hal_desc: completion ring descriptor pointer 282 * 283 * This function will get buffer physical address within hardware completion 284 * descriptor 285 * 286 * Return: Buffer physical address 287 */ 288 static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc) 289 { 290 uint32_t paddr_lo; 291 uint32_t paddr_hi; 292 293 paddr_lo = *(uint32_t *)(((uint8_t *)hal_desc) + 294 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET); 295 296 paddr_hi = *(uint32_t *)(((uint8_t *)hal_desc) + 297 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET); 298 299 paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) >> 300 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB; 301 302 return (qdf_dma_addr_t)(paddr_lo | (((uint64_t)paddr_hi) << 32)); 303 } 304 305 #endif /* _HAL_LI_TX_H_ */ 306