1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_LI_TX_H_ 20 #define _HAL_LI_TX_H_ 21 22 enum hal_li_tx_ret_buf_manager { 23 HAL_LI_WBM_SW0_BM_ID = 3, 24 HAL_LI_WBM_SW1_BM_ID = 4, 25 HAL_LI_WBM_SW2_BM_ID = 5, 26 HAL_LI_WBM_SW3_BM_ID = 6, 27 HAL_LI_WBM_SW4_BM_ID = 7, 28 }; 29 30 /*--------------------------------------------------------------------------- 31 * Function declarations and documentation 32 * --------------------------------------------------------------------------- 33 */ 34 35 /*--------------------------------------------------------------------------- 36 * TCL Descriptor accessor APIs 37 * --------------------------------------------------------------------------- 38 */ 39 40 /** 41 * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor 42 * @desc: Handle to Tx Descriptor 43 * @data_length: MSDU length in case of direct descriptor. 44 * Length of link extension descriptor in case of Link extension 45 * descriptor.Includes the length of Metadata 46 * Return: None 47 */ 48 static inline void hal_tx_desc_set_buf_length(void *desc, 49 uint16_t data_length) 50 { 51 HAL_SET_FLD(desc, TCL_DATA_CMD_3, DATA_LENGTH) |= 52 HAL_TX_SM(TCL_DATA_CMD_3, DATA_LENGTH, data_length); 53 } 54 55 /** 56 * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor 57 * @desc: Handle to Tx Descriptor 58 * @offset: Packet offset from Metadata in case of direct buffer descriptor. 59 * 60 * Return: void 61 */ 62 static inline void hal_tx_desc_set_buf_offset(void *desc, 63 uint8_t offset) 64 { 65 HAL_SET_FLD(desc, TCL_DATA_CMD_3, PACKET_OFFSET) |= 66 HAL_TX_SM(TCL_DATA_CMD_3, PACKET_OFFSET, offset); 67 } 68 69 /** 70 * hal_tx_desc_set_encap_type - Set encapsulation type in Tx Descriptor 71 * @desc: Handle to Tx Descriptor 72 * @encap_type: Encapsulation that HW will perform 73 * 74 * Return: void 75 * 76 */ 77 static inline void hal_tx_desc_set_encap_type(void *desc, 78 enum hal_tx_encap_type encap_type) 79 { 80 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCAP_TYPE) |= 81 HAL_TX_SM(TCL_DATA_CMD_2, ENCAP_TYPE, encap_type); 82 } 83 84 /** 85 * hal_tx_desc_set_encrypt_type - Sets the Encrypt Type in Tx Descriptor 86 * @desc: Handle to Tx Descriptor 87 * @type: Encrypt Type 88 * 89 * Return: void 90 */ 91 static inline void hal_tx_desc_set_encrypt_type(void *desc, 92 enum hal_tx_encrypt_type type) 93 { 94 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCRYPT_TYPE) |= 95 HAL_TX_SM(TCL_DATA_CMD_2, ENCRYPT_TYPE, type); 96 } 97 98 /** 99 * hal_tx_desc_set_addr_search_flags - Enable AddrX and AddrY search flags 100 * @desc: Handle to Tx Descriptor 101 * @flags: Bit 0 - AddrY search enable, Bit 1 - AddrX search enable 102 * 103 * Return: void 104 */ 105 static inline void hal_tx_desc_set_addr_search_flags(void *desc, 106 uint8_t flags) 107 { 108 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRX_EN) |= 109 HAL_TX_SM(TCL_DATA_CMD_2, ADDRX_EN, (flags & 0x1)); 110 111 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRY_EN) |= 112 HAL_TX_SM(TCL_DATA_CMD_2, ADDRY_EN, (flags >> 1)); 113 } 114 115 /** 116 * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags 117 * Tx Descriptor for MSDU_buffer type 118 * @desc: Handle to Tx Descriptor 119 * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits) 120 * 121 * Return: void 122 */ 123 static inline void hal_tx_desc_set_l4_checksum_en(void *desc, 124 uint8_t en) 125 { 126 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 127 (HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV4_CHECKSUM_EN, en) | 128 HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV6_CHECKSUM_EN, en) | 129 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV4_CHECKSUM_EN, en) | 130 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV6_CHECKSUM_EN, en)); 131 } 132 133 /** 134 * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in 135 * Tx Descriptor for MSDU_buffer type 136 * @desc: Handle to Tx Descriptor 137 * @checksum_en_flags: ipv4 checksum enable flags 138 * 139 * Return: void 140 */ 141 static inline void hal_tx_desc_set_l3_checksum_en(void *desc, 142 uint8_t en) 143 { 144 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 145 HAL_TX_SM(TCL_DATA_CMD_3, IPV4_CHECKSUM_EN, en); 146 } 147 148 /** 149 * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor 150 * @desc:Handle to Tx Descriptor 151 * @metadata: Metadata to be sent to Firmware 152 * 153 * Return: void 154 */ 155 static inline void hal_tx_desc_set_fw_metadata(void *desc, 156 uint16_t metadata) 157 { 158 HAL_SET_FLD(desc, TCL_DATA_CMD_2, TCL_CMD_NUMBER) |= 159 HAL_TX_SM(TCL_DATA_CMD_2, TCL_CMD_NUMBER, metadata); 160 } 161 162 /** 163 * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor. 164 * @desc:Handle to Tx Descriptor 165 * @to_fw: if set, Forward packet to FW along with classification result 166 * 167 * Return: void 168 */ 169 static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw) 170 { 171 HAL_SET_FLD(desc, TCL_DATA_CMD_3, TO_FW) |= 172 HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw); 173 } 174 175 /** 176 * hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor 177 * @hal_soc_hdl: hal soc handle 178 * @desc: Handle to Tx Descriptor 179 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 180 * enabling the interpretation of the 'Mesh Control Present' bit 181 * (bit 8) of QoS Control (otherwise this bit is ignored), 182 * For native WiFi frames, this indicates that a 'Mesh Control' field 183 * is present between the header and the LLC. 184 * 185 * Return: void 186 */ 187 static inline void hal_tx_desc_set_mesh_en(hal_soc_handle_t hal_soc_hdl, 188 void *desc, uint8_t en) 189 { 190 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 191 192 hal_soc->ops->hal_tx_desc_set_mesh_en(desc, en); 193 } 194 195 /** 196 * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in 197 * frame) to be used for Tx Frame 198 * @desc: Handle to Tx Descriptor 199 * @hlos_tid: HLOS TID 200 * 201 * Return: void 202 */ 203 static inline void hal_tx_desc_set_hlos_tid(void *desc, 204 uint8_t hlos_tid) 205 { 206 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID) |= 207 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID, hlos_tid); 208 209 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |= 210 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1); 211 } 212 213 /** 214 * hal_tx_desc_set_dscp_tid_table_id() - Sets DSCP to TID conversion table ID 215 * @hal_soc: Handle to HAL SoC structure 216 * @desc: Handle to Tx Descriptor 217 * @id: DSCP to tid conversion table to be used for this frame 218 * 219 * Return: void 220 */ 221 static inline 222 void hal_tx_desc_set_dscp_tid_table_id(hal_soc_handle_t hal_soc_hdl, 223 void *desc, uint8_t id) 224 { 225 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 226 227 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id(desc, id); 228 } 229 230 /** 231 * hal_tx_desc_clear - Clear the HW descriptor entry 232 * @hw_desc: Hardware descriptor to be cleared 233 * 234 * Return: void 235 */ 236 static inline void hal_tx_desc_clear(void *hw_desc) 237 { 238 qdf_mem_set(hw_desc + sizeof(struct tlv_32_hdr), 239 HAL_TX_DESC_LEN_BYTES, 0); 240 } 241 242 /** 243 * hal_tx_desc_sync - Commit the descriptor to Hardware 244 * @hal_tx_des_cached: Cached descriptor that software maintains 245 * @hw_desc: Hardware descriptor to be updated 246 */ 247 static inline void hal_tx_desc_sync(void *hal_tx_desc_cached, 248 void *hw_desc) 249 { 250 qdf_mem_copy((hw_desc + sizeof(struct tlv_32_hdr)), 251 hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES); 252 } 253 254 /*--------------------------------------------------------------------------- 255 * WBM Descriptor accessor APIs for Tx completions 256 *--------------------------------------------------------------------------- 257 */ 258 259 /** 260 * hal_tx_get_wbm_sw0_bm_id() - Get the BM ID for first tx completion ring 261 * 262 * Return: BM ID for first tx completion ring 263 */ 264 static inline uint32_t hal_tx_get_wbm_sw0_bm_id(void) 265 { 266 return HAL_LI_WBM_SW0_BM_ID; 267 } 268 269 /** 270 * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor 271 * @hal_desc: completion ring descriptor pointer 272 * 273 * This function will tx descriptor id, cookie, within hardware completion 274 * descriptor 275 * 276 * Return: cookie 277 */ 278 static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc) 279 { 280 uint32_t comp_desc = 281 *(uint32_t *)(((uint8_t *)hal_desc) + 282 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET); 283 284 /* Cookie is placed on 2nd word */ 285 return (comp_desc & BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) >> 286 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB; 287 } 288 289 /** 290 * hal_tx_comp_get_paddr() - Get paddr within comp descriptor 291 * @hal_desc: completion ring descriptor pointer 292 * 293 * This function will get buffer physical address within hardware completion 294 * descriptor 295 * 296 * Return: Buffer physical address 297 */ 298 static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc) 299 { 300 uint32_t paddr_lo; 301 uint32_t paddr_hi; 302 303 paddr_lo = *(uint32_t *)(((uint8_t *)hal_desc) + 304 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET); 305 306 paddr_hi = *(uint32_t *)(((uint8_t *)hal_desc) + 307 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET); 308 309 paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) >> 310 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB; 311 312 return (qdf_dma_addr_t)(paddr_lo | (((uint64_t)paddr_hi) << 32)); 313 } 314 #endif /* _HAL_LI_TX_H_ */ 315