1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_LI_TX_H_ 20 #define _HAL_LI_TX_H_ 21 22 enum hal_li_tx_ret_buf_manager { 23 HAL_LI_WBM_SW0_BM_ID = 3, 24 HAL_LI_WBM_SW1_BM_ID = 4, 25 HAL_LI_WBM_SW2_BM_ID = 5, 26 HAL_LI_WBM_SW3_BM_ID = 6, 27 HAL_LI_WBM_SW4_BM_ID = 7, 28 }; 29 30 /*--------------------------------------------------------------------------- 31 * Function declarations and documentation 32 * --------------------------------------------------------------------------- 33 */ 34 35 /*--------------------------------------------------------------------------- 36 * TCL Descriptor accessor APIs 37 * --------------------------------------------------------------------------- 38 */ 39 40 /** 41 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 42 * @desc: Handle to Tx Descriptor 43 * @paddr: Physical Address 44 * @pool_id: Return Buffer Manager ID 45 * @desc_id: Descriptor ID 46 * @type: 0 - Address points to a MSDU buffer 47 * 1 - Address points to MSDU extension descriptor 48 * 49 * Return: void 50 */ 51 static inline 52 void hal_tx_desc_set_buf_addr(hal_soc_handle_t hal_soc_hdl, void *desc, 53 dma_addr_t paddr, 54 uint8_t pool_id, uint32_t desc_id, 55 uint8_t type) 56 { 57 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 58 59 hal_soc->ops->hal_tx_desc_set_buf_addr(desc, paddr, pool_id, 60 desc_id, type); 61 } 62 63 /** 64 * hal_tx_desc_set_lmac_id_li - Set the lmac_id value 65 * @desc: Handle to Tx Descriptor 66 * @lmac_id: mac Id to ast matching 67 * b00 – mac 0 68 * b01 – mac 1 69 * b10 – mac 2 70 * b11 – all macs (legacy HK way) 71 * 72 * Return: void 73 */ 74 static inline void hal_tx_desc_set_lmac_id_li(hal_soc_handle_t hal_soc_hdl, 75 void *desc, uint8_t lmac_id) 76 { 77 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 78 79 hal_soc->ops->hal_tx_desc_set_lmac_id(desc, lmac_id); 80 } 81 82 /** 83 * hal_tx_desc_set_search_type_li - Set the search type value 84 * @desc: Handle to Tx Descriptor 85 * @search_type: search type 86 * 0 – Normal search 87 * 1 – Index based address search 88 * 2 – Index based flow search 89 * 90 * Return: void 91 */ 92 static inline void hal_tx_desc_set_search_type_li(hal_soc_handle_t hal_soc_hdl, 93 void *desc, 94 uint8_t search_type) 95 { 96 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 97 98 hal_soc->ops->hal_tx_desc_set_search_type(desc, search_type); 99 } 100 101 /** 102 * hal_tx_desc_set_search_index_li - Set the search index value 103 * @desc: Handle to Tx Descriptor 104 * @search_index: The index that will be used for index based address or 105 * flow search. The field is valid when 'search_type' is 106 * 1 0r 2 107 * 108 * Return: void 109 */ 110 static inline void hal_tx_desc_set_search_index_li(hal_soc_handle_t hal_soc_hdl, 111 void *desc, 112 uint32_t search_index) 113 { 114 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 115 116 hal_soc->ops->hal_tx_desc_set_search_index(desc, search_index); 117 } 118 119 /** 120 * hal_tx_desc_set_cache_set_num - Set the cache-set-num value 121 * @desc: Handle to Tx Descriptor 122 * @cache_num: Cache set number that should be used to cache the index 123 * based search results, for address and flow search. 124 * This value should be equal to LSB four bits of the hash value 125 * of match data, in case of search index points to an entry 126 * which may be used in content based search also. The value can 127 * be anything when the entry pointed by search index will not be 128 * used for content based search. 129 * 130 * Return: void 131 */ 132 static inline void hal_tx_desc_set_cache_set_num(hal_soc_handle_t hal_soc_hdl, 133 void *desc, 134 uint8_t cache_num) 135 { 136 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 137 138 hal_soc->ops->hal_tx_desc_set_cache_set_num(desc, cache_num); 139 } 140 141 /** 142 * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor 143 * @desc: Handle to Tx Descriptor 144 * @data_length: MSDU length in case of direct descriptor. 145 * Length of link extension descriptor in case of Link extension 146 * descriptor.Includes the length of Metadata 147 * Return: None 148 */ 149 static inline void hal_tx_desc_set_buf_length(void *desc, 150 uint16_t data_length) 151 { 152 HAL_SET_FLD(desc, TCL_DATA_CMD_3, DATA_LENGTH) |= 153 HAL_TX_SM(TCL_DATA_CMD_3, DATA_LENGTH, data_length); 154 } 155 156 /** 157 * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor 158 * @desc: Handle to Tx Descriptor 159 * @offset: Packet offset from Metadata in case of direct buffer descriptor. 160 * 161 * Return: void 162 */ 163 static inline void hal_tx_desc_set_buf_offset(void *desc, 164 uint8_t offset) 165 { 166 HAL_SET_FLD(desc, TCL_DATA_CMD_3, PACKET_OFFSET) |= 167 HAL_TX_SM(TCL_DATA_CMD_3, PACKET_OFFSET, offset); 168 } 169 170 /** 171 * hal_tx_desc_set_encap_type - Set encapsulation type in Tx Descriptor 172 * @desc: Handle to Tx Descriptor 173 * @encap_type: Encapsulation that HW will perform 174 * 175 * Return: void 176 * 177 */ 178 static inline void hal_tx_desc_set_encap_type(void *desc, 179 enum hal_tx_encap_type encap_type) 180 { 181 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCAP_TYPE) |= 182 HAL_TX_SM(TCL_DATA_CMD_2, ENCAP_TYPE, encap_type); 183 } 184 185 /** 186 * hal_tx_desc_set_encrypt_type - Sets the Encrypt Type in Tx Descriptor 187 * @desc: Handle to Tx Descriptor 188 * @type: Encrypt Type 189 * 190 * Return: void 191 */ 192 static inline void hal_tx_desc_set_encrypt_type(void *desc, 193 enum hal_tx_encrypt_type type) 194 { 195 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCRYPT_TYPE) |= 196 HAL_TX_SM(TCL_DATA_CMD_2, ENCRYPT_TYPE, type); 197 } 198 199 /** 200 * hal_tx_desc_set_addr_search_flags - Enable AddrX and AddrY search flags 201 * @desc: Handle to Tx Descriptor 202 * @flags: Bit 0 - AddrY search enable, Bit 1 - AddrX search enable 203 * 204 * Return: void 205 */ 206 static inline void hal_tx_desc_set_addr_search_flags(void *desc, 207 uint8_t flags) 208 { 209 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRX_EN) |= 210 HAL_TX_SM(TCL_DATA_CMD_2, ADDRX_EN, (flags & 0x1)); 211 212 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRY_EN) |= 213 HAL_TX_SM(TCL_DATA_CMD_2, ADDRY_EN, (flags >> 1)); 214 } 215 216 /** 217 * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags 218 * Tx Descriptor for MSDU_buffer type 219 * @desc: Handle to Tx Descriptor 220 * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits) 221 * 222 * Return: void 223 */ 224 static inline void hal_tx_desc_set_l4_checksum_en(void *desc, 225 uint8_t en) 226 { 227 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 228 (HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV4_CHECKSUM_EN, en) | 229 HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV6_CHECKSUM_EN, en) | 230 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV4_CHECKSUM_EN, en) | 231 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV6_CHECKSUM_EN, en)); 232 } 233 234 /** 235 * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in 236 * Tx Descriptor for MSDU_buffer type 237 * @desc: Handle to Tx Descriptor 238 * @checksum_en_flags: ipv4 checksum enable flags 239 * 240 * Return: void 241 */ 242 static inline void hal_tx_desc_set_l3_checksum_en(void *desc, 243 uint8_t en) 244 { 245 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 246 HAL_TX_SM(TCL_DATA_CMD_3, IPV4_CHECKSUM_EN, en); 247 } 248 249 /** 250 * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor 251 * @desc:Handle to Tx Descriptor 252 * @metadata: Metadata to be sent to Firmware 253 * 254 * Return: void 255 */ 256 static inline void hal_tx_desc_set_fw_metadata(void *desc, 257 uint16_t metadata) 258 { 259 HAL_SET_FLD(desc, TCL_DATA_CMD_2, TCL_CMD_NUMBER) |= 260 HAL_TX_SM(TCL_DATA_CMD_2, TCL_CMD_NUMBER, metadata); 261 } 262 263 /** 264 * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor. 265 * @desc:Handle to Tx Descriptor 266 * @to_fw: if set, Forward packet to FW along with classification result 267 * 268 * Return: void 269 */ 270 static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw) 271 { 272 HAL_SET_FLD(desc, TCL_DATA_CMD_3, TO_FW) |= 273 HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw); 274 } 275 276 /** 277 * hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor 278 * @hal_soc_hdl: hal soc handle 279 * @desc: Handle to Tx Descriptor 280 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 281 * enabling the interpretation of the 'Mesh Control Present' bit 282 * (bit 8) of QoS Control (otherwise this bit is ignored), 283 * For native WiFi frames, this indicates that a 'Mesh Control' field 284 * is present between the header and the LLC. 285 * 286 * Return: void 287 */ 288 static inline void hal_tx_desc_set_mesh_en(hal_soc_handle_t hal_soc_hdl, 289 void *desc, uint8_t en) 290 { 291 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 292 293 hal_soc->ops->hal_tx_desc_set_mesh_en(desc, en); 294 } 295 296 /** 297 * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in 298 * frame) to be used for Tx Frame 299 * @desc: Handle to Tx Descriptor 300 * @hlos_tid: HLOS TID 301 * 302 * Return: void 303 */ 304 static inline void hal_tx_desc_set_hlos_tid(void *desc, 305 uint8_t hlos_tid) 306 { 307 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID) |= 308 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID, hlos_tid); 309 310 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |= 311 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1); 312 } 313 314 /** 315 * hal_tx_desc_set_dscp_tid_table_id() - Sets DSCP to TID conversion table ID 316 * @hal_soc: Handle to HAL SoC structure 317 * @desc: Handle to Tx Descriptor 318 * @id: DSCP to tid conversion table to be used for this frame 319 * 320 * Return: void 321 */ 322 static inline 323 void hal_tx_desc_set_dscp_tid_table_id(hal_soc_handle_t hal_soc_hdl, 324 void *desc, uint8_t id) 325 { 326 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 327 328 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id(desc, id); 329 } 330 331 /** 332 * hal_tx_desc_clear - Clear the HW descriptor entry 333 * @hw_desc: Hardware descriptor to be cleared 334 * 335 * Return: void 336 */ 337 static inline void hal_tx_desc_clear(void *hw_desc) 338 { 339 qdf_mem_set(hw_desc + sizeof(struct tlv_32_hdr), 340 HAL_TX_DESC_LEN_BYTES, 0); 341 } 342 343 /** 344 * hal_tx_desc_sync - Commit the descriptor to Hardware 345 * @hal_tx_des_cached: Cached descriptor that software maintains 346 * @hw_desc: Hardware descriptor to be updated 347 */ 348 static inline void hal_tx_desc_sync(void *hal_tx_desc_cached, 349 void *hw_desc) 350 { 351 qdf_mem_copy((hw_desc + sizeof(struct tlv_32_hdr)), 352 hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES); 353 } 354 355 /*--------------------------------------------------------------------------- 356 * WBM Descriptor accessor APIs for Tx completions 357 *--------------------------------------------------------------------------- 358 */ 359 360 /** 361 * hal_tx_get_wbm_sw0_bm_id() - Get the BM ID for first tx completion ring 362 * 363 * Return: BM ID for first tx completion ring 364 */ 365 static inline uint32_t hal_tx_get_wbm_sw0_bm_id(void) 366 { 367 return HAL_LI_WBM_SW0_BM_ID; 368 } 369 370 /** 371 * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor 372 * @hal_desc: completion ring descriptor pointer 373 * 374 * This function will tx descriptor id, cookie, within hardware completion 375 * descriptor 376 * 377 * Return: cookie 378 */ 379 static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc) 380 { 381 uint32_t comp_desc = 382 *(uint32_t *)(((uint8_t *)hal_desc) + 383 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET); 384 385 /* Cookie is placed on 2nd word */ 386 return (comp_desc & BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) >> 387 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB; 388 } 389 390 /** 391 * hal_tx_comp_get_paddr() - Get paddr within comp descriptor 392 * @hal_desc: completion ring descriptor pointer 393 * 394 * This function will get buffer physical address within hardware completion 395 * descriptor 396 * 397 * Return: Buffer physical address 398 */ 399 static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc) 400 { 401 uint32_t paddr_lo; 402 uint32_t paddr_hi; 403 404 paddr_lo = *(uint32_t *)(((uint8_t *)hal_desc) + 405 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET); 406 407 paddr_hi = *(uint32_t *)(((uint8_t *)hal_desc) + 408 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET); 409 410 paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) >> 411 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB; 412 413 return (qdf_dma_addr_t)(paddr_lo | (((uint64_t)paddr_hi) << 32)); 414 } 415 #endif /* _HAL_LI_TX_H_ */ 416