1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_LI_RX_H_ 20 #define _HAL_LI_RX_H_ 21 22 #include <hal_rx.h> 23 24 /* 25 * macro to set the cookie into the rxdma ring entry 26 */ 27 #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \ 28 ((*(((unsigned int *)buff_addr_info) + \ 29 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ 30 ~BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK); \ 31 ((*(((unsigned int *)buff_addr_info) + \ 32 (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ 33 ((cookie) << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \ 34 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) 35 36 /* 37 * macro to set the manager into the rxdma ring entry 38 */ 39 #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \ 40 ((*(((unsigned int *)buff_addr_info) + \ 41 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \ 42 ~BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK); \ 43 ((*(((unsigned int *)buff_addr_info) + \ 44 (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \ 45 ((manager) << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \ 46 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK) 47 48 #define HAL_RX_ERROR_STATUS_GET(reo_desc) \ 49 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \ 50 REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET)),\ 51 REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK, \ 52 REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB)) 53 54 #define HAL_RX_BUF_COOKIE_GET(buff_addr_info) \ 55 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 56 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET)), \ 57 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK, \ 58 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB)) 59 60 #define HAL_RX_BUF_RBM_GET(buff_addr_info) \ 61 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 62 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET)),\ 63 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK, \ 64 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB)) 65 66 /* TODO: Convert the following structure fields accesseses to offsets */ 67 68 #define HAL_RX_REO_BUF_COOKIE_GET(reo_desc) \ 69 (HAL_RX_BUF_COOKIE_GET(& \ 70 (((struct reo_destination_ring *) \ 71 reo_desc)->buf_or_link_desc_addr_info))) 72 73 #define HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info_ptr) \ 74 ((mpdu_info_ptr \ 75 [RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET >> 2] & \ 76 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK) >> \ 77 RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB) 78 79 #define HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info_ptr) \ 80 ((mpdu_info_ptr \ 81 [RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET >> 2] & \ 82 RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK) >> \ 83 RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB) 84 85 #define HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info_ptr) \ 86 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET >> 2] & \ 87 RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK) >> \ 88 RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB) 89 90 #define HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) \ 91 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET >> 2] & \ 92 RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK) 93 94 #define HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) \ 95 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET >> 2] & \ 96 RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK) 97 98 #define HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) \ 99 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET >> 2] & \ 100 RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK) 101 102 #define HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr) \ 103 (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET >> 2] & \ 104 RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK) 105 106 #define HAL_RX_MPDU_FLAGS_GET(mpdu_info_ptr) \ 107 (HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) | \ 108 HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) | \ 109 HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) | \ 110 HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr)) 111 112 #define HAL_RX_MPDU_BAR_FRAME_GET(mpdu_info_ptr) \ 113 ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_BAR_FRAME_OFFSET >> 2] & \ 114 RX_MPDU_DESC_INFO_0_BAR_FRAME_MASK) >> \ 115 RX_MPDU_DESC_INFO_0_BAR_FRAME_LSB) 116 117 /* 118 * NOTE: None of the following _GET macros need a right 119 * shift by the corresponding _LSB. This is because, they are 120 * finally taken and "OR'ed" into a single word again. 121 */ 122 #define HAL_RX_MSDU_CONTINUATION_FLAG_SET(msdu_info_ptr, val) \ 123 ((*(((uint32_t *)msdu_info_ptr) + \ 124 (RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET >> 2))) |= \ 125 ((val) << RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB) & \ 126 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 127 128 #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \ 129 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 130 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \ 131 RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) 132 133 #define HAL_RX_MSDU_REO_DST_IND_GET(msdu_info_ptr) \ 134 (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 135 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET)), \ 136 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK, \ 137 RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB)) 138 139 #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 140 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 141 RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \ 142 RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK) 143 144 #define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 145 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 146 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \ 147 RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK) 148 149 #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \ 150 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 151 RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \ 152 RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK) 153 154 #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \ 155 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 156 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \ 157 RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK) 158 159 #define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ 160 ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ 161 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \ 162 RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK) 163 164 #define HAL_RX_REO_MSDU_REO_DST_IND_GET(reo_desc) \ 165 (HAL_RX_MSDU_REO_DST_IND_GET(& \ 166 (((struct reo_destination_ring *) \ 167 reo_desc)->rx_msdu_desc_info_details))) 168 169 #define HAL_RX_MPDU_ENCRYPT_TYPE_GET(_rx_mpdu_info) \ 170 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 171 RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET)), \ 172 RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK, \ 173 RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB)) 174 175 #define HAL_RX_MSDU_DESC_INFO_SET(_msdu_info_ptr, _field, _val) \ 176 HAL_RX_FLD_SET(_msdu_info_ptr, RX_MSDU_DESC_INFO_0, \ 177 _field, _val) 178 179 #define HAL_RX_MPDU_DESC_INFO_SET(_mpdu_info_ptr, _field, _val) \ 180 HAL_RX_FLD_SET(_mpdu_info_ptr, RX_MPDU_DESC_INFO_0, \ 181 _field, _val) 182 183 /* 184 * Structures & Macros to obtain fields from the TLV's in the Rx packet 185 * pre-header. 186 */ 187 188 /* 189 * Every Rx packet starts at an offset from the top of the buffer. 190 * If the host hasn't subscribed to any specific TLV, there is 191 * still space reserved for the following TLV's from the start of 192 * the buffer: 193 * -- RX ATTENTION 194 * -- RX MPDU START 195 * -- RX MSDU START 196 * -- RX MSDU END 197 * -- RX MPDU END 198 * -- RX PACKET HEADER (802.11) 199 * If the host subscribes to any of the TLV's above, that TLV 200 * if populated by the HW 201 */ 202 203 #define NUM_DWORDS_TAG 1 204 205 /* By default the packet header TLV is 128 bytes */ 206 #define NUM_OF_BYTES_RX_802_11_HDR_TLV 128 207 #define NUM_OF_DWORDS_RX_802_11_HDR_TLV \ 208 (NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2) 209 210 #define RX_PKT_OFFSET_WORDS \ 211 ( \ 212 NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \ 213 NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \ 214 NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \ 215 NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \ 216 NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \ 217 NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \ 218 ) 219 220 #define RX_PKT_OFFSET_BYTES \ 221 (RX_PKT_OFFSET_WORDS << 2) 222 223 #define RX_PKT_HDR_TLV_LEN 120 224 225 /* 226 * Each RX descriptor TLV is preceded by 1 DWORD "tag" 227 */ 228 struct rx_attention_tlv { 229 uint32_t tag; 230 struct rx_attention rx_attn; 231 }; 232 233 struct rx_mpdu_start_tlv { 234 uint32_t tag; 235 struct rx_mpdu_start rx_mpdu_start; 236 }; 237 238 struct rx_msdu_start_tlv { 239 uint32_t tag; 240 struct rx_msdu_start rx_msdu_start; 241 }; 242 243 struct rx_msdu_end_tlv { 244 uint32_t tag; 245 struct rx_msdu_end rx_msdu_end; 246 }; 247 248 struct rx_mpdu_end_tlv { 249 uint32_t tag; 250 struct rx_mpdu_end rx_mpdu_end; 251 }; 252 253 struct rx_pkt_hdr_tlv { 254 uint32_t tag; /* 4 B */ 255 uint32_t phy_ppdu_id; /* 4 B */ 256 char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */ 257 }; 258 259 /* rx_pkt_tlvs structure should be used to process Data buffers, monitor status 260 * buffers, monitor destination buffers and monitor descriptor buffers. 261 */ 262 #ifdef RXDMA_OPTIMIZATION 263 /* 264 * The RX_PADDING_BYTES is required so that the TLV's don't 265 * spread across the 128 byte boundary 266 * RXDMA optimization requires: 267 * 1) MSDU_END & ATTENTION TLV's follow in that order 268 * 2) TLV's don't span across 128 byte lines 269 * 3) Rx Buffer is nicely aligned on the 128 byte boundary 270 */ 271 #define RX_PADDING0_BYTES 4 272 #define RX_PADDING1_BYTES 16 273 struct rx_pkt_tlvs { 274 struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */ 275 struct rx_attention_tlv attn_tlv; /* 16 bytes */ 276 struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */ 277 uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */ 278 struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */ 279 struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */ 280 uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */ 281 #ifndef NO_RX_PKT_HDR_TLV 282 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 283 #endif 284 }; 285 #else /* RXDMA_OPTIMIZATION */ 286 struct rx_pkt_tlvs { 287 struct rx_attention_tlv attn_tlv; 288 struct rx_mpdu_start_tlv mpdu_start_tlv; 289 struct rx_msdu_start_tlv msdu_start_tlv; 290 struct rx_msdu_end_tlv msdu_end_tlv; 291 struct rx_mpdu_end_tlv mpdu_end_tlv; 292 struct rx_pkt_hdr_tlv pkt_hdr_tlv; 293 }; 294 #endif /* RXDMA_OPTIMIZATION */ 295 296 /* rx_mon_pkt_tlvs structure should be used to process monitor data buffers */ 297 #ifdef RXDMA_OPTIMIZATION 298 struct rx_mon_pkt_tlvs { 299 struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */ 300 struct rx_attention_tlv attn_tlv; /* 16 bytes */ 301 struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */ 302 uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */ 303 struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */ 304 struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */ 305 uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */ 306 struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ 307 }; 308 #else /* RXDMA_OPTIMIZATION */ 309 struct rx_mon_pkt_tlvs { 310 struct rx_attention_tlv attn_tlv; 311 struct rx_mpdu_start_tlv mpdu_start_tlv; 312 struct rx_msdu_start_tlv msdu_start_tlv; 313 struct rx_msdu_end_tlv msdu_end_tlv; 314 struct rx_mpdu_end_tlv mpdu_end_tlv; 315 struct rx_pkt_hdr_tlv pkt_hdr_tlv; 316 }; 317 #endif 318 319 #define SIZE_OF_MONITOR_TLV sizeof(struct rx_mon_pkt_tlvs) 320 #define SIZE_OF_DATA_RX_TLV sizeof(struct rx_pkt_tlvs) 321 322 #define RX_PKT_TLVS_LEN SIZE_OF_DATA_RX_TLV 323 324 #define RX_PKT_TLV_OFFSET(field) qdf_offsetof(struct rx_pkt_tlvs, field) 325 326 #define HAL_RX_PKT_TLV_MPDU_START_OFFSET(hal_soc) \ 327 RX_PKT_TLV_OFFSET(mpdu_start_tlv) 328 #define HAL_RX_PKT_TLV_MPDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(mpdu_end_tlv) 329 #define HAL_RX_PKT_TLV_MSDU_START_OFFSET(hal_soc) \ 330 RX_PKT_TLV_OFFSET(msdu_start_tlv) 331 #define HAL_RX_PKT_TLV_MSDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(msdu_end_tlv) 332 #define HAL_RX_PKT_TLV_ATTN_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(attn_tlv) 333 #define HAL_RX_PKT_TLV_PKT_HDR_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(pkt_hdr_tlv) 334 335 /** 336 * hal_rx_get_pkt_tlvs(): Function to retrieve pkt tlvs from nbuf 337 * 338 * @nbuf: Pointer to data buffer field 339 * Returns: pointer to rx_pkt_tlvs 340 */ 341 static inline 342 struct rx_pkt_tlvs *hal_rx_get_pkt_tlvs(uint8_t *rx_buf_start) 343 { 344 return (struct rx_pkt_tlvs *)rx_buf_start; 345 } 346 347 /** 348 * hal_rx_get_mpdu_info(): Function to retrieve mpdu info from pkt tlvs 349 * 350 * @pkt_tlvs: Pointer to pkt_tlvs 351 * Returns: pointer to rx_mpdu_info structure 352 */ 353 static inline 354 struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs) 355 { 356 return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 357 } 358 359 /** 360 * hal_rx_mon_dest_get_buffer_info_from_tlv(): Retrieve mon dest frame info 361 * from the reserved bytes of rx_tlv_hdr. 362 * @buf: start of rx_tlv_hdr 363 * @buf_info: hal_rx_mon_dest_buf_info structure 364 * 365 * Return: void 366 */ 367 static inline void hal_rx_mon_dest_get_buffer_info_from_tlv( 368 uint8_t *buf, 369 struct hal_rx_mon_dest_buf_info *buf_info) 370 { 371 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 372 373 qdf_mem_copy(buf_info, pkt_tlvs->rx_padding0, 374 sizeof(struct hal_rx_mon_dest_buf_info)); 375 } 376 377 /* 378 * Get msdu_done bit from the RX_ATTENTION TLV 379 */ 380 #define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \ 381 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 382 RX_ATTENTION_2_MSDU_DONE_OFFSET)), \ 383 RX_ATTENTION_2_MSDU_DONE_MASK, \ 384 RX_ATTENTION_2_MSDU_DONE_LSB)) 385 386 #define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \ 387 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 388 RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \ 389 RX_ATTENTION_1_FIRST_MPDU_MASK, \ 390 RX_ATTENTION_1_FIRST_MPDU_LSB)) 391 392 #define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \ 393 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 394 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \ 395 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK, \ 396 RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB)) 397 398 /* 399 * hal_rx_attn_tcp_udp_cksum_fail_get(): get tcp_udp cksum fail bit 400 * from rx attention 401 * @buf: pointer to rx_pkt_tlvs 402 * 403 * Return: tcp_udp_cksum_fail 404 */ 405 static inline bool 406 hal_rx_attn_tcp_udp_cksum_fail_get(uint8_t *buf) 407 { 408 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 409 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 410 uint8_t tcp_udp_cksum_fail; 411 412 tcp_udp_cksum_fail = HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(rx_attn); 413 414 return !!tcp_udp_cksum_fail; 415 } 416 417 #define HAL_RX_ATTN_IP_CKSUM_FAIL_GET(_rx_attn) \ 418 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 419 RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET)), \ 420 RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK, \ 421 RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB)) 422 423 /* 424 * hal_rx_attn_ip_cksum_fail_get(): get ip cksum fail bit 425 * from rx attention 426 * @buf: pointer to rx_pkt_tlvs 427 * 428 * Return: ip_cksum_fail 429 */ 430 static inline bool 431 hal_rx_attn_ip_cksum_fail_get(uint8_t *buf) 432 { 433 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 434 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 435 uint8_t ip_cksum_fail; 436 437 ip_cksum_fail = HAL_RX_ATTN_IP_CKSUM_FAIL_GET(rx_attn); 438 439 return !!ip_cksum_fail; 440 } 441 442 #define HAL_RX_ATTN_PHY_PPDU_ID_GET(_rx_attn) \ 443 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 444 RX_ATTENTION_0_PHY_PPDU_ID_OFFSET)), \ 445 RX_ATTENTION_0_PHY_PPDU_ID_MASK, \ 446 RX_ATTENTION_0_PHY_PPDU_ID_LSB)) 447 448 #define HAL_RX_ATTN_CCE_MATCH_GET(_rx_attn) \ 449 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 450 RX_ATTENTION_1_CCE_MATCH_OFFSET)), \ 451 RX_ATTENTION_1_CCE_MATCH_MASK, \ 452 RX_ATTENTION_1_CCE_MATCH_LSB)) 453 454 /* 455 * hal_rx_msdu_cce_match_get(): get CCE match bit 456 * from rx attention 457 * @buf: pointer to rx_pkt_tlvs 458 * Return: CCE match value 459 */ 460 static inline bool 461 hal_rx_msdu_cce_match_get(uint8_t *buf) 462 { 463 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 464 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 465 uint8_t cce_match_val; 466 467 cce_match_val = HAL_RX_ATTN_CCE_MATCH_GET(rx_attn); 468 return !!cce_match_val; 469 } 470 471 /* 472 * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START 473 */ 474 #define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \ 475 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 476 RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \ 477 RX_MPDU_INFO_8_PEER_META_DATA_MASK, \ 478 RX_MPDU_INFO_8_PEER_META_DATA_LSB)) 479 480 static inline uint32_t 481 hal_rx_mpdu_peer_meta_data_get(uint8_t *buf) 482 { 483 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 484 struct rx_mpdu_start *mpdu_start = 485 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 486 487 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 488 uint32_t peer_meta_data; 489 490 peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info); 491 492 return peer_meta_data; 493 } 494 495 #define HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(_rx_mpdu_info) \ 496 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 497 RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET)), \ 498 RX_MPDU_INFO_12_AMPDU_FLAG_MASK, \ 499 RX_MPDU_INFO_12_AMPDU_FLAG_LSB)) 500 501 #define HAL_RX_MPDU_PEER_META_DATA_SET(_rx_mpdu_info, peer_mdata) \ 502 ((*(((uint32_t *)_rx_mpdu_info) + \ 503 (RX_MPDU_INFO_8_PEER_META_DATA_OFFSET >> 2))) = \ 504 ((peer_mdata) << RX_MPDU_INFO_8_PEER_META_DATA_LSB) & \ 505 RX_MPDU_INFO_8_PEER_META_DATA_MASK) 506 507 /* 508 * @ hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv 509 * 510 * @ buf: rx_tlv_hdr of the received packet 511 * @ peer_mdata: peer meta data to be set. 512 * @ Return: void 513 */ 514 static inline void 515 hal_rx_mpdu_peer_meta_data_set(uint8_t *buf, uint32_t peer_mdata) 516 { 517 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 518 struct rx_mpdu_start *mpdu_start = 519 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 520 521 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 522 523 HAL_RX_MPDU_PEER_META_DATA_SET(mpdu_info, peer_mdata); 524 } 525 526 /** 527 * LRO information needed from the TLVs 528 */ 529 #define HAL_RX_TLV_GET_LRO_ELIGIBLE(buf) \ 530 (_HAL_MS( \ 531 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 532 msdu_end_tlv.rx_msdu_end), \ 533 RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET)), \ 534 RX_MSDU_END_9_LRO_ELIGIBLE_MASK, \ 535 RX_MSDU_END_9_LRO_ELIGIBLE_LSB)) 536 537 #define HAL_RX_TLV_GET_TCP_ACK(buf) \ 538 (_HAL_MS( \ 539 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 540 msdu_end_tlv.rx_msdu_end), \ 541 RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET)), \ 542 RX_MSDU_END_8_TCP_ACK_NUMBER_MASK, \ 543 RX_MSDU_END_8_TCP_ACK_NUMBER_LSB)) 544 545 #define HAL_RX_TLV_GET_TCP_SEQ(buf) \ 546 (_HAL_MS( \ 547 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 548 msdu_end_tlv.rx_msdu_end), \ 549 RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET)), \ 550 RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK, \ 551 RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB)) 552 553 #define HAL_RX_TLV_GET_TCP_WIN(buf) \ 554 (_HAL_MS( \ 555 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 556 msdu_end_tlv.rx_msdu_end), \ 557 RX_MSDU_END_9_WINDOW_SIZE_OFFSET)), \ 558 RX_MSDU_END_9_WINDOW_SIZE_MASK, \ 559 RX_MSDU_END_9_WINDOW_SIZE_LSB)) 560 561 #define HAL_RX_TLV_GET_TCP_PURE_ACK(buf) \ 562 (_HAL_MS( \ 563 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 564 msdu_start_tlv.rx_msdu_start), \ 565 RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET)), \ 566 RX_MSDU_START_2_TCP_ONLY_ACK_MASK, \ 567 RX_MSDU_START_2_TCP_ONLY_ACK_LSB)) 568 569 #define HAL_RX_TLV_GET_TCP_PROTO(buf) \ 570 (_HAL_MS( \ 571 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 572 msdu_start_tlv.rx_msdu_start), \ 573 RX_MSDU_START_2_TCP_PROTO_OFFSET)), \ 574 RX_MSDU_START_2_TCP_PROTO_MASK, \ 575 RX_MSDU_START_2_TCP_PROTO_LSB)) 576 577 #define HAL_RX_TLV_GET_UDP_PROTO(buf) \ 578 (_HAL_MS( \ 579 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 580 msdu_start_tlv.rx_msdu_start), \ 581 RX_MSDU_START_2_UDP_PROTO_OFFSET)), \ 582 RX_MSDU_START_2_UDP_PROTO_MASK, \ 583 RX_MSDU_START_2_UDP_PROTO_LSB)) 584 585 #define HAL_RX_TLV_GET_IPV6(buf) \ 586 (_HAL_MS( \ 587 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 588 msdu_start_tlv.rx_msdu_start), \ 589 RX_MSDU_START_2_IPV6_PROTO_OFFSET)), \ 590 RX_MSDU_START_2_IPV6_PROTO_MASK, \ 591 RX_MSDU_START_2_IPV6_PROTO_LSB)) 592 593 #define HAL_RX_TLV_GET_IP_OFFSET(buf) \ 594 (_HAL_MS( \ 595 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 596 msdu_start_tlv.rx_msdu_start), \ 597 RX_MSDU_START_1_L3_OFFSET_OFFSET)), \ 598 RX_MSDU_START_1_L3_OFFSET_MASK, \ 599 RX_MSDU_START_1_L3_OFFSET_LSB)) 600 601 #define HAL_RX_TLV_GET_TCP_OFFSET(buf) \ 602 (_HAL_MS( \ 603 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 604 msdu_start_tlv.rx_msdu_start), \ 605 RX_MSDU_START_1_L4_OFFSET_OFFSET)), \ 606 RX_MSDU_START_1_L4_OFFSET_MASK, \ 607 RX_MSDU_START_1_L4_OFFSET_LSB)) 608 609 #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(buf) \ 610 (_HAL_MS( \ 611 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 612 msdu_start_tlv.rx_msdu_start), \ 613 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 614 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 615 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 616 617 #define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \ 618 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 619 RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \ 620 RX_MSDU_START_1_MSDU_LENGTH_MASK, \ 621 RX_MSDU_START_1_MSDU_LENGTH_LSB)) 622 623 #define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \ 624 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 625 RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \ 626 RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \ 627 RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB)) 628 629 #define HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(_rx_msdu_start) \ 630 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 631 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ 632 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ 633 RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) 634 635 /** 636 * hal_rx_msdu_start_toeplitz_get: API to get the toeplitz hash 637 * from rx_msdu_start TLV 638 * 639 * @ buf: pointer to the start of RX PKT TLV headers 640 * Return: toeplitz hash 641 */ 642 static inline uint32_t 643 hal_rx_msdu_start_toeplitz_get(uint8_t *buf) 644 { 645 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 646 struct rx_msdu_start *msdu_start = 647 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 648 649 return HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(msdu_start); 650 } 651 652 #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \ 653 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 654 RX_MSDU_START_5_SGI_OFFSET)), \ 655 RX_MSDU_START_5_SGI_MASK, \ 656 RX_MSDU_START_5_SGI_LSB)) 657 658 #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \ 659 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 660 RX_MSDU_START_5_RATE_MCS_OFFSET)), \ 661 RX_MSDU_START_5_RATE_MCS_MASK, \ 662 RX_MSDU_START_5_RATE_MCS_LSB)) 663 664 #define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \ 665 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 666 RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \ 667 RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \ 668 RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB)) 669 670 /* 671 * Get key index from RX_MSDU_END 672 */ 673 #define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \ 674 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 675 RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \ 676 RX_MSDU_END_2_KEY_ID_OCTET_MASK, \ 677 RX_MSDU_END_2_KEY_ID_OCTET_LSB)) 678 679 #define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \ 680 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 681 RX_MSDU_START_5_USER_RSSI_OFFSET)), \ 682 RX_MSDU_START_5_USER_RSSI_MASK, \ 683 RX_MSDU_START_5_USER_RSSI_LSB)) 684 /* 685 * hal_rx_msdu_start_get_rssi(): API to get the rssi of received pkt 686 * from rx_msdu_start 687 * 688 * @buf: pointer to the start of RX PKT TLV header 689 * Return: uint32_t(rssi) 690 */ 691 static inline uint32_t 692 hal_rx_msdu_start_get_rssi(uint8_t *buf) 693 { 694 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 695 struct rx_msdu_start *msdu_start = 696 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 697 uint32_t rssi; 698 699 rssi = HAL_RX_MSDU_START_RSSI_GET(msdu_start); 700 701 return rssi; 702 } 703 704 #define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \ 705 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 706 RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \ 707 RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \ 708 RX_MSDU_START_7_SW_PHY_META_DATA_LSB)) 709 710 #define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \ 711 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ 712 RX_MSDU_START_5_PKT_TYPE_OFFSET)), \ 713 RX_MSDU_START_5_PKT_TYPE_MASK, \ 714 RX_MSDU_START_5_PKT_TYPE_LSB)) 715 716 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 717 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 718 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 719 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 720 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 721 722 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 723 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 724 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 725 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 726 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 727 728 /******************************************************************************* 729 * RX ERROR APIS 730 ******************************************************************************/ 731 732 #define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \ 733 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 734 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \ 735 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \ 736 RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB)) 737 738 #define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \ 739 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ 740 RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \ 741 RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \ 742 RX_MPDU_END_1_TKIP_MIC_ERR_LSB)) 743 744 745 /******************************************************************************* 746 * RX REO ERROR APIS 747 ******************************************************************************/ 748 749 750 #define HAL_RX_REO_BUF_TYPE_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \ 751 (REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET >> 2))) & \ 752 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK) >> \ 753 REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB) 754 755 #define HAL_RX_REO_QUEUE_NUMBER_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \ 756 (REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET >> 2))) & \ 757 REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK) >> \ 758 REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB) 759 760 #define HAL_RX_REO_ERROR_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \ 761 (REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET >> 2))) & \ 762 REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK) >> \ 763 REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB) 764 765 /* 766 * hal_rx_msdu_link_desc_reinject: Re-injects the MSDU link descriptor to 767 * REO entrance ring 768 * 769 * @ soc: HAL version of the SOC pointer 770 * @ pa: Physical address of the MSDU Link Descriptor 771 * @ cookie: SW cookie to get to the virtual address 772 * @ error_enabled_reo_q: Argument to determine whether this needs to go 773 * to the error enabled REO queue 774 * 775 * Return: void 776 */ 777 static inline 778 void hal_rx_msdu_link_desc_reinject(struct hal_soc *soc, 779 uint64_t pa, 780 uint32_t cookie, 781 bool error_enabled_reo_q) 782 { 783 /* TODO */ 784 } 785 786 #define HAL_RX_WBM_FIRST_MSDU_GET(wbm_desc) \ 787 (((*(((uint32_t *)wbm_desc) + \ 788 (WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET >> 2))) & \ 789 WBM_RELEASE_RING_4_FIRST_MSDU_MASK) >> \ 790 WBM_RELEASE_RING_4_FIRST_MSDU_LSB) 791 792 #define HAL_RX_WBM_LAST_MSDU_GET(wbm_desc) \ 793 (((*(((uint32_t *)wbm_desc) + \ 794 (WBM_RELEASE_RING_4_LAST_MSDU_OFFSET >> 2))) & \ 795 WBM_RELEASE_RING_4_LAST_MSDU_MASK) >> \ 796 WBM_RELEASE_RING_4_LAST_MSDU_LSB) 797 798 #define HAL_RX_WBM_BUF_COOKIE_GET(wbm_desc) \ 799 HAL_RX_BUF_COOKIE_GET(&((struct wbm_release_ring *) \ 800 wbm_desc)->released_buff_or_desc_addr_info) 801 802 static inline 803 uint32_t 804 HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) { 805 struct rx_msdu_start *rx_msdu_start; 806 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 807 808 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 809 810 return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); 811 } 812 813 /** 814 * hal_rx_dump_rx_attention_tlv: dump RX attention TLV in structured 815 * humman readable format. 816 * @ rx_attn: pointer the rx_attention TLV in pkt. 817 * @ dbg_level: log level. 818 * 819 * Return: void 820 */ 821 static inline void hal_rx_dump_rx_attention_tlv(struct rx_attention *rx_attn, 822 uint8_t dbg_level) 823 { 824 hal_verbose_debug("rx_attention tlv (1/2) - " 825 "rxpcu_mpdu_filter_in_category: %x " 826 "sw_frame_group_id: %x " 827 "reserved_0: %x " 828 "phy_ppdu_id: %x " 829 "first_mpdu : %x " 830 "reserved_1a: %x " 831 "mcast_bcast: %x " 832 "ast_index_not_found: %x " 833 "ast_index_timeout: %x " 834 "power_mgmt: %x " 835 "non_qos: %x " 836 "null_data: %x " 837 "mgmt_type: %x " 838 "ctrl_type: %x " 839 "more_data: %x " 840 "eosp: %x " 841 "a_msdu_error: %x " 842 "fragment_flag: %x " 843 "order: %x " 844 "cce_match: %x " 845 "overflow_err: %x " 846 "msdu_length_err: %x " 847 "tcp_udp_chksum_fail: %x " 848 "ip_chksum_fail: %x " 849 "sa_idx_invalid: %x " 850 "da_idx_invalid: %x " 851 "reserved_1b: %x " 852 "rx_in_tx_decrypt_byp: %x ", 853 rx_attn->rxpcu_mpdu_filter_in_category, 854 rx_attn->sw_frame_group_id, 855 rx_attn->reserved_0, 856 rx_attn->phy_ppdu_id, 857 rx_attn->first_mpdu, 858 rx_attn->reserved_1a, 859 rx_attn->mcast_bcast, 860 rx_attn->ast_index_not_found, 861 rx_attn->ast_index_timeout, 862 rx_attn->power_mgmt, 863 rx_attn->non_qos, 864 rx_attn->null_data, 865 rx_attn->mgmt_type, 866 rx_attn->ctrl_type, 867 rx_attn->more_data, 868 rx_attn->eosp, 869 rx_attn->a_msdu_error, 870 rx_attn->fragment_flag, 871 rx_attn->order, 872 rx_attn->cce_match, 873 rx_attn->overflow_err, 874 rx_attn->msdu_length_err, 875 rx_attn->tcp_udp_chksum_fail, 876 rx_attn->ip_chksum_fail, 877 rx_attn->sa_idx_invalid, 878 rx_attn->da_idx_invalid, 879 rx_attn->reserved_1b, 880 rx_attn->rx_in_tx_decrypt_byp); 881 882 hal_verbose_debug("rx_attention tlv (2/2) - " 883 "encrypt_required: %x " 884 "directed: %x " 885 "buffer_fragment: %x " 886 "mpdu_length_err: %x " 887 "tkip_mic_err: %x " 888 "decrypt_err: %x " 889 "unencrypted_frame_err: %x " 890 "fcs_err: %x " 891 "flow_idx_timeout: %x " 892 "flow_idx_invalid: %x " 893 "wifi_parser_error: %x " 894 "amsdu_parser_error: %x " 895 "sa_idx_timeout: %x " 896 "da_idx_timeout: %x " 897 "msdu_limit_error: %x " 898 "da_is_valid: %x " 899 "da_is_mcbc: %x " 900 "sa_is_valid: %x " 901 "decrypt_status_code: %x " 902 "rx_bitmap_not_updated: %x " 903 "reserved_2: %x " 904 "msdu_done: %x ", 905 rx_attn->encrypt_required, 906 rx_attn->directed, 907 rx_attn->buffer_fragment, 908 rx_attn->mpdu_length_err, 909 rx_attn->tkip_mic_err, 910 rx_attn->decrypt_err, 911 rx_attn->unencrypted_frame_err, 912 rx_attn->fcs_err, 913 rx_attn->flow_idx_timeout, 914 rx_attn->flow_idx_invalid, 915 rx_attn->wifi_parser_error, 916 rx_attn->amsdu_parser_error, 917 rx_attn->sa_idx_timeout, 918 rx_attn->da_idx_timeout, 919 rx_attn->msdu_limit_error, 920 rx_attn->da_is_valid, 921 rx_attn->da_is_mcbc, 922 rx_attn->sa_is_valid, 923 rx_attn->decrypt_status_code, 924 rx_attn->rx_bitmap_not_updated, 925 rx_attn->reserved_2, 926 rx_attn->msdu_done); 927 } 928 929 /** 930 * hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured 931 * human readable format. 932 * @ mpdu_end: pointer the mpdu_end TLV in pkt. 933 * @ dbg_level: log level. 934 * 935 * Return: void 936 */ 937 static inline void hal_rx_dump_mpdu_end_tlv(struct rx_mpdu_end *mpdu_end, 938 uint8_t dbg_level) 939 { 940 hal_verbose_debug("rx_mpdu_end tlv - " 941 "rxpcu_mpdu_filter_in_category: %x " 942 "sw_frame_group_id: %x " 943 "phy_ppdu_id: %x " 944 "unsup_ktype_short_frame: %x " 945 "rx_in_tx_decrypt_byp: %x " 946 "overflow_err: %x " 947 "mpdu_length_err: %x " 948 "tkip_mic_err: %x " 949 "decrypt_err: %x " 950 "unencrypted_frame_err: %x " 951 "pn_fields_contain_valid_info: %x " 952 "fcs_err: %x " 953 "msdu_length_err: %x " 954 "rxdma0_destination_ring: %x " 955 "rxdma1_destination_ring: %x " 956 "decrypt_status_code: %x " 957 "rx_bitmap_not_updated: %x ", 958 mpdu_end->rxpcu_mpdu_filter_in_category, 959 mpdu_end->sw_frame_group_id, 960 mpdu_end->phy_ppdu_id, 961 mpdu_end->unsup_ktype_short_frame, 962 mpdu_end->rx_in_tx_decrypt_byp, 963 mpdu_end->overflow_err, 964 mpdu_end->mpdu_length_err, 965 mpdu_end->tkip_mic_err, 966 mpdu_end->decrypt_err, 967 mpdu_end->unencrypted_frame_err, 968 mpdu_end->pn_fields_contain_valid_info, 969 mpdu_end->fcs_err, 970 mpdu_end->msdu_length_err, 971 mpdu_end->rxdma0_destination_ring, 972 mpdu_end->rxdma1_destination_ring, 973 mpdu_end->decrypt_status_code, 974 mpdu_end->rx_bitmap_not_updated); 975 } 976 977 #ifdef NO_RX_PKT_HDR_TLV 978 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, 979 uint8_t dbg_level) 980 { 981 } 982 #else 983 /** 984 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 985 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 986 * @ dbg_level: log level. 987 * 988 * Return: void 989 */ 990 static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, 991 uint8_t dbg_level) 992 { 993 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 994 995 hal_verbose_debug("\n---------------\nrx_pkt_hdr_tlv" 996 "\n---------------\nphy_ppdu_id %d ", 997 pkt_hdr_tlv->phy_ppdu_id); 998 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 128); 999 } 1000 #endif 1001 1002 #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_mpdu_info) \ 1003 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 1004 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET)), \ 1005 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK, \ 1006 RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB)) 1007 /** 1008 * hal_rx_get_rx_more_frag_bit(): Function to retrieve more fragment bit 1009 * 1010 * @nbuf: Network buffer 1011 * Returns: rx more fragment bit 1012 */ 1013 static inline 1014 uint8_t hal_rx_get_rx_more_frag_bit(uint8_t *buf) 1015 { 1016 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1017 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1018 uint16_t frame_ctrl = 0; 1019 1020 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info) >> 1021 DOT11_FC1_MORE_FRAG_OFFSET; 1022 1023 /* more fragment bit if at offset bit 4 */ 1024 return frame_ctrl; 1025 } 1026 1027 static inline 1028 void hal_rx_mpdu_desc_info_get_li(void *desc_addr, 1029 void *mpdu_desc_info_hdl) 1030 { 1031 struct reo_destination_ring *reo_dst_ring; 1032 struct hal_rx_mpdu_desc_info *mpdu_desc_info = 1033 (struct hal_rx_mpdu_desc_info *)mpdu_desc_info_hdl; 1034 uint32_t *mpdu_info; 1035 1036 reo_dst_ring = (struct reo_destination_ring *)desc_addr; 1037 1038 mpdu_info = (uint32_t *)&reo_dst_ring->rx_mpdu_desc_info_details; 1039 1040 mpdu_desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); 1041 mpdu_desc_info->mpdu_seq = HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info); 1042 mpdu_desc_info->mpdu_flags = HAL_RX_MPDU_FLAGS_GET(mpdu_info); 1043 mpdu_desc_info->peer_meta_data = 1044 HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info); 1045 mpdu_desc_info->bar_frame = HAL_RX_MPDU_BAR_FRAME_GET(mpdu_info); 1046 } 1047 1048 /** 1049 * hal_rx_attn_msdu_done_get_li() - Get msdi done flag from RX TLV 1050 * @buf: RX tlv address 1051 * 1052 * Return: msdu done flag 1053 */ 1054 static inline uint32_t hal_rx_attn_msdu_done_get_li(uint8_t *buf) 1055 { 1056 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1057 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 1058 uint32_t msdu_done; 1059 1060 msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn); 1061 1062 return msdu_done; 1063 } 1064 1065 #define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \ 1066 (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 1067 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ 1068 HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \ 1069 HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 1070 HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \ 1071 HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ 1072 HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \ 1073 HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr)) 1074 1075 /** 1076 * hal_rx_msdu_flags_get_li() - Get msdu flags from ring desc 1077 * @msdu_desc_info_hdl: msdu desc info handle 1078 * 1079 * Return: msdu flags 1080 */ 1081 static inline 1082 uint32_t hal_rx_msdu_flags_get_li(rx_msdu_desc_info_t msdu_desc_info_hdl) 1083 { 1084 struct rx_msdu_desc_info *msdu_desc_info = 1085 (struct rx_msdu_desc_info *)msdu_desc_info_hdl; 1086 1087 return HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); 1088 } 1089 1090 /* 1091 *hal_rx_msdu_desc_info_get_li: Gets the flags related to MSDU descriptor. 1092 *@desc_addr: REO ring descriptor addr 1093 *@msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor 1094 * 1095 * Specifically flags needed are: first_msdu_in_mpdu, 1096 * last_msdu_in_mpdu, msdu_continuation, sa_is_valid, 1097 * sa_idx_timeout, da_is_valid, da_idx_timeout, da_is_MCBC 1098 * 1099 1100 *Return: void 1101 */ 1102 static inline void 1103 hal_rx_msdu_desc_info_get_li(void *desc_addr, 1104 struct hal_rx_msdu_desc_info *msdu_desc_info) 1105 { 1106 struct reo_destination_ring *reo_dst_ring; 1107 uint32_t *msdu_info; 1108 1109 reo_dst_ring = (struct reo_destination_ring *)desc_addr; 1110 1111 msdu_info = (uint32_t *)&reo_dst_ring->rx_msdu_desc_info_details; 1112 msdu_desc_info->msdu_flags = 1113 hal_rx_msdu_flags_get_li((struct rx_msdu_desc_info *)msdu_info); 1114 msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info); 1115 } 1116 1117 #define HAL_RX_MSDU_START_NSS_GET(_rx_msdu_start) \ 1118 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 1119 RX_MSDU_START_5_NSS_OFFSET)), \ 1120 RX_MSDU_START_5_NSS_MASK, \ 1121 RX_MSDU_START_5_NSS_LSB)) 1122 1123 #define HAL_RX_ATTN_MSDU_LEN_ERR_GET(_rx_attn) \ 1124 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ 1125 RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET)), \ 1126 RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK, \ 1127 RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB)) 1128 1129 /** 1130 * hal_rx_attn_msdu_len_err_get_li(): Get msdu_len_err value from 1131 * rx attention tlvs 1132 * @buf: pointer to rx pkt tlvs hdr 1133 * 1134 * Return: msdu_len_err value 1135 */ 1136 static inline uint32_t 1137 hal_rx_attn_msdu_len_err_get_li(uint8_t *buf) 1138 { 1139 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1140 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 1141 1142 return HAL_RX_ATTN_MSDU_LEN_ERR_GET(rx_attn); 1143 } 1144 #endif /* _HAL_LI_RX_H_ */ 1145