1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_LI_GENERIC_API_H_ 21 #define _HAL_LI_GENERIC_API_H_ 22 23 #include "hal_tx.h" 24 #include "hal_li_tx.h" 25 #include "hal_li_rx.h" 26 27 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) \ 28 (_HAL_MS((*_OFFSET_TO_WORD_PTR(wbm_desc, \ 29 WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET)), \ 30 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK, \ 31 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB)) 32 33 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) \ 34 (_HAL_MS((*_OFFSET_TO_WORD_PTR(wbm_desc, \ 35 WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET)), \ 36 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK, \ 37 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB)) 38 39 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 40 (((*(((uint32_t *)wbm_desc) + \ 41 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 42 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 43 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 44 45 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 46 (((*(((uint32_t *)wbm_desc) + \ 47 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 48 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 49 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 50 51 /** 52 * hal_rx_wbm_err_info_get_generic_li(): Retrieves WBM error code and reason and 53 * save it to hal_wbm_err_desc_info structure passed by caller 54 * @wbm_desc: wbm ring descriptor 55 * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 56 * Return: void 57 */ 58 static inline 59 void hal_rx_wbm_err_info_get_generic_li(void *wbm_desc, 60 void *wbm_er_info1) 61 { 62 struct hal_wbm_err_desc_info *wbm_er_info = 63 (struct hal_wbm_err_desc_info *)wbm_er_info1; 64 65 wbm_er_info->wbm_err_src = HAL_WBM2SW_RELEASE_SRC_GET(wbm_desc); 66 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 67 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 68 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 69 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 70 } 71 72 #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(CONFIG_SAWF) 73 static inline void 74 hal_tx_comp_get_buffer_timestamp_li(void *desc, 75 struct hal_tx_completion_status *ts) 76 { 77 ts->buffer_timestamp = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 78 BUFFER_TIMESTAMP); 79 } 80 #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY || CONFIG_SAWF */ 81 static inline void 82 hal_tx_comp_get_buffer_timestamp_li(void *desc, 83 struct hal_tx_completion_status *ts) 84 { 85 } 86 #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY || CONFIG_SAWF */ 87 88 #ifdef QCA_UNDECODED_METADATA_SUPPORT 89 static inline void 90 hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv, 91 struct hal_rx_ppdu_info *ppdu_info){ 92 switch (hal->target_type) { 93 case TARGET_TYPE_QCN9000: 94 ppdu_info->rx_status.phyrx_abort = 95 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, 96 PHYRX_ABORT_REQUEST_INFO_VALID); 97 ppdu_info->rx_status.phyrx_abort_reason = 98 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_11, 99 PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON); 100 break; 101 default: 102 break; 103 } 104 } 105 106 static inline void 107 hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info, 108 uint8_t *ht_sig_info) 109 { 110 ppdu_info->rx_status.ht_length = 111 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_0, LENGTH); 112 ppdu_info->rx_status.smoothing = 113 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, SMOOTHING); 114 ppdu_info->rx_status.not_sounding = 115 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, NOT_SOUNDING); 116 ppdu_info->rx_status.aggregation = 117 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, AGGREGATION); 118 ppdu_info->rx_status.ht_stbc = 119 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, STBC); 120 ppdu_info->rx_status.ht_crc = 121 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, CRC); 122 } 123 124 static inline void 125 hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, 126 uint8_t *l_sig_a_info) 127 { 128 ppdu_info->rx_status.l_sig_length = 129 HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, LENGTH); 130 ppdu_info->rx_status.l_sig_a_parity = 131 HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PARITY); 132 ppdu_info->rx_status.l_sig_a_pkt_type = 133 HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PKT_TYPE); 134 ppdu_info->rx_status.l_sig_a_implicit_sounding = 135 HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, 136 CAPTURED_IMPLICIT_SOUNDING); 137 } 138 139 static inline void 140 hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, 141 uint8_t *vht_sig_a_info) 142 { 143 ppdu_info->rx_status.vht_no_txop_ps = 144 HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, 145 TXOP_PS_NOT_ALLOWED); 146 ppdu_info->rx_status.vht_crc = 147 HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, CRC); 148 } 149 150 static inline void 151 hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info, 152 uint8_t *he_sig_a_su_info) { 153 ppdu_info->rx_status.he_crc = 154 HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, CRC); 155 } 156 157 static inline void 158 hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info, 159 uint8_t *he_sig_a_mu_dl_info) { 160 ppdu_info->rx_status.he_crc = 161 HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, CRC); 162 } 163 #else 164 static inline void 165 hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv, 166 struct hal_rx_ppdu_info *ppdu_info) 167 { 168 } 169 170 static inline void 171 hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info, 172 uint8_t *ht_sig_info) 173 { 174 } 175 176 static inline void 177 hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, 178 uint8_t *l_sig_a_info) 179 { 180 } 181 182 static inline void 183 hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, 184 uint8_t *vht_sig_a_info) 185 { 186 } 187 188 static inline void 189 hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info, 190 uint8_t *he_sig_a_su_info) 191 { 192 } 193 194 static inline void 195 hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info, 196 uint8_t *he_sig_a_mu_dl_info) 197 { 198 } 199 #endif /* QCA_UNDECODED_METADATA_SUPPORT */ 200 201 /** 202 * hal_tx_comp_get_status() - TQM Release reason 203 * @hal_desc: completion ring Tx status 204 * 205 * This function will parse the WBM completion descriptor and populate in 206 * HAL structure 207 * 208 * Return: none 209 */ 210 static inline void 211 hal_tx_comp_get_status_generic_li(void *desc, void *ts1, 212 struct hal_soc *hal) 213 { 214 uint8_t rate_stats_valid = 0; 215 uint32_t rate_stats = 0; 216 struct hal_tx_completion_status *ts = 217 (struct hal_tx_completion_status *)ts1; 218 219 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 220 TQM_STATUS_NUMBER); 221 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 222 ACK_FRAME_RSSI); 223 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 224 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 225 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 226 MSDU_PART_OF_AMSDU); 227 228 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 229 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 230 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 231 TRANSMIT_COUNT); 232 233 rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS); 234 235 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 236 TX_RATE_STATS_INFO_VALID, rate_stats); 237 238 ts->valid = rate_stats_valid; 239 240 if (rate_stats_valid) { 241 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 242 rate_stats); 243 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 244 TRANSMIT_PKT_TYPE, rate_stats); 245 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 246 TRANSMIT_STBC, rate_stats); 247 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 248 rate_stats); 249 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 250 rate_stats); 251 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 252 rate_stats); 253 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 254 rate_stats); 255 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 256 rate_stats); 257 } 258 259 ts->release_src = hal_tx_comp_get_buffer_source( 260 hal_soc_to_hal_soc_handle(hal), 261 desc); 262 ts->status = hal_tx_comp_get_release_reason( 263 desc, 264 hal_soc_to_hal_soc_handle(hal)); 265 266 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 267 TX_RATE_STATS_INFO_TX_RATE_STATS); 268 269 hal_tx_comp_get_buffer_timestamp_li(desc, ts); 270 } 271 272 /** 273 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 274 * @desc: Handle to Tx Descriptor 275 * @paddr: Physical Address 276 * @pool_id: Return Buffer Manager ID 277 * @desc_id: Descriptor ID 278 * @type: 0 - Address points to a MSDU buffer 279 * 1 - Address points to MSDU extension descriptor 280 * 281 * Return: void 282 */ 283 static inline void 284 hal_tx_desc_set_buf_addr_generic_li(void *desc, dma_addr_t paddr, 285 uint8_t rbm_id, uint32_t desc_id, 286 uint8_t type) 287 { 288 /* Set buffer_addr_info.buffer_addr_31_0 */ 289 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, 290 BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 291 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 292 293 /* Set buffer_addr_info.buffer_addr_39_32 */ 294 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 295 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 296 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 297 (((uint64_t)paddr) >> 32)); 298 299 /* Set buffer_addr_info.return_buffer_manager = rbm id */ 300 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 301 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 302 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, 303 RETURN_BUFFER_MANAGER, rbm_id); 304 305 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 306 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 307 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 308 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, 309 desc_id); 310 311 /* Set Buffer or Ext Descriptor Type */ 312 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, 313 BUF_OR_EXT_DESC_TYPE) |= 314 HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 315 } 316 317 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) 318 /** 319 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 320 * tlv_tag: Taf of the TLVs 321 * rx_tlv: the pointer to the TLVs 322 * @ppdu_info: pointer to ppdu_info 323 * 324 * Return: true if the tlv is handled, false if not 325 */ 326 static inline bool 327 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 328 struct hal_rx_ppdu_info *ppdu_info) 329 { 330 uint32_t value; 331 332 switch (tlv_tag) { 333 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 334 { 335 uint8_t *he_sig_a_mu_ul_info = 336 (uint8_t *)rx_tlv + 337 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, 338 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 339 ppdu_info->rx_status.he_flags = 1; 340 341 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 342 FORMAT_INDICATION); 343 if (value == 0) { 344 ppdu_info->rx_status.he_data1 = 345 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 346 } else { 347 ppdu_info->rx_status.he_data1 = 348 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 349 } 350 351 /* data1 */ 352 ppdu_info->rx_status.he_data1 |= 353 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 354 QDF_MON_STATUS_HE_DL_UL_KNOWN | 355 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 356 357 /* data2 */ 358 ppdu_info->rx_status.he_data2 |= 359 QDF_MON_STATUS_TXOP_KNOWN; 360 361 /*data3*/ 362 value = HAL_RX_GET(he_sig_a_mu_ul_info, 363 HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID); 364 ppdu_info->rx_status.he_data3 = value; 365 /* 1 for UL and 0 for DL */ 366 value = 1; 367 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 368 ppdu_info->rx_status.he_data3 |= value; 369 370 /*data4*/ 371 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 372 SPATIAL_REUSE); 373 ppdu_info->rx_status.he_data4 = value; 374 375 /*data5*/ 376 value = HAL_RX_GET(he_sig_a_mu_ul_info, 377 HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW); 378 ppdu_info->rx_status.he_data5 = value; 379 ppdu_info->rx_status.bw = value; 380 381 /*data6*/ 382 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1, 383 TXOP_DURATION); 384 value = value << QDF_MON_STATUS_TXOP_SHIFT; 385 ppdu_info->rx_status.he_data6 |= value; 386 return true; 387 } 388 default: 389 return false; 390 } 391 } 392 #else 393 static inline bool 394 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 395 struct hal_rx_ppdu_info *ppdu_info) 396 { 397 return false; 398 } 399 #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */ 400 401 #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) && \ 402 defined(RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 403 404 static inline void 405 hal_rx_handle_mu_ul_info(void *rx_tlv, 406 struct mon_rx_user_status *mon_rx_user_status) 407 { 408 mon_rx_user_status->mu_ul_user_v0_word0 = 409 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_11, 410 SW_RESPONSE_REFERENCE_PTR); 411 412 mon_rx_user_status->mu_ul_user_v0_word1 = 413 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_22, 414 SW_RESPONSE_REFERENCE_PTR_EXT); 415 } 416 417 static inline void 418 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 419 struct mon_rx_user_status *mon_rx_user_status) 420 { 421 uint32_t mpdu_ok_byte_count; 422 uint32_t mpdu_err_byte_count; 423 424 mpdu_ok_byte_count = HAL_RX_GET(rx_tlv, 425 RX_PPDU_END_USER_STATS_17, 426 MPDU_OK_BYTE_COUNT); 427 mpdu_err_byte_count = HAL_RX_GET(rx_tlv, 428 RX_PPDU_END_USER_STATS_19, 429 MPDU_ERR_BYTE_COUNT); 430 431 mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count; 432 mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count; 433 } 434 #else 435 static inline void 436 hal_rx_handle_mu_ul_info(void *rx_tlv, 437 struct mon_rx_user_status *mon_rx_user_status) 438 { 439 } 440 441 static inline void 442 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 443 struct mon_rx_user_status *mon_rx_user_status) 444 { 445 struct hal_rx_ppdu_info *ppdu_info = 446 (struct hal_rx_ppdu_info *)ppduinfo; 447 448 /* HKV1: doesn't support mpdu byte count */ 449 mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len; 450 mon_rx_user_status->mpdu_err_byte_count = 0; 451 } 452 #endif 453 454 static inline void 455 hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id, 456 struct mon_rx_user_status *mon_rx_user_status) 457 { 458 struct mon_rx_info *mon_rx_info; 459 struct mon_rx_user_info *mon_rx_user_info; 460 struct hal_rx_ppdu_info *ppdu_info = 461 (struct hal_rx_ppdu_info *)ppduinfo; 462 463 mon_rx_info = &ppdu_info->rx_info; 464 mon_rx_user_info = &ppdu_info->rx_user_info[user_id]; 465 mon_rx_user_info->qos_control_info_valid = 466 mon_rx_info->qos_control_info_valid; 467 mon_rx_user_info->qos_control = mon_rx_info->qos_control; 468 469 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 470 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 471 mon_rx_user_status->tcp_msdu_count = 472 ppdu_info->rx_status.tcp_msdu_count; 473 mon_rx_user_status->udp_msdu_count = 474 ppdu_info->rx_status.udp_msdu_count; 475 mon_rx_user_status->other_msdu_count = 476 ppdu_info->rx_status.other_msdu_count; 477 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 478 mon_rx_user_status->frame_control_info_valid = 479 ppdu_info->rx_status.frame_control_info_valid; 480 mon_rx_user_status->data_sequence_control_info_valid = 481 ppdu_info->rx_status.data_sequence_control_info_valid; 482 mon_rx_user_status->first_data_seq_ctrl = 483 ppdu_info->rx_status.first_data_seq_ctrl; 484 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 485 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 486 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 487 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 488 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 489 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 490 491 mon_rx_user_status->mpdu_cnt_fcs_ok = 492 ppdu_info->com_info.mpdu_cnt_fcs_ok; 493 mon_rx_user_status->mpdu_cnt_fcs_err = 494 ppdu_info->com_info.mpdu_cnt_fcs_err; 495 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 496 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 497 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 498 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 499 500 hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status); 501 } 502 503 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \ 504 ppdu_info, rssi_info_tlv) \ 505 { \ 506 ppdu_info->rx_status.rssi_chain[chain][0] = \ 507 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 508 RSSI_PRI20_CHAIN##chain); \ 509 ppdu_info->rx_status.rssi_chain[chain][1] = \ 510 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 511 RSSI_EXT20_CHAIN##chain); \ 512 ppdu_info->rx_status.rssi_chain[chain][2] = \ 513 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 514 RSSI_EXT40_LOW20_CHAIN##chain); \ 515 ppdu_info->rx_status.rssi_chain[chain][3] = \ 516 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 517 RSSI_EXT40_HIGH20_CHAIN##chain); \ 518 ppdu_info->rx_status.rssi_chain[chain][4] = \ 519 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 520 RSSI_EXT80_LOW20_CHAIN##chain); \ 521 ppdu_info->rx_status.rssi_chain[chain][5] = \ 522 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 523 RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \ 524 ppdu_info->rx_status.rssi_chain[chain][6] = \ 525 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 526 RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \ 527 ppdu_info->rx_status.rssi_chain[chain][7] = \ 528 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 529 RSSI_EXT80_HIGH20_CHAIN##chain); \ 530 } \ 531 532 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 533 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \ 534 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \ 535 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \ 536 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \ 537 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \ 538 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \ 539 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \ 540 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \ 541 542 static inline uint32_t 543 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 544 uint8_t *rssi_info_tlv) 545 { 546 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 547 return 0; 548 } 549 550 #ifdef WLAN_TX_PKT_CAPTURE_ENH 551 static inline void 552 hal_get_qos_control(void *rx_tlv, 553 struct hal_rx_ppdu_info *ppdu_info) 554 { 555 ppdu_info->rx_info.qos_control_info_valid = 556 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 557 QOS_CONTROL_INFO_VALID); 558 559 if (ppdu_info->rx_info.qos_control_info_valid) 560 ppdu_info->rx_info.qos_control = 561 HAL_RX_GET(rx_tlv, 562 RX_PPDU_END_USER_STATS_5, 563 QOS_CONTROL_FIELD); 564 } 565 566 static inline void 567 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 568 struct hal_rx_ppdu_info *ppdu_info) 569 { 570 if ((ppdu_info->sw_frame_group_id 571 == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) || 572 (ppdu_info->sw_frame_group_id == 573 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) { 574 ppdu_info->rx_info.mac_addr1_valid = 575 HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start); 576 577 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] = 578 HAL_RX_GET(rx_mpdu_start, 579 RX_MPDU_INFO_15, 580 MAC_ADDR_AD1_31_0); 581 if (ppdu_info->sw_frame_group_id == 582 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) { 583 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] = 584 HAL_RX_GET(rx_mpdu_start, 585 RX_MPDU_INFO_16, 586 MAC_ADDR_AD1_47_32); 587 } 588 } 589 } 590 #else 591 static inline void 592 hal_get_qos_control(void *rx_tlv, 593 struct hal_rx_ppdu_info *ppdu_info) 594 { 595 } 596 597 static inline void 598 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 599 struct hal_rx_ppdu_info *ppdu_info) 600 { 601 } 602 #endif 603 604 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS 605 static inline void 606 hal_update_frame_type_cnt(uint8_t *rx_mpdu_start, 607 struct hal_rx_ppdu_info *ppdu_info) 608 { 609 uint16_t frame_ctrl; 610 uint8_t fc_type; 611 612 if (HAL_RX_GET_FC_VALID(rx_mpdu_start)) { 613 frame_ctrl = HAL_RX_GET(rx_mpdu_start, 614 RX_MPDU_INFO_14, 615 MPDU_FRAME_CONTROL_FIELD); 616 fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl); 617 if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT) 618 ppdu_info->frm_type_info.rx_mgmt_cnt++; 619 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL) 620 ppdu_info->frm_type_info.rx_ctrl_cnt++; 621 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA) 622 ppdu_info->frm_type_info.rx_data_cnt++; 623 } 624 } 625 #else 626 static inline void 627 hal_update_frame_type_cnt(uint8_t *rx_mpdu_start, 628 struct hal_rx_ppdu_info *ppdu_info) 629 { 630 } 631 #endif 632 633 /** 634 * hal_rx_status_get_tlv_info() - process receive info TLV 635 * @rx_tlv_hdr: pointer to TLV header 636 * @ppdu_info: pointer to ppdu_info 637 * 638 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 639 */ 640 static inline uint32_t 641 hal_rx_status_get_tlv_info_generic_li(void *rx_tlv_hdr, void *ppduinfo, 642 hal_soc_handle_t hal_soc_hdl, 643 qdf_nbuf_t nbuf) 644 { 645 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 646 uint32_t tlv_tag, user_id, tlv_len, value; 647 uint8_t group_id = 0; 648 uint8_t he_dcm = 0; 649 uint8_t he_stbc = 0; 650 uint16_t he_gi = 0; 651 uint16_t he_ltf = 0; 652 void *rx_tlv; 653 bool unhandled = false; 654 struct mon_rx_user_status *mon_rx_user_status; 655 struct hal_rx_ppdu_info *ppdu_info = 656 (struct hal_rx_ppdu_info *)ppduinfo; 657 658 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 659 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 660 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 661 662 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 663 664 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 665 rx_tlv, tlv_len); 666 667 switch (tlv_tag) { 668 case WIFIRX_PPDU_START_E: 669 { 670 if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id == 671 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, PHY_PPDU_ID))) 672 hal_err("Matching ppdu_id(%u) detected", 673 ppdu_info->com_info.last_ppdu_id); 674 675 /* Reset ppdu_info before processing the ppdu */ 676 qdf_mem_zero(ppdu_info, 677 sizeof(struct hal_rx_ppdu_info)); 678 679 ppdu_info->com_info.last_ppdu_id = 680 ppdu_info->com_info.ppdu_id = 681 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 682 PHY_PPDU_ID); 683 684 /* channel number is set in PHY meta data */ 685 ppdu_info->rx_status.chan_num = 686 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 687 SW_PHY_META_DATA) & 0x0000FFFF); 688 ppdu_info->rx_status.chan_freq = 689 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 690 SW_PHY_META_DATA) & 0xFFFF0000) >> 16; 691 if (ppdu_info->rx_status.chan_num) { 692 ppdu_info->rx_status.chan_freq = 693 hal_rx_radiotap_num_to_freq( 694 ppdu_info->rx_status.chan_num, 695 ppdu_info->rx_status.chan_freq); 696 } 697 ppdu_info->com_info.ppdu_timestamp = 698 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 699 PPDU_START_TIMESTAMP); 700 ppdu_info->rx_status.ppdu_timestamp = 701 ppdu_info->com_info.ppdu_timestamp; 702 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 703 704 break; 705 } 706 707 case WIFIRX_PPDU_START_USER_INFO_E: 708 break; 709 710 case WIFIRX_PPDU_END_E: 711 dp_nofl_debug("[%s][%d] ppdu_end_e len=%d", 712 __func__, __LINE__, tlv_len); 713 /* This is followed by sub-TLVs of PPDU_END */ 714 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 715 break; 716 717 case WIFIPHYRX_PKT_END_E: 718 hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); 719 break; 720 721 case WIFIRXPCU_PPDU_END_INFO_E: 722 ppdu_info->rx_status.rx_antenna = 723 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, RX_ANTENNA); 724 ppdu_info->rx_status.tsft = 725 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 726 WB_TIMESTAMP_UPPER_32); 727 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 728 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 729 WB_TIMESTAMP_LOWER_32); 730 ppdu_info->rx_status.duration = 731 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 732 RX_PPDU_DURATION); 733 hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); 734 hal_rx_get_phyrx_abort(hal, rx_tlv, ppdu_info); 735 break; 736 737 /* 738 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 739 * for MU, based on num users we see this tlv that many times. 740 */ 741 case WIFIRX_PPDU_END_USER_STATS_E: 742 { 743 unsigned long tid = 0; 744 uint16_t seq = 0; 745 746 ppdu_info->rx_status.ast_index = 747 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 748 AST_INDEX); 749 750 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 751 RECEIVED_QOS_DATA_TID_BITMAP); 752 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, 753 sizeof(tid) * 8); 754 755 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 756 ppdu_info->rx_status.tid = HAL_TID_INVALID; 757 758 ppdu_info->rx_status.tcp_msdu_count = 759 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 760 TCP_MSDU_COUNT) + 761 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 762 TCP_ACK_MSDU_COUNT); 763 ppdu_info->rx_status.udp_msdu_count = 764 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 765 UDP_MSDU_COUNT); 766 ppdu_info->rx_status.other_msdu_count = 767 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 768 OTHER_MSDU_COUNT); 769 770 if (ppdu_info->sw_frame_group_id 771 != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 772 ppdu_info->rx_status.frame_control_info_valid = 773 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 774 FRAME_CONTROL_INFO_VALID); 775 776 if (ppdu_info->rx_status.frame_control_info_valid) 777 ppdu_info->rx_status.frame_control = 778 HAL_RX_GET(rx_tlv, 779 RX_PPDU_END_USER_STATS_4, 780 FRAME_CONTROL_FIELD); 781 782 hal_get_qos_control(rx_tlv, ppdu_info); 783 } 784 785 ppdu_info->rx_status.data_sequence_control_info_valid = 786 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 787 DATA_SEQUENCE_CONTROL_INFO_VALID); 788 789 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 790 FIRST_DATA_SEQ_CTRL); 791 if (ppdu_info->rx_status.data_sequence_control_info_valid) 792 ppdu_info->rx_status.first_data_seq_ctrl = seq; 793 794 ppdu_info->rx_status.preamble_type = 795 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 796 HT_CONTROL_FIELD_PKT_TYPE); 797 switch (ppdu_info->rx_status.preamble_type) { 798 case HAL_RX_PKT_TYPE_11N: 799 ppdu_info->rx_status.ht_flags = 1; 800 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 801 break; 802 case HAL_RX_PKT_TYPE_11AC: 803 ppdu_info->rx_status.vht_flags = 1; 804 break; 805 case HAL_RX_PKT_TYPE_11AX: 806 ppdu_info->rx_status.he_flags = 1; 807 break; 808 default: 809 break; 810 } 811 812 ppdu_info->com_info.mpdu_cnt_fcs_ok = 813 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 814 MPDU_CNT_FCS_OK); 815 ppdu_info->com_info.mpdu_cnt_fcs_err = 816 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 817 MPDU_CNT_FCS_ERR); 818 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 819 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 820 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 821 else 822 ppdu_info->rx_status.rs_flags &= 823 (~IEEE80211_AMPDU_FLAG); 824 825 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 826 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_7, 827 FCS_OK_BITMAP_31_0); 828 829 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 830 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_8, 831 FCS_OK_BITMAP_63_32); 832 833 if (user_id < HAL_MAX_UL_MU_USERS) { 834 mon_rx_user_status = 835 &ppdu_info->rx_user_status[user_id]; 836 837 hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status); 838 839 ppdu_info->com_info.num_users++; 840 841 hal_rx_populate_mu_user_info(rx_tlv, ppdu_info, 842 user_id, 843 mon_rx_user_status); 844 } 845 break; 846 } 847 848 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 849 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 850 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_1, 851 FCS_OK_BITMAP_95_64); 852 853 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 854 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_2, 855 FCS_OK_BITMAP_127_96); 856 857 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 858 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_3, 859 FCS_OK_BITMAP_159_128); 860 861 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 862 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_4, 863 FCS_OK_BITMAP_191_160); 864 865 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 866 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_5, 867 FCS_OK_BITMAP_223_192); 868 869 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 870 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_6, 871 FCS_OK_BITMAP_255_224); 872 break; 873 874 case WIFIRX_PPDU_END_STATUS_DONE_E: 875 return HAL_TLV_STATUS_PPDU_DONE; 876 877 case WIFIDUMMY_E: 878 return HAL_TLV_STATUS_BUF_DONE; 879 880 case WIFIPHYRX_HT_SIG_E: 881 { 882 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 883 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 884 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 885 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 886 FEC_CODING); 887 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 888 1 : 0; 889 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 890 HT_SIG_INFO_0, MCS); 891 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 892 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 893 HT_SIG_INFO_0, CBW); 894 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 895 HT_SIG_INFO_1, SHORT_GI); 896 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 897 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 898 HT_SIG_SU_NSS_SHIFT) + 1; 899 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 900 hal_rx_get_ht_sig_info(ppdu_info, ht_sig_info); 901 break; 902 } 903 904 case WIFIPHYRX_L_SIG_B_E: 905 { 906 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 907 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 908 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 909 910 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 911 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 912 switch (value) { 913 case 1: 914 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 915 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 916 break; 917 case 2: 918 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 919 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 920 break; 921 case 3: 922 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 923 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 924 break; 925 case 4: 926 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 927 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 928 break; 929 case 5: 930 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 931 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 932 break; 933 case 6: 934 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 935 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 936 break; 937 case 7: 938 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 939 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 940 break; 941 default: 942 break; 943 } 944 ppdu_info->rx_status.cck_flag = 1; 945 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 946 break; 947 } 948 949 case WIFIPHYRX_L_SIG_A_E: 950 { 951 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 952 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 953 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 954 955 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 956 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 957 switch (value) { 958 case 8: 959 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 960 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 961 break; 962 case 9: 963 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 964 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 965 break; 966 case 10: 967 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 968 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 969 break; 970 case 11: 971 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 972 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 973 break; 974 case 12: 975 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 976 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 977 break; 978 case 13: 979 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 980 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 981 break; 982 case 14: 983 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 984 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 985 break; 986 case 15: 987 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 988 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 989 break; 990 default: 991 break; 992 } 993 ppdu_info->rx_status.ofdm_flag = 1; 994 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 995 hal_rx_get_l_sig_a_info(ppdu_info, l_sig_a_info); 996 break; 997 } 998 999 case WIFIPHYRX_VHT_SIG_A_E: 1000 { 1001 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 1002 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 1003 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 1004 1005 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 1006 SU_MU_CODING); 1007 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 1008 1 : 0; 1009 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, 1010 GROUP_ID); 1011 ppdu_info->rx_status.vht_flag_values5 = group_id; 1012 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 1013 VHT_SIG_A_INFO_1, MCS); 1014 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 1015 VHT_SIG_A_INFO_1, GI_SETTING); 1016 1017 switch (hal->target_type) { 1018 case TARGET_TYPE_QCA8074: 1019 case TARGET_TYPE_QCA8074V2: 1020 case TARGET_TYPE_QCA6018: 1021 case TARGET_TYPE_QCA5018: 1022 case TARGET_TYPE_QCN9000: 1023 case TARGET_TYPE_QCN6122: 1024 #ifdef QCA_WIFI_QCA6390 1025 case TARGET_TYPE_QCA6390: 1026 #endif 1027 case TARGET_TYPE_QCA6490: 1028 ppdu_info->rx_status.is_stbc = 1029 HAL_RX_GET(vht_sig_a_info, 1030 VHT_SIG_A_INFO_0, STBC); 1031 value = HAL_RX_GET(vht_sig_a_info, 1032 VHT_SIG_A_INFO_0, N_STS); 1033 value = value & VHT_SIG_SU_NSS_MASK; 1034 if (ppdu_info->rx_status.is_stbc && (value > 0)) 1035 value = ((value + 1) >> 1) - 1; 1036 ppdu_info->rx_status.nss = 1037 ((value & VHT_SIG_SU_NSS_MASK) + 1); 1038 1039 break; 1040 case TARGET_TYPE_QCA6290: 1041 #if !defined(QCA_WIFI_QCA6290_11AX) 1042 ppdu_info->rx_status.is_stbc = 1043 HAL_RX_GET(vht_sig_a_info, 1044 VHT_SIG_A_INFO_0, STBC); 1045 value = HAL_RX_GET(vht_sig_a_info, 1046 VHT_SIG_A_INFO_0, N_STS); 1047 value = value & VHT_SIG_SU_NSS_MASK; 1048 if (ppdu_info->rx_status.is_stbc && (value > 0)) 1049 value = ((value + 1) >> 1) - 1; 1050 ppdu_info->rx_status.nss = 1051 ((value & VHT_SIG_SU_NSS_MASK) + 1); 1052 #else 1053 ppdu_info->rx_status.nss = 0; 1054 #endif 1055 break; 1056 case TARGET_TYPE_QCA6750: 1057 ppdu_info->rx_status.nss = 0; 1058 break; 1059 default: 1060 break; 1061 } 1062 ppdu_info->rx_status.vht_flag_values3[0] = 1063 (((ppdu_info->rx_status.mcs) << 4) 1064 | ppdu_info->rx_status.nss); 1065 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 1066 VHT_SIG_A_INFO_0, BANDWIDTH); 1067 ppdu_info->rx_status.vht_flag_values2 = 1068 ppdu_info->rx_status.bw; 1069 ppdu_info->rx_status.vht_flag_values4 = 1070 HAL_RX_GET(vht_sig_a_info, 1071 VHT_SIG_A_INFO_1, SU_MU_CODING); 1072 1073 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 1074 VHT_SIG_A_INFO_1, BEAMFORMED); 1075 if (group_id == 0 || group_id == 63) 1076 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1077 else 1078 ppdu_info->rx_status.reception_type = 1079 HAL_RX_TYPE_MU_MIMO; 1080 1081 hal_rx_get_vht_sig_a_info(ppdu_info, vht_sig_a_info); 1082 break; 1083 } 1084 case WIFIPHYRX_HE_SIG_A_SU_E: 1085 { 1086 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 1087 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 1088 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 1089 ppdu_info->rx_status.he_flags = 1; 1090 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 1091 FORMAT_INDICATION); 1092 if (value == 0) { 1093 ppdu_info->rx_status.he_data1 = 1094 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1095 } else { 1096 ppdu_info->rx_status.he_data1 = 1097 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 1098 } 1099 1100 /* data1 */ 1101 ppdu_info->rx_status.he_data1 |= 1102 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 1103 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 1104 QDF_MON_STATUS_HE_DL_UL_KNOWN | 1105 QDF_MON_STATUS_HE_MCS_KNOWN | 1106 QDF_MON_STATUS_HE_DCM_KNOWN | 1107 QDF_MON_STATUS_HE_CODING_KNOWN | 1108 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 1109 QDF_MON_STATUS_HE_STBC_KNOWN | 1110 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 1111 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 1112 1113 /* data2 */ 1114 ppdu_info->rx_status.he_data2 = 1115 QDF_MON_STATUS_HE_GI_KNOWN; 1116 ppdu_info->rx_status.he_data2 |= 1117 QDF_MON_STATUS_TXBF_KNOWN | 1118 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1119 QDF_MON_STATUS_TXOP_KNOWN | 1120 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1121 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1122 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1123 1124 /* data3 */ 1125 value = HAL_RX_GET(he_sig_a_su_info, 1126 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 1127 ppdu_info->rx_status.he_data3 = value; 1128 value = HAL_RX_GET(he_sig_a_su_info, 1129 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 1130 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 1131 ppdu_info->rx_status.he_data3 |= value; 1132 value = HAL_RX_GET(he_sig_a_su_info, 1133 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 1134 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1135 ppdu_info->rx_status.he_data3 |= value; 1136 1137 value = HAL_RX_GET(he_sig_a_su_info, 1138 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 1139 ppdu_info->rx_status.mcs = value; 1140 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1141 ppdu_info->rx_status.he_data3 |= value; 1142 1143 value = HAL_RX_GET(he_sig_a_su_info, 1144 HE_SIG_A_SU_INFO_0, DCM); 1145 he_dcm = value; 1146 value = value << QDF_MON_STATUS_DCM_SHIFT; 1147 ppdu_info->rx_status.he_data3 |= value; 1148 value = HAL_RX_GET(he_sig_a_su_info, 1149 HE_SIG_A_SU_INFO_1, CODING); 1150 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 1151 1 : 0; 1152 value = value << QDF_MON_STATUS_CODING_SHIFT; 1153 ppdu_info->rx_status.he_data3 |= value; 1154 value = HAL_RX_GET(he_sig_a_su_info, 1155 HE_SIG_A_SU_INFO_1, 1156 LDPC_EXTRA_SYMBOL); 1157 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1158 ppdu_info->rx_status.he_data3 |= value; 1159 value = HAL_RX_GET(he_sig_a_su_info, 1160 HE_SIG_A_SU_INFO_1, STBC); 1161 he_stbc = value; 1162 value = value << QDF_MON_STATUS_STBC_SHIFT; 1163 ppdu_info->rx_status.he_data3 |= value; 1164 1165 /* data4 */ 1166 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 1167 SPATIAL_REUSE); 1168 ppdu_info->rx_status.he_data4 = value; 1169 1170 /* data5 */ 1171 value = HAL_RX_GET(he_sig_a_su_info, 1172 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 1173 ppdu_info->rx_status.he_data5 = value; 1174 ppdu_info->rx_status.bw = value; 1175 value = HAL_RX_GET(he_sig_a_su_info, 1176 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 1177 switch (value) { 1178 case 0: 1179 he_gi = HE_GI_0_8; 1180 he_ltf = HE_LTF_1_X; 1181 break; 1182 case 1: 1183 he_gi = HE_GI_0_8; 1184 he_ltf = HE_LTF_2_X; 1185 break; 1186 case 2: 1187 he_gi = HE_GI_1_6; 1188 he_ltf = HE_LTF_2_X; 1189 break; 1190 case 3: 1191 if (he_dcm && he_stbc) { 1192 he_gi = HE_GI_0_8; 1193 he_ltf = HE_LTF_4_X; 1194 } else { 1195 he_gi = HE_GI_3_2; 1196 he_ltf = HE_LTF_4_X; 1197 } 1198 break; 1199 } 1200 ppdu_info->rx_status.sgi = he_gi; 1201 ppdu_info->rx_status.ltf_size = he_ltf; 1202 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 1203 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1204 ppdu_info->rx_status.he_data5 |= value; 1205 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1206 ppdu_info->rx_status.he_data5 |= value; 1207 1208 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 1209 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1210 ppdu_info->rx_status.he_data5 |= value; 1211 1212 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1213 PACKET_EXTENSION_A_FACTOR); 1214 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1215 ppdu_info->rx_status.he_data5 |= value; 1216 1217 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 1218 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1219 ppdu_info->rx_status.he_data5 |= value; 1220 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1221 PACKET_EXTENSION_PE_DISAMBIGUITY); 1222 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1223 ppdu_info->rx_status.he_data5 |= value; 1224 1225 /* data6 */ 1226 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 1227 value++; 1228 ppdu_info->rx_status.nss = value; 1229 ppdu_info->rx_status.he_data6 = value; 1230 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1231 DOPPLER_INDICATION); 1232 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1233 ppdu_info->rx_status.he_data6 |= value; 1234 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1235 TXOP_DURATION); 1236 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1237 ppdu_info->rx_status.he_data6 |= value; 1238 1239 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 1240 HE_SIG_A_SU_INFO_1, TXBF); 1241 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1242 hal_rx_get_crc_he_sig_a_su_info(ppdu_info, he_sig_a_su_info); 1243 break; 1244 } 1245 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 1246 { 1247 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 1248 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 1249 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 1250 1251 ppdu_info->rx_status.he_mu_flags = 1; 1252 1253 /* HE Flags */ 1254 /*data1*/ 1255 ppdu_info->rx_status.he_data1 = 1256 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1257 ppdu_info->rx_status.he_data1 |= 1258 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 1259 QDF_MON_STATUS_HE_DL_UL_KNOWN | 1260 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 1261 QDF_MON_STATUS_HE_STBC_KNOWN | 1262 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 1263 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 1264 1265 /* data2 */ 1266 ppdu_info->rx_status.he_data2 = 1267 QDF_MON_STATUS_HE_GI_KNOWN; 1268 ppdu_info->rx_status.he_data2 |= 1269 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1270 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1271 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1272 QDF_MON_STATUS_TXOP_KNOWN | 1273 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1274 1275 /*data3*/ 1276 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1277 HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); 1278 ppdu_info->rx_status.he_data3 = value; 1279 1280 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1281 HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); 1282 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1283 ppdu_info->rx_status.he_data3 |= value; 1284 1285 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1286 HE_SIG_A_MU_DL_INFO_1, 1287 LDPC_EXTRA_SYMBOL); 1288 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1289 ppdu_info->rx_status.he_data3 |= value; 1290 1291 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1292 HE_SIG_A_MU_DL_INFO_1, STBC); 1293 he_stbc = value; 1294 value = value << QDF_MON_STATUS_STBC_SHIFT; 1295 ppdu_info->rx_status.he_data3 |= value; 1296 1297 /*data4*/ 1298 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1299 SPATIAL_REUSE); 1300 ppdu_info->rx_status.he_data4 = value; 1301 1302 /*data5*/ 1303 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1304 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1305 ppdu_info->rx_status.he_data5 = value; 1306 ppdu_info->rx_status.bw = value; 1307 1308 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1309 HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); 1310 switch (value) { 1311 case 0: 1312 he_gi = HE_GI_0_8; 1313 he_ltf = HE_LTF_4_X; 1314 break; 1315 case 1: 1316 he_gi = HE_GI_0_8; 1317 he_ltf = HE_LTF_2_X; 1318 break; 1319 case 2: 1320 he_gi = HE_GI_1_6; 1321 he_ltf = HE_LTF_2_X; 1322 break; 1323 case 3: 1324 he_gi = HE_GI_3_2; 1325 he_ltf = HE_LTF_4_X; 1326 break; 1327 } 1328 ppdu_info->rx_status.sgi = he_gi; 1329 ppdu_info->rx_status.ltf_size = he_ltf; 1330 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 1331 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1332 ppdu_info->rx_status.he_data5 |= value; 1333 1334 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1335 ppdu_info->rx_status.he_data5 |= value; 1336 1337 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1338 HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); 1339 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1340 ppdu_info->rx_status.he_data5 |= value; 1341 1342 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1343 PACKET_EXTENSION_A_FACTOR); 1344 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1345 ppdu_info->rx_status.he_data5 |= value; 1346 1347 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1348 PACKET_EXTENSION_PE_DISAMBIGUITY); 1349 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1350 ppdu_info->rx_status.he_data5 |= value; 1351 1352 /*data6*/ 1353 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1354 DOPPLER_INDICATION); 1355 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1356 ppdu_info->rx_status.he_data6 |= value; 1357 1358 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1359 TXOP_DURATION); 1360 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1361 ppdu_info->rx_status.he_data6 |= value; 1362 1363 /* HE-MU Flags */ 1364 /* HE-MU-flags1 */ 1365 ppdu_info->rx_status.he_flags1 = 1366 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1367 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1368 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 1369 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 1370 QDF_MON_STATUS_RU_0_KNOWN; 1371 1372 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1373 HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); 1374 ppdu_info->rx_status.he_flags1 |= value; 1375 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1376 HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); 1377 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 1378 ppdu_info->rx_status.he_flags1 |= value; 1379 1380 /* HE-MU-flags2 */ 1381 ppdu_info->rx_status.he_flags2 = 1382 QDF_MON_STATUS_BW_KNOWN; 1383 1384 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1385 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1386 ppdu_info->rx_status.he_flags2 |= value; 1387 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1388 HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); 1389 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1390 ppdu_info->rx_status.he_flags2 |= value; 1391 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1392 HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); 1393 value = value - 1; 1394 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 1395 ppdu_info->rx_status.he_flags2 |= value; 1396 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1397 hal_rx_get_crc_he_sig_a_mu_dl_info(ppdu_info, 1398 he_sig_a_mu_dl_info); 1399 break; 1400 } 1401 case WIFIPHYRX_HE_SIG_B1_MU_E: 1402 { 1403 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 1404 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 1405 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 1406 1407 ppdu_info->rx_status.he_sig_b_common_known |= 1408 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 1409 /* TODO: Check on the availability of other fields in 1410 * sig_b_common 1411 */ 1412 1413 value = HAL_RX_GET(he_sig_b1_mu_info, 1414 HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); 1415 ppdu_info->rx_status.he_RU[0] = value; 1416 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1417 break; 1418 } 1419 case WIFIPHYRX_HE_SIG_B2_MU_E: 1420 { 1421 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 1422 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 1423 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 1424 /* 1425 * Not all "HE" fields can be updated from 1426 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1427 * to populate rest of the "HE" fields for MU scenarios. 1428 */ 1429 1430 /* HE-data1 */ 1431 ppdu_info->rx_status.he_data1 |= 1432 QDF_MON_STATUS_HE_MCS_KNOWN | 1433 QDF_MON_STATUS_HE_CODING_KNOWN; 1434 1435 /* HE-data2 */ 1436 1437 /* HE-data3 */ 1438 value = HAL_RX_GET(he_sig_b2_mu_info, 1439 HE_SIG_B2_MU_INFO_0, STA_MCS); 1440 ppdu_info->rx_status.mcs = value; 1441 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1442 ppdu_info->rx_status.he_data3 |= value; 1443 1444 value = HAL_RX_GET(he_sig_b2_mu_info, 1445 HE_SIG_B2_MU_INFO_0, STA_CODING); 1446 value = value << QDF_MON_STATUS_CODING_SHIFT; 1447 ppdu_info->rx_status.he_data3 |= value; 1448 1449 /* HE-data4 */ 1450 value = HAL_RX_GET(he_sig_b2_mu_info, 1451 HE_SIG_B2_MU_INFO_0, STA_ID); 1452 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1453 ppdu_info->rx_status.he_data4 |= value; 1454 1455 /* HE-data5 */ 1456 1457 /* HE-data6 */ 1458 value = HAL_RX_GET(he_sig_b2_mu_info, 1459 HE_SIG_B2_MU_INFO_0, NSTS); 1460 /* value n indicates n+1 spatial streams */ 1461 value++; 1462 ppdu_info->rx_status.nss = value; 1463 ppdu_info->rx_status.he_data6 |= value; 1464 1465 break; 1466 } 1467 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 1468 { 1469 uint8_t *he_sig_b2_ofdma_info = 1470 (uint8_t *)rx_tlv + 1471 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 1472 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 1473 1474 /* 1475 * Not all "HE" fields can be updated from 1476 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1477 * to populate rest of "HE" fields for MU OFDMA scenarios. 1478 */ 1479 1480 /* HE-data1 */ 1481 ppdu_info->rx_status.he_data1 |= 1482 QDF_MON_STATUS_HE_MCS_KNOWN | 1483 QDF_MON_STATUS_HE_DCM_KNOWN | 1484 QDF_MON_STATUS_HE_CODING_KNOWN; 1485 1486 /* HE-data2 */ 1487 ppdu_info->rx_status.he_data2 |= 1488 QDF_MON_STATUS_TXBF_KNOWN; 1489 1490 /* HE-data3 */ 1491 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1492 HE_SIG_B2_OFDMA_INFO_0, STA_MCS); 1493 ppdu_info->rx_status.mcs = value; 1494 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1495 ppdu_info->rx_status.he_data3 |= value; 1496 1497 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1498 HE_SIG_B2_OFDMA_INFO_0, STA_DCM); 1499 he_dcm = value; 1500 value = value << QDF_MON_STATUS_DCM_SHIFT; 1501 ppdu_info->rx_status.he_data3 |= value; 1502 1503 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1504 HE_SIG_B2_OFDMA_INFO_0, STA_CODING); 1505 value = value << QDF_MON_STATUS_CODING_SHIFT; 1506 ppdu_info->rx_status.he_data3 |= value; 1507 1508 /* HE-data4 */ 1509 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1510 HE_SIG_B2_OFDMA_INFO_0, STA_ID); 1511 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1512 ppdu_info->rx_status.he_data4 |= value; 1513 1514 /* HE-data5 */ 1515 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1516 HE_SIG_B2_OFDMA_INFO_0, TXBF); 1517 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1518 ppdu_info->rx_status.he_data5 |= value; 1519 1520 /* HE-data6 */ 1521 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1522 HE_SIG_B2_OFDMA_INFO_0, NSTS); 1523 /* value n indicates n+1 spatial streams */ 1524 value++; 1525 ppdu_info->rx_status.nss = value; 1526 ppdu_info->rx_status.he_data6 |= value; 1527 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1528 break; 1529 } 1530 case WIFIPHYRX_RSSI_LEGACY_E: 1531 { 1532 uint8_t reception_type; 1533 int8_t rssi_value; 1534 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 1535 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 1536 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 1537 1538 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 1539 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 1540 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 1541 ppdu_info->rx_status.he_re = 0; 1542 1543 reception_type = HAL_RX_GET(rx_tlv, 1544 PHYRX_RSSI_LEGACY_0, 1545 RECEPTION_TYPE); 1546 switch (reception_type) { 1547 case QDF_RECEPTION_TYPE_ULOFMDA: 1548 ppdu_info->rx_status.reception_type = 1549 HAL_RX_TYPE_MU_OFDMA; 1550 ppdu_info->rx_status.ulofdma_flag = 1; 1551 ppdu_info->rx_status.he_data1 = 1552 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1553 break; 1554 case QDF_RECEPTION_TYPE_ULMIMO: 1555 ppdu_info->rx_status.reception_type = 1556 HAL_RX_TYPE_MU_MIMO; 1557 ppdu_info->rx_status.he_data1 = 1558 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1559 break; 1560 default: 1561 ppdu_info->rx_status.reception_type = 1562 HAL_RX_TYPE_SU; 1563 break; 1564 } 1565 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 1566 rssi_value = HAL_RX_GET(rssi_info_tlv, 1567 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 1568 ppdu_info->rx_status.rssi[0] = rssi_value; 1569 dp_nofl_debug("RSSI_PRI20_CHAIN0: %d\n", rssi_value); 1570 1571 rssi_value = HAL_RX_GET(rssi_info_tlv, 1572 RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1); 1573 ppdu_info->rx_status.rssi[1] = rssi_value; 1574 dp_nofl_debug("RSSI_PRI20_CHAIN1: %d\n", rssi_value); 1575 1576 rssi_value = HAL_RX_GET(rssi_info_tlv, 1577 RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2); 1578 ppdu_info->rx_status.rssi[2] = rssi_value; 1579 dp_nofl_debug("RSSI_PRI20_CHAIN2: %d\n", rssi_value); 1580 1581 rssi_value = HAL_RX_GET(rssi_info_tlv, 1582 RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3); 1583 ppdu_info->rx_status.rssi[3] = rssi_value; 1584 dp_nofl_debug("RSSI_PRI20_CHAIN3: %d\n", rssi_value); 1585 1586 rssi_value = HAL_RX_GET(rssi_info_tlv, 1587 RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4); 1588 ppdu_info->rx_status.rssi[4] = rssi_value; 1589 dp_nofl_debug("RSSI_PRI20_CHAIN4: %d\n", rssi_value); 1590 1591 rssi_value = HAL_RX_GET(rssi_info_tlv, 1592 RECEIVE_RSSI_INFO_10, 1593 RSSI_PRI20_CHAIN5); 1594 ppdu_info->rx_status.rssi[5] = rssi_value; 1595 dp_nofl_debug("RSSI_PRI20_CHAIN5: %d\n", rssi_value); 1596 1597 rssi_value = HAL_RX_GET(rssi_info_tlv, 1598 RECEIVE_RSSI_INFO_12, 1599 RSSI_PRI20_CHAIN6); 1600 ppdu_info->rx_status.rssi[6] = rssi_value; 1601 dp_nofl_debug("RSSI_PRI20_CHAIN6: %d\n", rssi_value); 1602 1603 rssi_value = HAL_RX_GET(rssi_info_tlv, 1604 RECEIVE_RSSI_INFO_14, 1605 RSSI_PRI20_CHAIN7); 1606 ppdu_info->rx_status.rssi[7] = rssi_value; 1607 dp_nofl_debug("RSSI_PRI20_CHAIN7: %d\n", rssi_value); 1608 break; 1609 } 1610 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1611 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1612 ppdu_info); 1613 break; 1614 case WIFIRX_HEADER_E: 1615 { 1616 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 1617 1618 if (ppdu_info->fcs_ok_cnt >= 1619 HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) { 1620 hal_err("Number of MPDUs(%d) per status buff exceeded", 1621 ppdu_info->fcs_ok_cnt); 1622 break; 1623 } 1624 1625 /* Update first_msdu_payload for every mpdu and increment 1626 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 1627 */ 1628 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload = 1629 rx_tlv; 1630 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len; 1631 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1632 ppdu_info->msdu_info.payload_len = tlv_len; 1633 ppdu_info->user_id = user_id; 1634 ppdu_info->hdr_len = tlv_len; 1635 ppdu_info->data = rx_tlv; 1636 ppdu_info->data += 4; 1637 1638 /* for every RX_HEADER TLV increment mpdu_cnt */ 1639 com_info->mpdu_cnt++; 1640 return HAL_TLV_STATUS_HEADER; 1641 } 1642 case WIFIRX_MPDU_START_E: 1643 { 1644 uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv; 1645 uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_mpdu_start); 1646 uint8_t filter_category = 0; 1647 1648 hal_update_frame_type_cnt(rx_mpdu_start, ppdu_info); 1649 1650 ppdu_info->nac_info.fc_valid = 1651 HAL_RX_GET_FC_VALID(rx_mpdu_start); 1652 1653 ppdu_info->nac_info.to_ds_flag = 1654 HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start); 1655 1656 ppdu_info->nac_info.frame_control = 1657 HAL_RX_GET(rx_mpdu_start, 1658 RX_MPDU_INFO_14, 1659 MPDU_FRAME_CONTROL_FIELD); 1660 1661 ppdu_info->sw_frame_group_id = 1662 HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start); 1663 1664 ppdu_info->rx_user_status[user_id].sw_peer_id = 1665 HAL_RX_GET_SW_PEER_ID(rx_mpdu_start); 1666 1667 if (ppdu_info->sw_frame_group_id == 1668 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 1669 ppdu_info->rx_status.frame_control_info_valid = 1670 ppdu_info->nac_info.fc_valid; 1671 ppdu_info->rx_status.frame_control = 1672 ppdu_info->nac_info.frame_control; 1673 } 1674 1675 hal_get_mac_addr1(rx_mpdu_start, 1676 ppdu_info); 1677 1678 ppdu_info->nac_info.mac_addr2_valid = 1679 HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start); 1680 1681 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1682 HAL_RX_GET(rx_mpdu_start, 1683 RX_MPDU_INFO_16, 1684 MAC_ADDR_AD2_15_0); 1685 1686 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1687 HAL_RX_GET(rx_mpdu_start, 1688 RX_MPDU_INFO_17, 1689 MAC_ADDR_AD2_47_16); 1690 1691 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1692 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1693 ppdu_info->rx_status.ppdu_len = 1694 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1695 MPDU_LENGTH); 1696 } else { 1697 ppdu_info->rx_status.ppdu_len += 1698 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1699 MPDU_LENGTH); 1700 } 1701 1702 filter_category = 1703 HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start); 1704 1705 if (filter_category == 0) 1706 ppdu_info->rx_status.rxpcu_filter_pass = 1; 1707 else if (filter_category == 1) 1708 ppdu_info->rx_status.monitor_direct_used = 1; 1709 1710 ppdu_info->nac_info.mcast_bcast = 1711 HAL_RX_GET(rx_mpdu_start, 1712 RX_MPDU_INFO_13, 1713 MCAST_BCAST); 1714 break; 1715 } 1716 case WIFIRX_MPDU_END_E: 1717 ppdu_info->user_id = user_id; 1718 ppdu_info->fcs_err = 1719 HAL_RX_GET(rx_tlv, RX_MPDU_END_1, 1720 FCS_ERR); 1721 return HAL_TLV_STATUS_MPDU_END; 1722 case WIFIRX_MSDU_END_E: 1723 if (user_id < HAL_MAX_UL_MU_USERS) { 1724 ppdu_info->rx_msdu_info[user_id].cce_metadata = 1725 HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv); 1726 ppdu_info->rx_msdu_info[user_id].fse_metadata = 1727 HAL_RX_MSDU_END_FSE_METADATA_GET(rx_tlv); 1728 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 1729 HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(rx_tlv); 1730 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 1731 HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(rx_tlv); 1732 ppdu_info->rx_msdu_info[user_id].flow_idx = 1733 HAL_RX_MSDU_END_FLOW_IDX_GET(rx_tlv); 1734 } 1735 return HAL_TLV_STATUS_MSDU_END; 1736 case 0: 1737 return HAL_TLV_STATUS_PPDU_DONE; 1738 1739 default: 1740 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1741 unhandled = false; 1742 else 1743 unhandled = true; 1744 break; 1745 } 1746 1747 if (!unhandled) 1748 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1749 "%s TLV type: %d, TLV len:%d %s", 1750 __func__, tlv_tag, tlv_len, 1751 unhandled == true ? "unhandled" : ""); 1752 1753 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1754 rx_tlv, tlv_len); 1755 1756 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1757 } 1758 1759 /** 1760 * hal_tx_comp_get_release_reason_generic_li() - TQM Release reason 1761 * @hal_desc: completion ring descriptor pointer 1762 * 1763 * This function will return the type of pointer - buffer or descriptor 1764 * 1765 * Return: buffer type 1766 */ 1767 static inline uint8_t hal_tx_comp_get_release_reason_generic_li(void *hal_desc) 1768 { 1769 uint32_t comp_desc = 1770 *(uint32_t *)(((uint8_t *)hal_desc) + 1771 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 1772 1773 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 1774 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 1775 } 1776 1777 /** 1778 * hal_get_wbm_internal_error_generic_li() - is WBM internal error 1779 * @hal_desc: completion ring descriptor pointer 1780 * 1781 * This function will return 0 or 1 - is it WBM internal error or not 1782 * 1783 * Return: uint8_t 1784 */ 1785 static inline uint8_t hal_get_wbm_internal_error_generic_li(void *hal_desc) 1786 { 1787 uint32_t comp_desc = 1788 *(uint32_t *)(((uint8_t *)hal_desc) + 1789 HAL_WBM_INTERNAL_ERROR_OFFSET); 1790 1791 return (comp_desc & HAL_WBM_INTERNAL_ERROR_MASK) >> 1792 HAL_WBM_INTERNAL_ERROR_LSB; 1793 } 1794 1795 /** 1796 * hal_rx_dump_mpdu_start_tlv_generic_li: dump RX mpdu_start TLV in structured 1797 * human readable format. 1798 * @mpdu_start: pointer the rx_attention TLV in pkt. 1799 * @dbg_level: log level. 1800 * 1801 * Return: void 1802 */ 1803 static inline void hal_rx_dump_mpdu_start_tlv_generic_li(void *mpdustart, 1804 uint8_t dbg_level) 1805 { 1806 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 1807 struct rx_mpdu_info *mpdu_info = 1808 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 1809 1810 hal_verbose_debug( 1811 "rx_mpdu_start tlv (1/5) - " 1812 "rxpcu_mpdu_filter_in_category: %x " 1813 "sw_frame_group_id: %x " 1814 "ndp_frame: %x " 1815 "phy_err: %x " 1816 "phy_err_during_mpdu_header: %x " 1817 "protocol_version_err: %x " 1818 "ast_based_lookup_valid: %x " 1819 "phy_ppdu_id: %x " 1820 "ast_index: %x " 1821 "sw_peer_id: %x " 1822 "mpdu_frame_control_valid: %x " 1823 "mpdu_duration_valid: %x " 1824 "mac_addr_ad1_valid: %x " 1825 "mac_addr_ad2_valid: %x " 1826 "mac_addr_ad3_valid: %x " 1827 "mac_addr_ad4_valid: %x " 1828 "mpdu_sequence_control_valid: %x " 1829 "mpdu_qos_control_valid: %x " 1830 "mpdu_ht_control_valid: %x " 1831 "frame_encryption_info_valid: %x ", 1832 mpdu_info->rxpcu_mpdu_filter_in_category, 1833 mpdu_info->sw_frame_group_id, 1834 mpdu_info->ndp_frame, 1835 mpdu_info->phy_err, 1836 mpdu_info->phy_err_during_mpdu_header, 1837 mpdu_info->protocol_version_err, 1838 mpdu_info->ast_based_lookup_valid, 1839 mpdu_info->phy_ppdu_id, 1840 mpdu_info->ast_index, 1841 mpdu_info->sw_peer_id, 1842 mpdu_info->mpdu_frame_control_valid, 1843 mpdu_info->mpdu_duration_valid, 1844 mpdu_info->mac_addr_ad1_valid, 1845 mpdu_info->mac_addr_ad2_valid, 1846 mpdu_info->mac_addr_ad3_valid, 1847 mpdu_info->mac_addr_ad4_valid, 1848 mpdu_info->mpdu_sequence_control_valid, 1849 mpdu_info->mpdu_qos_control_valid, 1850 mpdu_info->mpdu_ht_control_valid, 1851 mpdu_info->frame_encryption_info_valid); 1852 1853 hal_verbose_debug( 1854 "rx_mpdu_start tlv (2/5) - " 1855 "fr_ds: %x " 1856 "to_ds: %x " 1857 "encrypted: %x " 1858 "mpdu_retry: %x " 1859 "mpdu_sequence_number: %x " 1860 "epd_en: %x " 1861 "all_frames_shall_be_encrypted: %x " 1862 "encrypt_type: %x " 1863 "mesh_sta: %x " 1864 "bssid_hit: %x " 1865 "bssid_number: %x " 1866 "tid: %x " 1867 "pn_31_0: %x " 1868 "pn_63_32: %x " 1869 "pn_95_64: %x " 1870 "pn_127_96: %x " 1871 "peer_meta_data: %x " 1872 "rxpt_classify_info.reo_destination_indication: %x " 1873 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x " 1874 "rx_reo_queue_desc_addr_31_0: %x ", 1875 mpdu_info->fr_ds, 1876 mpdu_info->to_ds, 1877 mpdu_info->encrypted, 1878 mpdu_info->mpdu_retry, 1879 mpdu_info->mpdu_sequence_number, 1880 mpdu_info->epd_en, 1881 mpdu_info->all_frames_shall_be_encrypted, 1882 mpdu_info->encrypt_type, 1883 mpdu_info->mesh_sta, 1884 mpdu_info->bssid_hit, 1885 mpdu_info->bssid_number, 1886 mpdu_info->tid, 1887 mpdu_info->pn_31_0, 1888 mpdu_info->pn_63_32, 1889 mpdu_info->pn_95_64, 1890 mpdu_info->pn_127_96, 1891 mpdu_info->peer_meta_data, 1892 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 1893 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 1894 mpdu_info->rx_reo_queue_desc_addr_31_0); 1895 1896 hal_verbose_debug( 1897 "rx_mpdu_start tlv (3/5) - " 1898 "rx_reo_queue_desc_addr_39_32: %x " 1899 "receive_queue_number: %x " 1900 "pre_delim_err_warning: %x " 1901 "first_delim_err: %x " 1902 "key_id_octet: %x " 1903 "new_peer_entry: %x " 1904 "decrypt_needed: %x " 1905 "decap_type: %x " 1906 "rx_insert_vlan_c_tag_padding: %x " 1907 "rx_insert_vlan_s_tag_padding: %x " 1908 "strip_vlan_c_tag_decap: %x " 1909 "strip_vlan_s_tag_decap: %x " 1910 "pre_delim_count: %x " 1911 "ampdu_flag: %x " 1912 "bar_frame: %x " 1913 "mpdu_length: %x " 1914 "first_mpdu: %x " 1915 "mcast_bcast: %x " 1916 "ast_index_not_found: %x " 1917 "ast_index_timeout: %x ", 1918 mpdu_info->rx_reo_queue_desc_addr_39_32, 1919 mpdu_info->receive_queue_number, 1920 mpdu_info->pre_delim_err_warning, 1921 mpdu_info->first_delim_err, 1922 mpdu_info->key_id_octet, 1923 mpdu_info->new_peer_entry, 1924 mpdu_info->decrypt_needed, 1925 mpdu_info->decap_type, 1926 mpdu_info->rx_insert_vlan_c_tag_padding, 1927 mpdu_info->rx_insert_vlan_s_tag_padding, 1928 mpdu_info->strip_vlan_c_tag_decap, 1929 mpdu_info->strip_vlan_s_tag_decap, 1930 mpdu_info->pre_delim_count, 1931 mpdu_info->ampdu_flag, 1932 mpdu_info->bar_frame, 1933 mpdu_info->mpdu_length, 1934 mpdu_info->first_mpdu, 1935 mpdu_info->mcast_bcast, 1936 mpdu_info->ast_index_not_found, 1937 mpdu_info->ast_index_timeout); 1938 1939 hal_verbose_debug( 1940 "rx_mpdu_start tlv (4/5) - " 1941 "power_mgmt: %x " 1942 "non_qos: %x " 1943 "null_data: %x " 1944 "mgmt_type: %x " 1945 "ctrl_type: %x " 1946 "more_data: %x " 1947 "eosp: %x " 1948 "fragment_flag: %x " 1949 "order: %x " 1950 "u_apsd_trigger: %x " 1951 "encrypt_required: %x " 1952 "directed: %x " 1953 "mpdu_frame_control_field: %x " 1954 "mpdu_duration_field: %x " 1955 "mac_addr_ad1_31_0: %x " 1956 "mac_addr_ad1_47_32: %x " 1957 "mac_addr_ad2_15_0: %x " 1958 "mac_addr_ad2_47_16: %x " 1959 "mac_addr_ad3_31_0: %x " 1960 "mac_addr_ad3_47_32: %x ", 1961 mpdu_info->power_mgmt, 1962 mpdu_info->non_qos, 1963 mpdu_info->null_data, 1964 mpdu_info->mgmt_type, 1965 mpdu_info->ctrl_type, 1966 mpdu_info->more_data, 1967 mpdu_info->eosp, 1968 mpdu_info->fragment_flag, 1969 mpdu_info->order, 1970 mpdu_info->u_apsd_trigger, 1971 mpdu_info->encrypt_required, 1972 mpdu_info->directed, 1973 mpdu_info->mpdu_frame_control_field, 1974 mpdu_info->mpdu_duration_field, 1975 mpdu_info->mac_addr_ad1_31_0, 1976 mpdu_info->mac_addr_ad1_47_32, 1977 mpdu_info->mac_addr_ad2_15_0, 1978 mpdu_info->mac_addr_ad2_47_16, 1979 mpdu_info->mac_addr_ad3_31_0, 1980 mpdu_info->mac_addr_ad3_47_32); 1981 1982 hal_verbose_debug( 1983 "rx_mpdu_start tlv (5/5) - " 1984 "mpdu_sequence_control_field: %x " 1985 "mac_addr_ad4_31_0: %x " 1986 "mac_addr_ad4_47_32: %x " 1987 "mpdu_qos_control_field: %x " 1988 "mpdu_ht_control_field: %x ", 1989 mpdu_info->mpdu_sequence_control_field, 1990 mpdu_info->mac_addr_ad4_31_0, 1991 mpdu_info->mac_addr_ad4_47_32, 1992 mpdu_info->mpdu_qos_control_field, 1993 mpdu_info->mpdu_ht_control_field); 1994 } 1995 1996 /** 1997 * hal_tx_set_pcp_tid_map_generic_li() - Configure default PCP to TID map table 1998 * @soc: HAL SoC context 1999 * @map: PCP-TID mapping table 2000 * 2001 * PCP are mapped to 8 TID values using TID values programmed 2002 * in one set of mapping registers PCP_TID_MAP_<0 to 6> 2003 * The mapping register has TID mapping for 8 PCP values 2004 * 2005 * Return: none 2006 */ 2007 static void hal_tx_set_pcp_tid_map_generic_li(struct hal_soc *soc, uint8_t *map) 2008 { 2009 uint32_t addr, value; 2010 2011 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2012 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2013 2014 value = (map[0] | 2015 (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | 2016 (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | 2017 (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | 2018 (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | 2019 (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | 2020 (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | 2021 (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); 2022 2023 HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2024 } 2025 2026 /** 2027 * hal_tx_update_pcp_tid_generic_li() - Update the pcp tid map table with 2028 * value received from user-space 2029 * @soc: HAL SoC context 2030 * @pcp: pcp value 2031 * @tid : tid value 2032 * 2033 * Return: void 2034 */ 2035 static void 2036 hal_tx_update_pcp_tid_generic_li(struct hal_soc *soc, 2037 uint8_t pcp, uint8_t tid) 2038 { 2039 uint32_t addr, value, regval; 2040 2041 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2042 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2043 2044 value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); 2045 2046 /* Read back previous PCP TID config and update 2047 * with new config. 2048 */ 2049 regval = HAL_REG_READ(soc, addr); 2050 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); 2051 regval |= value; 2052 2053 HAL_REG_WRITE(soc, addr, 2054 (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2055 } 2056 2057 /** 2058 * hal_tx_update_tidmap_prty_generic_li() - Update the tid map priority 2059 * @soc: HAL SoC context 2060 * @val: priority value 2061 * 2062 * Return: void 2063 */ 2064 static 2065 void hal_tx_update_tidmap_prty_generic_li(struct hal_soc *soc, uint8_t value) 2066 { 2067 uint32_t addr; 2068 2069 addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( 2070 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2071 2072 HAL_REG_WRITE(soc, addr, 2073 (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); 2074 } 2075 2076 /** 2077 * hal_rx_msdu_packet_metadata_get(): API to get the 2078 * msdu information from rx_msdu_end TLV 2079 * 2080 * @ buf: pointer to the start of RX PKT TLV headers 2081 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 2082 */ 2083 static void 2084 hal_rx_msdu_packet_metadata_get_generic_li(uint8_t *buf, 2085 void *pkt_msdu_metadata) 2086 { 2087 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2088 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 2089 struct hal_rx_msdu_metadata *msdu_metadata = 2090 (struct hal_rx_msdu_metadata *)pkt_msdu_metadata; 2091 2092 msdu_metadata->l3_hdr_pad = 2093 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 2094 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 2095 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 2096 msdu_metadata->sa_sw_peer_id = 2097 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 2098 } 2099 2100 /** 2101 * hal_rx_msdu_end_offset_get_generic(): API to get the 2102 * msdu_end structure offset rx_pkt_tlv structure 2103 * 2104 * NOTE: API returns offset of msdu_end TLV from structure 2105 * rx_pkt_tlvs 2106 */ 2107 static uint32_t hal_rx_msdu_end_offset_get_generic(void) 2108 { 2109 return RX_PKT_TLV_OFFSET(msdu_end_tlv); 2110 } 2111 2112 /** 2113 * hal_rx_attn_offset_get_generic(): API to get the 2114 * msdu_end structure offset rx_pkt_tlv structure 2115 * 2116 * NOTE: API returns offset of attn TLV from structure 2117 * rx_pkt_tlvs 2118 */ 2119 static uint32_t hal_rx_attn_offset_get_generic(void) 2120 { 2121 return RX_PKT_TLV_OFFSET(attn_tlv); 2122 } 2123 2124 /** 2125 * hal_rx_msdu_start_offset_get_generic(): API to get the 2126 * msdu_start structure offset rx_pkt_tlv structure 2127 * 2128 * NOTE: API returns offset of attn TLV from structure 2129 * rx_pkt_tlvs 2130 */ 2131 static uint32_t hal_rx_msdu_start_offset_get_generic(void) 2132 { 2133 return RX_PKT_TLV_OFFSET(msdu_start_tlv); 2134 } 2135 2136 /** 2137 * hal_rx_mpdu_start_offset_get_generic(): API to get the 2138 * mpdu_start structure offset rx_pkt_tlv structure 2139 * 2140 * NOTE: API returns offset of attn TLV from structure 2141 * rx_pkt_tlvs 2142 */ 2143 static uint32_t hal_rx_mpdu_start_offset_get_generic(void) 2144 { 2145 return RX_PKT_TLV_OFFSET(mpdu_start_tlv); 2146 } 2147 2148 /** 2149 * hal_rx_mpdu_end_offset_get_generic(): API to get the 2150 * mpdu_end structure offset rx_pkt_tlv structure 2151 * 2152 * NOTE: API returns offset of attn TLV from structure 2153 * rx_pkt_tlvs 2154 */ 2155 static uint32_t hal_rx_mpdu_end_offset_get_generic(void) 2156 { 2157 return RX_PKT_TLV_OFFSET(mpdu_end_tlv); 2158 } 2159 2160 #ifndef NO_RX_PKT_HDR_TLV 2161 static uint32_t hal_rx_pkt_tlv_offset_get_generic(void) 2162 { 2163 return RX_PKT_TLV_OFFSET(pkt_hdr_tlv); 2164 } 2165 #endif 2166 2167 #if defined(QDF_BIG_ENDIAN_MACHINE) 2168 /** 2169 * hal_setup_reo_swap() - Set the swap flag for big endian machines 2170 * @soc: HAL soc handle 2171 * 2172 * Return: None 2173 */ 2174 static inline void hal_setup_reo_swap(struct hal_soc *soc) 2175 { 2176 uint32_t reg_val; 2177 2178 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR( 2179 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 2180 2181 reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, WRITE_STRUCT_SWAP, 1); 2182 reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, READ_STRUCT_SWAP, 1); 2183 2184 HAL_REG_WRITE(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR( 2185 SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val); 2186 } 2187 #else 2188 static inline void hal_setup_reo_swap(struct hal_soc *soc) 2189 { 2190 } 2191 #endif 2192 2193 /** 2194 * hal_reo_setup_generic_li - Initialize HW REO block 2195 * 2196 * @hal_soc: Opaque HAL SOC handle 2197 * @reo_params: parameters needed by HAL for REO config 2198 */ 2199 static 2200 void hal_reo_setup_generic_li(struct hal_soc *soc, void *reoparams) 2201 { 2202 uint32_t reg_val; 2203 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 2204 2205 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 2206 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 2207 2208 hal_reo_config(soc, reg_val, reo_params); 2209 /* Other ring enable bits and REO_ENABLE will be set by FW */ 2210 2211 /* TODO: Setup destination ring mapping if enabled */ 2212 2213 /* TODO: Error destination ring setting is left to default. 2214 * Default setting is to send all errors to release ring. 2215 */ 2216 2217 /* Set the reo descriptor swap bits in case of BIG endian platform */ 2218 hal_setup_reo_swap(soc); 2219 2220 HAL_REG_WRITE(soc, 2221 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 2222 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2223 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 2224 2225 HAL_REG_WRITE(soc, 2226 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 2227 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2228 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 2229 2230 HAL_REG_WRITE(soc, 2231 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 2232 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2233 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 2234 2235 HAL_REG_WRITE(soc, 2236 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 2237 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2238 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 2239 2240 /* 2241 * When hash based routing is enabled, routing of the rx packet 2242 * is done based on the following value: 1 _ _ _ _ The last 4 2243 * bits are based on hash[3:0]. This means the possible values 2244 * are 0x10 to 0x1f. This value is used to look-up the 2245 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 2246 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 2247 * registers need to be configured to set-up the 16 entries to 2248 * map the hash values to a ring number. There are 3 bits per 2249 * hash entry – which are mapped as follows: 2250 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 2251 * 7: NOT_USED. 2252 */ 2253 if (reo_params->rx_hash_enabled) { 2254 if (reo_params->remap0) 2255 HAL_REG_WRITE(soc, 2256 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR( 2257 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2258 reo_params->remap0); 2259 2260 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 0x%x", 2261 HAL_REG_READ(soc, 2262 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR( 2263 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 2264 2265 HAL_REG_WRITE(soc, 2266 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 2267 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2268 reo_params->remap1); 2269 2270 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 2271 HAL_REG_READ(soc, 2272 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 2273 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 2274 2275 HAL_REG_WRITE(soc, 2276 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 2277 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2278 reo_params->remap2); 2279 2280 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 2281 HAL_REG_READ(soc, 2282 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 2283 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 2284 } 2285 2286 /* TODO: Check if the following registers shoould be setup by host: 2287 * AGING_CONTROL 2288 * HIGH_MEMORY_THRESHOLD 2289 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 2290 * GLOBAL_LINK_DESC_COUNT_CTRL 2291 */ 2292 } 2293 2294 /** 2295 * hal_setup_link_idle_list_generic_li - Setup scattered idle list using the 2296 * buffer list provided 2297 * 2298 * @hal_soc: Opaque HAL SOC handle 2299 * @scatter_bufs_base_paddr: Array of physical base addresses 2300 * @scatter_bufs_base_vaddr: Array of virtual base addresses 2301 * @num_scatter_bufs: Number of scatter buffers in the above lists 2302 * @scatter_buf_size: Size of each scatter buffer 2303 * @last_buf_end_offset: Offset to the last entry 2304 * @num_entries: Total entries of all scatter bufs 2305 * 2306 * Return: None 2307 */ 2308 static void 2309 hal_setup_link_idle_list_generic_li(struct hal_soc *soc, 2310 qdf_dma_addr_t scatter_bufs_base_paddr[], 2311 void *scatter_bufs_base_vaddr[], 2312 uint32_t num_scatter_bufs, 2313 uint32_t scatter_buf_size, 2314 uint32_t last_buf_end_offset, 2315 uint32_t num_entries) 2316 { 2317 int i; 2318 uint32_t *prev_buf_link_ptr = NULL; 2319 uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size; 2320 uint32_t val; 2321 2322 /* Link the scatter buffers */ 2323 for (i = 0; i < num_scatter_bufs; i++) { 2324 if (i > 0) { 2325 prev_buf_link_ptr[0] = 2326 scatter_bufs_base_paddr[i] & 0xffffffff; 2327 prev_buf_link_ptr[1] = HAL_SM( 2328 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2329 BASE_ADDRESS_39_32, 2330 ((uint64_t)(scatter_bufs_base_paddr[i]) 2331 >> 32)) | HAL_SM( 2332 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2333 ADDRESS_MATCH_TAG, 2334 ADDRESS_MATCH_TAG_VAL); 2335 } 2336 prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] + 2337 scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE); 2338 } 2339 2340 /* TBD: Register programming partly based on MLD & the rest based on 2341 * inputs from HW team. Not complete yet. 2342 */ 2343 2344 reg_scatter_buf_size = (scatter_buf_size - 2345 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64; 2346 reg_tot_scatter_buf_size = ((scatter_buf_size - 2347 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64; 2348 2349 HAL_REG_WRITE(soc, 2350 HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR 2351 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2352 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, 2353 SCATTER_BUFFER_SIZE, 2354 reg_scatter_buf_size) | 2355 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, 2356 LINK_DESC_IDLE_LIST_MODE, 0x1)); 2357 2358 HAL_REG_WRITE(soc, 2359 HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR 2360 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2361 HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE, 2362 SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST, 2363 reg_tot_scatter_buf_size)); 2364 2365 HAL_REG_WRITE(soc, 2366 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR 2367 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2368 scatter_bufs_base_paddr[0] & 0xffffffff); 2369 2370 HAL_REG_WRITE(soc, 2371 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR 2372 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2373 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) & 2374 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK); 2375 2376 HAL_REG_WRITE(soc, 2377 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR 2378 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2379 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2380 BASE_ADDRESS_39_32, 2381 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32)) | 2382 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2383 ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL)); 2384 2385 /* ADDRESS_MATCH_TAG field in the above register is expected to match 2386 * with the upper bits of link pointer. The above write sets this field 2387 * to zero and we are also setting the upper bits of link pointers to 2388 * zero while setting up the link list of scatter buffers above 2389 */ 2390 2391 /* Setup head and tail pointers for the idle list */ 2392 HAL_REG_WRITE(soc, 2393 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR 2394 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2395 scatter_bufs_base_paddr[num_scatter_bufs - 1] & 2396 0xffffffff); 2397 HAL_REG_WRITE(soc, 2398 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR 2399 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2400 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 2401 BUFFER_ADDRESS_39_32, 2402 ((uint64_t)(scatter_bufs_base_paddr 2403 [num_scatter_bufs - 1]) >> 32)) | 2404 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 2405 HEAD_POINTER_OFFSET, last_buf_end_offset >> 2)); 2406 2407 HAL_REG_WRITE(soc, 2408 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR 2409 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2410 scatter_bufs_base_paddr[0] & 0xffffffff); 2411 2412 HAL_REG_WRITE(soc, 2413 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR 2414 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2415 scatter_bufs_base_paddr[0] & 0xffffffff); 2416 HAL_REG_WRITE(soc, 2417 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR 2418 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2419 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 2420 BUFFER_ADDRESS_39_32, 2421 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32)) | 2422 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 2423 TAIL_POINTER_OFFSET, 0)); 2424 2425 HAL_REG_WRITE(soc, 2426 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR 2427 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2 * num_entries); 2428 2429 /* Set RING_ID_DISABLE */ 2430 val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1); 2431 2432 /* 2433 * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence 2434 * check the presence of the bit before toggling it. 2435 */ 2436 #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK 2437 val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1); 2438 #endif 2439 HAL_REG_WRITE(soc, 2440 HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR 2441 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2442 val); 2443 } 2444 2445 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 2446 /** 2447 * hal_tx_desc_set_search_type_generic_li - Set the search type value 2448 * @desc: Handle to Tx Descriptor 2449 * @search_type: search type 2450 * 0 – Normal search 2451 * 1 – Index based address search 2452 * 2 – Index based flow search 2453 * 2454 * Return: void 2455 */ 2456 static inline 2457 void hal_tx_desc_set_search_type_generic_li(void *desc, uint8_t search_type) 2458 { 2459 HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= 2460 HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); 2461 } 2462 #else 2463 static inline 2464 void hal_tx_desc_set_search_type_generic_li(void *desc, uint8_t search_type) 2465 { 2466 } 2467 2468 #endif 2469 2470 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 2471 /** 2472 * hal_tx_desc_set_search_index_generic_li - Set the search index value 2473 * @desc: Handle to Tx Descriptor 2474 * @search_index: The index that will be used for index based address or 2475 * flow search. The field is valid when 'search_type' is 2476 * 1 0r 2 2477 * 2478 * Return: void 2479 */ 2480 static inline 2481 void hal_tx_desc_set_search_index_generic_li(void *desc, uint32_t search_index) 2482 { 2483 HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= 2484 HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); 2485 } 2486 #else 2487 static inline 2488 void hal_tx_desc_set_search_index_generic_li(void *desc, uint32_t search_index) 2489 { 2490 } 2491 #endif 2492 2493 #ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 2494 /** 2495 * hal_tx_desc_set_cache_set_num_generic_li - Set the cache-set-num value 2496 * @desc: Handle to Tx Descriptor 2497 * @cache_num: Cache set number that should be used to cache the index 2498 * based search results, for address and flow search. 2499 * This value should be equal to LSB four bits of the hash value 2500 * of match data, in case of search index points to an entry 2501 * which may be used in content based search also. The value can 2502 * be anything when the entry pointed by search index will not be 2503 * used for content based search. 2504 * 2505 * Return: void 2506 */ 2507 static inline 2508 void hal_tx_desc_set_cache_set_num_generic_li(void *desc, uint8_t cache_num) 2509 { 2510 HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |= 2511 HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num); 2512 } 2513 #else 2514 static inline 2515 void hal_tx_desc_set_cache_set_num_generic_li(void *desc, uint8_t cache_num) 2516 { 2517 } 2518 #endif 2519 2520 #ifdef WLAN_SUPPORT_RX_FISA 2521 /** 2522 * hal_rx_flow_get_tuple_info_li() - Setup a flow search entry in HW FST 2523 * @fst: Pointer to the Rx Flow Search Table 2524 * @hal_hash: HAL 5 tuple hash 2525 * @tuple_info: 5-tuple info of the flow returned to the caller 2526 * 2527 * Return: Success/Failure 2528 */ 2529 static void * 2530 hal_rx_flow_get_tuple_info_li(uint8_t *rx_fst, uint32_t hal_hash, 2531 uint8_t *flow_tuple_info) 2532 { 2533 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 2534 void *hal_fse = NULL; 2535 struct hal_flow_tuple_info *tuple_info 2536 = (struct hal_flow_tuple_info *)flow_tuple_info; 2537 2538 hal_fse = (uint8_t *)fst->base_vaddr + 2539 (hal_hash * HAL_RX_FST_ENTRY_SIZE); 2540 2541 if (!hal_fse || !tuple_info) 2542 return NULL; 2543 2544 if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY_9, VALID)) 2545 return NULL; 2546 2547 tuple_info->src_ip_127_96 = 2548 qdf_ntohl(HAL_GET_FLD(hal_fse, 2549 RX_FLOW_SEARCH_ENTRY_0, 2550 SRC_IP_127_96)); 2551 tuple_info->src_ip_95_64 = 2552 qdf_ntohl(HAL_GET_FLD(hal_fse, 2553 RX_FLOW_SEARCH_ENTRY_1, 2554 SRC_IP_95_64)); 2555 tuple_info->src_ip_63_32 = 2556 qdf_ntohl(HAL_GET_FLD(hal_fse, 2557 RX_FLOW_SEARCH_ENTRY_2, 2558 SRC_IP_63_32)); 2559 tuple_info->src_ip_31_0 = 2560 qdf_ntohl(HAL_GET_FLD(hal_fse, 2561 RX_FLOW_SEARCH_ENTRY_3, 2562 SRC_IP_31_0)); 2563 tuple_info->dest_ip_127_96 = 2564 qdf_ntohl(HAL_GET_FLD(hal_fse, 2565 RX_FLOW_SEARCH_ENTRY_4, 2566 DEST_IP_127_96)); 2567 tuple_info->dest_ip_95_64 = 2568 qdf_ntohl(HAL_GET_FLD(hal_fse, 2569 RX_FLOW_SEARCH_ENTRY_5, 2570 DEST_IP_95_64)); 2571 tuple_info->dest_ip_63_32 = 2572 qdf_ntohl(HAL_GET_FLD(hal_fse, 2573 RX_FLOW_SEARCH_ENTRY_6, 2574 DEST_IP_63_32)); 2575 tuple_info->dest_ip_31_0 = 2576 qdf_ntohl(HAL_GET_FLD(hal_fse, 2577 RX_FLOW_SEARCH_ENTRY_7, 2578 DEST_IP_31_0)); 2579 tuple_info->dest_port = HAL_GET_FLD(hal_fse, 2580 RX_FLOW_SEARCH_ENTRY_8, 2581 DEST_PORT); 2582 tuple_info->src_port = HAL_GET_FLD(hal_fse, 2583 RX_FLOW_SEARCH_ENTRY_8, 2584 SRC_PORT); 2585 tuple_info->l4_protocol = HAL_GET_FLD(hal_fse, 2586 RX_FLOW_SEARCH_ENTRY_9, 2587 L4_PROTOCOL); 2588 2589 return hal_fse; 2590 } 2591 2592 /** 2593 * hal_rx_flow_delete_entry_li() - Setup a flow search entry in HW FST 2594 * @fst: Pointer to the Rx Flow Search Table 2595 * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST 2596 * 2597 * Return: Success/Failure 2598 */ 2599 static QDF_STATUS 2600 hal_rx_flow_delete_entry_li(uint8_t *rx_fst, void *hal_rx_fse) 2601 { 2602 uint8_t *fse = (uint8_t *)hal_rx_fse; 2603 2604 if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID)) 2605 return QDF_STATUS_E_NOENT; 2606 2607 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 2608 2609 return QDF_STATUS_SUCCESS; 2610 } 2611 2612 /** 2613 * hal_rx_fst_get_fse_size_li() - Retrieve the size of each entry 2614 * 2615 * Return: size of each entry/flow in Rx FST 2616 */ 2617 static inline uint32_t 2618 hal_rx_fst_get_fse_size_li(void) 2619 { 2620 return HAL_RX_FST_ENTRY_SIZE; 2621 } 2622 #else 2623 static inline void * 2624 hal_rx_flow_get_tuple_info_li(uint8_t *rx_fst, uint32_t hal_hash, 2625 uint8_t *flow_tuple_info) 2626 { 2627 return NULL; 2628 } 2629 2630 static inline QDF_STATUS 2631 hal_rx_flow_delete_entry_li(uint8_t *rx_fst, void *hal_rx_fse) 2632 { 2633 return QDF_STATUS_SUCCESS; 2634 } 2635 2636 static inline uint32_t 2637 hal_rx_fst_get_fse_size_li(void) 2638 { 2639 return 0; 2640 } 2641 #endif /* WLAN_SUPPORT_RX_FISA */ 2642 #endif /* _HAL_LI_GENERIC_API_H_ */ 2643