1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_LI_GENERIC_API_H_ 21 #define _HAL_LI_GENERIC_API_H_ 22 23 #include "hal_tx.h" 24 #include "hal_li_tx.h" 25 #include "hal_li_rx.h" 26 27 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) \ 28 (_HAL_MS((*_OFFSET_TO_WORD_PTR(wbm_desc, \ 29 WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET)), \ 30 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK, \ 31 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB)) 32 33 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) \ 34 (_HAL_MS((*_OFFSET_TO_WORD_PTR(wbm_desc, \ 35 WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET)), \ 36 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK, \ 37 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB)) 38 39 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 40 (((*(((uint32_t *)wbm_desc) + \ 41 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 42 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 43 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 44 45 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 46 (((*(((uint32_t *)wbm_desc) + \ 47 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 48 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 49 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 50 51 /** 52 * hal_rx_wbm_err_info_get_generic_li(): Retrieves WBM error code and reason and 53 * save it to hal_wbm_err_desc_info structure passed by caller 54 * @wbm_desc: wbm ring descriptor 55 * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 56 * Return: void 57 */ 58 static inline 59 void hal_rx_wbm_err_info_get_generic_li(void *wbm_desc, 60 void *wbm_er_info1) 61 { 62 struct hal_wbm_err_desc_info *wbm_er_info = 63 (struct hal_wbm_err_desc_info *)wbm_er_info1; 64 65 wbm_er_info->wbm_err_src = HAL_WBM2SW_RELEASE_SRC_GET(wbm_desc); 66 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 67 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 68 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 69 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 70 } 71 72 #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY) 73 static inline void 74 hal_tx_comp_get_buffer_timestamp_li(void *desc, 75 struct hal_tx_completion_status *ts) 76 { 77 ts->buffer_timestamp = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 78 BUFFER_TIMESTAMP); 79 } 80 #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */ 81 static inline void 82 hal_tx_comp_get_buffer_timestamp_li(void *desc, 83 struct hal_tx_completion_status *ts) 84 { 85 } 86 #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */ 87 88 #ifdef QCA_UNDECODED_METADATA_SUPPORT 89 static inline void 90 hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv, 91 struct hal_rx_ppdu_info *ppdu_info){ 92 switch (hal->target_type) { 93 case TARGET_TYPE_QCN9000: 94 ppdu_info->rx_status.phyrx_abort = 95 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, 96 PHYRX_ABORT_REQUEST_INFO_VALID); 97 ppdu_info->rx_status.phyrx_abort_reason = 98 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_11, 99 PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON); 100 break; 101 default: 102 break; 103 } 104 } 105 106 static inline void 107 hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info, 108 uint8_t *ht_sig_info) 109 { 110 ppdu_info->rx_status.ht_length = 111 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_0, LENGTH); 112 ppdu_info->rx_status.smoothing = 113 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, SMOOTHING); 114 ppdu_info->rx_status.not_sounding = 115 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, NOT_SOUNDING); 116 ppdu_info->rx_status.aggregation = 117 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, AGGREGATION); 118 ppdu_info->rx_status.ht_stbc = 119 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, STBC); 120 ppdu_info->rx_status.ht_crc = 121 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, CRC); 122 } 123 124 static inline void 125 hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, 126 uint8_t *l_sig_a_info) 127 { 128 ppdu_info->rx_status.l_sig_length = 129 HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, LENGTH); 130 ppdu_info->rx_status.l_sig_a_parity = 131 HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PARITY); 132 ppdu_info->rx_status.l_sig_a_pkt_type = 133 HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PKT_TYPE); 134 ppdu_info->rx_status.l_sig_a_implicit_sounding = 135 HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, 136 CAPTURED_IMPLICIT_SOUNDING); 137 } 138 139 static inline void 140 hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, 141 uint8_t *vht_sig_a_info) 142 { 143 ppdu_info->rx_status.vht_no_txop_ps = 144 HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, 145 TXOP_PS_NOT_ALLOWED); 146 ppdu_info->rx_status.vht_crc = 147 HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, CRC); 148 } 149 150 static inline void 151 hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info, 152 uint8_t *he_sig_a_su_info) { 153 ppdu_info->rx_status.he_crc = 154 HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, CRC); 155 } 156 157 static inline void 158 hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info, 159 uint8_t *he_sig_a_mu_dl_info) { 160 ppdu_info->rx_status.he_crc = 161 HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, CRC); 162 } 163 #else 164 static inline void 165 hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv, 166 struct hal_rx_ppdu_info *ppdu_info) 167 { 168 } 169 170 static inline void 171 hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info, 172 uint8_t *ht_sig_info) 173 { 174 } 175 176 static inline void 177 hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, 178 uint8_t *l_sig_a_info) 179 { 180 } 181 182 static inline void 183 hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, 184 uint8_t *vht_sig_a_info) 185 { 186 } 187 188 static inline void 189 hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info, 190 uint8_t *he_sig_a_su_info) 191 { 192 } 193 194 static inline void 195 hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info, 196 uint8_t *he_sig_a_mu_dl_info) 197 { 198 } 199 #endif /* QCA_UNDECODED_METADATA_SUPPORT */ 200 201 /** 202 * hal_tx_comp_get_status() - TQM Release reason 203 * @hal_desc: completion ring Tx status 204 * 205 * This function will parse the WBM completion descriptor and populate in 206 * HAL structure 207 * 208 * Return: none 209 */ 210 static inline void 211 hal_tx_comp_get_status_generic_li(void *desc, void *ts1, 212 struct hal_soc *hal) 213 { 214 uint8_t rate_stats_valid = 0; 215 uint32_t rate_stats = 0; 216 struct hal_tx_completion_status *ts = 217 (struct hal_tx_completion_status *)ts1; 218 219 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 220 TQM_STATUS_NUMBER); 221 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 222 ACK_FRAME_RSSI); 223 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 224 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 225 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 226 MSDU_PART_OF_AMSDU); 227 228 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 229 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 230 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 231 TRANSMIT_COUNT); 232 233 rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS); 234 235 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 236 TX_RATE_STATS_INFO_VALID, rate_stats); 237 238 ts->valid = rate_stats_valid; 239 240 if (rate_stats_valid) { 241 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 242 rate_stats); 243 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 244 TRANSMIT_PKT_TYPE, rate_stats); 245 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 246 TRANSMIT_STBC, rate_stats); 247 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 248 rate_stats); 249 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 250 rate_stats); 251 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 252 rate_stats); 253 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 254 rate_stats); 255 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 256 rate_stats); 257 } 258 259 ts->release_src = hal_tx_comp_get_buffer_source( 260 hal_soc_to_hal_soc_handle(hal), 261 desc); 262 ts->status = hal_tx_comp_get_release_reason( 263 desc, 264 hal_soc_to_hal_soc_handle(hal)); 265 266 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 267 TX_RATE_STATS_INFO_TX_RATE_STATS); 268 269 hal_tx_comp_get_buffer_timestamp_li(desc, ts); 270 } 271 272 /** 273 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 274 * @desc: Handle to Tx Descriptor 275 * @paddr: Physical Address 276 * @pool_id: Return Buffer Manager ID 277 * @desc_id: Descriptor ID 278 * @type: 0 - Address points to a MSDU buffer 279 * 1 - Address points to MSDU extension descriptor 280 * 281 * Return: void 282 */ 283 static inline void 284 hal_tx_desc_set_buf_addr_generic_li(void *desc, dma_addr_t paddr, 285 uint8_t rbm_id, uint32_t desc_id, 286 uint8_t type) 287 { 288 /* Set buffer_addr_info.buffer_addr_31_0 */ 289 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, 290 BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 291 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 292 293 /* Set buffer_addr_info.buffer_addr_39_32 */ 294 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 295 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 296 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 297 (((uint64_t)paddr) >> 32)); 298 299 /* Set buffer_addr_info.return_buffer_manager = rbm id */ 300 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 301 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 302 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, 303 RETURN_BUFFER_MANAGER, rbm_id); 304 305 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 306 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 307 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 308 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, 309 desc_id); 310 311 /* Set Buffer or Ext Descriptor Type */ 312 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, 313 BUF_OR_EXT_DESC_TYPE) |= 314 HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 315 } 316 317 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) 318 /** 319 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 320 * tlv_tag: Taf of the TLVs 321 * rx_tlv: the pointer to the TLVs 322 * @ppdu_info: pointer to ppdu_info 323 * 324 * Return: true if the tlv is handled, false if not 325 */ 326 static inline bool 327 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 328 struct hal_rx_ppdu_info *ppdu_info) 329 { 330 uint32_t value; 331 332 switch (tlv_tag) { 333 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 334 { 335 uint8_t *he_sig_a_mu_ul_info = 336 (uint8_t *)rx_tlv + 337 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, 338 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 339 ppdu_info->rx_status.he_flags = 1; 340 341 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 342 FORMAT_INDICATION); 343 if (value == 0) { 344 ppdu_info->rx_status.he_data1 = 345 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 346 } else { 347 ppdu_info->rx_status.he_data1 = 348 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 349 } 350 351 /* data1 */ 352 ppdu_info->rx_status.he_data1 |= 353 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 354 QDF_MON_STATUS_HE_DL_UL_KNOWN | 355 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 356 357 /* data2 */ 358 ppdu_info->rx_status.he_data2 |= 359 QDF_MON_STATUS_TXOP_KNOWN; 360 361 /*data3*/ 362 value = HAL_RX_GET(he_sig_a_mu_ul_info, 363 HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID); 364 ppdu_info->rx_status.he_data3 = value; 365 /* 1 for UL and 0 for DL */ 366 value = 1; 367 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 368 ppdu_info->rx_status.he_data3 |= value; 369 370 /*data4*/ 371 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 372 SPATIAL_REUSE); 373 ppdu_info->rx_status.he_data4 = value; 374 375 /*data5*/ 376 value = HAL_RX_GET(he_sig_a_mu_ul_info, 377 HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW); 378 ppdu_info->rx_status.he_data5 = value; 379 ppdu_info->rx_status.bw = value; 380 381 /*data6*/ 382 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1, 383 TXOP_DURATION); 384 value = value << QDF_MON_STATUS_TXOP_SHIFT; 385 ppdu_info->rx_status.he_data6 |= value; 386 return true; 387 } 388 default: 389 return false; 390 } 391 } 392 #else 393 static inline bool 394 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 395 struct hal_rx_ppdu_info *ppdu_info) 396 { 397 return false; 398 } 399 #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */ 400 401 #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) && \ 402 defined(RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 403 404 static inline void 405 hal_rx_handle_mu_ul_info(void *rx_tlv, 406 struct mon_rx_user_status *mon_rx_user_status) 407 { 408 mon_rx_user_status->mu_ul_user_v0_word0 = 409 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_11, 410 SW_RESPONSE_REFERENCE_PTR); 411 412 mon_rx_user_status->mu_ul_user_v0_word1 = 413 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_22, 414 SW_RESPONSE_REFERENCE_PTR_EXT); 415 } 416 417 static inline void 418 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 419 struct mon_rx_user_status *mon_rx_user_status) 420 { 421 uint32_t mpdu_ok_byte_count; 422 uint32_t mpdu_err_byte_count; 423 424 mpdu_ok_byte_count = HAL_RX_GET(rx_tlv, 425 RX_PPDU_END_USER_STATS_17, 426 MPDU_OK_BYTE_COUNT); 427 mpdu_err_byte_count = HAL_RX_GET(rx_tlv, 428 RX_PPDU_END_USER_STATS_19, 429 MPDU_ERR_BYTE_COUNT); 430 431 mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count; 432 mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count; 433 } 434 #else 435 static inline void 436 hal_rx_handle_mu_ul_info(void *rx_tlv, 437 struct mon_rx_user_status *mon_rx_user_status) 438 { 439 } 440 441 static inline void 442 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 443 struct mon_rx_user_status *mon_rx_user_status) 444 { 445 struct hal_rx_ppdu_info *ppdu_info = 446 (struct hal_rx_ppdu_info *)ppduinfo; 447 448 /* HKV1: doesn't support mpdu byte count */ 449 mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len; 450 mon_rx_user_status->mpdu_err_byte_count = 0; 451 } 452 #endif 453 454 static inline void 455 hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id, 456 struct mon_rx_user_status *mon_rx_user_status) 457 { 458 struct mon_rx_info *mon_rx_info; 459 struct mon_rx_user_info *mon_rx_user_info; 460 struct hal_rx_ppdu_info *ppdu_info = 461 (struct hal_rx_ppdu_info *)ppduinfo; 462 463 mon_rx_info = &ppdu_info->rx_info; 464 mon_rx_user_info = &ppdu_info->rx_user_info[user_id]; 465 mon_rx_user_info->qos_control_info_valid = 466 mon_rx_info->qos_control_info_valid; 467 mon_rx_user_info->qos_control = mon_rx_info->qos_control; 468 469 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 470 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 471 mon_rx_user_status->tcp_msdu_count = 472 ppdu_info->rx_status.tcp_msdu_count; 473 mon_rx_user_status->udp_msdu_count = 474 ppdu_info->rx_status.udp_msdu_count; 475 mon_rx_user_status->other_msdu_count = 476 ppdu_info->rx_status.other_msdu_count; 477 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 478 mon_rx_user_status->frame_control_info_valid = 479 ppdu_info->rx_status.frame_control_info_valid; 480 mon_rx_user_status->data_sequence_control_info_valid = 481 ppdu_info->rx_status.data_sequence_control_info_valid; 482 mon_rx_user_status->first_data_seq_ctrl = 483 ppdu_info->rx_status.first_data_seq_ctrl; 484 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 485 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 486 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 487 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 488 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 489 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 490 491 mon_rx_user_status->mpdu_cnt_fcs_ok = 492 ppdu_info->com_info.mpdu_cnt_fcs_ok; 493 mon_rx_user_status->mpdu_cnt_fcs_err = 494 ppdu_info->com_info.mpdu_cnt_fcs_err; 495 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 496 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 497 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 498 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 499 500 hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status); 501 } 502 503 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \ 504 ppdu_info, rssi_info_tlv) \ 505 { \ 506 ppdu_info->rx_status.rssi_chain[chain][0] = \ 507 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 508 RSSI_PRI20_CHAIN##chain); \ 509 ppdu_info->rx_status.rssi_chain[chain][1] = \ 510 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 511 RSSI_EXT20_CHAIN##chain); \ 512 ppdu_info->rx_status.rssi_chain[chain][2] = \ 513 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 514 RSSI_EXT40_LOW20_CHAIN##chain); \ 515 ppdu_info->rx_status.rssi_chain[chain][3] = \ 516 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 517 RSSI_EXT40_HIGH20_CHAIN##chain); \ 518 ppdu_info->rx_status.rssi_chain[chain][4] = \ 519 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 520 RSSI_EXT80_LOW20_CHAIN##chain); \ 521 ppdu_info->rx_status.rssi_chain[chain][5] = \ 522 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 523 RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \ 524 ppdu_info->rx_status.rssi_chain[chain][6] = \ 525 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 526 RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \ 527 ppdu_info->rx_status.rssi_chain[chain][7] = \ 528 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 529 RSSI_EXT80_HIGH20_CHAIN##chain); \ 530 } \ 531 532 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 533 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \ 534 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \ 535 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \ 536 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \ 537 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \ 538 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \ 539 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \ 540 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \ 541 542 static inline uint32_t 543 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 544 uint8_t *rssi_info_tlv) 545 { 546 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 547 return 0; 548 } 549 550 #ifdef WLAN_TX_PKT_CAPTURE_ENH 551 static inline void 552 hal_get_qos_control(void *rx_tlv, 553 struct hal_rx_ppdu_info *ppdu_info) 554 { 555 ppdu_info->rx_info.qos_control_info_valid = 556 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 557 QOS_CONTROL_INFO_VALID); 558 559 if (ppdu_info->rx_info.qos_control_info_valid) 560 ppdu_info->rx_info.qos_control = 561 HAL_RX_GET(rx_tlv, 562 RX_PPDU_END_USER_STATS_5, 563 QOS_CONTROL_FIELD); 564 } 565 566 static inline void 567 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 568 struct hal_rx_ppdu_info *ppdu_info) 569 { 570 if ((ppdu_info->sw_frame_group_id 571 == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) || 572 (ppdu_info->sw_frame_group_id == 573 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) { 574 ppdu_info->rx_info.mac_addr1_valid = 575 HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start); 576 577 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] = 578 HAL_RX_GET(rx_mpdu_start, 579 RX_MPDU_INFO_15, 580 MAC_ADDR_AD1_31_0); 581 if (ppdu_info->sw_frame_group_id == 582 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) { 583 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] = 584 HAL_RX_GET(rx_mpdu_start, 585 RX_MPDU_INFO_16, 586 MAC_ADDR_AD1_47_32); 587 } 588 } 589 } 590 #else 591 static inline void 592 hal_get_qos_control(void *rx_tlv, 593 struct hal_rx_ppdu_info *ppdu_info) 594 { 595 } 596 597 static inline void 598 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 599 struct hal_rx_ppdu_info *ppdu_info) 600 { 601 } 602 #endif 603 604 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS 605 static inline void 606 hal_update_frame_type_cnt(uint8_t *rx_mpdu_start, 607 struct hal_rx_ppdu_info *ppdu_info) 608 { 609 uint16_t frame_ctrl; 610 uint8_t fc_type; 611 612 if (HAL_RX_GET_FC_VALID(rx_mpdu_start)) { 613 frame_ctrl = HAL_RX_GET(rx_mpdu_start, 614 RX_MPDU_INFO_14, 615 MPDU_FRAME_CONTROL_FIELD); 616 fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl); 617 if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT) 618 ppdu_info->frm_type_info.rx_mgmt_cnt++; 619 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL) 620 ppdu_info->frm_type_info.rx_ctrl_cnt++; 621 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA) 622 ppdu_info->frm_type_info.rx_data_cnt++; 623 } 624 } 625 #else 626 static inline void 627 hal_update_frame_type_cnt(uint8_t *rx_mpdu_start, 628 struct hal_rx_ppdu_info *ppdu_info) 629 { 630 } 631 #endif 632 633 #ifdef WLAN_SUPPORT_CTRL_FRAME_STATS 634 static inline void 635 hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info *ppdu_info, 636 uint32_t user_id) 637 { 638 uint16_t fc = ppdu_info->nac_info.frame_control; 639 640 if (HAL_RX_GET_FRAME_CTRL_TYPE(fc) == HAL_RX_FRAME_CTRL_TYPE_CTRL) { 641 if ((fc & QDF_IEEE80211_FC0_SUBTYPE_MASK) == 642 QDF_IEEE80211_FC0_SUBTYPE_VHT_NDP_AN) 643 ppdu_info->ctrl_frm_info[user_id].ndpa = 1; 644 if ((fc & QDF_IEEE80211_FC0_SUBTYPE_MASK) == 645 QDF_IEEE80211_FC0_SUBTYPE_BAR) 646 ppdu_info->ctrl_frm_info[user_id].bar = 1; 647 } 648 } 649 #else 650 static inline void 651 hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info *ppdu_info, 652 uint32_t user_id) 653 { 654 } 655 #endif /* WLAN_SUPPORT_CTRL_FRAME_STATS */ 656 657 /** 658 * hal_rx_status_get_tlv_info() - process receive info TLV 659 * @rx_tlv_hdr: pointer to TLV header 660 * @ppdu_info: pointer to ppdu_info 661 * 662 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 663 */ 664 static inline uint32_t 665 hal_rx_status_get_tlv_info_generic_li(void *rx_tlv_hdr, void *ppduinfo, 666 hal_soc_handle_t hal_soc_hdl, 667 qdf_nbuf_t nbuf) 668 { 669 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 670 uint32_t tlv_tag, user_id, tlv_len, value; 671 uint8_t group_id = 0; 672 uint8_t he_dcm = 0; 673 uint8_t he_stbc = 0; 674 uint16_t he_gi = 0; 675 uint16_t he_ltf = 0; 676 void *rx_tlv; 677 bool unhandled = false; 678 struct mon_rx_user_status *mon_rx_user_status; 679 struct hal_rx_ppdu_info *ppdu_info = 680 (struct hal_rx_ppdu_info *)ppduinfo; 681 682 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 683 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 684 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 685 686 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 687 688 switch (tlv_tag) { 689 case WIFIRX_PPDU_START_E: 690 { 691 if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id == 692 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, PHY_PPDU_ID))) 693 hal_err("Matching ppdu_id(%u) detected", 694 ppdu_info->com_info.last_ppdu_id); 695 696 /* Reset ppdu_info before processing the ppdu */ 697 qdf_mem_zero(ppdu_info, 698 sizeof(struct hal_rx_ppdu_info)); 699 700 ppdu_info->com_info.last_ppdu_id = 701 ppdu_info->com_info.ppdu_id = 702 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 703 PHY_PPDU_ID); 704 705 /* channel number is set in PHY meta data */ 706 ppdu_info->rx_status.chan_num = 707 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 708 SW_PHY_META_DATA) & 0x0000FFFF); 709 ppdu_info->rx_status.chan_freq = 710 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 711 SW_PHY_META_DATA) & 0xFFFF0000) >> 16; 712 if (ppdu_info->rx_status.chan_num) { 713 ppdu_info->rx_status.chan_freq = 714 hal_rx_radiotap_num_to_freq( 715 ppdu_info->rx_status.chan_num, 716 ppdu_info->rx_status.chan_freq); 717 } 718 ppdu_info->com_info.ppdu_timestamp = 719 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 720 PPDU_START_TIMESTAMP); 721 ppdu_info->rx_status.ppdu_timestamp = 722 ppdu_info->com_info.ppdu_timestamp; 723 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 724 725 break; 726 } 727 728 case WIFIRX_PPDU_START_USER_INFO_E: 729 break; 730 731 case WIFIRX_PPDU_END_E: 732 dp_nofl_debug("[%s][%d] ppdu_end_e len=%d", 733 __func__, __LINE__, tlv_len); 734 /* This is followed by sub-TLVs of PPDU_END */ 735 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 736 break; 737 738 case WIFIPHYRX_PKT_END_E: 739 hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); 740 break; 741 742 case WIFIRXPCU_PPDU_END_INFO_E: 743 ppdu_info->rx_status.rx_antenna = 744 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, RX_ANTENNA); 745 ppdu_info->rx_status.tsft = 746 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 747 WB_TIMESTAMP_UPPER_32); 748 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 749 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 750 WB_TIMESTAMP_LOWER_32); 751 ppdu_info->rx_status.duration = 752 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 753 RX_PPDU_DURATION); 754 hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); 755 hal_rx_get_phyrx_abort(hal, rx_tlv, ppdu_info); 756 break; 757 758 /* 759 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 760 * for MU, based on num users we see this tlv that many times. 761 */ 762 case WIFIRX_PPDU_END_USER_STATS_E: 763 { 764 unsigned long tid = 0; 765 uint16_t seq = 0; 766 767 ppdu_info->rx_status.ast_index = 768 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 769 AST_INDEX); 770 771 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 772 RECEIVED_QOS_DATA_TID_BITMAP); 773 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, 774 sizeof(tid) * 8); 775 776 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 777 ppdu_info->rx_status.tid = HAL_TID_INVALID; 778 779 ppdu_info->rx_status.tcp_msdu_count = 780 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 781 TCP_MSDU_COUNT) + 782 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 783 TCP_ACK_MSDU_COUNT); 784 ppdu_info->rx_status.udp_msdu_count = 785 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 786 UDP_MSDU_COUNT); 787 ppdu_info->rx_status.other_msdu_count = 788 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 789 OTHER_MSDU_COUNT); 790 791 if (ppdu_info->sw_frame_group_id 792 != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 793 ppdu_info->rx_status.frame_control_info_valid = 794 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 795 FRAME_CONTROL_INFO_VALID); 796 797 if (ppdu_info->rx_status.frame_control_info_valid) 798 ppdu_info->rx_status.frame_control = 799 HAL_RX_GET(rx_tlv, 800 RX_PPDU_END_USER_STATS_4, 801 FRAME_CONTROL_FIELD); 802 803 hal_get_qos_control(rx_tlv, ppdu_info); 804 } 805 806 ppdu_info->rx_status.data_sequence_control_info_valid = 807 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 808 DATA_SEQUENCE_CONTROL_INFO_VALID); 809 810 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 811 FIRST_DATA_SEQ_CTRL); 812 if (ppdu_info->rx_status.data_sequence_control_info_valid) 813 ppdu_info->rx_status.first_data_seq_ctrl = seq; 814 815 ppdu_info->rx_status.preamble_type = 816 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 817 HT_CONTROL_FIELD_PKT_TYPE); 818 switch (ppdu_info->rx_status.preamble_type) { 819 case HAL_RX_PKT_TYPE_11N: 820 ppdu_info->rx_status.ht_flags = 1; 821 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 822 break; 823 case HAL_RX_PKT_TYPE_11AC: 824 ppdu_info->rx_status.vht_flags = 1; 825 break; 826 case HAL_RX_PKT_TYPE_11AX: 827 ppdu_info->rx_status.he_flags = 1; 828 break; 829 default: 830 break; 831 } 832 833 ppdu_info->com_info.mpdu_cnt_fcs_ok = 834 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 835 MPDU_CNT_FCS_OK); 836 ppdu_info->com_info.mpdu_cnt_fcs_err = 837 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 838 MPDU_CNT_FCS_ERR); 839 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 840 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 841 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 842 else 843 ppdu_info->rx_status.rs_flags &= 844 (~IEEE80211_AMPDU_FLAG); 845 846 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 847 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_7, 848 FCS_OK_BITMAP_31_0); 849 850 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 851 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_8, 852 FCS_OK_BITMAP_63_32); 853 854 if (user_id < HAL_MAX_UL_MU_USERS) { 855 mon_rx_user_status = 856 &ppdu_info->rx_user_status[user_id]; 857 858 hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status); 859 860 ppdu_info->com_info.num_users++; 861 862 hal_rx_populate_mu_user_info(rx_tlv, ppdu_info, 863 user_id, 864 mon_rx_user_status); 865 } 866 break; 867 } 868 869 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 870 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 871 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_1, 872 FCS_OK_BITMAP_95_64); 873 874 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 875 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_2, 876 FCS_OK_BITMAP_127_96); 877 878 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 879 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_3, 880 FCS_OK_BITMAP_159_128); 881 882 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 883 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_4, 884 FCS_OK_BITMAP_191_160); 885 886 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 887 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_5, 888 FCS_OK_BITMAP_223_192); 889 890 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 891 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_6, 892 FCS_OK_BITMAP_255_224); 893 break; 894 895 case WIFIRX_PPDU_END_STATUS_DONE_E: 896 return HAL_TLV_STATUS_PPDU_DONE; 897 898 case WIFIDUMMY_E: 899 return HAL_TLV_STATUS_BUF_DONE; 900 901 case WIFIPHYRX_HT_SIG_E: 902 { 903 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 904 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 905 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 906 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 907 FEC_CODING); 908 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 909 1 : 0; 910 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 911 HT_SIG_INFO_0, MCS); 912 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 913 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 914 HT_SIG_INFO_0, CBW); 915 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 916 HT_SIG_INFO_1, SHORT_GI); 917 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 918 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 919 HT_SIG_SU_NSS_SHIFT) + 1; 920 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 921 hal_rx_get_ht_sig_info(ppdu_info, ht_sig_info); 922 break; 923 } 924 925 case WIFIPHYRX_L_SIG_B_E: 926 { 927 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 928 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 929 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 930 931 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 932 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 933 switch (value) { 934 case 1: 935 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 936 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 937 break; 938 case 2: 939 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 940 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 941 break; 942 case 3: 943 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 944 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 945 break; 946 case 4: 947 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 948 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 949 break; 950 case 5: 951 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 952 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 953 break; 954 case 6: 955 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 956 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 957 break; 958 case 7: 959 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 960 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 961 break; 962 default: 963 break; 964 } 965 ppdu_info->rx_status.cck_flag = 1; 966 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 967 break; 968 } 969 970 case WIFIPHYRX_L_SIG_A_E: 971 { 972 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 973 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 974 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 975 976 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 977 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 978 switch (value) { 979 case 8: 980 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 981 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 982 break; 983 case 9: 984 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 985 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 986 break; 987 case 10: 988 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 989 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 990 break; 991 case 11: 992 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 993 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 994 break; 995 case 12: 996 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 997 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 998 break; 999 case 13: 1000 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 1001 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 1002 break; 1003 case 14: 1004 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 1005 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 1006 break; 1007 case 15: 1008 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 1009 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 1010 break; 1011 default: 1012 break; 1013 } 1014 ppdu_info->rx_status.ofdm_flag = 1; 1015 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1016 hal_rx_get_l_sig_a_info(ppdu_info, l_sig_a_info); 1017 break; 1018 } 1019 1020 case WIFIPHYRX_VHT_SIG_A_E: 1021 { 1022 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 1023 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 1024 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 1025 1026 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 1027 SU_MU_CODING); 1028 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 1029 1 : 0; 1030 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, 1031 GROUP_ID); 1032 ppdu_info->rx_status.vht_flag_values5 = group_id; 1033 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 1034 VHT_SIG_A_INFO_1, MCS); 1035 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 1036 VHT_SIG_A_INFO_1, GI_SETTING); 1037 1038 switch (hal->target_type) { 1039 case TARGET_TYPE_QCA8074: 1040 case TARGET_TYPE_QCA8074V2: 1041 case TARGET_TYPE_QCA6018: 1042 case TARGET_TYPE_QCA5018: 1043 case TARGET_TYPE_QCN9000: 1044 case TARGET_TYPE_QCN6122: 1045 case TARGET_TYPE_QCN9160: 1046 #ifdef QCA_WIFI_QCA6390 1047 case TARGET_TYPE_QCA6390: 1048 #endif 1049 case TARGET_TYPE_QCA6490: 1050 ppdu_info->rx_status.is_stbc = 1051 HAL_RX_GET(vht_sig_a_info, 1052 VHT_SIG_A_INFO_0, STBC); 1053 value = HAL_RX_GET(vht_sig_a_info, 1054 VHT_SIG_A_INFO_0, N_STS); 1055 value = value & VHT_SIG_SU_NSS_MASK; 1056 if (ppdu_info->rx_status.is_stbc && (value > 0)) 1057 value = ((value + 1) >> 1) - 1; 1058 ppdu_info->rx_status.nss = 1059 ((value & VHT_SIG_SU_NSS_MASK) + 1); 1060 1061 break; 1062 case TARGET_TYPE_QCA6290: 1063 #if !defined(QCA_WIFI_QCA6290_11AX) 1064 ppdu_info->rx_status.is_stbc = 1065 HAL_RX_GET(vht_sig_a_info, 1066 VHT_SIG_A_INFO_0, STBC); 1067 value = HAL_RX_GET(vht_sig_a_info, 1068 VHT_SIG_A_INFO_0, N_STS); 1069 value = value & VHT_SIG_SU_NSS_MASK; 1070 if (ppdu_info->rx_status.is_stbc && (value > 0)) 1071 value = ((value + 1) >> 1) - 1; 1072 ppdu_info->rx_status.nss = 1073 ((value & VHT_SIG_SU_NSS_MASK) + 1); 1074 #else 1075 ppdu_info->rx_status.nss = 0; 1076 #endif 1077 break; 1078 case TARGET_TYPE_QCA6750: 1079 ppdu_info->rx_status.nss = 0; 1080 break; 1081 default: 1082 break; 1083 } 1084 ppdu_info->rx_status.vht_flag_values3[0] = 1085 (((ppdu_info->rx_status.mcs) << 4) 1086 | ppdu_info->rx_status.nss); 1087 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 1088 VHT_SIG_A_INFO_0, BANDWIDTH); 1089 ppdu_info->rx_status.vht_flag_values2 = 1090 ppdu_info->rx_status.bw; 1091 ppdu_info->rx_status.vht_flag_values4 = 1092 HAL_RX_GET(vht_sig_a_info, 1093 VHT_SIG_A_INFO_1, SU_MU_CODING); 1094 1095 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 1096 VHT_SIG_A_INFO_1, BEAMFORMED); 1097 if (group_id == 0 || group_id == 63) 1098 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1099 else 1100 ppdu_info->rx_status.reception_type = 1101 HAL_RX_TYPE_MU_MIMO; 1102 1103 hal_rx_get_vht_sig_a_info(ppdu_info, vht_sig_a_info); 1104 break; 1105 } 1106 case WIFIPHYRX_HE_SIG_A_SU_E: 1107 { 1108 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 1109 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 1110 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 1111 ppdu_info->rx_status.he_flags = 1; 1112 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 1113 FORMAT_INDICATION); 1114 if (value == 0) { 1115 ppdu_info->rx_status.he_data1 = 1116 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1117 } else { 1118 ppdu_info->rx_status.he_data1 = 1119 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 1120 } 1121 1122 /* data1 */ 1123 ppdu_info->rx_status.he_data1 |= 1124 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 1125 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 1126 QDF_MON_STATUS_HE_DL_UL_KNOWN | 1127 QDF_MON_STATUS_HE_MCS_KNOWN | 1128 QDF_MON_STATUS_HE_DCM_KNOWN | 1129 QDF_MON_STATUS_HE_CODING_KNOWN | 1130 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 1131 QDF_MON_STATUS_HE_STBC_KNOWN | 1132 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 1133 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 1134 1135 /* data2 */ 1136 ppdu_info->rx_status.he_data2 = 1137 QDF_MON_STATUS_HE_GI_KNOWN; 1138 ppdu_info->rx_status.he_data2 |= 1139 QDF_MON_STATUS_TXBF_KNOWN | 1140 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1141 QDF_MON_STATUS_TXOP_KNOWN | 1142 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1143 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1144 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1145 1146 /* data3 */ 1147 value = HAL_RX_GET(he_sig_a_su_info, 1148 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 1149 ppdu_info->rx_status.he_data3 = value; 1150 value = HAL_RX_GET(he_sig_a_su_info, 1151 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 1152 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 1153 ppdu_info->rx_status.he_data3 |= value; 1154 value = HAL_RX_GET(he_sig_a_su_info, 1155 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 1156 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1157 ppdu_info->rx_status.he_data3 |= value; 1158 1159 value = HAL_RX_GET(he_sig_a_su_info, 1160 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 1161 ppdu_info->rx_status.mcs = value; 1162 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1163 ppdu_info->rx_status.he_data3 |= value; 1164 1165 value = HAL_RX_GET(he_sig_a_su_info, 1166 HE_SIG_A_SU_INFO_0, DCM); 1167 he_dcm = value; 1168 value = value << QDF_MON_STATUS_DCM_SHIFT; 1169 ppdu_info->rx_status.he_data3 |= value; 1170 value = HAL_RX_GET(he_sig_a_su_info, 1171 HE_SIG_A_SU_INFO_1, CODING); 1172 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 1173 1 : 0; 1174 value = value << QDF_MON_STATUS_CODING_SHIFT; 1175 ppdu_info->rx_status.he_data3 |= value; 1176 value = HAL_RX_GET(he_sig_a_su_info, 1177 HE_SIG_A_SU_INFO_1, 1178 LDPC_EXTRA_SYMBOL); 1179 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1180 ppdu_info->rx_status.he_data3 |= value; 1181 value = HAL_RX_GET(he_sig_a_su_info, 1182 HE_SIG_A_SU_INFO_1, STBC); 1183 he_stbc = value; 1184 value = value << QDF_MON_STATUS_STBC_SHIFT; 1185 ppdu_info->rx_status.he_data3 |= value; 1186 1187 /* data4 */ 1188 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 1189 SPATIAL_REUSE); 1190 ppdu_info->rx_status.he_data4 = value; 1191 1192 /* data5 */ 1193 value = HAL_RX_GET(he_sig_a_su_info, 1194 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 1195 ppdu_info->rx_status.he_data5 = value; 1196 ppdu_info->rx_status.bw = value; 1197 value = HAL_RX_GET(he_sig_a_su_info, 1198 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 1199 switch (value) { 1200 case 0: 1201 he_gi = HE_GI_0_8; 1202 he_ltf = HE_LTF_1_X; 1203 break; 1204 case 1: 1205 he_gi = HE_GI_0_8; 1206 he_ltf = HE_LTF_2_X; 1207 break; 1208 case 2: 1209 he_gi = HE_GI_1_6; 1210 he_ltf = HE_LTF_2_X; 1211 break; 1212 case 3: 1213 if (he_dcm && he_stbc) { 1214 he_gi = HE_GI_0_8; 1215 he_ltf = HE_LTF_4_X; 1216 } else { 1217 he_gi = HE_GI_3_2; 1218 he_ltf = HE_LTF_4_X; 1219 } 1220 break; 1221 } 1222 ppdu_info->rx_status.sgi = he_gi; 1223 ppdu_info->rx_status.ltf_size = he_ltf; 1224 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 1225 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1226 ppdu_info->rx_status.he_data5 |= value; 1227 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1228 ppdu_info->rx_status.he_data5 |= value; 1229 1230 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 1231 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1232 ppdu_info->rx_status.he_data5 |= value; 1233 1234 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1235 PACKET_EXTENSION_A_FACTOR); 1236 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1237 ppdu_info->rx_status.he_data5 |= value; 1238 1239 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 1240 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1241 ppdu_info->rx_status.he_data5 |= value; 1242 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1243 PACKET_EXTENSION_PE_DISAMBIGUITY); 1244 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1245 ppdu_info->rx_status.he_data5 |= value; 1246 1247 /* data6 */ 1248 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 1249 value++; 1250 ppdu_info->rx_status.nss = value; 1251 ppdu_info->rx_status.he_data6 = value; 1252 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1253 DOPPLER_INDICATION); 1254 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1255 ppdu_info->rx_status.he_data6 |= value; 1256 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1257 TXOP_DURATION); 1258 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1259 ppdu_info->rx_status.he_data6 |= value; 1260 1261 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 1262 HE_SIG_A_SU_INFO_1, TXBF); 1263 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1264 hal_rx_get_crc_he_sig_a_su_info(ppdu_info, he_sig_a_su_info); 1265 break; 1266 } 1267 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 1268 { 1269 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 1270 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 1271 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 1272 1273 ppdu_info->rx_status.he_mu_flags = 1; 1274 1275 /* HE Flags */ 1276 /*data1*/ 1277 ppdu_info->rx_status.he_data1 = 1278 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1279 ppdu_info->rx_status.he_data1 |= 1280 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 1281 QDF_MON_STATUS_HE_DL_UL_KNOWN | 1282 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 1283 QDF_MON_STATUS_HE_STBC_KNOWN | 1284 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 1285 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 1286 1287 /* data2 */ 1288 ppdu_info->rx_status.he_data2 = 1289 QDF_MON_STATUS_HE_GI_KNOWN; 1290 ppdu_info->rx_status.he_data2 |= 1291 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1292 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1293 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1294 QDF_MON_STATUS_TXOP_KNOWN | 1295 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1296 1297 /*data3*/ 1298 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1299 HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); 1300 ppdu_info->rx_status.he_data3 = value; 1301 1302 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1303 HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); 1304 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1305 ppdu_info->rx_status.he_data3 |= value; 1306 1307 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1308 HE_SIG_A_MU_DL_INFO_1, 1309 LDPC_EXTRA_SYMBOL); 1310 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1311 ppdu_info->rx_status.he_data3 |= value; 1312 1313 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1314 HE_SIG_A_MU_DL_INFO_1, STBC); 1315 he_stbc = value; 1316 value = value << QDF_MON_STATUS_STBC_SHIFT; 1317 ppdu_info->rx_status.he_data3 |= value; 1318 1319 /*data4*/ 1320 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1321 SPATIAL_REUSE); 1322 ppdu_info->rx_status.he_data4 = value; 1323 1324 /*data5*/ 1325 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1326 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1327 ppdu_info->rx_status.he_data5 = value; 1328 ppdu_info->rx_status.bw = value; 1329 1330 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1331 HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); 1332 switch (value) { 1333 case 0: 1334 he_gi = HE_GI_0_8; 1335 he_ltf = HE_LTF_4_X; 1336 break; 1337 case 1: 1338 he_gi = HE_GI_0_8; 1339 he_ltf = HE_LTF_2_X; 1340 break; 1341 case 2: 1342 he_gi = HE_GI_1_6; 1343 he_ltf = HE_LTF_2_X; 1344 break; 1345 case 3: 1346 he_gi = HE_GI_3_2; 1347 he_ltf = HE_LTF_4_X; 1348 break; 1349 } 1350 ppdu_info->rx_status.sgi = he_gi; 1351 ppdu_info->rx_status.ltf_size = he_ltf; 1352 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 1353 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1354 ppdu_info->rx_status.he_data5 |= value; 1355 1356 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1357 ppdu_info->rx_status.he_data5 |= value; 1358 1359 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1360 HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); 1361 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1362 ppdu_info->rx_status.he_data5 |= value; 1363 1364 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1365 PACKET_EXTENSION_A_FACTOR); 1366 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1367 ppdu_info->rx_status.he_data5 |= value; 1368 1369 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1370 PACKET_EXTENSION_PE_DISAMBIGUITY); 1371 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1372 ppdu_info->rx_status.he_data5 |= value; 1373 1374 /*data6*/ 1375 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1376 DOPPLER_INDICATION); 1377 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1378 ppdu_info->rx_status.he_data6 |= value; 1379 1380 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1381 TXOP_DURATION); 1382 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1383 ppdu_info->rx_status.he_data6 |= value; 1384 1385 /* HE-MU Flags */ 1386 /* HE-MU-flags1 */ 1387 ppdu_info->rx_status.he_flags1 = 1388 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1389 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1390 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 1391 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 1392 QDF_MON_STATUS_RU_0_KNOWN; 1393 1394 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1395 HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); 1396 ppdu_info->rx_status.he_flags1 |= value; 1397 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1398 HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); 1399 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 1400 ppdu_info->rx_status.he_flags1 |= value; 1401 1402 /* HE-MU-flags2 */ 1403 ppdu_info->rx_status.he_flags2 = 1404 QDF_MON_STATUS_BW_KNOWN; 1405 1406 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1407 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1408 ppdu_info->rx_status.he_flags2 |= value; 1409 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1410 HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); 1411 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1412 ppdu_info->rx_status.he_flags2 |= value; 1413 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1414 HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); 1415 value = value - 1; 1416 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 1417 ppdu_info->rx_status.he_flags2 |= value; 1418 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1419 hal_rx_get_crc_he_sig_a_mu_dl_info(ppdu_info, 1420 he_sig_a_mu_dl_info); 1421 break; 1422 } 1423 case WIFIPHYRX_HE_SIG_B1_MU_E: 1424 { 1425 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 1426 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 1427 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 1428 1429 ppdu_info->rx_status.he_sig_b_common_known |= 1430 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 1431 /* TODO: Check on the availability of other fields in 1432 * sig_b_common 1433 */ 1434 1435 value = HAL_RX_GET(he_sig_b1_mu_info, 1436 HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); 1437 ppdu_info->rx_status.he_RU[0] = value; 1438 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1439 break; 1440 } 1441 case WIFIPHYRX_HE_SIG_B2_MU_E: 1442 { 1443 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 1444 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 1445 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 1446 /* 1447 * Not all "HE" fields can be updated from 1448 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1449 * to populate rest of the "HE" fields for MU scenarios. 1450 */ 1451 1452 /* HE-data1 */ 1453 ppdu_info->rx_status.he_data1 |= 1454 QDF_MON_STATUS_HE_MCS_KNOWN | 1455 QDF_MON_STATUS_HE_CODING_KNOWN; 1456 1457 /* HE-data2 */ 1458 1459 /* HE-data3 */ 1460 value = HAL_RX_GET(he_sig_b2_mu_info, 1461 HE_SIG_B2_MU_INFO_0, STA_MCS); 1462 ppdu_info->rx_status.mcs = value; 1463 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1464 ppdu_info->rx_status.he_data3 |= value; 1465 1466 value = HAL_RX_GET(he_sig_b2_mu_info, 1467 HE_SIG_B2_MU_INFO_0, STA_CODING); 1468 value = value << QDF_MON_STATUS_CODING_SHIFT; 1469 ppdu_info->rx_status.he_data3 |= value; 1470 1471 /* HE-data4 */ 1472 value = HAL_RX_GET(he_sig_b2_mu_info, 1473 HE_SIG_B2_MU_INFO_0, STA_ID); 1474 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1475 ppdu_info->rx_status.he_data4 |= value; 1476 1477 /* HE-data5 */ 1478 1479 /* HE-data6 */ 1480 value = HAL_RX_GET(he_sig_b2_mu_info, 1481 HE_SIG_B2_MU_INFO_0, NSTS); 1482 /* value n indicates n+1 spatial streams */ 1483 value++; 1484 ppdu_info->rx_status.nss = value; 1485 ppdu_info->rx_status.he_data6 |= value; 1486 1487 break; 1488 } 1489 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 1490 { 1491 uint8_t *he_sig_b2_ofdma_info = 1492 (uint8_t *)rx_tlv + 1493 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 1494 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 1495 1496 /* 1497 * Not all "HE" fields can be updated from 1498 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1499 * to populate rest of "HE" fields for MU OFDMA scenarios. 1500 */ 1501 1502 /* HE-data1 */ 1503 ppdu_info->rx_status.he_data1 |= 1504 QDF_MON_STATUS_HE_MCS_KNOWN | 1505 QDF_MON_STATUS_HE_DCM_KNOWN | 1506 QDF_MON_STATUS_HE_CODING_KNOWN; 1507 1508 /* HE-data2 */ 1509 ppdu_info->rx_status.he_data2 |= 1510 QDF_MON_STATUS_TXBF_KNOWN; 1511 1512 /* HE-data3 */ 1513 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1514 HE_SIG_B2_OFDMA_INFO_0, STA_MCS); 1515 ppdu_info->rx_status.mcs = value; 1516 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1517 ppdu_info->rx_status.he_data3 |= value; 1518 1519 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1520 HE_SIG_B2_OFDMA_INFO_0, STA_DCM); 1521 he_dcm = value; 1522 value = value << QDF_MON_STATUS_DCM_SHIFT; 1523 ppdu_info->rx_status.he_data3 |= value; 1524 1525 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1526 HE_SIG_B2_OFDMA_INFO_0, STA_CODING); 1527 value = value << QDF_MON_STATUS_CODING_SHIFT; 1528 ppdu_info->rx_status.he_data3 |= value; 1529 1530 /* HE-data4 */ 1531 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1532 HE_SIG_B2_OFDMA_INFO_0, STA_ID); 1533 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1534 ppdu_info->rx_status.he_data4 |= value; 1535 1536 /* HE-data5 */ 1537 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1538 HE_SIG_B2_OFDMA_INFO_0, TXBF); 1539 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1540 ppdu_info->rx_status.he_data5 |= value; 1541 1542 /* HE-data6 */ 1543 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1544 HE_SIG_B2_OFDMA_INFO_0, NSTS); 1545 /* value n indicates n+1 spatial streams */ 1546 value++; 1547 ppdu_info->rx_status.nss = value; 1548 ppdu_info->rx_status.he_data6 |= value; 1549 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1550 break; 1551 } 1552 case WIFIPHYRX_RSSI_LEGACY_E: 1553 { 1554 uint8_t reception_type; 1555 int8_t rssi_value; 1556 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 1557 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 1558 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 1559 1560 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 1561 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 1562 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 1563 ppdu_info->rx_status.he_re = 0; 1564 1565 reception_type = HAL_RX_GET(rx_tlv, 1566 PHYRX_RSSI_LEGACY_0, 1567 RECEPTION_TYPE); 1568 switch (reception_type) { 1569 case QDF_RECEPTION_TYPE_ULOFMDA: 1570 ppdu_info->rx_status.reception_type = 1571 HAL_RX_TYPE_MU_OFDMA; 1572 ppdu_info->rx_status.ulofdma_flag = 1; 1573 ppdu_info->rx_status.he_data1 = 1574 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1575 break; 1576 case QDF_RECEPTION_TYPE_ULMIMO: 1577 ppdu_info->rx_status.reception_type = 1578 HAL_RX_TYPE_MU_MIMO; 1579 ppdu_info->rx_status.he_data1 = 1580 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1581 break; 1582 default: 1583 ppdu_info->rx_status.reception_type = 1584 HAL_RX_TYPE_SU; 1585 break; 1586 } 1587 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 1588 rssi_value = HAL_RX_GET(rssi_info_tlv, 1589 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 1590 ppdu_info->rx_status.rssi[0] = rssi_value; 1591 dp_nofl_debug("RSSI_PRI20_CHAIN0: %d\n", rssi_value); 1592 1593 rssi_value = HAL_RX_GET(rssi_info_tlv, 1594 RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1); 1595 ppdu_info->rx_status.rssi[1] = rssi_value; 1596 dp_nofl_debug("RSSI_PRI20_CHAIN1: %d\n", rssi_value); 1597 1598 rssi_value = HAL_RX_GET(rssi_info_tlv, 1599 RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2); 1600 ppdu_info->rx_status.rssi[2] = rssi_value; 1601 dp_nofl_debug("RSSI_PRI20_CHAIN2: %d\n", rssi_value); 1602 1603 rssi_value = HAL_RX_GET(rssi_info_tlv, 1604 RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3); 1605 ppdu_info->rx_status.rssi[3] = rssi_value; 1606 dp_nofl_debug("RSSI_PRI20_CHAIN3: %d\n", rssi_value); 1607 1608 rssi_value = HAL_RX_GET(rssi_info_tlv, 1609 RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4); 1610 ppdu_info->rx_status.rssi[4] = rssi_value; 1611 dp_nofl_debug("RSSI_PRI20_CHAIN4: %d\n", rssi_value); 1612 1613 rssi_value = HAL_RX_GET(rssi_info_tlv, 1614 RECEIVE_RSSI_INFO_10, 1615 RSSI_PRI20_CHAIN5); 1616 ppdu_info->rx_status.rssi[5] = rssi_value; 1617 dp_nofl_debug("RSSI_PRI20_CHAIN5: %d\n", rssi_value); 1618 1619 rssi_value = HAL_RX_GET(rssi_info_tlv, 1620 RECEIVE_RSSI_INFO_12, 1621 RSSI_PRI20_CHAIN6); 1622 ppdu_info->rx_status.rssi[6] = rssi_value; 1623 dp_nofl_debug("RSSI_PRI20_CHAIN6: %d\n", rssi_value); 1624 1625 rssi_value = HAL_RX_GET(rssi_info_tlv, 1626 RECEIVE_RSSI_INFO_14, 1627 RSSI_PRI20_CHAIN7); 1628 ppdu_info->rx_status.rssi[7] = rssi_value; 1629 dp_nofl_debug("RSSI_PRI20_CHAIN7: %d\n", rssi_value); 1630 break; 1631 } 1632 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1633 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1634 ppdu_info); 1635 break; 1636 case WIFIRX_HEADER_E: 1637 { 1638 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 1639 1640 if (ppdu_info->fcs_ok_cnt >= 1641 HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) { 1642 hal_err("Number of MPDUs(%d) per status buff exceeded", 1643 ppdu_info->fcs_ok_cnt); 1644 break; 1645 } 1646 1647 /* Update first_msdu_payload for every mpdu and increment 1648 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 1649 */ 1650 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload = 1651 rx_tlv; 1652 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len; 1653 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1654 ppdu_info->msdu_info.payload_len = tlv_len; 1655 ppdu_info->user_id = user_id; 1656 ppdu_info->hdr_len = tlv_len; 1657 ppdu_info->data = rx_tlv; 1658 ppdu_info->data += 4; 1659 1660 /* for every RX_HEADER TLV increment mpdu_cnt */ 1661 com_info->mpdu_cnt++; 1662 return HAL_TLV_STATUS_HEADER; 1663 } 1664 case WIFIRX_MPDU_START_E: 1665 { 1666 uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv; 1667 uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_mpdu_start); 1668 uint8_t filter_category = 0; 1669 1670 hal_update_frame_type_cnt(rx_mpdu_start, ppdu_info); 1671 1672 ppdu_info->nac_info.fc_valid = 1673 HAL_RX_GET_FC_VALID(rx_mpdu_start); 1674 1675 ppdu_info->nac_info.to_ds_flag = 1676 HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start); 1677 1678 ppdu_info->nac_info.frame_control = 1679 HAL_RX_GET(rx_mpdu_start, 1680 RX_MPDU_INFO_14, 1681 MPDU_FRAME_CONTROL_FIELD); 1682 1683 ppdu_info->sw_frame_group_id = 1684 HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start); 1685 1686 ppdu_info->rx_user_status[user_id].sw_peer_id = 1687 HAL_RX_GET_SW_PEER_ID(rx_mpdu_start); 1688 1689 hal_update_rx_ctrl_frame_stats(ppdu_info, user_id); 1690 1691 if (ppdu_info->sw_frame_group_id == 1692 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 1693 ppdu_info->rx_status.frame_control_info_valid = 1694 ppdu_info->nac_info.fc_valid; 1695 ppdu_info->rx_status.frame_control = 1696 ppdu_info->nac_info.frame_control; 1697 } 1698 1699 hal_get_mac_addr1(rx_mpdu_start, 1700 ppdu_info); 1701 1702 ppdu_info->nac_info.mac_addr2_valid = 1703 HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start); 1704 1705 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1706 HAL_RX_GET(rx_mpdu_start, 1707 RX_MPDU_INFO_16, 1708 MAC_ADDR_AD2_15_0); 1709 1710 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1711 HAL_RX_GET(rx_mpdu_start, 1712 RX_MPDU_INFO_17, 1713 MAC_ADDR_AD2_47_16); 1714 1715 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1716 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1717 ppdu_info->rx_status.ppdu_len = 1718 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1719 MPDU_LENGTH); 1720 } else { 1721 ppdu_info->rx_status.ppdu_len += 1722 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1723 MPDU_LENGTH); 1724 } 1725 1726 filter_category = 1727 HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start); 1728 1729 if (filter_category == 0) 1730 ppdu_info->rx_status.rxpcu_filter_pass = 1; 1731 else if (filter_category == 1) 1732 ppdu_info->rx_status.monitor_direct_used = 1; 1733 1734 ppdu_info->nac_info.mcast_bcast = 1735 HAL_RX_GET(rx_mpdu_start, 1736 RX_MPDU_INFO_13, 1737 MCAST_BCAST); 1738 break; 1739 } 1740 case WIFIRX_MPDU_END_E: 1741 ppdu_info->user_id = user_id; 1742 ppdu_info->fcs_err = 1743 HAL_RX_GET(rx_tlv, RX_MPDU_END_1, 1744 FCS_ERR); 1745 return HAL_TLV_STATUS_MPDU_END; 1746 case WIFIRX_MSDU_END_E: 1747 if (user_id < HAL_MAX_UL_MU_USERS) { 1748 ppdu_info->rx_msdu_info[user_id].cce_metadata = 1749 HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv); 1750 ppdu_info->rx_msdu_info[user_id].fse_metadata = 1751 HAL_RX_MSDU_END_FSE_METADATA_GET(rx_tlv); 1752 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 1753 HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(rx_tlv); 1754 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 1755 HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(rx_tlv); 1756 ppdu_info->rx_msdu_info[user_id].flow_idx = 1757 HAL_RX_MSDU_END_FLOW_IDX_GET(rx_tlv); 1758 } 1759 return HAL_TLV_STATUS_MSDU_END; 1760 case 0: 1761 return HAL_TLV_STATUS_PPDU_DONE; 1762 1763 default: 1764 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1765 unhandled = false; 1766 else 1767 unhandled = true; 1768 break; 1769 } 1770 1771 if (!unhandled) 1772 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1773 "%s TLV type: %d, TLV len:%d %s", 1774 __func__, tlv_tag, tlv_len, 1775 unhandled == true ? "unhandled" : ""); 1776 1777 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1778 } 1779 1780 /** 1781 * hal_tx_comp_get_release_reason_generic_li() - TQM Release reason 1782 * @hal_desc: completion ring descriptor pointer 1783 * 1784 * This function will return the type of pointer - buffer or descriptor 1785 * 1786 * Return: buffer type 1787 */ 1788 static inline uint8_t hal_tx_comp_get_release_reason_generic_li(void *hal_desc) 1789 { 1790 uint32_t comp_desc = 1791 *(uint32_t *)(((uint8_t *)hal_desc) + 1792 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 1793 1794 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 1795 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 1796 } 1797 1798 /** 1799 * hal_get_wbm_internal_error_generic_li() - is WBM internal error 1800 * @hal_desc: completion ring descriptor pointer 1801 * 1802 * This function will return 0 or 1 - is it WBM internal error or not 1803 * 1804 * Return: uint8_t 1805 */ 1806 static inline uint8_t hal_get_wbm_internal_error_generic_li(void *hal_desc) 1807 { 1808 uint32_t comp_desc = 1809 *(uint32_t *)(((uint8_t *)hal_desc) + 1810 HAL_WBM_INTERNAL_ERROR_OFFSET); 1811 1812 return (comp_desc & HAL_WBM_INTERNAL_ERROR_MASK) >> 1813 HAL_WBM_INTERNAL_ERROR_LSB; 1814 } 1815 1816 /** 1817 * hal_rx_dump_mpdu_start_tlv_generic_li: dump RX mpdu_start TLV in structured 1818 * human readable format. 1819 * @mpdu_start: pointer the rx_attention TLV in pkt. 1820 * @dbg_level: log level. 1821 * 1822 * Return: void 1823 */ 1824 static inline void hal_rx_dump_mpdu_start_tlv_generic_li(void *mpdustart, 1825 uint8_t dbg_level) 1826 { 1827 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 1828 struct rx_mpdu_info *mpdu_info = 1829 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 1830 1831 hal_verbose_debug( 1832 "rx_mpdu_start tlv (1/5) - " 1833 "rxpcu_mpdu_filter_in_category: %x " 1834 "sw_frame_group_id: %x " 1835 "ndp_frame: %x " 1836 "phy_err: %x " 1837 "phy_err_during_mpdu_header: %x " 1838 "protocol_version_err: %x " 1839 "ast_based_lookup_valid: %x " 1840 "phy_ppdu_id: %x " 1841 "ast_index: %x " 1842 "sw_peer_id: %x " 1843 "mpdu_frame_control_valid: %x " 1844 "mpdu_duration_valid: %x " 1845 "mac_addr_ad1_valid: %x " 1846 "mac_addr_ad2_valid: %x " 1847 "mac_addr_ad3_valid: %x " 1848 "mac_addr_ad4_valid: %x " 1849 "mpdu_sequence_control_valid: %x " 1850 "mpdu_qos_control_valid: %x " 1851 "mpdu_ht_control_valid: %x " 1852 "frame_encryption_info_valid: %x ", 1853 mpdu_info->rxpcu_mpdu_filter_in_category, 1854 mpdu_info->sw_frame_group_id, 1855 mpdu_info->ndp_frame, 1856 mpdu_info->phy_err, 1857 mpdu_info->phy_err_during_mpdu_header, 1858 mpdu_info->protocol_version_err, 1859 mpdu_info->ast_based_lookup_valid, 1860 mpdu_info->phy_ppdu_id, 1861 mpdu_info->ast_index, 1862 mpdu_info->sw_peer_id, 1863 mpdu_info->mpdu_frame_control_valid, 1864 mpdu_info->mpdu_duration_valid, 1865 mpdu_info->mac_addr_ad1_valid, 1866 mpdu_info->mac_addr_ad2_valid, 1867 mpdu_info->mac_addr_ad3_valid, 1868 mpdu_info->mac_addr_ad4_valid, 1869 mpdu_info->mpdu_sequence_control_valid, 1870 mpdu_info->mpdu_qos_control_valid, 1871 mpdu_info->mpdu_ht_control_valid, 1872 mpdu_info->frame_encryption_info_valid); 1873 1874 hal_verbose_debug( 1875 "rx_mpdu_start tlv (2/5) - " 1876 "fr_ds: %x " 1877 "to_ds: %x " 1878 "encrypted: %x " 1879 "mpdu_retry: %x " 1880 "mpdu_sequence_number: %x " 1881 "epd_en: %x " 1882 "all_frames_shall_be_encrypted: %x " 1883 "encrypt_type: %x " 1884 "mesh_sta: %x " 1885 "bssid_hit: %x " 1886 "bssid_number: %x " 1887 "tid: %x " 1888 "pn_31_0: %x " 1889 "pn_63_32: %x " 1890 "pn_95_64: %x " 1891 "pn_127_96: %x " 1892 "peer_meta_data: %x " 1893 "rxpt_classify_info.reo_destination_indication: %x " 1894 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x " 1895 "rx_reo_queue_desc_addr_31_0: %x ", 1896 mpdu_info->fr_ds, 1897 mpdu_info->to_ds, 1898 mpdu_info->encrypted, 1899 mpdu_info->mpdu_retry, 1900 mpdu_info->mpdu_sequence_number, 1901 mpdu_info->epd_en, 1902 mpdu_info->all_frames_shall_be_encrypted, 1903 mpdu_info->encrypt_type, 1904 mpdu_info->mesh_sta, 1905 mpdu_info->bssid_hit, 1906 mpdu_info->bssid_number, 1907 mpdu_info->tid, 1908 mpdu_info->pn_31_0, 1909 mpdu_info->pn_63_32, 1910 mpdu_info->pn_95_64, 1911 mpdu_info->pn_127_96, 1912 mpdu_info->peer_meta_data, 1913 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 1914 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 1915 mpdu_info->rx_reo_queue_desc_addr_31_0); 1916 1917 hal_verbose_debug( 1918 "rx_mpdu_start tlv (3/5) - " 1919 "rx_reo_queue_desc_addr_39_32: %x " 1920 "receive_queue_number: %x " 1921 "pre_delim_err_warning: %x " 1922 "first_delim_err: %x " 1923 "key_id_octet: %x " 1924 "new_peer_entry: %x " 1925 "decrypt_needed: %x " 1926 "decap_type: %x " 1927 "rx_insert_vlan_c_tag_padding: %x " 1928 "rx_insert_vlan_s_tag_padding: %x " 1929 "strip_vlan_c_tag_decap: %x " 1930 "strip_vlan_s_tag_decap: %x " 1931 "pre_delim_count: %x " 1932 "ampdu_flag: %x " 1933 "bar_frame: %x " 1934 "mpdu_length: %x " 1935 "first_mpdu: %x " 1936 "mcast_bcast: %x " 1937 "ast_index_not_found: %x " 1938 "ast_index_timeout: %x ", 1939 mpdu_info->rx_reo_queue_desc_addr_39_32, 1940 mpdu_info->receive_queue_number, 1941 mpdu_info->pre_delim_err_warning, 1942 mpdu_info->first_delim_err, 1943 mpdu_info->key_id_octet, 1944 mpdu_info->new_peer_entry, 1945 mpdu_info->decrypt_needed, 1946 mpdu_info->decap_type, 1947 mpdu_info->rx_insert_vlan_c_tag_padding, 1948 mpdu_info->rx_insert_vlan_s_tag_padding, 1949 mpdu_info->strip_vlan_c_tag_decap, 1950 mpdu_info->strip_vlan_s_tag_decap, 1951 mpdu_info->pre_delim_count, 1952 mpdu_info->ampdu_flag, 1953 mpdu_info->bar_frame, 1954 mpdu_info->mpdu_length, 1955 mpdu_info->first_mpdu, 1956 mpdu_info->mcast_bcast, 1957 mpdu_info->ast_index_not_found, 1958 mpdu_info->ast_index_timeout); 1959 1960 hal_verbose_debug( 1961 "rx_mpdu_start tlv (4/5) - " 1962 "power_mgmt: %x " 1963 "non_qos: %x " 1964 "null_data: %x " 1965 "mgmt_type: %x " 1966 "ctrl_type: %x " 1967 "more_data: %x " 1968 "eosp: %x " 1969 "fragment_flag: %x " 1970 "order: %x " 1971 "u_apsd_trigger: %x " 1972 "encrypt_required: %x " 1973 "directed: %x " 1974 "mpdu_frame_control_field: %x " 1975 "mpdu_duration_field: %x " 1976 "mac_addr_ad1_31_0: %x " 1977 "mac_addr_ad1_47_32: %x " 1978 "mac_addr_ad2_15_0: %x " 1979 "mac_addr_ad2_47_16: %x " 1980 "mac_addr_ad3_31_0: %x " 1981 "mac_addr_ad3_47_32: %x ", 1982 mpdu_info->power_mgmt, 1983 mpdu_info->non_qos, 1984 mpdu_info->null_data, 1985 mpdu_info->mgmt_type, 1986 mpdu_info->ctrl_type, 1987 mpdu_info->more_data, 1988 mpdu_info->eosp, 1989 mpdu_info->fragment_flag, 1990 mpdu_info->order, 1991 mpdu_info->u_apsd_trigger, 1992 mpdu_info->encrypt_required, 1993 mpdu_info->directed, 1994 mpdu_info->mpdu_frame_control_field, 1995 mpdu_info->mpdu_duration_field, 1996 mpdu_info->mac_addr_ad1_31_0, 1997 mpdu_info->mac_addr_ad1_47_32, 1998 mpdu_info->mac_addr_ad2_15_0, 1999 mpdu_info->mac_addr_ad2_47_16, 2000 mpdu_info->mac_addr_ad3_31_0, 2001 mpdu_info->mac_addr_ad3_47_32); 2002 2003 hal_verbose_debug( 2004 "rx_mpdu_start tlv (5/5) - " 2005 "mpdu_sequence_control_field: %x " 2006 "mac_addr_ad4_31_0: %x " 2007 "mac_addr_ad4_47_32: %x " 2008 "mpdu_qos_control_field: %x " 2009 "mpdu_ht_control_field: %x ", 2010 mpdu_info->mpdu_sequence_control_field, 2011 mpdu_info->mac_addr_ad4_31_0, 2012 mpdu_info->mac_addr_ad4_47_32, 2013 mpdu_info->mpdu_qos_control_field, 2014 mpdu_info->mpdu_ht_control_field); 2015 } 2016 2017 /** 2018 * hal_tx_set_pcp_tid_map_generic_li() - Configure default PCP to TID map table 2019 * @soc: HAL SoC context 2020 * @map: PCP-TID mapping table 2021 * 2022 * PCP are mapped to 8 TID values using TID values programmed 2023 * in one set of mapping registers PCP_TID_MAP_<0 to 6> 2024 * The mapping register has TID mapping for 8 PCP values 2025 * 2026 * Return: none 2027 */ 2028 static void hal_tx_set_pcp_tid_map_generic_li(struct hal_soc *soc, uint8_t *map) 2029 { 2030 uint32_t addr, value; 2031 2032 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2033 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2034 2035 value = (map[0] | 2036 (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | 2037 (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | 2038 (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | 2039 (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | 2040 (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | 2041 (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | 2042 (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); 2043 2044 HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2045 } 2046 2047 /** 2048 * hal_tx_update_pcp_tid_generic_li() - Update the pcp tid map table with 2049 * value received from user-space 2050 * @soc: HAL SoC context 2051 * @pcp: pcp value 2052 * @tid : tid value 2053 * 2054 * Return: void 2055 */ 2056 static void 2057 hal_tx_update_pcp_tid_generic_li(struct hal_soc *soc, 2058 uint8_t pcp, uint8_t tid) 2059 { 2060 uint32_t addr, value, regval; 2061 2062 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2063 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2064 2065 value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); 2066 2067 /* Read back previous PCP TID config and update 2068 * with new config. 2069 */ 2070 regval = HAL_REG_READ(soc, addr); 2071 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); 2072 regval |= value; 2073 2074 HAL_REG_WRITE(soc, addr, 2075 (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2076 } 2077 2078 /** 2079 * hal_tx_update_tidmap_prty_generic_li() - Update the tid map priority 2080 * @soc: HAL SoC context 2081 * @val: priority value 2082 * 2083 * Return: void 2084 */ 2085 static 2086 void hal_tx_update_tidmap_prty_generic_li(struct hal_soc *soc, uint8_t value) 2087 { 2088 uint32_t addr; 2089 2090 addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( 2091 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2092 2093 HAL_REG_WRITE(soc, addr, 2094 (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); 2095 } 2096 2097 /** 2098 * hal_rx_msdu_packet_metadata_get(): API to get the 2099 * msdu information from rx_msdu_end TLV 2100 * 2101 * @ buf: pointer to the start of RX PKT TLV headers 2102 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 2103 */ 2104 static void 2105 hal_rx_msdu_packet_metadata_get_generic_li(uint8_t *buf, 2106 void *pkt_msdu_metadata) 2107 { 2108 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2109 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 2110 struct hal_rx_msdu_metadata *msdu_metadata = 2111 (struct hal_rx_msdu_metadata *)pkt_msdu_metadata; 2112 2113 msdu_metadata->l3_hdr_pad = 2114 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 2115 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 2116 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 2117 msdu_metadata->sa_sw_peer_id = 2118 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 2119 } 2120 2121 /** 2122 * hal_rx_msdu_end_offset_get_generic(): API to get the 2123 * msdu_end structure offset rx_pkt_tlv structure 2124 * 2125 * NOTE: API returns offset of msdu_end TLV from structure 2126 * rx_pkt_tlvs 2127 */ 2128 static uint32_t hal_rx_msdu_end_offset_get_generic(void) 2129 { 2130 return RX_PKT_TLV_OFFSET(msdu_end_tlv); 2131 } 2132 2133 /** 2134 * hal_rx_attn_offset_get_generic(): API to get the 2135 * msdu_end structure offset rx_pkt_tlv structure 2136 * 2137 * NOTE: API returns offset of attn TLV from structure 2138 * rx_pkt_tlvs 2139 */ 2140 static uint32_t hal_rx_attn_offset_get_generic(void) 2141 { 2142 return RX_PKT_TLV_OFFSET(attn_tlv); 2143 } 2144 2145 /** 2146 * hal_rx_msdu_start_offset_get_generic(): API to get the 2147 * msdu_start structure offset rx_pkt_tlv structure 2148 * 2149 * NOTE: API returns offset of attn TLV from structure 2150 * rx_pkt_tlvs 2151 */ 2152 static uint32_t hal_rx_msdu_start_offset_get_generic(void) 2153 { 2154 return RX_PKT_TLV_OFFSET(msdu_start_tlv); 2155 } 2156 2157 /** 2158 * hal_rx_mpdu_start_offset_get_generic(): API to get the 2159 * mpdu_start structure offset rx_pkt_tlv structure 2160 * 2161 * NOTE: API returns offset of attn TLV from structure 2162 * rx_pkt_tlvs 2163 */ 2164 static uint32_t hal_rx_mpdu_start_offset_get_generic(void) 2165 { 2166 return RX_PKT_TLV_OFFSET(mpdu_start_tlv); 2167 } 2168 2169 /** 2170 * hal_rx_mpdu_end_offset_get_generic(): API to get the 2171 * mpdu_end structure offset rx_pkt_tlv structure 2172 * 2173 * NOTE: API returns offset of attn TLV from structure 2174 * rx_pkt_tlvs 2175 */ 2176 static uint32_t hal_rx_mpdu_end_offset_get_generic(void) 2177 { 2178 return RX_PKT_TLV_OFFSET(mpdu_end_tlv); 2179 } 2180 2181 #ifndef NO_RX_PKT_HDR_TLV 2182 static uint32_t hal_rx_pkt_tlv_offset_get_generic(void) 2183 { 2184 return RX_PKT_TLV_OFFSET(pkt_hdr_tlv); 2185 } 2186 #endif 2187 2188 #if defined(QDF_BIG_ENDIAN_MACHINE) 2189 /** 2190 * hal_setup_reo_swap() - Set the swap flag for big endian machines 2191 * @soc: HAL soc handle 2192 * 2193 * Return: None 2194 */ 2195 static inline void hal_setup_reo_swap(struct hal_soc *soc) 2196 { 2197 uint32_t reg_val; 2198 2199 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR( 2200 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 2201 2202 reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, WRITE_STRUCT_SWAP, 1); 2203 reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, READ_STRUCT_SWAP, 1); 2204 2205 HAL_REG_WRITE(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR( 2206 SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val); 2207 } 2208 #else 2209 static inline void hal_setup_reo_swap(struct hal_soc *soc) 2210 { 2211 } 2212 #endif 2213 2214 /** 2215 * hal_reo_setup_generic_li - Initialize HW REO block 2216 * 2217 * @hal_soc: Opaque HAL SOC handle 2218 * @reo_params: parameters needed by HAL for REO config 2219 * @qref_reset: reset qref 2220 */ 2221 static 2222 void hal_reo_setup_generic_li(struct hal_soc *soc, void *reoparams, 2223 int qref_reset) 2224 { 2225 uint32_t reg_val; 2226 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 2227 2228 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 2229 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 2230 2231 hal_reo_config(soc, reg_val, reo_params); 2232 /* Other ring enable bits and REO_ENABLE will be set by FW */ 2233 2234 /* TODO: Setup destination ring mapping if enabled */ 2235 2236 /* TODO: Error destination ring setting is left to default. 2237 * Default setting is to send all errors to release ring. 2238 */ 2239 2240 /* Set the reo descriptor swap bits in case of BIG endian platform */ 2241 hal_setup_reo_swap(soc); 2242 2243 HAL_REG_WRITE(soc, 2244 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 2245 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2246 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 2247 2248 HAL_REG_WRITE(soc, 2249 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 2250 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2251 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 2252 2253 HAL_REG_WRITE(soc, 2254 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 2255 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2256 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 2257 2258 HAL_REG_WRITE(soc, 2259 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 2260 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2261 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 2262 2263 /* 2264 * When hash based routing is enabled, routing of the rx packet 2265 * is done based on the following value: 1 _ _ _ _ The last 4 2266 * bits are based on hash[3:0]. This means the possible values 2267 * are 0x10 to 0x1f. This value is used to look-up the 2268 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 2269 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 2270 * registers need to be configured to set-up the 16 entries to 2271 * map the hash values to a ring number. There are 3 bits per 2272 * hash entry – which are mapped as follows: 2273 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 2274 * 7: NOT_USED. 2275 */ 2276 if (reo_params->rx_hash_enabled) { 2277 if (reo_params->remap0) 2278 HAL_REG_WRITE(soc, 2279 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR( 2280 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2281 reo_params->remap0); 2282 2283 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 0x%x", 2284 HAL_REG_READ(soc, 2285 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR( 2286 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 2287 2288 HAL_REG_WRITE(soc, 2289 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 2290 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2291 reo_params->remap1); 2292 2293 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 2294 HAL_REG_READ(soc, 2295 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 2296 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 2297 2298 HAL_REG_WRITE(soc, 2299 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 2300 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2301 reo_params->remap2); 2302 2303 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 2304 HAL_REG_READ(soc, 2305 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 2306 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 2307 } 2308 2309 /* TODO: Check if the following registers shoould be setup by host: 2310 * AGING_CONTROL 2311 * HIGH_MEMORY_THRESHOLD 2312 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 2313 * GLOBAL_LINK_DESC_COUNT_CTRL 2314 */ 2315 } 2316 2317 /** 2318 * hal_setup_link_idle_list_generic_li - Setup scattered idle list using the 2319 * buffer list provided 2320 * 2321 * @hal_soc: Opaque HAL SOC handle 2322 * @scatter_bufs_base_paddr: Array of physical base addresses 2323 * @scatter_bufs_base_vaddr: Array of virtual base addresses 2324 * @num_scatter_bufs: Number of scatter buffers in the above lists 2325 * @scatter_buf_size: Size of each scatter buffer 2326 * @last_buf_end_offset: Offset to the last entry 2327 * @num_entries: Total entries of all scatter bufs 2328 * 2329 * Return: None 2330 */ 2331 static void 2332 hal_setup_link_idle_list_generic_li(struct hal_soc *soc, 2333 qdf_dma_addr_t scatter_bufs_base_paddr[], 2334 void *scatter_bufs_base_vaddr[], 2335 uint32_t num_scatter_bufs, 2336 uint32_t scatter_buf_size, 2337 uint32_t last_buf_end_offset, 2338 uint32_t num_entries) 2339 { 2340 int i; 2341 uint32_t *prev_buf_link_ptr = NULL; 2342 uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size; 2343 uint32_t val; 2344 2345 /* Link the scatter buffers */ 2346 for (i = 0; i < num_scatter_bufs; i++) { 2347 if (i > 0) { 2348 prev_buf_link_ptr[0] = 2349 scatter_bufs_base_paddr[i] & 0xffffffff; 2350 prev_buf_link_ptr[1] = HAL_SM( 2351 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2352 BASE_ADDRESS_39_32, 2353 ((uint64_t)(scatter_bufs_base_paddr[i]) 2354 >> 32)) | HAL_SM( 2355 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2356 ADDRESS_MATCH_TAG, 2357 ADDRESS_MATCH_TAG_VAL); 2358 } 2359 prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] + 2360 scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE); 2361 } 2362 2363 /* TBD: Register programming partly based on MLD & the rest based on 2364 * inputs from HW team. Not complete yet. 2365 */ 2366 2367 reg_scatter_buf_size = (scatter_buf_size - 2368 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64; 2369 reg_tot_scatter_buf_size = ((scatter_buf_size - 2370 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64; 2371 2372 HAL_REG_WRITE(soc, 2373 HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR 2374 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2375 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, 2376 SCATTER_BUFFER_SIZE, 2377 reg_scatter_buf_size) | 2378 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, 2379 LINK_DESC_IDLE_LIST_MODE, 0x1)); 2380 2381 HAL_REG_WRITE(soc, 2382 HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR 2383 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2384 HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE, 2385 SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST, 2386 reg_tot_scatter_buf_size)); 2387 2388 HAL_REG_WRITE(soc, 2389 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR 2390 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2391 scatter_bufs_base_paddr[0] & 0xffffffff); 2392 2393 HAL_REG_WRITE(soc, 2394 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR 2395 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2396 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) & 2397 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK); 2398 2399 HAL_REG_WRITE(soc, 2400 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR 2401 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2402 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2403 BASE_ADDRESS_39_32, 2404 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32)) | 2405 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2406 ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL)); 2407 2408 /* ADDRESS_MATCH_TAG field in the above register is expected to match 2409 * with the upper bits of link pointer. The above write sets this field 2410 * to zero and we are also setting the upper bits of link pointers to 2411 * zero while setting up the link list of scatter buffers above 2412 */ 2413 2414 /* Setup head and tail pointers for the idle list */ 2415 HAL_REG_WRITE(soc, 2416 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR 2417 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2418 scatter_bufs_base_paddr[num_scatter_bufs - 1] & 2419 0xffffffff); 2420 HAL_REG_WRITE(soc, 2421 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR 2422 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2423 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 2424 BUFFER_ADDRESS_39_32, 2425 ((uint64_t)(scatter_bufs_base_paddr 2426 [num_scatter_bufs - 1]) >> 32)) | 2427 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 2428 HEAD_POINTER_OFFSET, last_buf_end_offset >> 2)); 2429 2430 HAL_REG_WRITE(soc, 2431 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR 2432 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2433 scatter_bufs_base_paddr[0] & 0xffffffff); 2434 2435 HAL_REG_WRITE(soc, 2436 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR 2437 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2438 scatter_bufs_base_paddr[0] & 0xffffffff); 2439 HAL_REG_WRITE(soc, 2440 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR 2441 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2442 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 2443 BUFFER_ADDRESS_39_32, 2444 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32)) | 2445 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 2446 TAIL_POINTER_OFFSET, 0)); 2447 2448 HAL_REG_WRITE(soc, 2449 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR 2450 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2 * num_entries); 2451 2452 /* Set RING_ID_DISABLE */ 2453 val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1); 2454 2455 /* 2456 * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence 2457 * check the presence of the bit before toggling it. 2458 */ 2459 #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK 2460 val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1); 2461 #endif 2462 HAL_REG_WRITE(soc, 2463 HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR 2464 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2465 val); 2466 } 2467 2468 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 2469 /** 2470 * hal_tx_desc_set_search_type_generic_li - Set the search type value 2471 * @desc: Handle to Tx Descriptor 2472 * @search_type: search type 2473 * 0 – Normal search 2474 * 1 – Index based address search 2475 * 2 – Index based flow search 2476 * 2477 * Return: void 2478 */ 2479 static inline 2480 void hal_tx_desc_set_search_type_generic_li(void *desc, uint8_t search_type) 2481 { 2482 HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= 2483 HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); 2484 } 2485 #else 2486 static inline 2487 void hal_tx_desc_set_search_type_generic_li(void *desc, uint8_t search_type) 2488 { 2489 } 2490 2491 #endif 2492 2493 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 2494 /** 2495 * hal_tx_desc_set_search_index_generic_li - Set the search index value 2496 * @desc: Handle to Tx Descriptor 2497 * @search_index: The index that will be used for index based address or 2498 * flow search. The field is valid when 'search_type' is 2499 * 1 0r 2 2500 * 2501 * Return: void 2502 */ 2503 static inline 2504 void hal_tx_desc_set_search_index_generic_li(void *desc, uint32_t search_index) 2505 { 2506 HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= 2507 HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); 2508 } 2509 #else 2510 static inline 2511 void hal_tx_desc_set_search_index_generic_li(void *desc, uint32_t search_index) 2512 { 2513 } 2514 #endif 2515 2516 #ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 2517 /** 2518 * hal_tx_desc_set_cache_set_num_generic_li - Set the cache-set-num value 2519 * @desc: Handle to Tx Descriptor 2520 * @cache_num: Cache set number that should be used to cache the index 2521 * based search results, for address and flow search. 2522 * This value should be equal to LSB four bits of the hash value 2523 * of match data, in case of search index points to an entry 2524 * which may be used in content based search also. The value can 2525 * be anything when the entry pointed by search index will not be 2526 * used for content based search. 2527 * 2528 * Return: void 2529 */ 2530 static inline 2531 void hal_tx_desc_set_cache_set_num_generic_li(void *desc, uint8_t cache_num) 2532 { 2533 HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |= 2534 HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num); 2535 } 2536 #else 2537 static inline 2538 void hal_tx_desc_set_cache_set_num_generic_li(void *desc, uint8_t cache_num) 2539 { 2540 } 2541 #endif 2542 2543 #ifdef WLAN_SUPPORT_RX_FISA 2544 /** 2545 * hal_rx_flow_get_tuple_info_li() - Setup a flow search entry in HW FST 2546 * @fst: Pointer to the Rx Flow Search Table 2547 * @hal_hash: HAL 5 tuple hash 2548 * @tuple_info: 5-tuple info of the flow returned to the caller 2549 * 2550 * Return: Success/Failure 2551 */ 2552 static void * 2553 hal_rx_flow_get_tuple_info_li(uint8_t *rx_fst, uint32_t hal_hash, 2554 uint8_t *flow_tuple_info) 2555 { 2556 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 2557 void *hal_fse = NULL; 2558 struct hal_flow_tuple_info *tuple_info 2559 = (struct hal_flow_tuple_info *)flow_tuple_info; 2560 2561 hal_fse = (uint8_t *)fst->base_vaddr + 2562 (hal_hash * HAL_RX_FST_ENTRY_SIZE); 2563 2564 if (!hal_fse || !tuple_info) 2565 return NULL; 2566 2567 if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY_9, VALID)) 2568 return NULL; 2569 2570 tuple_info->src_ip_127_96 = 2571 qdf_ntohl(HAL_GET_FLD(hal_fse, 2572 RX_FLOW_SEARCH_ENTRY_0, 2573 SRC_IP_127_96)); 2574 tuple_info->src_ip_95_64 = 2575 qdf_ntohl(HAL_GET_FLD(hal_fse, 2576 RX_FLOW_SEARCH_ENTRY_1, 2577 SRC_IP_95_64)); 2578 tuple_info->src_ip_63_32 = 2579 qdf_ntohl(HAL_GET_FLD(hal_fse, 2580 RX_FLOW_SEARCH_ENTRY_2, 2581 SRC_IP_63_32)); 2582 tuple_info->src_ip_31_0 = 2583 qdf_ntohl(HAL_GET_FLD(hal_fse, 2584 RX_FLOW_SEARCH_ENTRY_3, 2585 SRC_IP_31_0)); 2586 tuple_info->dest_ip_127_96 = 2587 qdf_ntohl(HAL_GET_FLD(hal_fse, 2588 RX_FLOW_SEARCH_ENTRY_4, 2589 DEST_IP_127_96)); 2590 tuple_info->dest_ip_95_64 = 2591 qdf_ntohl(HAL_GET_FLD(hal_fse, 2592 RX_FLOW_SEARCH_ENTRY_5, 2593 DEST_IP_95_64)); 2594 tuple_info->dest_ip_63_32 = 2595 qdf_ntohl(HAL_GET_FLD(hal_fse, 2596 RX_FLOW_SEARCH_ENTRY_6, 2597 DEST_IP_63_32)); 2598 tuple_info->dest_ip_31_0 = 2599 qdf_ntohl(HAL_GET_FLD(hal_fse, 2600 RX_FLOW_SEARCH_ENTRY_7, 2601 DEST_IP_31_0)); 2602 tuple_info->dest_port = HAL_GET_FLD(hal_fse, 2603 RX_FLOW_SEARCH_ENTRY_8, 2604 DEST_PORT); 2605 tuple_info->src_port = HAL_GET_FLD(hal_fse, 2606 RX_FLOW_SEARCH_ENTRY_8, 2607 SRC_PORT); 2608 tuple_info->l4_protocol = HAL_GET_FLD(hal_fse, 2609 RX_FLOW_SEARCH_ENTRY_9, 2610 L4_PROTOCOL); 2611 2612 return hal_fse; 2613 } 2614 2615 /** 2616 * hal_rx_flow_delete_entry_li() - Setup a flow search entry in HW FST 2617 * @fst: Pointer to the Rx Flow Search Table 2618 * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST 2619 * 2620 * Return: Success/Failure 2621 */ 2622 static QDF_STATUS 2623 hal_rx_flow_delete_entry_li(uint8_t *rx_fst, void *hal_rx_fse) 2624 { 2625 uint8_t *fse = (uint8_t *)hal_rx_fse; 2626 2627 if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID)) 2628 return QDF_STATUS_E_NOENT; 2629 2630 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 2631 2632 return QDF_STATUS_SUCCESS; 2633 } 2634 2635 /** 2636 * hal_rx_fst_get_fse_size_li() - Retrieve the size of each entry 2637 * 2638 * Return: size of each entry/flow in Rx FST 2639 */ 2640 static inline uint32_t 2641 hal_rx_fst_get_fse_size_li(void) 2642 { 2643 return HAL_RX_FST_ENTRY_SIZE; 2644 } 2645 #else 2646 static inline void * 2647 hal_rx_flow_get_tuple_info_li(uint8_t *rx_fst, uint32_t hal_hash, 2648 uint8_t *flow_tuple_info) 2649 { 2650 return NULL; 2651 } 2652 2653 static inline QDF_STATUS 2654 hal_rx_flow_delete_entry_li(uint8_t *rx_fst, void *hal_rx_fse) 2655 { 2656 return QDF_STATUS_SUCCESS; 2657 } 2658 2659 static inline uint32_t 2660 hal_rx_fst_get_fse_size_li(void) 2661 { 2662 return 0; 2663 } 2664 #endif /* WLAN_SUPPORT_RX_FISA */ 2665 2666 /** 2667 * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field 2668 * 2669 * @nbuf: Network buffer 2670 * Returns: rx more fragment bit 2671 * 2672 */ 2673 static uint16_t hal_rx_get_frame_ctrl_field_li(uint8_t *buf) 2674 { 2675 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2676 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2677 uint16_t frame_ctrl = 0; 2678 2679 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 2680 2681 return frame_ctrl; 2682 } 2683 #endif /* _HAL_LI_GENERIC_API_H_ */ 2684