1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_LI_GENERIC_API_H_ 21 #define _HAL_LI_GENERIC_API_H_ 22 23 #include "hal_tx.h" 24 #include "hal_li_tx.h" 25 #include "hal_li_rx.h" 26 27 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) \ 28 (_HAL_MS((*_OFFSET_TO_WORD_PTR(wbm_desc, \ 29 WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET)), \ 30 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK, \ 31 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB)) 32 33 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) \ 34 (_HAL_MS((*_OFFSET_TO_WORD_PTR(wbm_desc, \ 35 WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET)), \ 36 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK, \ 37 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB)) 38 39 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 40 (((*(((uint32_t *)wbm_desc) + \ 41 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 42 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 43 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 44 45 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 46 (((*(((uint32_t *)wbm_desc) + \ 47 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 48 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 49 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 50 51 /** 52 * hal_rx_wbm_err_info_get_generic_li() - Retrieves WBM error code and 53 * reason and save it to hal_wbm_err_desc_info structure passed 54 * by caller 55 * @wbm_desc: wbm ring descriptor 56 * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 57 * 58 * Return: void 59 */ 60 static inline 61 void hal_rx_wbm_err_info_get_generic_li(void *wbm_desc, 62 void *wbm_er_info1) 63 { 64 struct hal_wbm_err_desc_info *wbm_er_info = 65 (struct hal_wbm_err_desc_info *)wbm_er_info1; 66 67 wbm_er_info->wbm_err_src = HAL_WBM2SW_RELEASE_SRC_GET(wbm_desc); 68 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 69 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 70 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 71 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 72 } 73 74 #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY) 75 static inline void 76 hal_tx_comp_get_buffer_timestamp_li(void *desc, 77 struct hal_tx_completion_status *ts) 78 { 79 ts->buffer_timestamp = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 80 BUFFER_TIMESTAMP); 81 } 82 #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */ 83 static inline void 84 hal_tx_comp_get_buffer_timestamp_li(void *desc, 85 struct hal_tx_completion_status *ts) 86 { 87 } 88 #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */ 89 90 #ifdef QCA_UNDECODED_METADATA_SUPPORT 91 static inline void 92 hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv, 93 struct hal_rx_ppdu_info *ppdu_info){ 94 switch (hal->target_type) { 95 case TARGET_TYPE_QCN9000: 96 ppdu_info->rx_status.phyrx_abort = 97 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, 98 PHYRX_ABORT_REQUEST_INFO_VALID); 99 ppdu_info->rx_status.phyrx_abort_reason = 100 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_11, 101 PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON); 102 break; 103 default: 104 break; 105 } 106 } 107 108 static inline void 109 hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info, 110 uint8_t *ht_sig_info) 111 { 112 ppdu_info->rx_status.ht_length = 113 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_0, LENGTH); 114 ppdu_info->rx_status.smoothing = 115 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, SMOOTHING); 116 ppdu_info->rx_status.not_sounding = 117 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, NOT_SOUNDING); 118 ppdu_info->rx_status.aggregation = 119 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, AGGREGATION); 120 ppdu_info->rx_status.ht_stbc = 121 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, STBC); 122 ppdu_info->rx_status.ht_crc = 123 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, CRC); 124 } 125 126 static inline void 127 hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, 128 uint8_t *l_sig_a_info) 129 { 130 ppdu_info->rx_status.l_sig_length = 131 HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, LENGTH); 132 ppdu_info->rx_status.l_sig_a_parity = 133 HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PARITY); 134 ppdu_info->rx_status.l_sig_a_pkt_type = 135 HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PKT_TYPE); 136 ppdu_info->rx_status.l_sig_a_implicit_sounding = 137 HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, 138 CAPTURED_IMPLICIT_SOUNDING); 139 } 140 141 static inline void 142 hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, 143 uint8_t *vht_sig_a_info) 144 { 145 ppdu_info->rx_status.vht_no_txop_ps = 146 HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, 147 TXOP_PS_NOT_ALLOWED); 148 ppdu_info->rx_status.vht_crc = 149 HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, CRC); 150 } 151 152 static inline void 153 hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info, 154 uint8_t *he_sig_a_su_info) { 155 ppdu_info->rx_status.he_crc = 156 HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, CRC); 157 } 158 159 static inline void 160 hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info, 161 uint8_t *he_sig_a_mu_dl_info) { 162 ppdu_info->rx_status.he_crc = 163 HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, CRC); 164 } 165 #else 166 static inline void 167 hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv, 168 struct hal_rx_ppdu_info *ppdu_info) 169 { 170 } 171 172 static inline void 173 hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info, 174 uint8_t *ht_sig_info) 175 { 176 } 177 178 static inline void 179 hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, 180 uint8_t *l_sig_a_info) 181 { 182 } 183 184 static inline void 185 hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, 186 uint8_t *vht_sig_a_info) 187 { 188 } 189 190 static inline void 191 hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info, 192 uint8_t *he_sig_a_su_info) 193 { 194 } 195 196 static inline void 197 hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info, 198 uint8_t *he_sig_a_mu_dl_info) 199 { 200 } 201 #endif /* QCA_UNDECODED_METADATA_SUPPORT */ 202 203 /** 204 * hal_tx_comp_get_status_generic_li() - Get tx completion status 205 * @desc: tx descriptor 206 * @ts1: completion ring Tx status 207 * @hal: hal_soc object 208 * 209 * This function will parse the WBM completion descriptor and populate in 210 * HAL structure 211 * 212 * Return: none 213 */ 214 static inline void 215 hal_tx_comp_get_status_generic_li(void *desc, void *ts1, 216 struct hal_soc *hal) 217 { 218 uint8_t rate_stats_valid = 0; 219 uint32_t rate_stats = 0; 220 struct hal_tx_completion_status *ts = 221 (struct hal_tx_completion_status *)ts1; 222 223 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 224 TQM_STATUS_NUMBER); 225 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 226 ACK_FRAME_RSSI); 227 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 228 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 229 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 230 MSDU_PART_OF_AMSDU); 231 232 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 233 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 234 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 235 TRANSMIT_COUNT); 236 237 rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS); 238 239 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 240 TX_RATE_STATS_INFO_VALID, rate_stats); 241 242 ts->valid = rate_stats_valid; 243 244 if (rate_stats_valid) { 245 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 246 rate_stats); 247 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 248 TRANSMIT_PKT_TYPE, rate_stats); 249 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 250 TRANSMIT_STBC, rate_stats); 251 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 252 rate_stats); 253 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 254 rate_stats); 255 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 256 rate_stats); 257 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 258 rate_stats); 259 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 260 rate_stats); 261 } 262 263 ts->release_src = hal_tx_comp_get_buffer_source( 264 hal_soc_to_hal_soc_handle(hal), 265 desc); 266 ts->status = hal_tx_comp_get_release_reason( 267 desc, 268 hal_soc_to_hal_soc_handle(hal)); 269 270 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 271 TX_RATE_STATS_INFO_TX_RATE_STATS); 272 273 hal_tx_comp_get_buffer_timestamp_li(desc, ts); 274 } 275 276 /** 277 * hal_tx_desc_set_buf_addr_generic_li() - Fill Buffer Address 278 * information in Tx Descriptor 279 * @desc: Handle to Tx Descriptor 280 * @paddr: Physical Address 281 * @rbm_id: Return Buffer Manager ID 282 * @desc_id: Descriptor ID 283 * @type: 0 - Address points to a MSDU buffer 284 * 1 - Address points to MSDU extension descriptor 285 * 286 * Return: void 287 */ 288 static inline void 289 hal_tx_desc_set_buf_addr_generic_li(void *desc, dma_addr_t paddr, 290 uint8_t rbm_id, uint32_t desc_id, 291 uint8_t type) 292 { 293 /* Set buffer_addr_info.buffer_addr_31_0 */ 294 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, 295 BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 296 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 297 298 /* Set buffer_addr_info.buffer_addr_39_32 */ 299 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 300 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 301 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 302 (((uint64_t)paddr) >> 32)); 303 304 /* Set buffer_addr_info.return_buffer_manager = rbm id */ 305 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 306 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 307 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, 308 RETURN_BUFFER_MANAGER, rbm_id); 309 310 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 311 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 312 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 313 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, 314 desc_id); 315 316 /* Set Buffer or Ext Descriptor Type */ 317 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, 318 BUF_OR_EXT_DESC_TYPE) |= 319 HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 320 } 321 322 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) 323 /** 324 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 325 * @tlv_tag: Tag of the TLVs 326 * @rx_tlv: the pointer to the TLVs 327 * @ppdu_info: pointer to ppdu_info 328 * 329 * Return: true if the tlv is handled, false if not 330 */ 331 static inline bool 332 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 333 struct hal_rx_ppdu_info *ppdu_info) 334 { 335 uint32_t value; 336 337 switch (tlv_tag) { 338 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 339 { 340 uint8_t *he_sig_a_mu_ul_info = 341 (uint8_t *)rx_tlv + 342 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, 343 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 344 ppdu_info->rx_status.he_flags = 1; 345 346 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 347 FORMAT_INDICATION); 348 if (value == 0) { 349 ppdu_info->rx_status.he_data1 = 350 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 351 } else { 352 ppdu_info->rx_status.he_data1 = 353 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 354 } 355 356 /* data1 */ 357 ppdu_info->rx_status.he_data1 |= 358 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 359 QDF_MON_STATUS_HE_DL_UL_KNOWN | 360 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 361 362 /* data2 */ 363 ppdu_info->rx_status.he_data2 |= 364 QDF_MON_STATUS_TXOP_KNOWN; 365 366 /*data3*/ 367 value = HAL_RX_GET(he_sig_a_mu_ul_info, 368 HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID); 369 ppdu_info->rx_status.he_data3 = value; 370 /* 1 for UL and 0 for DL */ 371 value = 1; 372 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 373 ppdu_info->rx_status.he_data3 |= value; 374 375 /*data4*/ 376 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 377 SPATIAL_REUSE); 378 ppdu_info->rx_status.he_data4 = value; 379 380 /*data5*/ 381 value = HAL_RX_GET(he_sig_a_mu_ul_info, 382 HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW); 383 ppdu_info->rx_status.he_data5 = value; 384 ppdu_info->rx_status.bw = value; 385 386 /*data6*/ 387 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1, 388 TXOP_DURATION); 389 value = value << QDF_MON_STATUS_TXOP_SHIFT; 390 ppdu_info->rx_status.he_data6 |= value; 391 return true; 392 } 393 default: 394 return false; 395 } 396 } 397 #else 398 static inline bool 399 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 400 struct hal_rx_ppdu_info *ppdu_info) 401 { 402 return false; 403 } 404 #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */ 405 406 #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) && \ 407 defined(RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 408 409 static inline void 410 hal_rx_handle_mu_ul_info(void *rx_tlv, 411 struct mon_rx_user_status *mon_rx_user_status) 412 { 413 mon_rx_user_status->mu_ul_user_v0_word0 = 414 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_11, 415 SW_RESPONSE_REFERENCE_PTR); 416 417 mon_rx_user_status->mu_ul_user_v0_word1 = 418 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_22, 419 SW_RESPONSE_REFERENCE_PTR_EXT); 420 } 421 422 static inline void 423 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 424 struct mon_rx_user_status *mon_rx_user_status) 425 { 426 uint32_t mpdu_ok_byte_count; 427 uint32_t mpdu_err_byte_count; 428 429 mpdu_ok_byte_count = HAL_RX_GET(rx_tlv, 430 RX_PPDU_END_USER_STATS_17, 431 MPDU_OK_BYTE_COUNT); 432 mpdu_err_byte_count = HAL_RX_GET(rx_tlv, 433 RX_PPDU_END_USER_STATS_19, 434 MPDU_ERR_BYTE_COUNT); 435 436 mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count; 437 mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count; 438 } 439 #else 440 static inline void 441 hal_rx_handle_mu_ul_info(void *rx_tlv, 442 struct mon_rx_user_status *mon_rx_user_status) 443 { 444 } 445 446 static inline void 447 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 448 struct mon_rx_user_status *mon_rx_user_status) 449 { 450 struct hal_rx_ppdu_info *ppdu_info = 451 (struct hal_rx_ppdu_info *)ppduinfo; 452 453 /* HKV1: doesn't support mpdu byte count */ 454 mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len; 455 mon_rx_user_status->mpdu_err_byte_count = 0; 456 } 457 #endif 458 459 static inline void 460 hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id, 461 struct mon_rx_user_status *mon_rx_user_status) 462 { 463 struct mon_rx_info *mon_rx_info; 464 struct mon_rx_user_info *mon_rx_user_info; 465 struct hal_rx_ppdu_info *ppdu_info = 466 (struct hal_rx_ppdu_info *)ppduinfo; 467 468 mon_rx_info = &ppdu_info->rx_info; 469 mon_rx_user_info = &ppdu_info->rx_user_info[user_id]; 470 mon_rx_user_info->qos_control_info_valid = 471 mon_rx_info->qos_control_info_valid; 472 mon_rx_user_info->qos_control = mon_rx_info->qos_control; 473 474 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 475 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 476 mon_rx_user_status->tcp_msdu_count = 477 ppdu_info->rx_status.tcp_msdu_count; 478 mon_rx_user_status->udp_msdu_count = 479 ppdu_info->rx_status.udp_msdu_count; 480 mon_rx_user_status->other_msdu_count = 481 ppdu_info->rx_status.other_msdu_count; 482 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 483 mon_rx_user_status->frame_control_info_valid = 484 ppdu_info->rx_status.frame_control_info_valid; 485 mon_rx_user_status->data_sequence_control_info_valid = 486 ppdu_info->rx_status.data_sequence_control_info_valid; 487 mon_rx_user_status->first_data_seq_ctrl = 488 ppdu_info->rx_status.first_data_seq_ctrl; 489 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 490 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 491 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 492 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 493 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 494 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 495 496 mon_rx_user_status->mpdu_cnt_fcs_ok = 497 ppdu_info->com_info.mpdu_cnt_fcs_ok; 498 mon_rx_user_status->mpdu_cnt_fcs_err = 499 ppdu_info->com_info.mpdu_cnt_fcs_err; 500 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 501 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 502 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 503 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 504 505 hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status); 506 } 507 508 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \ 509 ppdu_info, rssi_info_tlv) \ 510 { \ 511 ppdu_info->rx_status.rssi_chain[chain][0] = \ 512 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 513 RSSI_PRI20_CHAIN##chain); \ 514 ppdu_info->rx_status.rssi_chain[chain][1] = \ 515 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 516 RSSI_EXT20_CHAIN##chain); \ 517 ppdu_info->rx_status.rssi_chain[chain][2] = \ 518 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 519 RSSI_EXT40_LOW20_CHAIN##chain); \ 520 ppdu_info->rx_status.rssi_chain[chain][3] = \ 521 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 522 RSSI_EXT40_HIGH20_CHAIN##chain); \ 523 ppdu_info->rx_status.rssi_chain[chain][4] = \ 524 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 525 RSSI_EXT80_LOW20_CHAIN##chain); \ 526 ppdu_info->rx_status.rssi_chain[chain][5] = \ 527 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 528 RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \ 529 ppdu_info->rx_status.rssi_chain[chain][6] = \ 530 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 531 RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \ 532 ppdu_info->rx_status.rssi_chain[chain][7] = \ 533 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 534 RSSI_EXT80_HIGH20_CHAIN##chain); \ 535 } \ 536 537 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 538 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \ 539 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \ 540 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \ 541 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \ 542 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \ 543 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \ 544 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \ 545 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \ 546 547 static inline uint32_t 548 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 549 uint8_t *rssi_info_tlv) 550 { 551 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 552 return 0; 553 } 554 555 #ifdef WLAN_TX_PKT_CAPTURE_ENH 556 static inline void 557 hal_get_qos_control(void *rx_tlv, 558 struct hal_rx_ppdu_info *ppdu_info) 559 { 560 ppdu_info->rx_info.qos_control_info_valid = 561 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 562 QOS_CONTROL_INFO_VALID); 563 564 if (ppdu_info->rx_info.qos_control_info_valid) 565 ppdu_info->rx_info.qos_control = 566 HAL_RX_GET(rx_tlv, 567 RX_PPDU_END_USER_STATS_5, 568 QOS_CONTROL_FIELD); 569 } 570 571 static inline void 572 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 573 struct hal_rx_ppdu_info *ppdu_info) 574 { 575 if ((ppdu_info->sw_frame_group_id 576 == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) || 577 (ppdu_info->sw_frame_group_id == 578 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) { 579 ppdu_info->rx_info.mac_addr1_valid = 580 HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start); 581 582 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] = 583 HAL_RX_GET(rx_mpdu_start, 584 RX_MPDU_INFO_15, 585 MAC_ADDR_AD1_31_0); 586 if (ppdu_info->sw_frame_group_id == 587 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) { 588 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] = 589 HAL_RX_GET(rx_mpdu_start, 590 RX_MPDU_INFO_16, 591 MAC_ADDR_AD1_47_32); 592 } 593 } 594 } 595 #else 596 static inline void 597 hal_get_qos_control(void *rx_tlv, 598 struct hal_rx_ppdu_info *ppdu_info) 599 { 600 } 601 602 static inline void 603 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 604 struct hal_rx_ppdu_info *ppdu_info) 605 { 606 } 607 #endif 608 609 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS 610 static inline void 611 hal_update_frame_type_cnt(uint8_t *rx_mpdu_start, 612 struct hal_rx_ppdu_info *ppdu_info) 613 { 614 uint16_t frame_ctrl; 615 uint8_t fc_type; 616 617 if (HAL_RX_GET_FC_VALID(rx_mpdu_start)) { 618 frame_ctrl = HAL_RX_GET(rx_mpdu_start, 619 RX_MPDU_INFO_14, 620 MPDU_FRAME_CONTROL_FIELD); 621 fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl); 622 if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT) 623 ppdu_info->frm_type_info.rx_mgmt_cnt++; 624 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL) 625 ppdu_info->frm_type_info.rx_ctrl_cnt++; 626 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA) 627 ppdu_info->frm_type_info.rx_data_cnt++; 628 } 629 } 630 #else 631 static inline void 632 hal_update_frame_type_cnt(uint8_t *rx_mpdu_start, 633 struct hal_rx_ppdu_info *ppdu_info) 634 { 635 } 636 #endif 637 638 #ifdef WLAN_SUPPORT_CTRL_FRAME_STATS 639 static inline void 640 hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info *ppdu_info, 641 uint32_t user_id) 642 { 643 uint16_t fc = ppdu_info->nac_info.frame_control; 644 645 if (HAL_RX_GET_FRAME_CTRL_TYPE(fc) == HAL_RX_FRAME_CTRL_TYPE_CTRL) { 646 if ((fc & QDF_IEEE80211_FC0_SUBTYPE_MASK) == 647 QDF_IEEE80211_FC0_SUBTYPE_VHT_NDP_AN) 648 ppdu_info->ctrl_frm_info[user_id].ndpa = 1; 649 if ((fc & QDF_IEEE80211_FC0_SUBTYPE_MASK) == 650 QDF_IEEE80211_FC0_SUBTYPE_BAR) 651 ppdu_info->ctrl_frm_info[user_id].bar = 1; 652 } 653 } 654 #else 655 static inline void 656 hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info *ppdu_info, 657 uint32_t user_id) 658 { 659 } 660 #endif /* WLAN_SUPPORT_CTRL_FRAME_STATS */ 661 662 /** 663 * hal_rx_status_get_tlv_info_generic_li() - process receive info TLV 664 * @rx_tlv_hdr: pointer to TLV header 665 * @ppduinfo: pointer to ppdu_info 666 * @hal_soc_hdl: hal_soc handle 667 * @nbuf: pointer the pkt buffer. 668 * 669 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 670 */ 671 static inline uint32_t 672 hal_rx_status_get_tlv_info_generic_li(void *rx_tlv_hdr, void *ppduinfo, 673 hal_soc_handle_t hal_soc_hdl, 674 qdf_nbuf_t nbuf) 675 { 676 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 677 uint32_t tlv_tag, user_id, tlv_len, value; 678 uint8_t group_id = 0; 679 uint8_t he_dcm = 0; 680 uint8_t he_stbc = 0; 681 uint16_t he_gi = 0; 682 uint16_t he_ltf = 0; 683 void *rx_tlv; 684 bool unhandled = false; 685 struct mon_rx_user_status *mon_rx_user_status; 686 struct hal_rx_ppdu_info *ppdu_info = 687 (struct hal_rx_ppdu_info *)ppduinfo; 688 689 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 690 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 691 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 692 693 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 694 695 switch (tlv_tag) { 696 case WIFIRX_PPDU_START_E: 697 { 698 if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id == 699 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, PHY_PPDU_ID))) 700 hal_err("Matching ppdu_id(%u) detected", 701 ppdu_info->com_info.last_ppdu_id); 702 703 /* Reset ppdu_info before processing the ppdu */ 704 qdf_mem_zero(ppdu_info, 705 sizeof(struct hal_rx_ppdu_info)); 706 707 ppdu_info->com_info.last_ppdu_id = 708 ppdu_info->com_info.ppdu_id = 709 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 710 PHY_PPDU_ID); 711 712 /* channel number is set in PHY meta data */ 713 ppdu_info->rx_status.chan_num = 714 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 715 SW_PHY_META_DATA) & 0x0000FFFF); 716 ppdu_info->rx_status.chan_freq = 717 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 718 SW_PHY_META_DATA) & 0xFFFF0000) >> 16; 719 if (ppdu_info->rx_status.chan_num) { 720 ppdu_info->rx_status.chan_freq = 721 hal_rx_radiotap_num_to_freq( 722 ppdu_info->rx_status.chan_num, 723 ppdu_info->rx_status.chan_freq); 724 } 725 ppdu_info->com_info.ppdu_timestamp = 726 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 727 PPDU_START_TIMESTAMP); 728 ppdu_info->rx_status.ppdu_timestamp = 729 ppdu_info->com_info.ppdu_timestamp; 730 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 731 732 break; 733 } 734 735 case WIFIRX_PPDU_START_USER_INFO_E: 736 break; 737 738 case WIFIRX_PPDU_END_E: 739 dp_nofl_debug("[%s][%d] ppdu_end_e len=%d", 740 __func__, __LINE__, tlv_len); 741 /* This is followed by sub-TLVs of PPDU_END */ 742 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 743 break; 744 745 case WIFIPHYRX_PKT_END_E: 746 hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); 747 break; 748 749 case WIFIRXPCU_PPDU_END_INFO_E: 750 ppdu_info->rx_status.rx_antenna = 751 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, RX_ANTENNA); 752 ppdu_info->rx_status.tsft = 753 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 754 WB_TIMESTAMP_UPPER_32); 755 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 756 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 757 WB_TIMESTAMP_LOWER_32); 758 ppdu_info->rx_status.duration = 759 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 760 RX_PPDU_DURATION); 761 hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); 762 hal_rx_get_phyrx_abort(hal, rx_tlv, ppdu_info); 763 break; 764 765 /* 766 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 767 * for MU, based on num users we see this tlv that many times. 768 */ 769 case WIFIRX_PPDU_END_USER_STATS_E: 770 { 771 unsigned long tid = 0; 772 uint16_t seq = 0; 773 774 ppdu_info->rx_status.ast_index = 775 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 776 AST_INDEX); 777 778 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 779 RECEIVED_QOS_DATA_TID_BITMAP); 780 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, 781 sizeof(tid) * 8); 782 783 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 784 ppdu_info->rx_status.tid = HAL_TID_INVALID; 785 786 ppdu_info->rx_status.tcp_msdu_count = 787 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 788 TCP_MSDU_COUNT) + 789 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 790 TCP_ACK_MSDU_COUNT); 791 ppdu_info->rx_status.udp_msdu_count = 792 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 793 UDP_MSDU_COUNT); 794 ppdu_info->rx_status.other_msdu_count = 795 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 796 OTHER_MSDU_COUNT); 797 798 if (ppdu_info->sw_frame_group_id 799 != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 800 ppdu_info->rx_status.frame_control_info_valid = 801 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 802 FRAME_CONTROL_INFO_VALID); 803 804 if (ppdu_info->rx_status.frame_control_info_valid) 805 ppdu_info->rx_status.frame_control = 806 HAL_RX_GET(rx_tlv, 807 RX_PPDU_END_USER_STATS_4, 808 FRAME_CONTROL_FIELD); 809 810 hal_get_qos_control(rx_tlv, ppdu_info); 811 } 812 813 ppdu_info->rx_status.data_sequence_control_info_valid = 814 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 815 DATA_SEQUENCE_CONTROL_INFO_VALID); 816 817 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 818 FIRST_DATA_SEQ_CTRL); 819 if (ppdu_info->rx_status.data_sequence_control_info_valid) 820 ppdu_info->rx_status.first_data_seq_ctrl = seq; 821 822 ppdu_info->rx_status.preamble_type = 823 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 824 HT_CONTROL_FIELD_PKT_TYPE); 825 switch (ppdu_info->rx_status.preamble_type) { 826 case HAL_RX_PKT_TYPE_11N: 827 ppdu_info->rx_status.ht_flags = 1; 828 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 829 break; 830 case HAL_RX_PKT_TYPE_11AC: 831 ppdu_info->rx_status.vht_flags = 1; 832 break; 833 case HAL_RX_PKT_TYPE_11AX: 834 ppdu_info->rx_status.he_flags = 1; 835 break; 836 default: 837 break; 838 } 839 840 ppdu_info->com_info.mpdu_cnt_fcs_ok = 841 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 842 MPDU_CNT_FCS_OK); 843 ppdu_info->com_info.mpdu_cnt_fcs_err = 844 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 845 MPDU_CNT_FCS_ERR); 846 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 847 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 848 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 849 else 850 ppdu_info->rx_status.rs_flags &= 851 (~IEEE80211_AMPDU_FLAG); 852 853 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 854 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_7, 855 FCS_OK_BITMAP_31_0); 856 857 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 858 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_8, 859 FCS_OK_BITMAP_63_32); 860 861 if (user_id < HAL_MAX_UL_MU_USERS) { 862 mon_rx_user_status = 863 &ppdu_info->rx_user_status[user_id]; 864 865 hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status); 866 867 ppdu_info->com_info.num_users++; 868 869 hal_rx_populate_mu_user_info(rx_tlv, ppdu_info, 870 user_id, 871 mon_rx_user_status); 872 } 873 break; 874 } 875 876 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 877 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 878 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_1, 879 FCS_OK_BITMAP_95_64); 880 881 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 882 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_2, 883 FCS_OK_BITMAP_127_96); 884 885 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 886 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_3, 887 FCS_OK_BITMAP_159_128); 888 889 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 890 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_4, 891 FCS_OK_BITMAP_191_160); 892 893 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 894 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_5, 895 FCS_OK_BITMAP_223_192); 896 897 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 898 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_6, 899 FCS_OK_BITMAP_255_224); 900 break; 901 902 case WIFIRX_PPDU_END_STATUS_DONE_E: 903 return HAL_TLV_STATUS_PPDU_DONE; 904 905 case WIFIDUMMY_E: 906 return HAL_TLV_STATUS_BUF_DONE; 907 908 case WIFIPHYRX_HT_SIG_E: 909 { 910 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 911 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 912 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 913 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 914 FEC_CODING); 915 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 916 1 : 0; 917 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 918 HT_SIG_INFO_0, MCS); 919 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 920 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 921 HT_SIG_INFO_0, CBW); 922 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 923 HT_SIG_INFO_1, SHORT_GI); 924 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 925 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 926 HT_SIG_SU_NSS_SHIFT) + 1; 927 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 928 hal_rx_get_ht_sig_info(ppdu_info, ht_sig_info); 929 break; 930 } 931 932 case WIFIPHYRX_L_SIG_B_E: 933 { 934 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 935 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 936 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 937 938 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 939 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 940 switch (value) { 941 case 1: 942 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 943 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 944 break; 945 case 2: 946 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 947 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 948 break; 949 case 3: 950 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 951 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 952 break; 953 case 4: 954 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 955 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 956 break; 957 case 5: 958 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 959 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 960 break; 961 case 6: 962 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 963 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 964 break; 965 case 7: 966 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 967 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 968 break; 969 default: 970 break; 971 } 972 ppdu_info->rx_status.cck_flag = 1; 973 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 974 break; 975 } 976 977 case WIFIPHYRX_L_SIG_A_E: 978 { 979 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 980 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 981 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 982 983 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 984 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 985 switch (value) { 986 case 8: 987 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 988 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 989 break; 990 case 9: 991 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 992 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 993 break; 994 case 10: 995 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 996 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 997 break; 998 case 11: 999 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 1000 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 1001 break; 1002 case 12: 1003 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 1004 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 1005 break; 1006 case 13: 1007 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 1008 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 1009 break; 1010 case 14: 1011 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 1012 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 1013 break; 1014 case 15: 1015 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 1016 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 1017 break; 1018 default: 1019 break; 1020 } 1021 ppdu_info->rx_status.ofdm_flag = 1; 1022 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1023 hal_rx_get_l_sig_a_info(ppdu_info, l_sig_a_info); 1024 break; 1025 } 1026 1027 case WIFIPHYRX_VHT_SIG_A_E: 1028 { 1029 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 1030 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 1031 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 1032 1033 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 1034 SU_MU_CODING); 1035 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 1036 1 : 0; 1037 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, 1038 GROUP_ID); 1039 ppdu_info->rx_status.vht_flag_values5 = group_id; 1040 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 1041 VHT_SIG_A_INFO_1, MCS); 1042 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 1043 VHT_SIG_A_INFO_1, GI_SETTING); 1044 1045 switch (hal->target_type) { 1046 case TARGET_TYPE_QCA8074: 1047 case TARGET_TYPE_QCA8074V2: 1048 case TARGET_TYPE_QCA6018: 1049 case TARGET_TYPE_QCA5018: 1050 case TARGET_TYPE_QCN9000: 1051 case TARGET_TYPE_QCN6122: 1052 case TARGET_TYPE_QCN9160: 1053 #ifdef QCA_WIFI_QCA6390 1054 case TARGET_TYPE_QCA6390: 1055 #endif 1056 case TARGET_TYPE_QCA6490: 1057 ppdu_info->rx_status.is_stbc = 1058 HAL_RX_GET(vht_sig_a_info, 1059 VHT_SIG_A_INFO_0, STBC); 1060 value = HAL_RX_GET(vht_sig_a_info, 1061 VHT_SIG_A_INFO_0, N_STS); 1062 value = value & VHT_SIG_SU_NSS_MASK; 1063 if (ppdu_info->rx_status.is_stbc && (value > 0)) 1064 value = ((value + 1) >> 1) - 1; 1065 ppdu_info->rx_status.nss = 1066 ((value & VHT_SIG_SU_NSS_MASK) + 1); 1067 1068 break; 1069 case TARGET_TYPE_QCA6290: 1070 #if !defined(QCA_WIFI_QCA6290_11AX) 1071 ppdu_info->rx_status.is_stbc = 1072 HAL_RX_GET(vht_sig_a_info, 1073 VHT_SIG_A_INFO_0, STBC); 1074 value = HAL_RX_GET(vht_sig_a_info, 1075 VHT_SIG_A_INFO_0, N_STS); 1076 value = value & VHT_SIG_SU_NSS_MASK; 1077 if (ppdu_info->rx_status.is_stbc && (value > 0)) 1078 value = ((value + 1) >> 1) - 1; 1079 ppdu_info->rx_status.nss = 1080 ((value & VHT_SIG_SU_NSS_MASK) + 1); 1081 #else 1082 ppdu_info->rx_status.nss = 0; 1083 #endif 1084 break; 1085 case TARGET_TYPE_QCA6750: 1086 ppdu_info->rx_status.nss = 0; 1087 break; 1088 default: 1089 break; 1090 } 1091 ppdu_info->rx_status.vht_flag_values3[0] = 1092 (((ppdu_info->rx_status.mcs) << 4) 1093 | ppdu_info->rx_status.nss); 1094 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 1095 VHT_SIG_A_INFO_0, BANDWIDTH); 1096 ppdu_info->rx_status.vht_flag_values2 = 1097 ppdu_info->rx_status.bw; 1098 ppdu_info->rx_status.vht_flag_values4 = 1099 HAL_RX_GET(vht_sig_a_info, 1100 VHT_SIG_A_INFO_1, SU_MU_CODING); 1101 1102 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 1103 VHT_SIG_A_INFO_1, BEAMFORMED); 1104 if (group_id == 0 || group_id == 63) 1105 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1106 else 1107 ppdu_info->rx_status.reception_type = 1108 HAL_RX_TYPE_MU_MIMO; 1109 1110 hal_rx_get_vht_sig_a_info(ppdu_info, vht_sig_a_info); 1111 break; 1112 } 1113 case WIFIPHYRX_HE_SIG_A_SU_E: 1114 { 1115 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 1116 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 1117 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 1118 ppdu_info->rx_status.he_flags = 1; 1119 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 1120 FORMAT_INDICATION); 1121 if (value == 0) { 1122 ppdu_info->rx_status.he_data1 = 1123 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1124 } else { 1125 ppdu_info->rx_status.he_data1 = 1126 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 1127 } 1128 1129 /* data1 */ 1130 ppdu_info->rx_status.he_data1 |= 1131 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 1132 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 1133 QDF_MON_STATUS_HE_DL_UL_KNOWN | 1134 QDF_MON_STATUS_HE_MCS_KNOWN | 1135 QDF_MON_STATUS_HE_DCM_KNOWN | 1136 QDF_MON_STATUS_HE_CODING_KNOWN | 1137 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 1138 QDF_MON_STATUS_HE_STBC_KNOWN | 1139 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 1140 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 1141 1142 /* data2 */ 1143 ppdu_info->rx_status.he_data2 = 1144 QDF_MON_STATUS_HE_GI_KNOWN; 1145 ppdu_info->rx_status.he_data2 |= 1146 QDF_MON_STATUS_TXBF_KNOWN | 1147 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1148 QDF_MON_STATUS_TXOP_KNOWN | 1149 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1150 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1151 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1152 1153 /* data3 */ 1154 value = HAL_RX_GET(he_sig_a_su_info, 1155 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 1156 ppdu_info->rx_status.he_data3 = value; 1157 value = HAL_RX_GET(he_sig_a_su_info, 1158 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 1159 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 1160 ppdu_info->rx_status.he_data3 |= value; 1161 value = HAL_RX_GET(he_sig_a_su_info, 1162 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 1163 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1164 ppdu_info->rx_status.he_data3 |= value; 1165 1166 value = HAL_RX_GET(he_sig_a_su_info, 1167 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 1168 ppdu_info->rx_status.mcs = value; 1169 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1170 ppdu_info->rx_status.he_data3 |= value; 1171 1172 value = HAL_RX_GET(he_sig_a_su_info, 1173 HE_SIG_A_SU_INFO_0, DCM); 1174 he_dcm = value; 1175 value = value << QDF_MON_STATUS_DCM_SHIFT; 1176 ppdu_info->rx_status.he_data3 |= value; 1177 value = HAL_RX_GET(he_sig_a_su_info, 1178 HE_SIG_A_SU_INFO_1, CODING); 1179 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 1180 1 : 0; 1181 value = value << QDF_MON_STATUS_CODING_SHIFT; 1182 ppdu_info->rx_status.he_data3 |= value; 1183 value = HAL_RX_GET(he_sig_a_su_info, 1184 HE_SIG_A_SU_INFO_1, 1185 LDPC_EXTRA_SYMBOL); 1186 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1187 ppdu_info->rx_status.he_data3 |= value; 1188 value = HAL_RX_GET(he_sig_a_su_info, 1189 HE_SIG_A_SU_INFO_1, STBC); 1190 he_stbc = value; 1191 value = value << QDF_MON_STATUS_STBC_SHIFT; 1192 ppdu_info->rx_status.he_data3 |= value; 1193 1194 /* data4 */ 1195 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 1196 SPATIAL_REUSE); 1197 ppdu_info->rx_status.he_data4 = value; 1198 1199 /* data5 */ 1200 value = HAL_RX_GET(he_sig_a_su_info, 1201 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 1202 ppdu_info->rx_status.he_data5 = value; 1203 ppdu_info->rx_status.bw = value; 1204 value = HAL_RX_GET(he_sig_a_su_info, 1205 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 1206 switch (value) { 1207 case 0: 1208 he_gi = HE_GI_0_8; 1209 he_ltf = HE_LTF_1_X; 1210 break; 1211 case 1: 1212 he_gi = HE_GI_0_8; 1213 he_ltf = HE_LTF_2_X; 1214 break; 1215 case 2: 1216 he_gi = HE_GI_1_6; 1217 he_ltf = HE_LTF_2_X; 1218 break; 1219 case 3: 1220 if (he_dcm && he_stbc) { 1221 he_gi = HE_GI_0_8; 1222 he_ltf = HE_LTF_4_X; 1223 } else { 1224 he_gi = HE_GI_3_2; 1225 he_ltf = HE_LTF_4_X; 1226 } 1227 break; 1228 } 1229 ppdu_info->rx_status.sgi = he_gi; 1230 ppdu_info->rx_status.ltf_size = he_ltf; 1231 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 1232 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1233 ppdu_info->rx_status.he_data5 |= value; 1234 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1235 ppdu_info->rx_status.he_data5 |= value; 1236 1237 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 1238 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1239 ppdu_info->rx_status.he_data5 |= value; 1240 1241 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1242 PACKET_EXTENSION_A_FACTOR); 1243 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1244 ppdu_info->rx_status.he_data5 |= value; 1245 1246 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 1247 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1248 ppdu_info->rx_status.he_data5 |= value; 1249 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1250 PACKET_EXTENSION_PE_DISAMBIGUITY); 1251 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1252 ppdu_info->rx_status.he_data5 |= value; 1253 1254 /* data6 */ 1255 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 1256 value++; 1257 ppdu_info->rx_status.nss = value; 1258 ppdu_info->rx_status.he_data6 = value; 1259 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1260 DOPPLER_INDICATION); 1261 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1262 ppdu_info->rx_status.he_data6 |= value; 1263 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1264 TXOP_DURATION); 1265 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1266 ppdu_info->rx_status.he_data6 |= value; 1267 1268 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 1269 HE_SIG_A_SU_INFO_1, TXBF); 1270 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1271 hal_rx_get_crc_he_sig_a_su_info(ppdu_info, he_sig_a_su_info); 1272 break; 1273 } 1274 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 1275 { 1276 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 1277 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 1278 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 1279 1280 ppdu_info->rx_status.he_mu_flags = 1; 1281 1282 /* HE Flags */ 1283 /*data1*/ 1284 ppdu_info->rx_status.he_data1 = 1285 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1286 ppdu_info->rx_status.he_data1 |= 1287 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 1288 QDF_MON_STATUS_HE_DL_UL_KNOWN | 1289 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 1290 QDF_MON_STATUS_HE_STBC_KNOWN | 1291 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 1292 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 1293 1294 /* data2 */ 1295 ppdu_info->rx_status.he_data2 = 1296 QDF_MON_STATUS_HE_GI_KNOWN; 1297 ppdu_info->rx_status.he_data2 |= 1298 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1299 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1300 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1301 QDF_MON_STATUS_TXOP_KNOWN | 1302 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1303 1304 /*data3*/ 1305 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1306 HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); 1307 ppdu_info->rx_status.he_data3 = value; 1308 1309 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1310 HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); 1311 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1312 ppdu_info->rx_status.he_data3 |= value; 1313 1314 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1315 HE_SIG_A_MU_DL_INFO_1, 1316 LDPC_EXTRA_SYMBOL); 1317 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1318 ppdu_info->rx_status.he_data3 |= value; 1319 1320 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1321 HE_SIG_A_MU_DL_INFO_1, STBC); 1322 he_stbc = value; 1323 value = value << QDF_MON_STATUS_STBC_SHIFT; 1324 ppdu_info->rx_status.he_data3 |= value; 1325 1326 /*data4*/ 1327 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1328 SPATIAL_REUSE); 1329 ppdu_info->rx_status.he_data4 = value; 1330 1331 /*data5*/ 1332 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1333 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1334 ppdu_info->rx_status.he_data5 = value; 1335 ppdu_info->rx_status.bw = value; 1336 1337 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1338 HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); 1339 switch (value) { 1340 case 0: 1341 he_gi = HE_GI_0_8; 1342 he_ltf = HE_LTF_4_X; 1343 break; 1344 case 1: 1345 he_gi = HE_GI_0_8; 1346 he_ltf = HE_LTF_2_X; 1347 break; 1348 case 2: 1349 he_gi = HE_GI_1_6; 1350 he_ltf = HE_LTF_2_X; 1351 break; 1352 case 3: 1353 he_gi = HE_GI_3_2; 1354 he_ltf = HE_LTF_4_X; 1355 break; 1356 } 1357 ppdu_info->rx_status.sgi = he_gi; 1358 ppdu_info->rx_status.ltf_size = he_ltf; 1359 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 1360 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1361 ppdu_info->rx_status.he_data5 |= value; 1362 1363 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1364 ppdu_info->rx_status.he_data5 |= value; 1365 1366 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1367 HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); 1368 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1369 ppdu_info->rx_status.he_data5 |= value; 1370 1371 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1372 PACKET_EXTENSION_A_FACTOR); 1373 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1374 ppdu_info->rx_status.he_data5 |= value; 1375 1376 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1377 PACKET_EXTENSION_PE_DISAMBIGUITY); 1378 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1379 ppdu_info->rx_status.he_data5 |= value; 1380 1381 /*data6*/ 1382 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1383 DOPPLER_INDICATION); 1384 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1385 ppdu_info->rx_status.he_data6 |= value; 1386 1387 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1388 TXOP_DURATION); 1389 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1390 ppdu_info->rx_status.he_data6 |= value; 1391 1392 /* HE-MU Flags */ 1393 /* HE-MU-flags1 */ 1394 ppdu_info->rx_status.he_flags1 = 1395 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1396 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1397 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 1398 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 1399 QDF_MON_STATUS_RU_0_KNOWN; 1400 1401 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1402 HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); 1403 ppdu_info->rx_status.he_flags1 |= value; 1404 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1405 HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); 1406 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 1407 ppdu_info->rx_status.he_flags1 |= value; 1408 1409 /* HE-MU-flags2 */ 1410 ppdu_info->rx_status.he_flags2 = 1411 QDF_MON_STATUS_BW_KNOWN; 1412 1413 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1414 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1415 ppdu_info->rx_status.he_flags2 |= value; 1416 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1417 HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); 1418 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1419 ppdu_info->rx_status.he_flags2 |= value; 1420 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1421 HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); 1422 value = value - 1; 1423 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 1424 ppdu_info->rx_status.he_flags2 |= value; 1425 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1426 hal_rx_get_crc_he_sig_a_mu_dl_info(ppdu_info, 1427 he_sig_a_mu_dl_info); 1428 break; 1429 } 1430 case WIFIPHYRX_HE_SIG_B1_MU_E: 1431 { 1432 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 1433 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 1434 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 1435 1436 ppdu_info->rx_status.he_sig_b_common_known |= 1437 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 1438 /* TODO: Check on the availability of other fields in 1439 * sig_b_common 1440 */ 1441 1442 value = HAL_RX_GET(he_sig_b1_mu_info, 1443 HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); 1444 ppdu_info->rx_status.he_RU[0] = value; 1445 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1446 break; 1447 } 1448 case WIFIPHYRX_HE_SIG_B2_MU_E: 1449 { 1450 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 1451 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 1452 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 1453 /* 1454 * Not all "HE" fields can be updated from 1455 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1456 * to populate rest of the "HE" fields for MU scenarios. 1457 */ 1458 1459 /* HE-data1 */ 1460 ppdu_info->rx_status.he_data1 |= 1461 QDF_MON_STATUS_HE_MCS_KNOWN | 1462 QDF_MON_STATUS_HE_CODING_KNOWN; 1463 1464 /* HE-data2 */ 1465 1466 /* HE-data3 */ 1467 value = HAL_RX_GET(he_sig_b2_mu_info, 1468 HE_SIG_B2_MU_INFO_0, STA_MCS); 1469 ppdu_info->rx_status.mcs = value; 1470 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1471 ppdu_info->rx_status.he_data3 |= value; 1472 1473 value = HAL_RX_GET(he_sig_b2_mu_info, 1474 HE_SIG_B2_MU_INFO_0, STA_CODING); 1475 value = value << QDF_MON_STATUS_CODING_SHIFT; 1476 ppdu_info->rx_status.he_data3 |= value; 1477 1478 /* HE-data4 */ 1479 value = HAL_RX_GET(he_sig_b2_mu_info, 1480 HE_SIG_B2_MU_INFO_0, STA_ID); 1481 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1482 ppdu_info->rx_status.he_data4 |= value; 1483 1484 /* HE-data5 */ 1485 1486 /* HE-data6 */ 1487 value = HAL_RX_GET(he_sig_b2_mu_info, 1488 HE_SIG_B2_MU_INFO_0, NSTS); 1489 /* value n indicates n+1 spatial streams */ 1490 value++; 1491 ppdu_info->rx_status.nss = value; 1492 ppdu_info->rx_status.he_data6 |= value; 1493 1494 break; 1495 } 1496 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 1497 { 1498 uint8_t *he_sig_b2_ofdma_info = 1499 (uint8_t *)rx_tlv + 1500 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 1501 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 1502 1503 /* 1504 * Not all "HE" fields can be updated from 1505 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1506 * to populate rest of "HE" fields for MU OFDMA scenarios. 1507 */ 1508 1509 /* HE-data1 */ 1510 ppdu_info->rx_status.he_data1 |= 1511 QDF_MON_STATUS_HE_MCS_KNOWN | 1512 QDF_MON_STATUS_HE_DCM_KNOWN | 1513 QDF_MON_STATUS_HE_CODING_KNOWN; 1514 1515 /* HE-data2 */ 1516 ppdu_info->rx_status.he_data2 |= 1517 QDF_MON_STATUS_TXBF_KNOWN; 1518 1519 /* HE-data3 */ 1520 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1521 HE_SIG_B2_OFDMA_INFO_0, STA_MCS); 1522 ppdu_info->rx_status.mcs = value; 1523 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1524 ppdu_info->rx_status.he_data3 |= value; 1525 1526 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1527 HE_SIG_B2_OFDMA_INFO_0, STA_DCM); 1528 he_dcm = value; 1529 value = value << QDF_MON_STATUS_DCM_SHIFT; 1530 ppdu_info->rx_status.he_data3 |= value; 1531 1532 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1533 HE_SIG_B2_OFDMA_INFO_0, STA_CODING); 1534 value = value << QDF_MON_STATUS_CODING_SHIFT; 1535 ppdu_info->rx_status.he_data3 |= value; 1536 1537 /* HE-data4 */ 1538 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1539 HE_SIG_B2_OFDMA_INFO_0, STA_ID); 1540 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1541 ppdu_info->rx_status.he_data4 |= value; 1542 1543 /* HE-data5 */ 1544 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1545 HE_SIG_B2_OFDMA_INFO_0, TXBF); 1546 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1547 ppdu_info->rx_status.he_data5 |= value; 1548 1549 /* HE-data6 */ 1550 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1551 HE_SIG_B2_OFDMA_INFO_0, NSTS); 1552 /* value n indicates n+1 spatial streams */ 1553 value++; 1554 ppdu_info->rx_status.nss = value; 1555 ppdu_info->rx_status.he_data6 |= value; 1556 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1557 break; 1558 } 1559 case WIFIPHYRX_RSSI_LEGACY_E: 1560 { 1561 uint8_t reception_type; 1562 int8_t rssi_value; 1563 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 1564 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 1565 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 1566 1567 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 1568 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 1569 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 1570 ppdu_info->rx_status.he_re = 0; 1571 1572 reception_type = HAL_RX_GET(rx_tlv, 1573 PHYRX_RSSI_LEGACY_0, 1574 RECEPTION_TYPE); 1575 switch (reception_type) { 1576 case QDF_RECEPTION_TYPE_ULOFMDA: 1577 ppdu_info->rx_status.reception_type = 1578 HAL_RX_TYPE_MU_OFDMA; 1579 ppdu_info->rx_status.ulofdma_flag = 1; 1580 ppdu_info->rx_status.he_data1 = 1581 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1582 break; 1583 case QDF_RECEPTION_TYPE_ULMIMO: 1584 ppdu_info->rx_status.reception_type = 1585 HAL_RX_TYPE_MU_MIMO; 1586 ppdu_info->rx_status.he_data1 = 1587 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1588 break; 1589 default: 1590 ppdu_info->rx_status.reception_type = 1591 HAL_RX_TYPE_SU; 1592 break; 1593 } 1594 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 1595 rssi_value = HAL_RX_GET(rssi_info_tlv, 1596 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 1597 ppdu_info->rx_status.rssi[0] = rssi_value; 1598 dp_nofl_debug("RSSI_PRI20_CHAIN0: %d\n", rssi_value); 1599 1600 rssi_value = HAL_RX_GET(rssi_info_tlv, 1601 RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1); 1602 ppdu_info->rx_status.rssi[1] = rssi_value; 1603 dp_nofl_debug("RSSI_PRI20_CHAIN1: %d\n", rssi_value); 1604 1605 rssi_value = HAL_RX_GET(rssi_info_tlv, 1606 RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2); 1607 ppdu_info->rx_status.rssi[2] = rssi_value; 1608 dp_nofl_debug("RSSI_PRI20_CHAIN2: %d\n", rssi_value); 1609 1610 rssi_value = HAL_RX_GET(rssi_info_tlv, 1611 RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3); 1612 ppdu_info->rx_status.rssi[3] = rssi_value; 1613 dp_nofl_debug("RSSI_PRI20_CHAIN3: %d\n", rssi_value); 1614 1615 rssi_value = HAL_RX_GET(rssi_info_tlv, 1616 RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4); 1617 ppdu_info->rx_status.rssi[4] = rssi_value; 1618 dp_nofl_debug("RSSI_PRI20_CHAIN4: %d\n", rssi_value); 1619 1620 rssi_value = HAL_RX_GET(rssi_info_tlv, 1621 RECEIVE_RSSI_INFO_10, 1622 RSSI_PRI20_CHAIN5); 1623 ppdu_info->rx_status.rssi[5] = rssi_value; 1624 dp_nofl_debug("RSSI_PRI20_CHAIN5: %d\n", rssi_value); 1625 1626 rssi_value = HAL_RX_GET(rssi_info_tlv, 1627 RECEIVE_RSSI_INFO_12, 1628 RSSI_PRI20_CHAIN6); 1629 ppdu_info->rx_status.rssi[6] = rssi_value; 1630 dp_nofl_debug("RSSI_PRI20_CHAIN6: %d\n", rssi_value); 1631 1632 rssi_value = HAL_RX_GET(rssi_info_tlv, 1633 RECEIVE_RSSI_INFO_14, 1634 RSSI_PRI20_CHAIN7); 1635 ppdu_info->rx_status.rssi[7] = rssi_value; 1636 dp_nofl_debug("RSSI_PRI20_CHAIN7: %d\n", rssi_value); 1637 break; 1638 } 1639 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1640 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1641 ppdu_info); 1642 break; 1643 case WIFIRX_HEADER_E: 1644 { 1645 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 1646 1647 if (ppdu_info->fcs_ok_cnt >= 1648 HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) { 1649 hal_err("Number of MPDUs(%d) per status buff exceeded", 1650 ppdu_info->fcs_ok_cnt); 1651 break; 1652 } 1653 1654 /* Update first_msdu_payload for every mpdu and increment 1655 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 1656 */ 1657 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload = 1658 rx_tlv; 1659 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len; 1660 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1661 ppdu_info->msdu_info.payload_len = tlv_len; 1662 ppdu_info->user_id = user_id; 1663 ppdu_info->hdr_len = tlv_len; 1664 ppdu_info->data = rx_tlv; 1665 ppdu_info->data += 4; 1666 1667 /* for every RX_HEADER TLV increment mpdu_cnt */ 1668 com_info->mpdu_cnt++; 1669 return HAL_TLV_STATUS_HEADER; 1670 } 1671 case WIFIRX_MPDU_START_E: 1672 { 1673 uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv; 1674 uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_mpdu_start); 1675 uint8_t filter_category = 0; 1676 1677 hal_update_frame_type_cnt(rx_mpdu_start, ppdu_info); 1678 1679 ppdu_info->nac_info.fc_valid = 1680 HAL_RX_GET_FC_VALID(rx_mpdu_start); 1681 1682 ppdu_info->nac_info.to_ds_flag = 1683 HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start); 1684 1685 ppdu_info->nac_info.frame_control = 1686 HAL_RX_GET(rx_mpdu_start, 1687 RX_MPDU_INFO_14, 1688 MPDU_FRAME_CONTROL_FIELD); 1689 1690 ppdu_info->sw_frame_group_id = 1691 HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start); 1692 1693 ppdu_info->rx_user_status[user_id].sw_peer_id = 1694 HAL_RX_GET_SW_PEER_ID(rx_mpdu_start); 1695 1696 hal_update_rx_ctrl_frame_stats(ppdu_info, user_id); 1697 1698 if (ppdu_info->sw_frame_group_id == 1699 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 1700 ppdu_info->rx_status.frame_control_info_valid = 1701 ppdu_info->nac_info.fc_valid; 1702 ppdu_info->rx_status.frame_control = 1703 ppdu_info->nac_info.frame_control; 1704 } 1705 1706 hal_get_mac_addr1(rx_mpdu_start, 1707 ppdu_info); 1708 1709 ppdu_info->nac_info.mac_addr2_valid = 1710 HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start); 1711 1712 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1713 HAL_RX_GET(rx_mpdu_start, 1714 RX_MPDU_INFO_16, 1715 MAC_ADDR_AD2_15_0); 1716 1717 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1718 HAL_RX_GET(rx_mpdu_start, 1719 RX_MPDU_INFO_17, 1720 MAC_ADDR_AD2_47_16); 1721 1722 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1723 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1724 ppdu_info->rx_status.ppdu_len = 1725 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1726 MPDU_LENGTH); 1727 } else { 1728 ppdu_info->rx_status.ppdu_len += 1729 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1730 MPDU_LENGTH); 1731 } 1732 1733 filter_category = 1734 HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start); 1735 1736 if (filter_category == 0) 1737 ppdu_info->rx_status.rxpcu_filter_pass = 1; 1738 else if (filter_category == 1) 1739 ppdu_info->rx_status.monitor_direct_used = 1; 1740 1741 ppdu_info->nac_info.mcast_bcast = 1742 HAL_RX_GET(rx_mpdu_start, 1743 RX_MPDU_INFO_13, 1744 MCAST_BCAST); 1745 break; 1746 } 1747 case WIFIRX_MPDU_END_E: 1748 ppdu_info->user_id = user_id; 1749 ppdu_info->fcs_err = 1750 HAL_RX_GET(rx_tlv, RX_MPDU_END_1, 1751 FCS_ERR); 1752 return HAL_TLV_STATUS_MPDU_END; 1753 case WIFIRX_MSDU_END_E: 1754 if (user_id < HAL_MAX_UL_MU_USERS) { 1755 ppdu_info->rx_msdu_info[user_id].cce_metadata = 1756 HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv); 1757 ppdu_info->rx_msdu_info[user_id].fse_metadata = 1758 HAL_RX_MSDU_END_FSE_METADATA_GET(rx_tlv); 1759 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 1760 HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(rx_tlv); 1761 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 1762 HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(rx_tlv); 1763 ppdu_info->rx_msdu_info[user_id].flow_idx = 1764 HAL_RX_MSDU_END_FLOW_IDX_GET(rx_tlv); 1765 } 1766 return HAL_TLV_STATUS_MSDU_END; 1767 case 0: 1768 return HAL_TLV_STATUS_PPDU_DONE; 1769 1770 default: 1771 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1772 unhandled = false; 1773 else 1774 unhandled = true; 1775 break; 1776 } 1777 1778 if (!unhandled) 1779 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1780 "%s TLV type: %d, TLV len:%d %s", 1781 __func__, tlv_tag, tlv_len, 1782 unhandled == true ? "unhandled" : ""); 1783 1784 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1785 } 1786 1787 /** 1788 * hal_tx_comp_get_release_reason_generic_li() - TQM Release reason 1789 * @hal_desc: completion ring descriptor pointer 1790 * 1791 * This function will return the type of pointer - buffer or descriptor 1792 * 1793 * Return: buffer type 1794 */ 1795 static inline uint8_t hal_tx_comp_get_release_reason_generic_li(void *hal_desc) 1796 { 1797 uint32_t comp_desc = 1798 *(uint32_t *)(((uint8_t *)hal_desc) + 1799 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 1800 1801 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 1802 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 1803 } 1804 1805 /** 1806 * hal_get_wbm_internal_error_generic_li() - is WBM internal error 1807 * @hal_desc: completion ring descriptor pointer 1808 * 1809 * This function will return 0 or 1 - is it WBM internal error or not 1810 * 1811 * Return: uint8_t 1812 */ 1813 static inline uint8_t hal_get_wbm_internal_error_generic_li(void *hal_desc) 1814 { 1815 uint32_t comp_desc = 1816 *(uint32_t *)(((uint8_t *)hal_desc) + 1817 HAL_WBM_INTERNAL_ERROR_OFFSET); 1818 1819 return (comp_desc & HAL_WBM_INTERNAL_ERROR_MASK) >> 1820 HAL_WBM_INTERNAL_ERROR_LSB; 1821 } 1822 1823 /** 1824 * hal_rx_dump_mpdu_start_tlv_generic_li() - dump RX mpdu_start TLV in 1825 * structured human readable 1826 * format. 1827 * @mpdustart: pointer the rx_attention TLV in pkt. 1828 * @dbg_level: log level. 1829 * 1830 * Return: void 1831 */ 1832 static inline void hal_rx_dump_mpdu_start_tlv_generic_li(void *mpdustart, 1833 uint8_t dbg_level) 1834 { 1835 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 1836 struct rx_mpdu_info *mpdu_info = 1837 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 1838 1839 hal_verbose_debug( 1840 "rx_mpdu_start tlv (1/5) - " 1841 "rxpcu_mpdu_filter_in_category: %x " 1842 "sw_frame_group_id: %x " 1843 "ndp_frame: %x " 1844 "phy_err: %x " 1845 "phy_err_during_mpdu_header: %x " 1846 "protocol_version_err: %x " 1847 "ast_based_lookup_valid: %x " 1848 "phy_ppdu_id: %x " 1849 "ast_index: %x " 1850 "sw_peer_id: %x " 1851 "mpdu_frame_control_valid: %x " 1852 "mpdu_duration_valid: %x " 1853 "mac_addr_ad1_valid: %x " 1854 "mac_addr_ad2_valid: %x " 1855 "mac_addr_ad3_valid: %x " 1856 "mac_addr_ad4_valid: %x " 1857 "mpdu_sequence_control_valid: %x " 1858 "mpdu_qos_control_valid: %x " 1859 "mpdu_ht_control_valid: %x " 1860 "frame_encryption_info_valid: %x ", 1861 mpdu_info->rxpcu_mpdu_filter_in_category, 1862 mpdu_info->sw_frame_group_id, 1863 mpdu_info->ndp_frame, 1864 mpdu_info->phy_err, 1865 mpdu_info->phy_err_during_mpdu_header, 1866 mpdu_info->protocol_version_err, 1867 mpdu_info->ast_based_lookup_valid, 1868 mpdu_info->phy_ppdu_id, 1869 mpdu_info->ast_index, 1870 mpdu_info->sw_peer_id, 1871 mpdu_info->mpdu_frame_control_valid, 1872 mpdu_info->mpdu_duration_valid, 1873 mpdu_info->mac_addr_ad1_valid, 1874 mpdu_info->mac_addr_ad2_valid, 1875 mpdu_info->mac_addr_ad3_valid, 1876 mpdu_info->mac_addr_ad4_valid, 1877 mpdu_info->mpdu_sequence_control_valid, 1878 mpdu_info->mpdu_qos_control_valid, 1879 mpdu_info->mpdu_ht_control_valid, 1880 mpdu_info->frame_encryption_info_valid); 1881 1882 hal_verbose_debug( 1883 "rx_mpdu_start tlv (2/5) - " 1884 "fr_ds: %x " 1885 "to_ds: %x " 1886 "encrypted: %x " 1887 "mpdu_retry: %x " 1888 "mpdu_sequence_number: %x " 1889 "epd_en: %x " 1890 "all_frames_shall_be_encrypted: %x " 1891 "encrypt_type: %x " 1892 "mesh_sta: %x " 1893 "bssid_hit: %x " 1894 "bssid_number: %x " 1895 "tid: %x " 1896 "pn_31_0: %x " 1897 "pn_63_32: %x " 1898 "pn_95_64: %x " 1899 "pn_127_96: %x " 1900 "peer_meta_data: %x " 1901 "rxpt_classify_info.reo_destination_indication: %x " 1902 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x " 1903 "rx_reo_queue_desc_addr_31_0: %x ", 1904 mpdu_info->fr_ds, 1905 mpdu_info->to_ds, 1906 mpdu_info->encrypted, 1907 mpdu_info->mpdu_retry, 1908 mpdu_info->mpdu_sequence_number, 1909 mpdu_info->epd_en, 1910 mpdu_info->all_frames_shall_be_encrypted, 1911 mpdu_info->encrypt_type, 1912 mpdu_info->mesh_sta, 1913 mpdu_info->bssid_hit, 1914 mpdu_info->bssid_number, 1915 mpdu_info->tid, 1916 mpdu_info->pn_31_0, 1917 mpdu_info->pn_63_32, 1918 mpdu_info->pn_95_64, 1919 mpdu_info->pn_127_96, 1920 mpdu_info->peer_meta_data, 1921 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 1922 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 1923 mpdu_info->rx_reo_queue_desc_addr_31_0); 1924 1925 hal_verbose_debug( 1926 "rx_mpdu_start tlv (3/5) - " 1927 "rx_reo_queue_desc_addr_39_32: %x " 1928 "receive_queue_number: %x " 1929 "pre_delim_err_warning: %x " 1930 "first_delim_err: %x " 1931 "key_id_octet: %x " 1932 "new_peer_entry: %x " 1933 "decrypt_needed: %x " 1934 "decap_type: %x " 1935 "rx_insert_vlan_c_tag_padding: %x " 1936 "rx_insert_vlan_s_tag_padding: %x " 1937 "strip_vlan_c_tag_decap: %x " 1938 "strip_vlan_s_tag_decap: %x " 1939 "pre_delim_count: %x " 1940 "ampdu_flag: %x " 1941 "bar_frame: %x " 1942 "mpdu_length: %x " 1943 "first_mpdu: %x " 1944 "mcast_bcast: %x " 1945 "ast_index_not_found: %x " 1946 "ast_index_timeout: %x ", 1947 mpdu_info->rx_reo_queue_desc_addr_39_32, 1948 mpdu_info->receive_queue_number, 1949 mpdu_info->pre_delim_err_warning, 1950 mpdu_info->first_delim_err, 1951 mpdu_info->key_id_octet, 1952 mpdu_info->new_peer_entry, 1953 mpdu_info->decrypt_needed, 1954 mpdu_info->decap_type, 1955 mpdu_info->rx_insert_vlan_c_tag_padding, 1956 mpdu_info->rx_insert_vlan_s_tag_padding, 1957 mpdu_info->strip_vlan_c_tag_decap, 1958 mpdu_info->strip_vlan_s_tag_decap, 1959 mpdu_info->pre_delim_count, 1960 mpdu_info->ampdu_flag, 1961 mpdu_info->bar_frame, 1962 mpdu_info->mpdu_length, 1963 mpdu_info->first_mpdu, 1964 mpdu_info->mcast_bcast, 1965 mpdu_info->ast_index_not_found, 1966 mpdu_info->ast_index_timeout); 1967 1968 hal_verbose_debug( 1969 "rx_mpdu_start tlv (4/5) - " 1970 "power_mgmt: %x " 1971 "non_qos: %x " 1972 "null_data: %x " 1973 "mgmt_type: %x " 1974 "ctrl_type: %x " 1975 "more_data: %x " 1976 "eosp: %x " 1977 "fragment_flag: %x " 1978 "order: %x " 1979 "u_apsd_trigger: %x " 1980 "encrypt_required: %x " 1981 "directed: %x " 1982 "mpdu_frame_control_field: %x " 1983 "mpdu_duration_field: %x " 1984 "mac_addr_ad1_31_0: %x " 1985 "mac_addr_ad1_47_32: %x " 1986 "mac_addr_ad2_15_0: %x " 1987 "mac_addr_ad2_47_16: %x " 1988 "mac_addr_ad3_31_0: %x " 1989 "mac_addr_ad3_47_32: %x ", 1990 mpdu_info->power_mgmt, 1991 mpdu_info->non_qos, 1992 mpdu_info->null_data, 1993 mpdu_info->mgmt_type, 1994 mpdu_info->ctrl_type, 1995 mpdu_info->more_data, 1996 mpdu_info->eosp, 1997 mpdu_info->fragment_flag, 1998 mpdu_info->order, 1999 mpdu_info->u_apsd_trigger, 2000 mpdu_info->encrypt_required, 2001 mpdu_info->directed, 2002 mpdu_info->mpdu_frame_control_field, 2003 mpdu_info->mpdu_duration_field, 2004 mpdu_info->mac_addr_ad1_31_0, 2005 mpdu_info->mac_addr_ad1_47_32, 2006 mpdu_info->mac_addr_ad2_15_0, 2007 mpdu_info->mac_addr_ad2_47_16, 2008 mpdu_info->mac_addr_ad3_31_0, 2009 mpdu_info->mac_addr_ad3_47_32); 2010 2011 hal_verbose_debug( 2012 "rx_mpdu_start tlv (5/5) - " 2013 "mpdu_sequence_control_field: %x " 2014 "mac_addr_ad4_31_0: %x " 2015 "mac_addr_ad4_47_32: %x " 2016 "mpdu_qos_control_field: %x " 2017 "mpdu_ht_control_field: %x ", 2018 mpdu_info->mpdu_sequence_control_field, 2019 mpdu_info->mac_addr_ad4_31_0, 2020 mpdu_info->mac_addr_ad4_47_32, 2021 mpdu_info->mpdu_qos_control_field, 2022 mpdu_info->mpdu_ht_control_field); 2023 } 2024 2025 /** 2026 * hal_tx_set_pcp_tid_map_generic_li() - Configure default PCP to TID map table 2027 * @soc: HAL SoC context 2028 * @map: PCP-TID mapping table 2029 * 2030 * PCP are mapped to 8 TID values using TID values programmed 2031 * in one set of mapping registers PCP_TID_MAP_<0 to 6> 2032 * The mapping register has TID mapping for 8 PCP values 2033 * 2034 * Return: none 2035 */ 2036 static void hal_tx_set_pcp_tid_map_generic_li(struct hal_soc *soc, uint8_t *map) 2037 { 2038 uint32_t addr, value; 2039 2040 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2041 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2042 2043 value = (map[0] | 2044 (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | 2045 (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | 2046 (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | 2047 (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | 2048 (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | 2049 (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | 2050 (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); 2051 2052 HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2053 } 2054 2055 /** 2056 * hal_tx_update_pcp_tid_generic_li() - Update the pcp tid map table with 2057 * value received from user-space 2058 * @soc: HAL SoC context 2059 * @pcp: pcp value 2060 * @tid : tid value 2061 * 2062 * Return: void 2063 */ 2064 static void 2065 hal_tx_update_pcp_tid_generic_li(struct hal_soc *soc, 2066 uint8_t pcp, uint8_t tid) 2067 { 2068 uint32_t addr, value, regval; 2069 2070 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2071 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2072 2073 value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); 2074 2075 /* Read back previous PCP TID config and update 2076 * with new config. 2077 */ 2078 regval = HAL_REG_READ(soc, addr); 2079 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); 2080 regval |= value; 2081 2082 HAL_REG_WRITE(soc, addr, 2083 (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2084 } 2085 2086 /** 2087 * hal_tx_update_tidmap_prty_generic_li() - Update the tid map priority 2088 * @soc: HAL SoC context 2089 * @value: priority value 2090 * 2091 * Return: void 2092 */ 2093 static 2094 void hal_tx_update_tidmap_prty_generic_li(struct hal_soc *soc, uint8_t value) 2095 { 2096 uint32_t addr; 2097 2098 addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( 2099 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2100 2101 HAL_REG_WRITE(soc, addr, 2102 (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); 2103 } 2104 2105 /** 2106 * hal_rx_msdu_packet_metadata_get_generic_li() - API to get the msdu 2107 * information from 2108 * rx_msdu_end TLV 2109 * @buf: pointer to the start of RX PKT TLV headers 2110 * @pkt_msdu_metadata: pointer to the msdu info structure 2111 */ 2112 static void 2113 hal_rx_msdu_packet_metadata_get_generic_li(uint8_t *buf, 2114 void *pkt_msdu_metadata) 2115 { 2116 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2117 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 2118 struct hal_rx_msdu_metadata *msdu_metadata = 2119 (struct hal_rx_msdu_metadata *)pkt_msdu_metadata; 2120 2121 msdu_metadata->l3_hdr_pad = 2122 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 2123 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 2124 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 2125 msdu_metadata->sa_sw_peer_id = 2126 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 2127 } 2128 2129 /** 2130 * hal_rx_msdu_end_offset_get_generic() - API to get the 2131 * msdu_end structure offset rx_pkt_tlv structure 2132 * 2133 * NOTE: API returns offset of msdu_end TLV from structure 2134 * rx_pkt_tlvs 2135 */ 2136 static uint32_t hal_rx_msdu_end_offset_get_generic(void) 2137 { 2138 return RX_PKT_TLV_OFFSET(msdu_end_tlv); 2139 } 2140 2141 /** 2142 * hal_rx_attn_offset_get_generic() - API to get the 2143 * msdu_end structure offset rx_pkt_tlv structure 2144 * 2145 * NOTE: API returns offset of attn TLV from structure 2146 * rx_pkt_tlvs 2147 */ 2148 static uint32_t hal_rx_attn_offset_get_generic(void) 2149 { 2150 return RX_PKT_TLV_OFFSET(attn_tlv); 2151 } 2152 2153 /** 2154 * hal_rx_msdu_start_offset_get_generic() - API to get the 2155 * msdu_start structure offset rx_pkt_tlv structure 2156 * 2157 * NOTE: API returns offset of attn TLV from structure 2158 * rx_pkt_tlvs 2159 */ 2160 static uint32_t hal_rx_msdu_start_offset_get_generic(void) 2161 { 2162 return RX_PKT_TLV_OFFSET(msdu_start_tlv); 2163 } 2164 2165 /** 2166 * hal_rx_mpdu_start_offset_get_generic() - API to get the 2167 * mpdu_start structure offset rx_pkt_tlv structure 2168 * 2169 * NOTE: API returns offset of attn TLV from structure 2170 * rx_pkt_tlvs 2171 */ 2172 static uint32_t hal_rx_mpdu_start_offset_get_generic(void) 2173 { 2174 return RX_PKT_TLV_OFFSET(mpdu_start_tlv); 2175 } 2176 2177 /** 2178 * hal_rx_mpdu_end_offset_get_generic() - API to get the 2179 * mpdu_end structure offset rx_pkt_tlv structure 2180 * 2181 * NOTE: API returns offset of attn TLV from structure 2182 * rx_pkt_tlvs 2183 */ 2184 static uint32_t hal_rx_mpdu_end_offset_get_generic(void) 2185 { 2186 return RX_PKT_TLV_OFFSET(mpdu_end_tlv); 2187 } 2188 2189 #ifndef NO_RX_PKT_HDR_TLV 2190 static uint32_t hal_rx_pkt_tlv_offset_get_generic(void) 2191 { 2192 return RX_PKT_TLV_OFFSET(pkt_hdr_tlv); 2193 } 2194 #endif 2195 2196 #if defined(QDF_BIG_ENDIAN_MACHINE) 2197 /** 2198 * hal_setup_reo_swap() - Set the swap flag for big endian machines 2199 * @soc: HAL soc handle 2200 * 2201 * Return: None 2202 */ 2203 static inline void hal_setup_reo_swap(struct hal_soc *soc) 2204 { 2205 uint32_t reg_val; 2206 2207 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR( 2208 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 2209 2210 reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, WRITE_STRUCT_SWAP, 1); 2211 reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, READ_STRUCT_SWAP, 1); 2212 2213 HAL_REG_WRITE(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR( 2214 SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val); 2215 } 2216 #else 2217 static inline void hal_setup_reo_swap(struct hal_soc *soc) 2218 { 2219 } 2220 #endif 2221 2222 /** 2223 * hal_reo_setup_generic_li() - Initialize HW REO block 2224 * @soc: Opaque HAL SOC handle 2225 * @reoparams: parameters needed by HAL for REO config 2226 * @qref_reset: reset qref 2227 */ 2228 static 2229 void hal_reo_setup_generic_li(struct hal_soc *soc, void *reoparams, 2230 int qref_reset) 2231 { 2232 uint32_t reg_val; 2233 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 2234 2235 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 2236 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 2237 2238 hal_reo_config(soc, reg_val, reo_params); 2239 /* Other ring enable bits and REO_ENABLE will be set by FW */ 2240 2241 /* TODO: Setup destination ring mapping if enabled */ 2242 2243 /* TODO: Error destination ring setting is left to default. 2244 * Default setting is to send all errors to release ring. 2245 */ 2246 2247 /* Set the reo descriptor swap bits in case of BIG endian platform */ 2248 hal_setup_reo_swap(soc); 2249 2250 HAL_REG_WRITE(soc, 2251 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 2252 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2253 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 2254 2255 HAL_REG_WRITE(soc, 2256 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 2257 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2258 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 2259 2260 HAL_REG_WRITE(soc, 2261 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 2262 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2263 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 2264 2265 HAL_REG_WRITE(soc, 2266 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 2267 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2268 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 2269 2270 /* 2271 * When hash based routing is enabled, routing of the rx packet 2272 * is done based on the following value: 1 _ _ _ _ The last 4 2273 * bits are based on hash[3:0]. This means the possible values 2274 * are 0x10 to 0x1f. This value is used to look-up the 2275 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 2276 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 2277 * registers need to be configured to set-up the 16 entries to 2278 * map the hash values to a ring number. There are 3 bits per 2279 * hash entry – which are mapped as follows: 2280 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 2281 * 7: NOT_USED. 2282 */ 2283 if (reo_params->rx_hash_enabled) { 2284 if (reo_params->remap0) 2285 HAL_REG_WRITE(soc, 2286 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR( 2287 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2288 reo_params->remap0); 2289 2290 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 0x%x", 2291 HAL_REG_READ(soc, 2292 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR( 2293 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 2294 2295 HAL_REG_WRITE(soc, 2296 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 2297 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2298 reo_params->remap1); 2299 2300 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 2301 HAL_REG_READ(soc, 2302 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 2303 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 2304 2305 HAL_REG_WRITE(soc, 2306 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 2307 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2308 reo_params->remap2); 2309 2310 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 2311 HAL_REG_READ(soc, 2312 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 2313 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 2314 } 2315 2316 /* TODO: Check if the following registers shoould be setup by host: 2317 * AGING_CONTROL 2318 * HIGH_MEMORY_THRESHOLD 2319 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 2320 * GLOBAL_LINK_DESC_COUNT_CTRL 2321 */ 2322 } 2323 2324 /** 2325 * hal_setup_link_idle_list_generic_li() - Setup scattered idle list 2326 * using the buffer list provided 2327 * @soc: Opaque HAL SOC handle 2328 * @scatter_bufs_base_paddr: Array of physical base addresses 2329 * @scatter_bufs_base_vaddr: Array of virtual base addresses 2330 * @num_scatter_bufs: Number of scatter buffers in the above lists 2331 * @scatter_buf_size: Size of each scatter buffer 2332 * @last_buf_end_offset: Offset to the last entry 2333 * @num_entries: Total entries of all scatter bufs 2334 * 2335 * Return: None 2336 */ 2337 static void 2338 hal_setup_link_idle_list_generic_li(struct hal_soc *soc, 2339 qdf_dma_addr_t scatter_bufs_base_paddr[], 2340 void *scatter_bufs_base_vaddr[], 2341 uint32_t num_scatter_bufs, 2342 uint32_t scatter_buf_size, 2343 uint32_t last_buf_end_offset, 2344 uint32_t num_entries) 2345 { 2346 int i; 2347 uint32_t *prev_buf_link_ptr = NULL; 2348 uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size; 2349 uint32_t val; 2350 2351 /* Link the scatter buffers */ 2352 for (i = 0; i < num_scatter_bufs; i++) { 2353 if (i > 0) { 2354 prev_buf_link_ptr[0] = 2355 scatter_bufs_base_paddr[i] & 0xffffffff; 2356 prev_buf_link_ptr[1] = HAL_SM( 2357 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2358 BASE_ADDRESS_39_32, 2359 ((uint64_t)(scatter_bufs_base_paddr[i]) 2360 >> 32)) | HAL_SM( 2361 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2362 ADDRESS_MATCH_TAG, 2363 ADDRESS_MATCH_TAG_VAL); 2364 } 2365 prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] + 2366 scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE); 2367 } 2368 2369 /* TBD: Register programming partly based on MLD & the rest based on 2370 * inputs from HW team. Not complete yet. 2371 */ 2372 2373 reg_scatter_buf_size = (scatter_buf_size - 2374 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64; 2375 reg_tot_scatter_buf_size = ((scatter_buf_size - 2376 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64; 2377 2378 HAL_REG_WRITE(soc, 2379 HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR 2380 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2381 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, 2382 SCATTER_BUFFER_SIZE, 2383 reg_scatter_buf_size) | 2384 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, 2385 LINK_DESC_IDLE_LIST_MODE, 0x1)); 2386 2387 HAL_REG_WRITE(soc, 2388 HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR 2389 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2390 HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE, 2391 SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST, 2392 reg_tot_scatter_buf_size)); 2393 2394 HAL_REG_WRITE(soc, 2395 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR 2396 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2397 scatter_bufs_base_paddr[0] & 0xffffffff); 2398 2399 HAL_REG_WRITE(soc, 2400 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR 2401 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2402 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) & 2403 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK); 2404 2405 HAL_REG_WRITE(soc, 2406 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR 2407 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2408 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2409 BASE_ADDRESS_39_32, 2410 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32)) | 2411 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2412 ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL)); 2413 2414 /* ADDRESS_MATCH_TAG field in the above register is expected to match 2415 * with the upper bits of link pointer. The above write sets this field 2416 * to zero and we are also setting the upper bits of link pointers to 2417 * zero while setting up the link list of scatter buffers above 2418 */ 2419 2420 /* Setup head and tail pointers for the idle list */ 2421 HAL_REG_WRITE(soc, 2422 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR 2423 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2424 scatter_bufs_base_paddr[num_scatter_bufs - 1] & 2425 0xffffffff); 2426 HAL_REG_WRITE(soc, 2427 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR 2428 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2429 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 2430 BUFFER_ADDRESS_39_32, 2431 ((uint64_t)(scatter_bufs_base_paddr 2432 [num_scatter_bufs - 1]) >> 32)) | 2433 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 2434 HEAD_POINTER_OFFSET, last_buf_end_offset >> 2)); 2435 2436 HAL_REG_WRITE(soc, 2437 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR 2438 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2439 scatter_bufs_base_paddr[0] & 0xffffffff); 2440 2441 HAL_REG_WRITE(soc, 2442 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR 2443 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2444 scatter_bufs_base_paddr[0] & 0xffffffff); 2445 HAL_REG_WRITE(soc, 2446 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR 2447 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2448 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 2449 BUFFER_ADDRESS_39_32, 2450 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32)) | 2451 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 2452 TAIL_POINTER_OFFSET, 0)); 2453 2454 HAL_REG_WRITE(soc, 2455 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR 2456 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2 * num_entries); 2457 2458 /* Set RING_ID_DISABLE */ 2459 val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1); 2460 2461 /* 2462 * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence 2463 * check the presence of the bit before toggling it. 2464 */ 2465 #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK 2466 val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1); 2467 #endif 2468 HAL_REG_WRITE(soc, 2469 HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR 2470 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2471 val); 2472 } 2473 2474 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 2475 /** 2476 * hal_tx_desc_set_search_type_generic_li() - Set the search type value 2477 * @desc: Handle to Tx Descriptor 2478 * @search_type: search type 2479 * 0 – Normal search 2480 * 1 – Index based address search 2481 * 2 – Index based flow search 2482 * 2483 * Return: void 2484 */ 2485 static inline 2486 void hal_tx_desc_set_search_type_generic_li(void *desc, uint8_t search_type) 2487 { 2488 HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= 2489 HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); 2490 } 2491 #else 2492 static inline 2493 void hal_tx_desc_set_search_type_generic_li(void *desc, uint8_t search_type) 2494 { 2495 } 2496 2497 #endif 2498 2499 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 2500 /** 2501 * hal_tx_desc_set_search_index_generic_li() - Set the search index value 2502 * @desc: Handle to Tx Descriptor 2503 * @search_index: The index that will be used for index based address or 2504 * flow search. The field is valid when 'search_type' is 2505 * 1 0r 2 2506 * 2507 * Return: void 2508 */ 2509 static inline 2510 void hal_tx_desc_set_search_index_generic_li(void *desc, uint32_t search_index) 2511 { 2512 HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= 2513 HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); 2514 } 2515 #else 2516 static inline 2517 void hal_tx_desc_set_search_index_generic_li(void *desc, uint32_t search_index) 2518 { 2519 } 2520 #endif 2521 2522 #ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 2523 /** 2524 * hal_tx_desc_set_cache_set_num_generic_li() - Set the cache-set-num value 2525 * @desc: Handle to Tx Descriptor 2526 * @cache_num: Cache set number that should be used to cache the index 2527 * based search results, for address and flow search. 2528 * This value should be equal to LSB four bits of the hash value 2529 * of match data, in case of search index points to an entry 2530 * which may be used in content based search also. The value can 2531 * be anything when the entry pointed by search index will not be 2532 * used for content based search. 2533 * 2534 * Return: void 2535 */ 2536 static inline 2537 void hal_tx_desc_set_cache_set_num_generic_li(void *desc, uint8_t cache_num) 2538 { 2539 HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |= 2540 HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num); 2541 } 2542 #else 2543 static inline 2544 void hal_tx_desc_set_cache_set_num_generic_li(void *desc, uint8_t cache_num) 2545 { 2546 } 2547 #endif 2548 2549 #ifdef WLAN_SUPPORT_RX_FISA 2550 /** 2551 * hal_rx_flow_get_tuple_info_li() - Setup a flow search entry in HW FST 2552 * @rx_fst: Pointer to the Rx Flow Search Table 2553 * @hal_hash: HAL 5 tuple hash 2554 * @flow_tuple_info: 5-tuple info of the flow returned to the caller 2555 * 2556 * Return: Success/Failure 2557 */ 2558 static void * 2559 hal_rx_flow_get_tuple_info_li(uint8_t *rx_fst, uint32_t hal_hash, 2560 uint8_t *flow_tuple_info) 2561 { 2562 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 2563 void *hal_fse = NULL; 2564 struct hal_flow_tuple_info *tuple_info 2565 = (struct hal_flow_tuple_info *)flow_tuple_info; 2566 2567 hal_fse = (uint8_t *)fst->base_vaddr + 2568 (hal_hash * HAL_RX_FST_ENTRY_SIZE); 2569 2570 if (!hal_fse || !tuple_info) 2571 return NULL; 2572 2573 if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY_9, VALID)) 2574 return NULL; 2575 2576 tuple_info->src_ip_127_96 = 2577 qdf_ntohl(HAL_GET_FLD(hal_fse, 2578 RX_FLOW_SEARCH_ENTRY_0, 2579 SRC_IP_127_96)); 2580 tuple_info->src_ip_95_64 = 2581 qdf_ntohl(HAL_GET_FLD(hal_fse, 2582 RX_FLOW_SEARCH_ENTRY_1, 2583 SRC_IP_95_64)); 2584 tuple_info->src_ip_63_32 = 2585 qdf_ntohl(HAL_GET_FLD(hal_fse, 2586 RX_FLOW_SEARCH_ENTRY_2, 2587 SRC_IP_63_32)); 2588 tuple_info->src_ip_31_0 = 2589 qdf_ntohl(HAL_GET_FLD(hal_fse, 2590 RX_FLOW_SEARCH_ENTRY_3, 2591 SRC_IP_31_0)); 2592 tuple_info->dest_ip_127_96 = 2593 qdf_ntohl(HAL_GET_FLD(hal_fse, 2594 RX_FLOW_SEARCH_ENTRY_4, 2595 DEST_IP_127_96)); 2596 tuple_info->dest_ip_95_64 = 2597 qdf_ntohl(HAL_GET_FLD(hal_fse, 2598 RX_FLOW_SEARCH_ENTRY_5, 2599 DEST_IP_95_64)); 2600 tuple_info->dest_ip_63_32 = 2601 qdf_ntohl(HAL_GET_FLD(hal_fse, 2602 RX_FLOW_SEARCH_ENTRY_6, 2603 DEST_IP_63_32)); 2604 tuple_info->dest_ip_31_0 = 2605 qdf_ntohl(HAL_GET_FLD(hal_fse, 2606 RX_FLOW_SEARCH_ENTRY_7, 2607 DEST_IP_31_0)); 2608 tuple_info->dest_port = HAL_GET_FLD(hal_fse, 2609 RX_FLOW_SEARCH_ENTRY_8, 2610 DEST_PORT); 2611 tuple_info->src_port = HAL_GET_FLD(hal_fse, 2612 RX_FLOW_SEARCH_ENTRY_8, 2613 SRC_PORT); 2614 tuple_info->l4_protocol = HAL_GET_FLD(hal_fse, 2615 RX_FLOW_SEARCH_ENTRY_9, 2616 L4_PROTOCOL); 2617 2618 return hal_fse; 2619 } 2620 2621 /** 2622 * hal_rx_flow_delete_entry_li() - Setup a flow search entry in HW FST 2623 * @rx_fst: Pointer to the Rx Flow Search Table 2624 * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST 2625 * 2626 * Return: Success/Failure 2627 */ 2628 static QDF_STATUS 2629 hal_rx_flow_delete_entry_li(uint8_t *rx_fst, void *hal_rx_fse) 2630 { 2631 uint8_t *fse = (uint8_t *)hal_rx_fse; 2632 2633 if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID)) 2634 return QDF_STATUS_E_NOENT; 2635 2636 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 2637 2638 return QDF_STATUS_SUCCESS; 2639 } 2640 2641 /** 2642 * hal_rx_fst_get_fse_size_li() - Retrieve the size of each entry 2643 * 2644 * Return: size of each entry/flow in Rx FST 2645 */ 2646 static inline uint32_t 2647 hal_rx_fst_get_fse_size_li(void) 2648 { 2649 return HAL_RX_FST_ENTRY_SIZE; 2650 } 2651 #else 2652 static inline void * 2653 hal_rx_flow_get_tuple_info_li(uint8_t *rx_fst, uint32_t hal_hash, 2654 uint8_t *flow_tuple_info) 2655 { 2656 return NULL; 2657 } 2658 2659 static inline QDF_STATUS 2660 hal_rx_flow_delete_entry_li(uint8_t *rx_fst, void *hal_rx_fse) 2661 { 2662 return QDF_STATUS_SUCCESS; 2663 } 2664 2665 static inline uint32_t 2666 hal_rx_fst_get_fse_size_li(void) 2667 { 2668 return 0; 2669 } 2670 #endif /* WLAN_SUPPORT_RX_FISA */ 2671 2672 /** 2673 * hal_rx_get_frame_ctrl_field_li() - Function to retrieve frame control field 2674 * @buf: Network buffer 2675 * 2676 * Return: rx more fragment bit 2677 */ 2678 static uint16_t hal_rx_get_frame_ctrl_field_li(uint8_t *buf) 2679 { 2680 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2681 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2682 uint16_t frame_ctrl = 0; 2683 2684 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 2685 2686 return frame_ctrl; 2687 } 2688 #endif /* _HAL_LI_GENERIC_API_H_ */ 2689