1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_LI_GENERIC_API_H_ 21 #define _HAL_LI_GENERIC_API_H_ 22 23 #include "hal_tx.h" 24 #include "hal_li_tx.h" 25 #include "hal_li_rx.h" 26 27 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) \ 28 (_HAL_MS((*_OFFSET_TO_WORD_PTR(wbm_desc, \ 29 WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET)), \ 30 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK, \ 31 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB)) 32 33 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) \ 34 (_HAL_MS((*_OFFSET_TO_WORD_PTR(wbm_desc, \ 35 WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET)), \ 36 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK, \ 37 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB)) 38 39 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 40 (((*(((uint32_t *)wbm_desc) + \ 41 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 42 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 43 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 44 45 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 46 (((*(((uint32_t *)wbm_desc) + \ 47 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 48 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 49 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 50 51 /** 52 * hal_rx_wbm_err_info_get_generic_li(): Retrieves WBM error code and reason and 53 * save it to hal_wbm_err_desc_info structure passed by caller 54 * @wbm_desc: wbm ring descriptor 55 * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 56 * Return: void 57 */ 58 static inline 59 void hal_rx_wbm_err_info_get_generic_li(void *wbm_desc, 60 void *wbm_er_info1) 61 { 62 struct hal_wbm_err_desc_info *wbm_er_info = 63 (struct hal_wbm_err_desc_info *)wbm_er_info1; 64 65 wbm_er_info->wbm_err_src = HAL_WBM2SW_RELEASE_SRC_GET(wbm_desc); 66 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 67 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 68 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 69 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 70 } 71 72 #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY) 73 static inline void 74 hal_tx_comp_get_buffer_timestamp_li(void *desc, 75 struct hal_tx_completion_status *ts) 76 { 77 ts->buffer_timestamp = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 78 BUFFER_TIMESTAMP); 79 } 80 #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */ 81 static inline void 82 hal_tx_comp_get_buffer_timestamp_li(void *desc, 83 struct hal_tx_completion_status *ts) 84 { 85 } 86 #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */ 87 88 #ifdef QCA_UNDECODED_METADATA_SUPPORT 89 static inline void 90 hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv, 91 struct hal_rx_ppdu_info *ppdu_info){ 92 switch (hal->target_type) { 93 case TARGET_TYPE_QCN9000: 94 ppdu_info->rx_status.phyrx_abort = 95 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, 96 PHYRX_ABORT_REQUEST_INFO_VALID); 97 ppdu_info->rx_status.phyrx_abort_reason = 98 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_11, 99 PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON); 100 break; 101 default: 102 break; 103 } 104 } 105 106 static inline void 107 hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info, 108 uint8_t *ht_sig_info) 109 { 110 ppdu_info->rx_status.ht_length = 111 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_0, LENGTH); 112 ppdu_info->rx_status.smoothing = 113 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, SMOOTHING); 114 ppdu_info->rx_status.not_sounding = 115 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, NOT_SOUNDING); 116 ppdu_info->rx_status.aggregation = 117 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, AGGREGATION); 118 ppdu_info->rx_status.ht_stbc = 119 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, STBC); 120 ppdu_info->rx_status.ht_crc = 121 HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, CRC); 122 } 123 124 static inline void 125 hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, 126 uint8_t *l_sig_a_info) 127 { 128 ppdu_info->rx_status.l_sig_length = 129 HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, LENGTH); 130 ppdu_info->rx_status.l_sig_a_parity = 131 HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PARITY); 132 ppdu_info->rx_status.l_sig_a_pkt_type = 133 HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PKT_TYPE); 134 ppdu_info->rx_status.l_sig_a_implicit_sounding = 135 HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, 136 CAPTURED_IMPLICIT_SOUNDING); 137 } 138 139 static inline void 140 hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, 141 uint8_t *vht_sig_a_info) 142 { 143 ppdu_info->rx_status.vht_no_txop_ps = 144 HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, 145 TXOP_PS_NOT_ALLOWED); 146 ppdu_info->rx_status.vht_crc = 147 HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, CRC); 148 } 149 150 static inline void 151 hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info, 152 uint8_t *he_sig_a_su_info) { 153 ppdu_info->rx_status.he_crc = 154 HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, CRC); 155 } 156 157 static inline void 158 hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info, 159 uint8_t *he_sig_a_mu_dl_info) { 160 ppdu_info->rx_status.he_crc = 161 HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, CRC); 162 } 163 #else 164 static inline void 165 hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv, 166 struct hal_rx_ppdu_info *ppdu_info) 167 { 168 } 169 170 static inline void 171 hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info, 172 uint8_t *ht_sig_info) 173 { 174 } 175 176 static inline void 177 hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, 178 uint8_t *l_sig_a_info) 179 { 180 } 181 182 static inline void 183 hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, 184 uint8_t *vht_sig_a_info) 185 { 186 } 187 188 static inline void 189 hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info, 190 uint8_t *he_sig_a_su_info) 191 { 192 } 193 194 static inline void 195 hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info, 196 uint8_t *he_sig_a_mu_dl_info) 197 { 198 } 199 #endif /* QCA_UNDECODED_METADATA_SUPPORT */ 200 201 /** 202 * hal_tx_comp_get_status() - TQM Release reason 203 * @hal_desc: completion ring Tx status 204 * 205 * This function will parse the WBM completion descriptor and populate in 206 * HAL structure 207 * 208 * Return: none 209 */ 210 static inline void 211 hal_tx_comp_get_status_generic_li(void *desc, void *ts1, 212 struct hal_soc *hal) 213 { 214 uint8_t rate_stats_valid = 0; 215 uint32_t rate_stats = 0; 216 struct hal_tx_completion_status *ts = 217 (struct hal_tx_completion_status *)ts1; 218 219 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 220 TQM_STATUS_NUMBER); 221 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 222 ACK_FRAME_RSSI); 223 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 224 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 225 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 226 MSDU_PART_OF_AMSDU); 227 228 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 229 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 230 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 231 TRANSMIT_COUNT); 232 233 rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS); 234 235 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 236 TX_RATE_STATS_INFO_VALID, rate_stats); 237 238 ts->valid = rate_stats_valid; 239 240 if (rate_stats_valid) { 241 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 242 rate_stats); 243 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 244 TRANSMIT_PKT_TYPE, rate_stats); 245 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 246 TRANSMIT_STBC, rate_stats); 247 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 248 rate_stats); 249 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 250 rate_stats); 251 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 252 rate_stats); 253 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 254 rate_stats); 255 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 256 rate_stats); 257 } 258 259 ts->release_src = hal_tx_comp_get_buffer_source( 260 hal_soc_to_hal_soc_handle(hal), 261 desc); 262 ts->status = hal_tx_comp_get_release_reason( 263 desc, 264 hal_soc_to_hal_soc_handle(hal)); 265 266 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 267 TX_RATE_STATS_INFO_TX_RATE_STATS); 268 269 hal_tx_comp_get_buffer_timestamp_li(desc, ts); 270 } 271 272 /** 273 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 274 * @desc: Handle to Tx Descriptor 275 * @paddr: Physical Address 276 * @pool_id: Return Buffer Manager ID 277 * @desc_id: Descriptor ID 278 * @type: 0 - Address points to a MSDU buffer 279 * 1 - Address points to MSDU extension descriptor 280 * 281 * Return: void 282 */ 283 static inline void 284 hal_tx_desc_set_buf_addr_generic_li(void *desc, dma_addr_t paddr, 285 uint8_t rbm_id, uint32_t desc_id, 286 uint8_t type) 287 { 288 /* Set buffer_addr_info.buffer_addr_31_0 */ 289 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, 290 BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 291 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 292 293 /* Set buffer_addr_info.buffer_addr_39_32 */ 294 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 295 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 296 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 297 (((uint64_t)paddr) >> 32)); 298 299 /* Set buffer_addr_info.return_buffer_manager = rbm id */ 300 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 301 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 302 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, 303 RETURN_BUFFER_MANAGER, rbm_id); 304 305 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 306 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 307 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 308 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, 309 desc_id); 310 311 /* Set Buffer or Ext Descriptor Type */ 312 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, 313 BUF_OR_EXT_DESC_TYPE) |= 314 HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 315 } 316 317 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) 318 /** 319 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 320 * tlv_tag: Taf of the TLVs 321 * rx_tlv: the pointer to the TLVs 322 * @ppdu_info: pointer to ppdu_info 323 * 324 * Return: true if the tlv is handled, false if not 325 */ 326 static inline bool 327 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 328 struct hal_rx_ppdu_info *ppdu_info) 329 { 330 uint32_t value; 331 332 switch (tlv_tag) { 333 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 334 { 335 uint8_t *he_sig_a_mu_ul_info = 336 (uint8_t *)rx_tlv + 337 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, 338 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 339 ppdu_info->rx_status.he_flags = 1; 340 341 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 342 FORMAT_INDICATION); 343 if (value == 0) { 344 ppdu_info->rx_status.he_data1 = 345 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 346 } else { 347 ppdu_info->rx_status.he_data1 = 348 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 349 } 350 351 /* data1 */ 352 ppdu_info->rx_status.he_data1 |= 353 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 354 QDF_MON_STATUS_HE_DL_UL_KNOWN | 355 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 356 357 /* data2 */ 358 ppdu_info->rx_status.he_data2 |= 359 QDF_MON_STATUS_TXOP_KNOWN; 360 361 /*data3*/ 362 value = HAL_RX_GET(he_sig_a_mu_ul_info, 363 HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID); 364 ppdu_info->rx_status.he_data3 = value; 365 /* 1 for UL and 0 for DL */ 366 value = 1; 367 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 368 ppdu_info->rx_status.he_data3 |= value; 369 370 /*data4*/ 371 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 372 SPATIAL_REUSE); 373 ppdu_info->rx_status.he_data4 = value; 374 375 /*data5*/ 376 value = HAL_RX_GET(he_sig_a_mu_ul_info, 377 HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW); 378 ppdu_info->rx_status.he_data5 = value; 379 ppdu_info->rx_status.bw = value; 380 381 /*data6*/ 382 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1, 383 TXOP_DURATION); 384 value = value << QDF_MON_STATUS_TXOP_SHIFT; 385 ppdu_info->rx_status.he_data6 |= value; 386 return true; 387 } 388 default: 389 return false; 390 } 391 } 392 #else 393 static inline bool 394 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 395 struct hal_rx_ppdu_info *ppdu_info) 396 { 397 return false; 398 } 399 #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */ 400 401 #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) && \ 402 defined(RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 403 404 static inline void 405 hal_rx_handle_mu_ul_info(void *rx_tlv, 406 struct mon_rx_user_status *mon_rx_user_status) 407 { 408 mon_rx_user_status->mu_ul_user_v0_word0 = 409 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_11, 410 SW_RESPONSE_REFERENCE_PTR); 411 412 mon_rx_user_status->mu_ul_user_v0_word1 = 413 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_22, 414 SW_RESPONSE_REFERENCE_PTR_EXT); 415 } 416 417 static inline void 418 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 419 struct mon_rx_user_status *mon_rx_user_status) 420 { 421 uint32_t mpdu_ok_byte_count; 422 uint32_t mpdu_err_byte_count; 423 424 mpdu_ok_byte_count = HAL_RX_GET(rx_tlv, 425 RX_PPDU_END_USER_STATS_17, 426 MPDU_OK_BYTE_COUNT); 427 mpdu_err_byte_count = HAL_RX_GET(rx_tlv, 428 RX_PPDU_END_USER_STATS_19, 429 MPDU_ERR_BYTE_COUNT); 430 431 mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count; 432 mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count; 433 } 434 #else 435 static inline void 436 hal_rx_handle_mu_ul_info(void *rx_tlv, 437 struct mon_rx_user_status *mon_rx_user_status) 438 { 439 } 440 441 static inline void 442 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 443 struct mon_rx_user_status *mon_rx_user_status) 444 { 445 struct hal_rx_ppdu_info *ppdu_info = 446 (struct hal_rx_ppdu_info *)ppduinfo; 447 448 /* HKV1: doesn't support mpdu byte count */ 449 mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len; 450 mon_rx_user_status->mpdu_err_byte_count = 0; 451 } 452 #endif 453 454 static inline void 455 hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id, 456 struct mon_rx_user_status *mon_rx_user_status) 457 { 458 struct mon_rx_info *mon_rx_info; 459 struct mon_rx_user_info *mon_rx_user_info; 460 struct hal_rx_ppdu_info *ppdu_info = 461 (struct hal_rx_ppdu_info *)ppduinfo; 462 463 mon_rx_info = &ppdu_info->rx_info; 464 mon_rx_user_info = &ppdu_info->rx_user_info[user_id]; 465 mon_rx_user_info->qos_control_info_valid = 466 mon_rx_info->qos_control_info_valid; 467 mon_rx_user_info->qos_control = mon_rx_info->qos_control; 468 469 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 470 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 471 mon_rx_user_status->tcp_msdu_count = 472 ppdu_info->rx_status.tcp_msdu_count; 473 mon_rx_user_status->udp_msdu_count = 474 ppdu_info->rx_status.udp_msdu_count; 475 mon_rx_user_status->other_msdu_count = 476 ppdu_info->rx_status.other_msdu_count; 477 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 478 mon_rx_user_status->frame_control_info_valid = 479 ppdu_info->rx_status.frame_control_info_valid; 480 mon_rx_user_status->data_sequence_control_info_valid = 481 ppdu_info->rx_status.data_sequence_control_info_valid; 482 mon_rx_user_status->first_data_seq_ctrl = 483 ppdu_info->rx_status.first_data_seq_ctrl; 484 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 485 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 486 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 487 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 488 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 489 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 490 491 mon_rx_user_status->mpdu_cnt_fcs_ok = 492 ppdu_info->com_info.mpdu_cnt_fcs_ok; 493 mon_rx_user_status->mpdu_cnt_fcs_err = 494 ppdu_info->com_info.mpdu_cnt_fcs_err; 495 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 496 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 497 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 498 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 499 500 hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status); 501 } 502 503 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \ 504 ppdu_info, rssi_info_tlv) \ 505 { \ 506 ppdu_info->rx_status.rssi_chain[chain][0] = \ 507 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 508 RSSI_PRI20_CHAIN##chain); \ 509 ppdu_info->rx_status.rssi_chain[chain][1] = \ 510 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 511 RSSI_EXT20_CHAIN##chain); \ 512 ppdu_info->rx_status.rssi_chain[chain][2] = \ 513 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 514 RSSI_EXT40_LOW20_CHAIN##chain); \ 515 ppdu_info->rx_status.rssi_chain[chain][3] = \ 516 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 517 RSSI_EXT40_HIGH20_CHAIN##chain); \ 518 ppdu_info->rx_status.rssi_chain[chain][4] = \ 519 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 520 RSSI_EXT80_LOW20_CHAIN##chain); \ 521 ppdu_info->rx_status.rssi_chain[chain][5] = \ 522 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 523 RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \ 524 ppdu_info->rx_status.rssi_chain[chain][6] = \ 525 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 526 RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \ 527 ppdu_info->rx_status.rssi_chain[chain][7] = \ 528 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 529 RSSI_EXT80_HIGH20_CHAIN##chain); \ 530 } \ 531 532 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 533 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \ 534 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \ 535 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \ 536 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \ 537 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \ 538 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \ 539 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \ 540 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \ 541 542 static inline uint32_t 543 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 544 uint8_t *rssi_info_tlv) 545 { 546 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 547 return 0; 548 } 549 550 #ifdef WLAN_TX_PKT_CAPTURE_ENH 551 static inline void 552 hal_get_qos_control(void *rx_tlv, 553 struct hal_rx_ppdu_info *ppdu_info) 554 { 555 ppdu_info->rx_info.qos_control_info_valid = 556 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 557 QOS_CONTROL_INFO_VALID); 558 559 if (ppdu_info->rx_info.qos_control_info_valid) 560 ppdu_info->rx_info.qos_control = 561 HAL_RX_GET(rx_tlv, 562 RX_PPDU_END_USER_STATS_5, 563 QOS_CONTROL_FIELD); 564 } 565 566 static inline void 567 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 568 struct hal_rx_ppdu_info *ppdu_info) 569 { 570 if ((ppdu_info->sw_frame_group_id 571 == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) || 572 (ppdu_info->sw_frame_group_id == 573 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) { 574 ppdu_info->rx_info.mac_addr1_valid = 575 HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start); 576 577 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] = 578 HAL_RX_GET(rx_mpdu_start, 579 RX_MPDU_INFO_15, 580 MAC_ADDR_AD1_31_0); 581 if (ppdu_info->sw_frame_group_id == 582 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) { 583 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] = 584 HAL_RX_GET(rx_mpdu_start, 585 RX_MPDU_INFO_16, 586 MAC_ADDR_AD1_47_32); 587 } 588 } 589 } 590 #else 591 static inline void 592 hal_get_qos_control(void *rx_tlv, 593 struct hal_rx_ppdu_info *ppdu_info) 594 { 595 } 596 597 static inline void 598 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 599 struct hal_rx_ppdu_info *ppdu_info) 600 { 601 } 602 #endif 603 604 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS 605 static inline void 606 hal_update_frame_type_cnt(uint8_t *rx_mpdu_start, 607 struct hal_rx_ppdu_info *ppdu_info) 608 { 609 uint16_t frame_ctrl; 610 uint8_t fc_type; 611 612 if (HAL_RX_GET_FC_VALID(rx_mpdu_start)) { 613 frame_ctrl = HAL_RX_GET(rx_mpdu_start, 614 RX_MPDU_INFO_14, 615 MPDU_FRAME_CONTROL_FIELD); 616 fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl); 617 if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT) 618 ppdu_info->frm_type_info.rx_mgmt_cnt++; 619 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL) 620 ppdu_info->frm_type_info.rx_ctrl_cnt++; 621 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA) 622 ppdu_info->frm_type_info.rx_data_cnt++; 623 } 624 } 625 #else 626 static inline void 627 hal_update_frame_type_cnt(uint8_t *rx_mpdu_start, 628 struct hal_rx_ppdu_info *ppdu_info) 629 { 630 } 631 #endif 632 633 /** 634 * hal_rx_status_get_tlv_info() - process receive info TLV 635 * @rx_tlv_hdr: pointer to TLV header 636 * @ppdu_info: pointer to ppdu_info 637 * 638 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 639 */ 640 static inline uint32_t 641 hal_rx_status_get_tlv_info_generic_li(void *rx_tlv_hdr, void *ppduinfo, 642 hal_soc_handle_t hal_soc_hdl, 643 qdf_nbuf_t nbuf) 644 { 645 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 646 uint32_t tlv_tag, user_id, tlv_len, value; 647 uint8_t group_id = 0; 648 uint8_t he_dcm = 0; 649 uint8_t he_stbc = 0; 650 uint16_t he_gi = 0; 651 uint16_t he_ltf = 0; 652 void *rx_tlv; 653 bool unhandled = false; 654 struct mon_rx_user_status *mon_rx_user_status; 655 struct hal_rx_ppdu_info *ppdu_info = 656 (struct hal_rx_ppdu_info *)ppduinfo; 657 658 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 659 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 660 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 661 662 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 663 664 switch (tlv_tag) { 665 case WIFIRX_PPDU_START_E: 666 { 667 if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id == 668 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, PHY_PPDU_ID))) 669 hal_err("Matching ppdu_id(%u) detected", 670 ppdu_info->com_info.last_ppdu_id); 671 672 /* Reset ppdu_info before processing the ppdu */ 673 qdf_mem_zero(ppdu_info, 674 sizeof(struct hal_rx_ppdu_info)); 675 676 ppdu_info->com_info.last_ppdu_id = 677 ppdu_info->com_info.ppdu_id = 678 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 679 PHY_PPDU_ID); 680 681 /* channel number is set in PHY meta data */ 682 ppdu_info->rx_status.chan_num = 683 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 684 SW_PHY_META_DATA) & 0x0000FFFF); 685 ppdu_info->rx_status.chan_freq = 686 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 687 SW_PHY_META_DATA) & 0xFFFF0000) >> 16; 688 if (ppdu_info->rx_status.chan_num) { 689 ppdu_info->rx_status.chan_freq = 690 hal_rx_radiotap_num_to_freq( 691 ppdu_info->rx_status.chan_num, 692 ppdu_info->rx_status.chan_freq); 693 } 694 ppdu_info->com_info.ppdu_timestamp = 695 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 696 PPDU_START_TIMESTAMP); 697 ppdu_info->rx_status.ppdu_timestamp = 698 ppdu_info->com_info.ppdu_timestamp; 699 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 700 701 break; 702 } 703 704 case WIFIRX_PPDU_START_USER_INFO_E: 705 break; 706 707 case WIFIRX_PPDU_END_E: 708 dp_nofl_debug("[%s][%d] ppdu_end_e len=%d", 709 __func__, __LINE__, tlv_len); 710 /* This is followed by sub-TLVs of PPDU_END */ 711 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 712 break; 713 714 case WIFIPHYRX_PKT_END_E: 715 hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); 716 break; 717 718 case WIFIRXPCU_PPDU_END_INFO_E: 719 ppdu_info->rx_status.rx_antenna = 720 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, RX_ANTENNA); 721 ppdu_info->rx_status.tsft = 722 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 723 WB_TIMESTAMP_UPPER_32); 724 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 725 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 726 WB_TIMESTAMP_LOWER_32); 727 ppdu_info->rx_status.duration = 728 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 729 RX_PPDU_DURATION); 730 hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); 731 hal_rx_get_phyrx_abort(hal, rx_tlv, ppdu_info); 732 break; 733 734 /* 735 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 736 * for MU, based on num users we see this tlv that many times. 737 */ 738 case WIFIRX_PPDU_END_USER_STATS_E: 739 { 740 unsigned long tid = 0; 741 uint16_t seq = 0; 742 743 ppdu_info->rx_status.ast_index = 744 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 745 AST_INDEX); 746 747 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 748 RECEIVED_QOS_DATA_TID_BITMAP); 749 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, 750 sizeof(tid) * 8); 751 752 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 753 ppdu_info->rx_status.tid = HAL_TID_INVALID; 754 755 ppdu_info->rx_status.tcp_msdu_count = 756 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 757 TCP_MSDU_COUNT) + 758 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 759 TCP_ACK_MSDU_COUNT); 760 ppdu_info->rx_status.udp_msdu_count = 761 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 762 UDP_MSDU_COUNT); 763 ppdu_info->rx_status.other_msdu_count = 764 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 765 OTHER_MSDU_COUNT); 766 767 if (ppdu_info->sw_frame_group_id 768 != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 769 ppdu_info->rx_status.frame_control_info_valid = 770 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 771 FRAME_CONTROL_INFO_VALID); 772 773 if (ppdu_info->rx_status.frame_control_info_valid) 774 ppdu_info->rx_status.frame_control = 775 HAL_RX_GET(rx_tlv, 776 RX_PPDU_END_USER_STATS_4, 777 FRAME_CONTROL_FIELD); 778 779 hal_get_qos_control(rx_tlv, ppdu_info); 780 } 781 782 ppdu_info->rx_status.data_sequence_control_info_valid = 783 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 784 DATA_SEQUENCE_CONTROL_INFO_VALID); 785 786 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 787 FIRST_DATA_SEQ_CTRL); 788 if (ppdu_info->rx_status.data_sequence_control_info_valid) 789 ppdu_info->rx_status.first_data_seq_ctrl = seq; 790 791 ppdu_info->rx_status.preamble_type = 792 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 793 HT_CONTROL_FIELD_PKT_TYPE); 794 switch (ppdu_info->rx_status.preamble_type) { 795 case HAL_RX_PKT_TYPE_11N: 796 ppdu_info->rx_status.ht_flags = 1; 797 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 798 break; 799 case HAL_RX_PKT_TYPE_11AC: 800 ppdu_info->rx_status.vht_flags = 1; 801 break; 802 case HAL_RX_PKT_TYPE_11AX: 803 ppdu_info->rx_status.he_flags = 1; 804 break; 805 default: 806 break; 807 } 808 809 ppdu_info->com_info.mpdu_cnt_fcs_ok = 810 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 811 MPDU_CNT_FCS_OK); 812 ppdu_info->com_info.mpdu_cnt_fcs_err = 813 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 814 MPDU_CNT_FCS_ERR); 815 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 816 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 817 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 818 else 819 ppdu_info->rx_status.rs_flags &= 820 (~IEEE80211_AMPDU_FLAG); 821 822 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 823 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_7, 824 FCS_OK_BITMAP_31_0); 825 826 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 827 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_8, 828 FCS_OK_BITMAP_63_32); 829 830 if (user_id < HAL_MAX_UL_MU_USERS) { 831 mon_rx_user_status = 832 &ppdu_info->rx_user_status[user_id]; 833 834 hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status); 835 836 ppdu_info->com_info.num_users++; 837 838 hal_rx_populate_mu_user_info(rx_tlv, ppdu_info, 839 user_id, 840 mon_rx_user_status); 841 } 842 break; 843 } 844 845 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 846 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 847 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_1, 848 FCS_OK_BITMAP_95_64); 849 850 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 851 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_2, 852 FCS_OK_BITMAP_127_96); 853 854 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 855 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_3, 856 FCS_OK_BITMAP_159_128); 857 858 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 859 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_4, 860 FCS_OK_BITMAP_191_160); 861 862 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 863 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_5, 864 FCS_OK_BITMAP_223_192); 865 866 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 867 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_6, 868 FCS_OK_BITMAP_255_224); 869 break; 870 871 case WIFIRX_PPDU_END_STATUS_DONE_E: 872 return HAL_TLV_STATUS_PPDU_DONE; 873 874 case WIFIDUMMY_E: 875 return HAL_TLV_STATUS_BUF_DONE; 876 877 case WIFIPHYRX_HT_SIG_E: 878 { 879 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 880 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 881 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 882 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 883 FEC_CODING); 884 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 885 1 : 0; 886 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 887 HT_SIG_INFO_0, MCS); 888 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 889 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 890 HT_SIG_INFO_0, CBW); 891 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 892 HT_SIG_INFO_1, SHORT_GI); 893 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 894 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 895 HT_SIG_SU_NSS_SHIFT) + 1; 896 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 897 hal_rx_get_ht_sig_info(ppdu_info, ht_sig_info); 898 break; 899 } 900 901 case WIFIPHYRX_L_SIG_B_E: 902 { 903 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 904 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 905 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 906 907 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 908 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 909 switch (value) { 910 case 1: 911 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 912 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 913 break; 914 case 2: 915 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 916 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 917 break; 918 case 3: 919 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 920 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 921 break; 922 case 4: 923 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 924 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 925 break; 926 case 5: 927 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 928 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 929 break; 930 case 6: 931 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 932 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 933 break; 934 case 7: 935 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 936 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 937 break; 938 default: 939 break; 940 } 941 ppdu_info->rx_status.cck_flag = 1; 942 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 943 break; 944 } 945 946 case WIFIPHYRX_L_SIG_A_E: 947 { 948 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 949 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 950 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 951 952 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 953 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 954 switch (value) { 955 case 8: 956 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 957 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 958 break; 959 case 9: 960 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 961 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 962 break; 963 case 10: 964 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 965 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 966 break; 967 case 11: 968 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 969 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 970 break; 971 case 12: 972 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 973 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 974 break; 975 case 13: 976 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 977 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 978 break; 979 case 14: 980 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 981 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 982 break; 983 case 15: 984 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 985 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 986 break; 987 default: 988 break; 989 } 990 ppdu_info->rx_status.ofdm_flag = 1; 991 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 992 hal_rx_get_l_sig_a_info(ppdu_info, l_sig_a_info); 993 break; 994 } 995 996 case WIFIPHYRX_VHT_SIG_A_E: 997 { 998 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 999 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 1000 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 1001 1002 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 1003 SU_MU_CODING); 1004 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 1005 1 : 0; 1006 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, 1007 GROUP_ID); 1008 ppdu_info->rx_status.vht_flag_values5 = group_id; 1009 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 1010 VHT_SIG_A_INFO_1, MCS); 1011 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 1012 VHT_SIG_A_INFO_1, GI_SETTING); 1013 1014 switch (hal->target_type) { 1015 case TARGET_TYPE_QCA8074: 1016 case TARGET_TYPE_QCA8074V2: 1017 case TARGET_TYPE_QCA6018: 1018 case TARGET_TYPE_QCA5018: 1019 case TARGET_TYPE_QCN9000: 1020 case TARGET_TYPE_QCN6122: 1021 #ifdef QCA_WIFI_QCA6390 1022 case TARGET_TYPE_QCA6390: 1023 #endif 1024 case TARGET_TYPE_QCA6490: 1025 ppdu_info->rx_status.is_stbc = 1026 HAL_RX_GET(vht_sig_a_info, 1027 VHT_SIG_A_INFO_0, STBC); 1028 value = HAL_RX_GET(vht_sig_a_info, 1029 VHT_SIG_A_INFO_0, N_STS); 1030 value = value & VHT_SIG_SU_NSS_MASK; 1031 if (ppdu_info->rx_status.is_stbc && (value > 0)) 1032 value = ((value + 1) >> 1) - 1; 1033 ppdu_info->rx_status.nss = 1034 ((value & VHT_SIG_SU_NSS_MASK) + 1); 1035 1036 break; 1037 case TARGET_TYPE_QCA6290: 1038 #if !defined(QCA_WIFI_QCA6290_11AX) 1039 ppdu_info->rx_status.is_stbc = 1040 HAL_RX_GET(vht_sig_a_info, 1041 VHT_SIG_A_INFO_0, STBC); 1042 value = HAL_RX_GET(vht_sig_a_info, 1043 VHT_SIG_A_INFO_0, N_STS); 1044 value = value & VHT_SIG_SU_NSS_MASK; 1045 if (ppdu_info->rx_status.is_stbc && (value > 0)) 1046 value = ((value + 1) >> 1) - 1; 1047 ppdu_info->rx_status.nss = 1048 ((value & VHT_SIG_SU_NSS_MASK) + 1); 1049 #else 1050 ppdu_info->rx_status.nss = 0; 1051 #endif 1052 break; 1053 case TARGET_TYPE_QCA6750: 1054 ppdu_info->rx_status.nss = 0; 1055 break; 1056 default: 1057 break; 1058 } 1059 ppdu_info->rx_status.vht_flag_values3[0] = 1060 (((ppdu_info->rx_status.mcs) << 4) 1061 | ppdu_info->rx_status.nss); 1062 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 1063 VHT_SIG_A_INFO_0, BANDWIDTH); 1064 ppdu_info->rx_status.vht_flag_values2 = 1065 ppdu_info->rx_status.bw; 1066 ppdu_info->rx_status.vht_flag_values4 = 1067 HAL_RX_GET(vht_sig_a_info, 1068 VHT_SIG_A_INFO_1, SU_MU_CODING); 1069 1070 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 1071 VHT_SIG_A_INFO_1, BEAMFORMED); 1072 if (group_id == 0 || group_id == 63) 1073 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1074 else 1075 ppdu_info->rx_status.reception_type = 1076 HAL_RX_TYPE_MU_MIMO; 1077 1078 hal_rx_get_vht_sig_a_info(ppdu_info, vht_sig_a_info); 1079 break; 1080 } 1081 case WIFIPHYRX_HE_SIG_A_SU_E: 1082 { 1083 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 1084 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 1085 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 1086 ppdu_info->rx_status.he_flags = 1; 1087 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 1088 FORMAT_INDICATION); 1089 if (value == 0) { 1090 ppdu_info->rx_status.he_data1 = 1091 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1092 } else { 1093 ppdu_info->rx_status.he_data1 = 1094 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 1095 } 1096 1097 /* data1 */ 1098 ppdu_info->rx_status.he_data1 |= 1099 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 1100 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 1101 QDF_MON_STATUS_HE_DL_UL_KNOWN | 1102 QDF_MON_STATUS_HE_MCS_KNOWN | 1103 QDF_MON_STATUS_HE_DCM_KNOWN | 1104 QDF_MON_STATUS_HE_CODING_KNOWN | 1105 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 1106 QDF_MON_STATUS_HE_STBC_KNOWN | 1107 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 1108 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 1109 1110 /* data2 */ 1111 ppdu_info->rx_status.he_data2 = 1112 QDF_MON_STATUS_HE_GI_KNOWN; 1113 ppdu_info->rx_status.he_data2 |= 1114 QDF_MON_STATUS_TXBF_KNOWN | 1115 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1116 QDF_MON_STATUS_TXOP_KNOWN | 1117 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1118 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1119 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1120 1121 /* data3 */ 1122 value = HAL_RX_GET(he_sig_a_su_info, 1123 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 1124 ppdu_info->rx_status.he_data3 = value; 1125 value = HAL_RX_GET(he_sig_a_su_info, 1126 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 1127 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 1128 ppdu_info->rx_status.he_data3 |= value; 1129 value = HAL_RX_GET(he_sig_a_su_info, 1130 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 1131 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1132 ppdu_info->rx_status.he_data3 |= value; 1133 1134 value = HAL_RX_GET(he_sig_a_su_info, 1135 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 1136 ppdu_info->rx_status.mcs = value; 1137 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1138 ppdu_info->rx_status.he_data3 |= value; 1139 1140 value = HAL_RX_GET(he_sig_a_su_info, 1141 HE_SIG_A_SU_INFO_0, DCM); 1142 he_dcm = value; 1143 value = value << QDF_MON_STATUS_DCM_SHIFT; 1144 ppdu_info->rx_status.he_data3 |= value; 1145 value = HAL_RX_GET(he_sig_a_su_info, 1146 HE_SIG_A_SU_INFO_1, CODING); 1147 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 1148 1 : 0; 1149 value = value << QDF_MON_STATUS_CODING_SHIFT; 1150 ppdu_info->rx_status.he_data3 |= value; 1151 value = HAL_RX_GET(he_sig_a_su_info, 1152 HE_SIG_A_SU_INFO_1, 1153 LDPC_EXTRA_SYMBOL); 1154 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1155 ppdu_info->rx_status.he_data3 |= value; 1156 value = HAL_RX_GET(he_sig_a_su_info, 1157 HE_SIG_A_SU_INFO_1, STBC); 1158 he_stbc = value; 1159 value = value << QDF_MON_STATUS_STBC_SHIFT; 1160 ppdu_info->rx_status.he_data3 |= value; 1161 1162 /* data4 */ 1163 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 1164 SPATIAL_REUSE); 1165 ppdu_info->rx_status.he_data4 = value; 1166 1167 /* data5 */ 1168 value = HAL_RX_GET(he_sig_a_su_info, 1169 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 1170 ppdu_info->rx_status.he_data5 = value; 1171 ppdu_info->rx_status.bw = value; 1172 value = HAL_RX_GET(he_sig_a_su_info, 1173 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 1174 switch (value) { 1175 case 0: 1176 he_gi = HE_GI_0_8; 1177 he_ltf = HE_LTF_1_X; 1178 break; 1179 case 1: 1180 he_gi = HE_GI_0_8; 1181 he_ltf = HE_LTF_2_X; 1182 break; 1183 case 2: 1184 he_gi = HE_GI_1_6; 1185 he_ltf = HE_LTF_2_X; 1186 break; 1187 case 3: 1188 if (he_dcm && he_stbc) { 1189 he_gi = HE_GI_0_8; 1190 he_ltf = HE_LTF_4_X; 1191 } else { 1192 he_gi = HE_GI_3_2; 1193 he_ltf = HE_LTF_4_X; 1194 } 1195 break; 1196 } 1197 ppdu_info->rx_status.sgi = he_gi; 1198 ppdu_info->rx_status.ltf_size = he_ltf; 1199 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 1200 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1201 ppdu_info->rx_status.he_data5 |= value; 1202 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1203 ppdu_info->rx_status.he_data5 |= value; 1204 1205 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 1206 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1207 ppdu_info->rx_status.he_data5 |= value; 1208 1209 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1210 PACKET_EXTENSION_A_FACTOR); 1211 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1212 ppdu_info->rx_status.he_data5 |= value; 1213 1214 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 1215 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1216 ppdu_info->rx_status.he_data5 |= value; 1217 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1218 PACKET_EXTENSION_PE_DISAMBIGUITY); 1219 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1220 ppdu_info->rx_status.he_data5 |= value; 1221 1222 /* data6 */ 1223 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 1224 value++; 1225 ppdu_info->rx_status.nss = value; 1226 ppdu_info->rx_status.he_data6 = value; 1227 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1228 DOPPLER_INDICATION); 1229 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1230 ppdu_info->rx_status.he_data6 |= value; 1231 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1232 TXOP_DURATION); 1233 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1234 ppdu_info->rx_status.he_data6 |= value; 1235 1236 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 1237 HE_SIG_A_SU_INFO_1, TXBF); 1238 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1239 hal_rx_get_crc_he_sig_a_su_info(ppdu_info, he_sig_a_su_info); 1240 break; 1241 } 1242 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 1243 { 1244 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 1245 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 1246 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 1247 1248 ppdu_info->rx_status.he_mu_flags = 1; 1249 1250 /* HE Flags */ 1251 /*data1*/ 1252 ppdu_info->rx_status.he_data1 = 1253 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1254 ppdu_info->rx_status.he_data1 |= 1255 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 1256 QDF_MON_STATUS_HE_DL_UL_KNOWN | 1257 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 1258 QDF_MON_STATUS_HE_STBC_KNOWN | 1259 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 1260 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 1261 1262 /* data2 */ 1263 ppdu_info->rx_status.he_data2 = 1264 QDF_MON_STATUS_HE_GI_KNOWN; 1265 ppdu_info->rx_status.he_data2 |= 1266 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1267 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1268 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1269 QDF_MON_STATUS_TXOP_KNOWN | 1270 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1271 1272 /*data3*/ 1273 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1274 HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); 1275 ppdu_info->rx_status.he_data3 = value; 1276 1277 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1278 HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); 1279 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1280 ppdu_info->rx_status.he_data3 |= value; 1281 1282 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1283 HE_SIG_A_MU_DL_INFO_1, 1284 LDPC_EXTRA_SYMBOL); 1285 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1286 ppdu_info->rx_status.he_data3 |= value; 1287 1288 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1289 HE_SIG_A_MU_DL_INFO_1, STBC); 1290 he_stbc = value; 1291 value = value << QDF_MON_STATUS_STBC_SHIFT; 1292 ppdu_info->rx_status.he_data3 |= value; 1293 1294 /*data4*/ 1295 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1296 SPATIAL_REUSE); 1297 ppdu_info->rx_status.he_data4 = value; 1298 1299 /*data5*/ 1300 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1301 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1302 ppdu_info->rx_status.he_data5 = value; 1303 ppdu_info->rx_status.bw = value; 1304 1305 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1306 HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); 1307 switch (value) { 1308 case 0: 1309 he_gi = HE_GI_0_8; 1310 he_ltf = HE_LTF_4_X; 1311 break; 1312 case 1: 1313 he_gi = HE_GI_0_8; 1314 he_ltf = HE_LTF_2_X; 1315 break; 1316 case 2: 1317 he_gi = HE_GI_1_6; 1318 he_ltf = HE_LTF_2_X; 1319 break; 1320 case 3: 1321 he_gi = HE_GI_3_2; 1322 he_ltf = HE_LTF_4_X; 1323 break; 1324 } 1325 ppdu_info->rx_status.sgi = he_gi; 1326 ppdu_info->rx_status.ltf_size = he_ltf; 1327 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 1328 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1329 ppdu_info->rx_status.he_data5 |= value; 1330 1331 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1332 ppdu_info->rx_status.he_data5 |= value; 1333 1334 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1335 HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); 1336 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1337 ppdu_info->rx_status.he_data5 |= value; 1338 1339 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1340 PACKET_EXTENSION_A_FACTOR); 1341 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1342 ppdu_info->rx_status.he_data5 |= value; 1343 1344 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1345 PACKET_EXTENSION_PE_DISAMBIGUITY); 1346 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1347 ppdu_info->rx_status.he_data5 |= value; 1348 1349 /*data6*/ 1350 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1351 DOPPLER_INDICATION); 1352 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1353 ppdu_info->rx_status.he_data6 |= value; 1354 1355 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1356 TXOP_DURATION); 1357 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1358 ppdu_info->rx_status.he_data6 |= value; 1359 1360 /* HE-MU Flags */ 1361 /* HE-MU-flags1 */ 1362 ppdu_info->rx_status.he_flags1 = 1363 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1364 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1365 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 1366 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 1367 QDF_MON_STATUS_RU_0_KNOWN; 1368 1369 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1370 HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); 1371 ppdu_info->rx_status.he_flags1 |= value; 1372 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1373 HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); 1374 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 1375 ppdu_info->rx_status.he_flags1 |= value; 1376 1377 /* HE-MU-flags2 */ 1378 ppdu_info->rx_status.he_flags2 = 1379 QDF_MON_STATUS_BW_KNOWN; 1380 1381 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1382 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1383 ppdu_info->rx_status.he_flags2 |= value; 1384 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1385 HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); 1386 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1387 ppdu_info->rx_status.he_flags2 |= value; 1388 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1389 HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); 1390 value = value - 1; 1391 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 1392 ppdu_info->rx_status.he_flags2 |= value; 1393 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1394 hal_rx_get_crc_he_sig_a_mu_dl_info(ppdu_info, 1395 he_sig_a_mu_dl_info); 1396 break; 1397 } 1398 case WIFIPHYRX_HE_SIG_B1_MU_E: 1399 { 1400 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 1401 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 1402 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 1403 1404 ppdu_info->rx_status.he_sig_b_common_known |= 1405 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 1406 /* TODO: Check on the availability of other fields in 1407 * sig_b_common 1408 */ 1409 1410 value = HAL_RX_GET(he_sig_b1_mu_info, 1411 HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); 1412 ppdu_info->rx_status.he_RU[0] = value; 1413 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1414 break; 1415 } 1416 case WIFIPHYRX_HE_SIG_B2_MU_E: 1417 { 1418 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 1419 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 1420 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 1421 /* 1422 * Not all "HE" fields can be updated from 1423 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1424 * to populate rest of the "HE" fields for MU scenarios. 1425 */ 1426 1427 /* HE-data1 */ 1428 ppdu_info->rx_status.he_data1 |= 1429 QDF_MON_STATUS_HE_MCS_KNOWN | 1430 QDF_MON_STATUS_HE_CODING_KNOWN; 1431 1432 /* HE-data2 */ 1433 1434 /* HE-data3 */ 1435 value = HAL_RX_GET(he_sig_b2_mu_info, 1436 HE_SIG_B2_MU_INFO_0, STA_MCS); 1437 ppdu_info->rx_status.mcs = value; 1438 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1439 ppdu_info->rx_status.he_data3 |= value; 1440 1441 value = HAL_RX_GET(he_sig_b2_mu_info, 1442 HE_SIG_B2_MU_INFO_0, STA_CODING); 1443 value = value << QDF_MON_STATUS_CODING_SHIFT; 1444 ppdu_info->rx_status.he_data3 |= value; 1445 1446 /* HE-data4 */ 1447 value = HAL_RX_GET(he_sig_b2_mu_info, 1448 HE_SIG_B2_MU_INFO_0, STA_ID); 1449 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1450 ppdu_info->rx_status.he_data4 |= value; 1451 1452 /* HE-data5 */ 1453 1454 /* HE-data6 */ 1455 value = HAL_RX_GET(he_sig_b2_mu_info, 1456 HE_SIG_B2_MU_INFO_0, NSTS); 1457 /* value n indicates n+1 spatial streams */ 1458 value++; 1459 ppdu_info->rx_status.nss = value; 1460 ppdu_info->rx_status.he_data6 |= value; 1461 1462 break; 1463 } 1464 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 1465 { 1466 uint8_t *he_sig_b2_ofdma_info = 1467 (uint8_t *)rx_tlv + 1468 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 1469 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 1470 1471 /* 1472 * Not all "HE" fields can be updated from 1473 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1474 * to populate rest of "HE" fields for MU OFDMA scenarios. 1475 */ 1476 1477 /* HE-data1 */ 1478 ppdu_info->rx_status.he_data1 |= 1479 QDF_MON_STATUS_HE_MCS_KNOWN | 1480 QDF_MON_STATUS_HE_DCM_KNOWN | 1481 QDF_MON_STATUS_HE_CODING_KNOWN; 1482 1483 /* HE-data2 */ 1484 ppdu_info->rx_status.he_data2 |= 1485 QDF_MON_STATUS_TXBF_KNOWN; 1486 1487 /* HE-data3 */ 1488 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1489 HE_SIG_B2_OFDMA_INFO_0, STA_MCS); 1490 ppdu_info->rx_status.mcs = value; 1491 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1492 ppdu_info->rx_status.he_data3 |= value; 1493 1494 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1495 HE_SIG_B2_OFDMA_INFO_0, STA_DCM); 1496 he_dcm = value; 1497 value = value << QDF_MON_STATUS_DCM_SHIFT; 1498 ppdu_info->rx_status.he_data3 |= value; 1499 1500 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1501 HE_SIG_B2_OFDMA_INFO_0, STA_CODING); 1502 value = value << QDF_MON_STATUS_CODING_SHIFT; 1503 ppdu_info->rx_status.he_data3 |= value; 1504 1505 /* HE-data4 */ 1506 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1507 HE_SIG_B2_OFDMA_INFO_0, STA_ID); 1508 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1509 ppdu_info->rx_status.he_data4 |= value; 1510 1511 /* HE-data5 */ 1512 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1513 HE_SIG_B2_OFDMA_INFO_0, TXBF); 1514 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1515 ppdu_info->rx_status.he_data5 |= value; 1516 1517 /* HE-data6 */ 1518 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1519 HE_SIG_B2_OFDMA_INFO_0, NSTS); 1520 /* value n indicates n+1 spatial streams */ 1521 value++; 1522 ppdu_info->rx_status.nss = value; 1523 ppdu_info->rx_status.he_data6 |= value; 1524 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1525 break; 1526 } 1527 case WIFIPHYRX_RSSI_LEGACY_E: 1528 { 1529 uint8_t reception_type; 1530 int8_t rssi_value; 1531 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 1532 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 1533 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 1534 1535 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 1536 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 1537 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 1538 ppdu_info->rx_status.he_re = 0; 1539 1540 reception_type = HAL_RX_GET(rx_tlv, 1541 PHYRX_RSSI_LEGACY_0, 1542 RECEPTION_TYPE); 1543 switch (reception_type) { 1544 case QDF_RECEPTION_TYPE_ULOFMDA: 1545 ppdu_info->rx_status.reception_type = 1546 HAL_RX_TYPE_MU_OFDMA; 1547 ppdu_info->rx_status.ulofdma_flag = 1; 1548 ppdu_info->rx_status.he_data1 = 1549 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1550 break; 1551 case QDF_RECEPTION_TYPE_ULMIMO: 1552 ppdu_info->rx_status.reception_type = 1553 HAL_RX_TYPE_MU_MIMO; 1554 ppdu_info->rx_status.he_data1 = 1555 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1556 break; 1557 default: 1558 ppdu_info->rx_status.reception_type = 1559 HAL_RX_TYPE_SU; 1560 break; 1561 } 1562 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 1563 rssi_value = HAL_RX_GET(rssi_info_tlv, 1564 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 1565 ppdu_info->rx_status.rssi[0] = rssi_value; 1566 dp_nofl_debug("RSSI_PRI20_CHAIN0: %d\n", rssi_value); 1567 1568 rssi_value = HAL_RX_GET(rssi_info_tlv, 1569 RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1); 1570 ppdu_info->rx_status.rssi[1] = rssi_value; 1571 dp_nofl_debug("RSSI_PRI20_CHAIN1: %d\n", rssi_value); 1572 1573 rssi_value = HAL_RX_GET(rssi_info_tlv, 1574 RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2); 1575 ppdu_info->rx_status.rssi[2] = rssi_value; 1576 dp_nofl_debug("RSSI_PRI20_CHAIN2: %d\n", rssi_value); 1577 1578 rssi_value = HAL_RX_GET(rssi_info_tlv, 1579 RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3); 1580 ppdu_info->rx_status.rssi[3] = rssi_value; 1581 dp_nofl_debug("RSSI_PRI20_CHAIN3: %d\n", rssi_value); 1582 1583 rssi_value = HAL_RX_GET(rssi_info_tlv, 1584 RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4); 1585 ppdu_info->rx_status.rssi[4] = rssi_value; 1586 dp_nofl_debug("RSSI_PRI20_CHAIN4: %d\n", rssi_value); 1587 1588 rssi_value = HAL_RX_GET(rssi_info_tlv, 1589 RECEIVE_RSSI_INFO_10, 1590 RSSI_PRI20_CHAIN5); 1591 ppdu_info->rx_status.rssi[5] = rssi_value; 1592 dp_nofl_debug("RSSI_PRI20_CHAIN5: %d\n", rssi_value); 1593 1594 rssi_value = HAL_RX_GET(rssi_info_tlv, 1595 RECEIVE_RSSI_INFO_12, 1596 RSSI_PRI20_CHAIN6); 1597 ppdu_info->rx_status.rssi[6] = rssi_value; 1598 dp_nofl_debug("RSSI_PRI20_CHAIN6: %d\n", rssi_value); 1599 1600 rssi_value = HAL_RX_GET(rssi_info_tlv, 1601 RECEIVE_RSSI_INFO_14, 1602 RSSI_PRI20_CHAIN7); 1603 ppdu_info->rx_status.rssi[7] = rssi_value; 1604 dp_nofl_debug("RSSI_PRI20_CHAIN7: %d\n", rssi_value); 1605 break; 1606 } 1607 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1608 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1609 ppdu_info); 1610 break; 1611 case WIFIRX_HEADER_E: 1612 { 1613 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 1614 1615 if (ppdu_info->fcs_ok_cnt >= 1616 HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) { 1617 hal_err("Number of MPDUs(%d) per status buff exceeded", 1618 ppdu_info->fcs_ok_cnt); 1619 break; 1620 } 1621 1622 /* Update first_msdu_payload for every mpdu and increment 1623 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 1624 */ 1625 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload = 1626 rx_tlv; 1627 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len; 1628 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1629 ppdu_info->msdu_info.payload_len = tlv_len; 1630 ppdu_info->user_id = user_id; 1631 ppdu_info->hdr_len = tlv_len; 1632 ppdu_info->data = rx_tlv; 1633 ppdu_info->data += 4; 1634 1635 /* for every RX_HEADER TLV increment mpdu_cnt */ 1636 com_info->mpdu_cnt++; 1637 return HAL_TLV_STATUS_HEADER; 1638 } 1639 case WIFIRX_MPDU_START_E: 1640 { 1641 uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv; 1642 uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_mpdu_start); 1643 uint8_t filter_category = 0; 1644 1645 hal_update_frame_type_cnt(rx_mpdu_start, ppdu_info); 1646 1647 ppdu_info->nac_info.fc_valid = 1648 HAL_RX_GET_FC_VALID(rx_mpdu_start); 1649 1650 ppdu_info->nac_info.to_ds_flag = 1651 HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start); 1652 1653 ppdu_info->nac_info.frame_control = 1654 HAL_RX_GET(rx_mpdu_start, 1655 RX_MPDU_INFO_14, 1656 MPDU_FRAME_CONTROL_FIELD); 1657 1658 ppdu_info->sw_frame_group_id = 1659 HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start); 1660 1661 ppdu_info->rx_user_status[user_id].sw_peer_id = 1662 HAL_RX_GET_SW_PEER_ID(rx_mpdu_start); 1663 1664 if (ppdu_info->sw_frame_group_id == 1665 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 1666 ppdu_info->rx_status.frame_control_info_valid = 1667 ppdu_info->nac_info.fc_valid; 1668 ppdu_info->rx_status.frame_control = 1669 ppdu_info->nac_info.frame_control; 1670 } 1671 1672 hal_get_mac_addr1(rx_mpdu_start, 1673 ppdu_info); 1674 1675 ppdu_info->nac_info.mac_addr2_valid = 1676 HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start); 1677 1678 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1679 HAL_RX_GET(rx_mpdu_start, 1680 RX_MPDU_INFO_16, 1681 MAC_ADDR_AD2_15_0); 1682 1683 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1684 HAL_RX_GET(rx_mpdu_start, 1685 RX_MPDU_INFO_17, 1686 MAC_ADDR_AD2_47_16); 1687 1688 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1689 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1690 ppdu_info->rx_status.ppdu_len = 1691 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1692 MPDU_LENGTH); 1693 } else { 1694 ppdu_info->rx_status.ppdu_len += 1695 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1696 MPDU_LENGTH); 1697 } 1698 1699 filter_category = 1700 HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start); 1701 1702 if (filter_category == 0) 1703 ppdu_info->rx_status.rxpcu_filter_pass = 1; 1704 else if (filter_category == 1) 1705 ppdu_info->rx_status.monitor_direct_used = 1; 1706 1707 ppdu_info->nac_info.mcast_bcast = 1708 HAL_RX_GET(rx_mpdu_start, 1709 RX_MPDU_INFO_13, 1710 MCAST_BCAST); 1711 break; 1712 } 1713 case WIFIRX_MPDU_END_E: 1714 ppdu_info->user_id = user_id; 1715 ppdu_info->fcs_err = 1716 HAL_RX_GET(rx_tlv, RX_MPDU_END_1, 1717 FCS_ERR); 1718 return HAL_TLV_STATUS_MPDU_END; 1719 case WIFIRX_MSDU_END_E: 1720 if (user_id < HAL_MAX_UL_MU_USERS) { 1721 ppdu_info->rx_msdu_info[user_id].cce_metadata = 1722 HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv); 1723 ppdu_info->rx_msdu_info[user_id].fse_metadata = 1724 HAL_RX_MSDU_END_FSE_METADATA_GET(rx_tlv); 1725 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 1726 HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(rx_tlv); 1727 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 1728 HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(rx_tlv); 1729 ppdu_info->rx_msdu_info[user_id].flow_idx = 1730 HAL_RX_MSDU_END_FLOW_IDX_GET(rx_tlv); 1731 } 1732 return HAL_TLV_STATUS_MSDU_END; 1733 case 0: 1734 return HAL_TLV_STATUS_PPDU_DONE; 1735 1736 default: 1737 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1738 unhandled = false; 1739 else 1740 unhandled = true; 1741 break; 1742 } 1743 1744 if (!unhandled) 1745 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1746 "%s TLV type: %d, TLV len:%d %s", 1747 __func__, tlv_tag, tlv_len, 1748 unhandled == true ? "unhandled" : ""); 1749 1750 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1751 } 1752 1753 /** 1754 * hal_tx_comp_get_release_reason_generic_li() - TQM Release reason 1755 * @hal_desc: completion ring descriptor pointer 1756 * 1757 * This function will return the type of pointer - buffer or descriptor 1758 * 1759 * Return: buffer type 1760 */ 1761 static inline uint8_t hal_tx_comp_get_release_reason_generic_li(void *hal_desc) 1762 { 1763 uint32_t comp_desc = 1764 *(uint32_t *)(((uint8_t *)hal_desc) + 1765 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 1766 1767 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 1768 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 1769 } 1770 1771 /** 1772 * hal_get_wbm_internal_error_generic_li() - is WBM internal error 1773 * @hal_desc: completion ring descriptor pointer 1774 * 1775 * This function will return 0 or 1 - is it WBM internal error or not 1776 * 1777 * Return: uint8_t 1778 */ 1779 static inline uint8_t hal_get_wbm_internal_error_generic_li(void *hal_desc) 1780 { 1781 uint32_t comp_desc = 1782 *(uint32_t *)(((uint8_t *)hal_desc) + 1783 HAL_WBM_INTERNAL_ERROR_OFFSET); 1784 1785 return (comp_desc & HAL_WBM_INTERNAL_ERROR_MASK) >> 1786 HAL_WBM_INTERNAL_ERROR_LSB; 1787 } 1788 1789 /** 1790 * hal_rx_dump_mpdu_start_tlv_generic_li: dump RX mpdu_start TLV in structured 1791 * human readable format. 1792 * @mpdu_start: pointer the rx_attention TLV in pkt. 1793 * @dbg_level: log level. 1794 * 1795 * Return: void 1796 */ 1797 static inline void hal_rx_dump_mpdu_start_tlv_generic_li(void *mpdustart, 1798 uint8_t dbg_level) 1799 { 1800 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 1801 struct rx_mpdu_info *mpdu_info = 1802 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 1803 1804 hal_verbose_debug( 1805 "rx_mpdu_start tlv (1/5) - " 1806 "rxpcu_mpdu_filter_in_category: %x " 1807 "sw_frame_group_id: %x " 1808 "ndp_frame: %x " 1809 "phy_err: %x " 1810 "phy_err_during_mpdu_header: %x " 1811 "protocol_version_err: %x " 1812 "ast_based_lookup_valid: %x " 1813 "phy_ppdu_id: %x " 1814 "ast_index: %x " 1815 "sw_peer_id: %x " 1816 "mpdu_frame_control_valid: %x " 1817 "mpdu_duration_valid: %x " 1818 "mac_addr_ad1_valid: %x " 1819 "mac_addr_ad2_valid: %x " 1820 "mac_addr_ad3_valid: %x " 1821 "mac_addr_ad4_valid: %x " 1822 "mpdu_sequence_control_valid: %x " 1823 "mpdu_qos_control_valid: %x " 1824 "mpdu_ht_control_valid: %x " 1825 "frame_encryption_info_valid: %x ", 1826 mpdu_info->rxpcu_mpdu_filter_in_category, 1827 mpdu_info->sw_frame_group_id, 1828 mpdu_info->ndp_frame, 1829 mpdu_info->phy_err, 1830 mpdu_info->phy_err_during_mpdu_header, 1831 mpdu_info->protocol_version_err, 1832 mpdu_info->ast_based_lookup_valid, 1833 mpdu_info->phy_ppdu_id, 1834 mpdu_info->ast_index, 1835 mpdu_info->sw_peer_id, 1836 mpdu_info->mpdu_frame_control_valid, 1837 mpdu_info->mpdu_duration_valid, 1838 mpdu_info->mac_addr_ad1_valid, 1839 mpdu_info->mac_addr_ad2_valid, 1840 mpdu_info->mac_addr_ad3_valid, 1841 mpdu_info->mac_addr_ad4_valid, 1842 mpdu_info->mpdu_sequence_control_valid, 1843 mpdu_info->mpdu_qos_control_valid, 1844 mpdu_info->mpdu_ht_control_valid, 1845 mpdu_info->frame_encryption_info_valid); 1846 1847 hal_verbose_debug( 1848 "rx_mpdu_start tlv (2/5) - " 1849 "fr_ds: %x " 1850 "to_ds: %x " 1851 "encrypted: %x " 1852 "mpdu_retry: %x " 1853 "mpdu_sequence_number: %x " 1854 "epd_en: %x " 1855 "all_frames_shall_be_encrypted: %x " 1856 "encrypt_type: %x " 1857 "mesh_sta: %x " 1858 "bssid_hit: %x " 1859 "bssid_number: %x " 1860 "tid: %x " 1861 "pn_31_0: %x " 1862 "pn_63_32: %x " 1863 "pn_95_64: %x " 1864 "pn_127_96: %x " 1865 "peer_meta_data: %x " 1866 "rxpt_classify_info.reo_destination_indication: %x " 1867 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x " 1868 "rx_reo_queue_desc_addr_31_0: %x ", 1869 mpdu_info->fr_ds, 1870 mpdu_info->to_ds, 1871 mpdu_info->encrypted, 1872 mpdu_info->mpdu_retry, 1873 mpdu_info->mpdu_sequence_number, 1874 mpdu_info->epd_en, 1875 mpdu_info->all_frames_shall_be_encrypted, 1876 mpdu_info->encrypt_type, 1877 mpdu_info->mesh_sta, 1878 mpdu_info->bssid_hit, 1879 mpdu_info->bssid_number, 1880 mpdu_info->tid, 1881 mpdu_info->pn_31_0, 1882 mpdu_info->pn_63_32, 1883 mpdu_info->pn_95_64, 1884 mpdu_info->pn_127_96, 1885 mpdu_info->peer_meta_data, 1886 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 1887 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 1888 mpdu_info->rx_reo_queue_desc_addr_31_0); 1889 1890 hal_verbose_debug( 1891 "rx_mpdu_start tlv (3/5) - " 1892 "rx_reo_queue_desc_addr_39_32: %x " 1893 "receive_queue_number: %x " 1894 "pre_delim_err_warning: %x " 1895 "first_delim_err: %x " 1896 "key_id_octet: %x " 1897 "new_peer_entry: %x " 1898 "decrypt_needed: %x " 1899 "decap_type: %x " 1900 "rx_insert_vlan_c_tag_padding: %x " 1901 "rx_insert_vlan_s_tag_padding: %x " 1902 "strip_vlan_c_tag_decap: %x " 1903 "strip_vlan_s_tag_decap: %x " 1904 "pre_delim_count: %x " 1905 "ampdu_flag: %x " 1906 "bar_frame: %x " 1907 "mpdu_length: %x " 1908 "first_mpdu: %x " 1909 "mcast_bcast: %x " 1910 "ast_index_not_found: %x " 1911 "ast_index_timeout: %x ", 1912 mpdu_info->rx_reo_queue_desc_addr_39_32, 1913 mpdu_info->receive_queue_number, 1914 mpdu_info->pre_delim_err_warning, 1915 mpdu_info->first_delim_err, 1916 mpdu_info->key_id_octet, 1917 mpdu_info->new_peer_entry, 1918 mpdu_info->decrypt_needed, 1919 mpdu_info->decap_type, 1920 mpdu_info->rx_insert_vlan_c_tag_padding, 1921 mpdu_info->rx_insert_vlan_s_tag_padding, 1922 mpdu_info->strip_vlan_c_tag_decap, 1923 mpdu_info->strip_vlan_s_tag_decap, 1924 mpdu_info->pre_delim_count, 1925 mpdu_info->ampdu_flag, 1926 mpdu_info->bar_frame, 1927 mpdu_info->mpdu_length, 1928 mpdu_info->first_mpdu, 1929 mpdu_info->mcast_bcast, 1930 mpdu_info->ast_index_not_found, 1931 mpdu_info->ast_index_timeout); 1932 1933 hal_verbose_debug( 1934 "rx_mpdu_start tlv (4/5) - " 1935 "power_mgmt: %x " 1936 "non_qos: %x " 1937 "null_data: %x " 1938 "mgmt_type: %x " 1939 "ctrl_type: %x " 1940 "more_data: %x " 1941 "eosp: %x " 1942 "fragment_flag: %x " 1943 "order: %x " 1944 "u_apsd_trigger: %x " 1945 "encrypt_required: %x " 1946 "directed: %x " 1947 "mpdu_frame_control_field: %x " 1948 "mpdu_duration_field: %x " 1949 "mac_addr_ad1_31_0: %x " 1950 "mac_addr_ad1_47_32: %x " 1951 "mac_addr_ad2_15_0: %x " 1952 "mac_addr_ad2_47_16: %x " 1953 "mac_addr_ad3_31_0: %x " 1954 "mac_addr_ad3_47_32: %x ", 1955 mpdu_info->power_mgmt, 1956 mpdu_info->non_qos, 1957 mpdu_info->null_data, 1958 mpdu_info->mgmt_type, 1959 mpdu_info->ctrl_type, 1960 mpdu_info->more_data, 1961 mpdu_info->eosp, 1962 mpdu_info->fragment_flag, 1963 mpdu_info->order, 1964 mpdu_info->u_apsd_trigger, 1965 mpdu_info->encrypt_required, 1966 mpdu_info->directed, 1967 mpdu_info->mpdu_frame_control_field, 1968 mpdu_info->mpdu_duration_field, 1969 mpdu_info->mac_addr_ad1_31_0, 1970 mpdu_info->mac_addr_ad1_47_32, 1971 mpdu_info->mac_addr_ad2_15_0, 1972 mpdu_info->mac_addr_ad2_47_16, 1973 mpdu_info->mac_addr_ad3_31_0, 1974 mpdu_info->mac_addr_ad3_47_32); 1975 1976 hal_verbose_debug( 1977 "rx_mpdu_start tlv (5/5) - " 1978 "mpdu_sequence_control_field: %x " 1979 "mac_addr_ad4_31_0: %x " 1980 "mac_addr_ad4_47_32: %x " 1981 "mpdu_qos_control_field: %x " 1982 "mpdu_ht_control_field: %x ", 1983 mpdu_info->mpdu_sequence_control_field, 1984 mpdu_info->mac_addr_ad4_31_0, 1985 mpdu_info->mac_addr_ad4_47_32, 1986 mpdu_info->mpdu_qos_control_field, 1987 mpdu_info->mpdu_ht_control_field); 1988 } 1989 1990 /** 1991 * hal_tx_set_pcp_tid_map_generic_li() - Configure default PCP to TID map table 1992 * @soc: HAL SoC context 1993 * @map: PCP-TID mapping table 1994 * 1995 * PCP are mapped to 8 TID values using TID values programmed 1996 * in one set of mapping registers PCP_TID_MAP_<0 to 6> 1997 * The mapping register has TID mapping for 8 PCP values 1998 * 1999 * Return: none 2000 */ 2001 static void hal_tx_set_pcp_tid_map_generic_li(struct hal_soc *soc, uint8_t *map) 2002 { 2003 uint32_t addr, value; 2004 2005 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2006 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2007 2008 value = (map[0] | 2009 (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | 2010 (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | 2011 (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | 2012 (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | 2013 (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | 2014 (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | 2015 (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); 2016 2017 HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2018 } 2019 2020 /** 2021 * hal_tx_update_pcp_tid_generic_li() - Update the pcp tid map table with 2022 * value received from user-space 2023 * @soc: HAL SoC context 2024 * @pcp: pcp value 2025 * @tid : tid value 2026 * 2027 * Return: void 2028 */ 2029 static void 2030 hal_tx_update_pcp_tid_generic_li(struct hal_soc *soc, 2031 uint8_t pcp, uint8_t tid) 2032 { 2033 uint32_t addr, value, regval; 2034 2035 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 2036 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2037 2038 value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); 2039 2040 /* Read back previous PCP TID config and update 2041 * with new config. 2042 */ 2043 regval = HAL_REG_READ(soc, addr); 2044 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); 2045 regval |= value; 2046 2047 HAL_REG_WRITE(soc, addr, 2048 (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 2049 } 2050 2051 /** 2052 * hal_tx_update_tidmap_prty_generic_li() - Update the tid map priority 2053 * @soc: HAL SoC context 2054 * @val: priority value 2055 * 2056 * Return: void 2057 */ 2058 static 2059 void hal_tx_update_tidmap_prty_generic_li(struct hal_soc *soc, uint8_t value) 2060 { 2061 uint32_t addr; 2062 2063 addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( 2064 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 2065 2066 HAL_REG_WRITE(soc, addr, 2067 (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); 2068 } 2069 2070 /** 2071 * hal_rx_msdu_packet_metadata_get(): API to get the 2072 * msdu information from rx_msdu_end TLV 2073 * 2074 * @ buf: pointer to the start of RX PKT TLV headers 2075 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 2076 */ 2077 static void 2078 hal_rx_msdu_packet_metadata_get_generic_li(uint8_t *buf, 2079 void *pkt_msdu_metadata) 2080 { 2081 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 2082 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 2083 struct hal_rx_msdu_metadata *msdu_metadata = 2084 (struct hal_rx_msdu_metadata *)pkt_msdu_metadata; 2085 2086 msdu_metadata->l3_hdr_pad = 2087 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 2088 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 2089 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 2090 msdu_metadata->sa_sw_peer_id = 2091 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 2092 } 2093 2094 /** 2095 * hal_rx_msdu_end_offset_get_generic(): API to get the 2096 * msdu_end structure offset rx_pkt_tlv structure 2097 * 2098 * NOTE: API returns offset of msdu_end TLV from structure 2099 * rx_pkt_tlvs 2100 */ 2101 static uint32_t hal_rx_msdu_end_offset_get_generic(void) 2102 { 2103 return RX_PKT_TLV_OFFSET(msdu_end_tlv); 2104 } 2105 2106 /** 2107 * hal_rx_attn_offset_get_generic(): API to get the 2108 * msdu_end structure offset rx_pkt_tlv structure 2109 * 2110 * NOTE: API returns offset of attn TLV from structure 2111 * rx_pkt_tlvs 2112 */ 2113 static uint32_t hal_rx_attn_offset_get_generic(void) 2114 { 2115 return RX_PKT_TLV_OFFSET(attn_tlv); 2116 } 2117 2118 /** 2119 * hal_rx_msdu_start_offset_get_generic(): API to get the 2120 * msdu_start structure offset rx_pkt_tlv structure 2121 * 2122 * NOTE: API returns offset of attn TLV from structure 2123 * rx_pkt_tlvs 2124 */ 2125 static uint32_t hal_rx_msdu_start_offset_get_generic(void) 2126 { 2127 return RX_PKT_TLV_OFFSET(msdu_start_tlv); 2128 } 2129 2130 /** 2131 * hal_rx_mpdu_start_offset_get_generic(): API to get the 2132 * mpdu_start structure offset rx_pkt_tlv structure 2133 * 2134 * NOTE: API returns offset of attn TLV from structure 2135 * rx_pkt_tlvs 2136 */ 2137 static uint32_t hal_rx_mpdu_start_offset_get_generic(void) 2138 { 2139 return RX_PKT_TLV_OFFSET(mpdu_start_tlv); 2140 } 2141 2142 /** 2143 * hal_rx_mpdu_end_offset_get_generic(): API to get the 2144 * mpdu_end structure offset rx_pkt_tlv structure 2145 * 2146 * NOTE: API returns offset of attn TLV from structure 2147 * rx_pkt_tlvs 2148 */ 2149 static uint32_t hal_rx_mpdu_end_offset_get_generic(void) 2150 { 2151 return RX_PKT_TLV_OFFSET(mpdu_end_tlv); 2152 } 2153 2154 #ifndef NO_RX_PKT_HDR_TLV 2155 static uint32_t hal_rx_pkt_tlv_offset_get_generic(void) 2156 { 2157 return RX_PKT_TLV_OFFSET(pkt_hdr_tlv); 2158 } 2159 #endif 2160 2161 #if defined(QDF_BIG_ENDIAN_MACHINE) 2162 /** 2163 * hal_setup_reo_swap() - Set the swap flag for big endian machines 2164 * @soc: HAL soc handle 2165 * 2166 * Return: None 2167 */ 2168 static inline void hal_setup_reo_swap(struct hal_soc *soc) 2169 { 2170 uint32_t reg_val; 2171 2172 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR( 2173 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 2174 2175 reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, WRITE_STRUCT_SWAP, 1); 2176 reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, READ_STRUCT_SWAP, 1); 2177 2178 HAL_REG_WRITE(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR( 2179 SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val); 2180 } 2181 #else 2182 static inline void hal_setup_reo_swap(struct hal_soc *soc) 2183 { 2184 } 2185 #endif 2186 2187 /** 2188 * hal_reo_setup_generic_li - Initialize HW REO block 2189 * 2190 * @hal_soc: Opaque HAL SOC handle 2191 * @reo_params: parameters needed by HAL for REO config 2192 * @qref_reset: reset qref 2193 */ 2194 static 2195 void hal_reo_setup_generic_li(struct hal_soc *soc, void *reoparams, 2196 int qref_reset) 2197 { 2198 uint32_t reg_val; 2199 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 2200 2201 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 2202 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 2203 2204 hal_reo_config(soc, reg_val, reo_params); 2205 /* Other ring enable bits and REO_ENABLE will be set by FW */ 2206 2207 /* TODO: Setup destination ring mapping if enabled */ 2208 2209 /* TODO: Error destination ring setting is left to default. 2210 * Default setting is to send all errors to release ring. 2211 */ 2212 2213 /* Set the reo descriptor swap bits in case of BIG endian platform */ 2214 hal_setup_reo_swap(soc); 2215 2216 HAL_REG_WRITE(soc, 2217 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 2218 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2219 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 2220 2221 HAL_REG_WRITE(soc, 2222 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 2223 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2224 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 2225 2226 HAL_REG_WRITE(soc, 2227 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 2228 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2229 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 2230 2231 HAL_REG_WRITE(soc, 2232 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 2233 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2234 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 2235 2236 /* 2237 * When hash based routing is enabled, routing of the rx packet 2238 * is done based on the following value: 1 _ _ _ _ The last 4 2239 * bits are based on hash[3:0]. This means the possible values 2240 * are 0x10 to 0x1f. This value is used to look-up the 2241 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 2242 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 2243 * registers need to be configured to set-up the 16 entries to 2244 * map the hash values to a ring number. There are 3 bits per 2245 * hash entry – which are mapped as follows: 2246 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 2247 * 7: NOT_USED. 2248 */ 2249 if (reo_params->rx_hash_enabled) { 2250 if (reo_params->remap0) 2251 HAL_REG_WRITE(soc, 2252 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR( 2253 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2254 reo_params->remap0); 2255 2256 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 0x%x", 2257 HAL_REG_READ(soc, 2258 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR( 2259 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 2260 2261 HAL_REG_WRITE(soc, 2262 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 2263 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2264 reo_params->remap1); 2265 2266 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 2267 HAL_REG_READ(soc, 2268 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 2269 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 2270 2271 HAL_REG_WRITE(soc, 2272 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 2273 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2274 reo_params->remap2); 2275 2276 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 2277 HAL_REG_READ(soc, 2278 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 2279 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 2280 } 2281 2282 /* TODO: Check if the following registers shoould be setup by host: 2283 * AGING_CONTROL 2284 * HIGH_MEMORY_THRESHOLD 2285 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 2286 * GLOBAL_LINK_DESC_COUNT_CTRL 2287 */ 2288 } 2289 2290 /** 2291 * hal_setup_link_idle_list_generic_li - Setup scattered idle list using the 2292 * buffer list provided 2293 * 2294 * @hal_soc: Opaque HAL SOC handle 2295 * @scatter_bufs_base_paddr: Array of physical base addresses 2296 * @scatter_bufs_base_vaddr: Array of virtual base addresses 2297 * @num_scatter_bufs: Number of scatter buffers in the above lists 2298 * @scatter_buf_size: Size of each scatter buffer 2299 * @last_buf_end_offset: Offset to the last entry 2300 * @num_entries: Total entries of all scatter bufs 2301 * 2302 * Return: None 2303 */ 2304 static void 2305 hal_setup_link_idle_list_generic_li(struct hal_soc *soc, 2306 qdf_dma_addr_t scatter_bufs_base_paddr[], 2307 void *scatter_bufs_base_vaddr[], 2308 uint32_t num_scatter_bufs, 2309 uint32_t scatter_buf_size, 2310 uint32_t last_buf_end_offset, 2311 uint32_t num_entries) 2312 { 2313 int i; 2314 uint32_t *prev_buf_link_ptr = NULL; 2315 uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size; 2316 uint32_t val; 2317 2318 /* Link the scatter buffers */ 2319 for (i = 0; i < num_scatter_bufs; i++) { 2320 if (i > 0) { 2321 prev_buf_link_ptr[0] = 2322 scatter_bufs_base_paddr[i] & 0xffffffff; 2323 prev_buf_link_ptr[1] = HAL_SM( 2324 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2325 BASE_ADDRESS_39_32, 2326 ((uint64_t)(scatter_bufs_base_paddr[i]) 2327 >> 32)) | HAL_SM( 2328 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2329 ADDRESS_MATCH_TAG, 2330 ADDRESS_MATCH_TAG_VAL); 2331 } 2332 prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] + 2333 scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE); 2334 } 2335 2336 /* TBD: Register programming partly based on MLD & the rest based on 2337 * inputs from HW team. Not complete yet. 2338 */ 2339 2340 reg_scatter_buf_size = (scatter_buf_size - 2341 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64; 2342 reg_tot_scatter_buf_size = ((scatter_buf_size - 2343 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64; 2344 2345 HAL_REG_WRITE(soc, 2346 HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR 2347 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2348 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, 2349 SCATTER_BUFFER_SIZE, 2350 reg_scatter_buf_size) | 2351 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, 2352 LINK_DESC_IDLE_LIST_MODE, 0x1)); 2353 2354 HAL_REG_WRITE(soc, 2355 HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR 2356 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2357 HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE, 2358 SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST, 2359 reg_tot_scatter_buf_size)); 2360 2361 HAL_REG_WRITE(soc, 2362 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR 2363 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2364 scatter_bufs_base_paddr[0] & 0xffffffff); 2365 2366 HAL_REG_WRITE(soc, 2367 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR 2368 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2369 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) & 2370 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK); 2371 2372 HAL_REG_WRITE(soc, 2373 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR 2374 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2375 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2376 BASE_ADDRESS_39_32, 2377 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32)) | 2378 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2379 ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL)); 2380 2381 /* ADDRESS_MATCH_TAG field in the above register is expected to match 2382 * with the upper bits of link pointer. The above write sets this field 2383 * to zero and we are also setting the upper bits of link pointers to 2384 * zero while setting up the link list of scatter buffers above 2385 */ 2386 2387 /* Setup head and tail pointers for the idle list */ 2388 HAL_REG_WRITE(soc, 2389 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR 2390 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2391 scatter_bufs_base_paddr[num_scatter_bufs - 1] & 2392 0xffffffff); 2393 HAL_REG_WRITE(soc, 2394 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR 2395 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2396 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 2397 BUFFER_ADDRESS_39_32, 2398 ((uint64_t)(scatter_bufs_base_paddr 2399 [num_scatter_bufs - 1]) >> 32)) | 2400 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 2401 HEAD_POINTER_OFFSET, last_buf_end_offset >> 2)); 2402 2403 HAL_REG_WRITE(soc, 2404 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR 2405 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2406 scatter_bufs_base_paddr[0] & 0xffffffff); 2407 2408 HAL_REG_WRITE(soc, 2409 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR 2410 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2411 scatter_bufs_base_paddr[0] & 0xffffffff); 2412 HAL_REG_WRITE(soc, 2413 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR 2414 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2415 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 2416 BUFFER_ADDRESS_39_32, 2417 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32)) | 2418 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 2419 TAIL_POINTER_OFFSET, 0)); 2420 2421 HAL_REG_WRITE(soc, 2422 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR 2423 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2 * num_entries); 2424 2425 /* Set RING_ID_DISABLE */ 2426 val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1); 2427 2428 /* 2429 * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence 2430 * check the presence of the bit before toggling it. 2431 */ 2432 #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK 2433 val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1); 2434 #endif 2435 HAL_REG_WRITE(soc, 2436 HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR 2437 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2438 val); 2439 } 2440 2441 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 2442 /** 2443 * hal_tx_desc_set_search_type_generic_li - Set the search type value 2444 * @desc: Handle to Tx Descriptor 2445 * @search_type: search type 2446 * 0 – Normal search 2447 * 1 – Index based address search 2448 * 2 – Index based flow search 2449 * 2450 * Return: void 2451 */ 2452 static inline 2453 void hal_tx_desc_set_search_type_generic_li(void *desc, uint8_t search_type) 2454 { 2455 HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= 2456 HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); 2457 } 2458 #else 2459 static inline 2460 void hal_tx_desc_set_search_type_generic_li(void *desc, uint8_t search_type) 2461 { 2462 } 2463 2464 #endif 2465 2466 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 2467 /** 2468 * hal_tx_desc_set_search_index_generic_li - Set the search index value 2469 * @desc: Handle to Tx Descriptor 2470 * @search_index: The index that will be used for index based address or 2471 * flow search. The field is valid when 'search_type' is 2472 * 1 0r 2 2473 * 2474 * Return: void 2475 */ 2476 static inline 2477 void hal_tx_desc_set_search_index_generic_li(void *desc, uint32_t search_index) 2478 { 2479 HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= 2480 HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); 2481 } 2482 #else 2483 static inline 2484 void hal_tx_desc_set_search_index_generic_li(void *desc, uint32_t search_index) 2485 { 2486 } 2487 #endif 2488 2489 #ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 2490 /** 2491 * hal_tx_desc_set_cache_set_num_generic_li - Set the cache-set-num value 2492 * @desc: Handle to Tx Descriptor 2493 * @cache_num: Cache set number that should be used to cache the index 2494 * based search results, for address and flow search. 2495 * This value should be equal to LSB four bits of the hash value 2496 * of match data, in case of search index points to an entry 2497 * which may be used in content based search also. The value can 2498 * be anything when the entry pointed by search index will not be 2499 * used for content based search. 2500 * 2501 * Return: void 2502 */ 2503 static inline 2504 void hal_tx_desc_set_cache_set_num_generic_li(void *desc, uint8_t cache_num) 2505 { 2506 HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |= 2507 HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num); 2508 } 2509 #else 2510 static inline 2511 void hal_tx_desc_set_cache_set_num_generic_li(void *desc, uint8_t cache_num) 2512 { 2513 } 2514 #endif 2515 2516 #ifdef WLAN_SUPPORT_RX_FISA 2517 /** 2518 * hal_rx_flow_get_tuple_info_li() - Setup a flow search entry in HW FST 2519 * @fst: Pointer to the Rx Flow Search Table 2520 * @hal_hash: HAL 5 tuple hash 2521 * @tuple_info: 5-tuple info of the flow returned to the caller 2522 * 2523 * Return: Success/Failure 2524 */ 2525 static void * 2526 hal_rx_flow_get_tuple_info_li(uint8_t *rx_fst, uint32_t hal_hash, 2527 uint8_t *flow_tuple_info) 2528 { 2529 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 2530 void *hal_fse = NULL; 2531 struct hal_flow_tuple_info *tuple_info 2532 = (struct hal_flow_tuple_info *)flow_tuple_info; 2533 2534 hal_fse = (uint8_t *)fst->base_vaddr + 2535 (hal_hash * HAL_RX_FST_ENTRY_SIZE); 2536 2537 if (!hal_fse || !tuple_info) 2538 return NULL; 2539 2540 if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY_9, VALID)) 2541 return NULL; 2542 2543 tuple_info->src_ip_127_96 = 2544 qdf_ntohl(HAL_GET_FLD(hal_fse, 2545 RX_FLOW_SEARCH_ENTRY_0, 2546 SRC_IP_127_96)); 2547 tuple_info->src_ip_95_64 = 2548 qdf_ntohl(HAL_GET_FLD(hal_fse, 2549 RX_FLOW_SEARCH_ENTRY_1, 2550 SRC_IP_95_64)); 2551 tuple_info->src_ip_63_32 = 2552 qdf_ntohl(HAL_GET_FLD(hal_fse, 2553 RX_FLOW_SEARCH_ENTRY_2, 2554 SRC_IP_63_32)); 2555 tuple_info->src_ip_31_0 = 2556 qdf_ntohl(HAL_GET_FLD(hal_fse, 2557 RX_FLOW_SEARCH_ENTRY_3, 2558 SRC_IP_31_0)); 2559 tuple_info->dest_ip_127_96 = 2560 qdf_ntohl(HAL_GET_FLD(hal_fse, 2561 RX_FLOW_SEARCH_ENTRY_4, 2562 DEST_IP_127_96)); 2563 tuple_info->dest_ip_95_64 = 2564 qdf_ntohl(HAL_GET_FLD(hal_fse, 2565 RX_FLOW_SEARCH_ENTRY_5, 2566 DEST_IP_95_64)); 2567 tuple_info->dest_ip_63_32 = 2568 qdf_ntohl(HAL_GET_FLD(hal_fse, 2569 RX_FLOW_SEARCH_ENTRY_6, 2570 DEST_IP_63_32)); 2571 tuple_info->dest_ip_31_0 = 2572 qdf_ntohl(HAL_GET_FLD(hal_fse, 2573 RX_FLOW_SEARCH_ENTRY_7, 2574 DEST_IP_31_0)); 2575 tuple_info->dest_port = HAL_GET_FLD(hal_fse, 2576 RX_FLOW_SEARCH_ENTRY_8, 2577 DEST_PORT); 2578 tuple_info->src_port = HAL_GET_FLD(hal_fse, 2579 RX_FLOW_SEARCH_ENTRY_8, 2580 SRC_PORT); 2581 tuple_info->l4_protocol = HAL_GET_FLD(hal_fse, 2582 RX_FLOW_SEARCH_ENTRY_9, 2583 L4_PROTOCOL); 2584 2585 return hal_fse; 2586 } 2587 2588 /** 2589 * hal_rx_flow_delete_entry_li() - Setup a flow search entry in HW FST 2590 * @fst: Pointer to the Rx Flow Search Table 2591 * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST 2592 * 2593 * Return: Success/Failure 2594 */ 2595 static QDF_STATUS 2596 hal_rx_flow_delete_entry_li(uint8_t *rx_fst, void *hal_rx_fse) 2597 { 2598 uint8_t *fse = (uint8_t *)hal_rx_fse; 2599 2600 if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID)) 2601 return QDF_STATUS_E_NOENT; 2602 2603 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 2604 2605 return QDF_STATUS_SUCCESS; 2606 } 2607 2608 /** 2609 * hal_rx_fst_get_fse_size_li() - Retrieve the size of each entry 2610 * 2611 * Return: size of each entry/flow in Rx FST 2612 */ 2613 static inline uint32_t 2614 hal_rx_fst_get_fse_size_li(void) 2615 { 2616 return HAL_RX_FST_ENTRY_SIZE; 2617 } 2618 #else 2619 static inline void * 2620 hal_rx_flow_get_tuple_info_li(uint8_t *rx_fst, uint32_t hal_hash, 2621 uint8_t *flow_tuple_info) 2622 { 2623 return NULL; 2624 } 2625 2626 static inline QDF_STATUS 2627 hal_rx_flow_delete_entry_li(uint8_t *rx_fst, void *hal_rx_fse) 2628 { 2629 return QDF_STATUS_SUCCESS; 2630 } 2631 2632 static inline uint32_t 2633 hal_rx_fst_get_fse_size_li(void) 2634 { 2635 return 0; 2636 } 2637 #endif /* WLAN_SUPPORT_RX_FISA */ 2638 2639 /** 2640 * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field 2641 * 2642 * @nbuf: Network buffer 2643 * Returns: rx more fragment bit 2644 * 2645 */ 2646 static uint16_t hal_rx_get_frame_ctrl_field_li(uint8_t *buf) 2647 { 2648 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 2649 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 2650 uint16_t frame_ctrl = 0; 2651 2652 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 2653 2654 return frame_ctrl; 2655 } 2656 #endif /* _HAL_LI_GENERIC_API_H_ */ 2657