1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _HAL_LI_GENERIC_API_H_ 20 #define _HAL_LI_GENERIC_API_H_ 21 22 #include "hal_tx.h" 23 #include "hal_li_tx.h" 24 #include "hal_li_rx.h" 25 26 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) \ 27 (_HAL_MS((*_OFFSET_TO_WORD_PTR(wbm_desc, \ 28 WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET)), \ 29 WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK, \ 30 WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB)) 31 32 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) \ 33 (_HAL_MS((*_OFFSET_TO_WORD_PTR(wbm_desc, \ 34 WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET)), \ 35 WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK, \ 36 WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB)) 37 38 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \ 39 (((*(((uint32_t *)wbm_desc) + \ 40 (WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \ 41 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >> \ 42 WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB) 43 44 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \ 45 (((*(((uint32_t *)wbm_desc) + \ 46 (WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \ 47 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >> \ 48 WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB) 49 50 /** 51 * hal_rx_wbm_err_info_get_generic_li(): Retrieves WBM error code and reason and 52 * save it to hal_wbm_err_desc_info structure passed by caller 53 * @wbm_desc: wbm ring descriptor 54 * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 55 * Return: void 56 */ 57 static inline 58 void hal_rx_wbm_err_info_get_generic_li(void *wbm_desc, 59 void *wbm_er_info1) 60 { 61 struct hal_wbm_err_desc_info *wbm_er_info = 62 (struct hal_wbm_err_desc_info *)wbm_er_info1; 63 64 wbm_er_info->wbm_err_src = HAL_WBM2SW_RELEASE_SRC_GET(wbm_desc); 65 wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc); 66 wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc); 67 wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc); 68 wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc); 69 } 70 71 #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY 72 static inline void 73 hal_tx_comp_get_buffer_timestamp(void *desc, 74 struct hal_tx_completion_status *ts) 75 { 76 ts->buffer_timestamp = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 77 BUFFER_TIMESTAMP); 78 } 79 #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */ 80 static inline void 81 hal_tx_comp_get_buffer_timestamp(void *desc, 82 struct hal_tx_completion_status *ts) 83 { 84 } 85 #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */ 86 87 /** 88 * hal_tx_comp_get_status() - TQM Release reason 89 * @hal_desc: completion ring Tx status 90 * 91 * This function will parse the WBM completion descriptor and populate in 92 * HAL structure 93 * 94 * Return: none 95 */ 96 static inline void 97 hal_tx_comp_get_status_generic_li(void *desc, void *ts1, 98 struct hal_soc *hal) 99 { 100 uint8_t rate_stats_valid = 0; 101 uint32_t rate_stats = 0; 102 struct hal_tx_completion_status *ts = 103 (struct hal_tx_completion_status *)ts1; 104 105 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 106 TQM_STATUS_NUMBER); 107 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 108 ACK_FRAME_RSSI); 109 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 110 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 111 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 112 MSDU_PART_OF_AMSDU); 113 114 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 115 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 116 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 117 TRANSMIT_COUNT); 118 119 rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS); 120 121 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 122 TX_RATE_STATS_INFO_VALID, rate_stats); 123 124 ts->valid = rate_stats_valid; 125 126 if (rate_stats_valid) { 127 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 128 rate_stats); 129 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 130 TRANSMIT_PKT_TYPE, rate_stats); 131 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 132 TRANSMIT_STBC, rate_stats); 133 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 134 rate_stats); 135 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 136 rate_stats); 137 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 138 rate_stats); 139 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 140 rate_stats); 141 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 142 rate_stats); 143 } 144 145 ts->release_src = hal_tx_comp_get_buffer_source( 146 hal_soc_to_hal_soc_handle(hal), 147 desc); 148 ts->status = hal_tx_comp_get_release_reason( 149 desc, 150 hal_soc_to_hal_soc_handle(hal)); 151 152 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 153 TX_RATE_STATS_INFO_TX_RATE_STATS); 154 155 hal_tx_comp_get_buffer_timestamp(desc, ts); 156 } 157 158 /** 159 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 160 * @desc: Handle to Tx Descriptor 161 * @paddr: Physical Address 162 * @pool_id: Return Buffer Manager ID 163 * @desc_id: Descriptor ID 164 * @type: 0 - Address points to a MSDU buffer 165 * 1 - Address points to MSDU extension descriptor 166 * 167 * Return: void 168 */ 169 static inline void 170 hal_tx_desc_set_buf_addr_generic_li(void *desc, dma_addr_t paddr, 171 uint8_t rbm_id, uint32_t desc_id, 172 uint8_t type) 173 { 174 /* Set buffer_addr_info.buffer_addr_31_0 */ 175 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, 176 BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 177 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 178 179 /* Set buffer_addr_info.buffer_addr_39_32 */ 180 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 181 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 182 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 183 (((uint64_t)paddr) >> 32)); 184 185 /* Set buffer_addr_info.return_buffer_manager = rbm id */ 186 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 187 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 188 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, 189 RETURN_BUFFER_MANAGER, rbm_id); 190 191 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 192 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, 193 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 194 HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, 195 desc_id); 196 197 /* Set Buffer or Ext Descriptor Type */ 198 HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, 199 BUF_OR_EXT_DESC_TYPE) |= 200 HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 201 } 202 203 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) 204 /** 205 * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL 206 * tlv_tag: Taf of the TLVs 207 * rx_tlv: the pointer to the TLVs 208 * @ppdu_info: pointer to ppdu_info 209 * 210 * Return: true if the tlv is handled, false if not 211 */ 212 static inline bool 213 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 214 struct hal_rx_ppdu_info *ppdu_info) 215 { 216 uint32_t value; 217 218 switch (tlv_tag) { 219 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 220 { 221 uint8_t *he_sig_a_mu_ul_info = 222 (uint8_t *)rx_tlv + 223 HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, 224 HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); 225 ppdu_info->rx_status.he_flags = 1; 226 227 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 228 FORMAT_INDICATION); 229 if (value == 0) { 230 ppdu_info->rx_status.he_data1 = 231 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 232 } else { 233 ppdu_info->rx_status.he_data1 = 234 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 235 } 236 237 /* data1 */ 238 ppdu_info->rx_status.he_data1 |= 239 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 240 QDF_MON_STATUS_HE_DL_UL_KNOWN | 241 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 242 243 /* data2 */ 244 ppdu_info->rx_status.he_data2 |= 245 QDF_MON_STATUS_TXOP_KNOWN; 246 247 /*data3*/ 248 value = HAL_RX_GET(he_sig_a_mu_ul_info, 249 HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID); 250 ppdu_info->rx_status.he_data3 = value; 251 /* 1 for UL and 0 for DL */ 252 value = 1; 253 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 254 ppdu_info->rx_status.he_data3 |= value; 255 256 /*data4*/ 257 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, 258 SPATIAL_REUSE); 259 ppdu_info->rx_status.he_data4 = value; 260 261 /*data5*/ 262 value = HAL_RX_GET(he_sig_a_mu_ul_info, 263 HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW); 264 ppdu_info->rx_status.he_data5 = value; 265 ppdu_info->rx_status.bw = value; 266 267 /*data6*/ 268 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1, 269 TXOP_DURATION); 270 value = value << QDF_MON_STATUS_TXOP_SHIFT; 271 ppdu_info->rx_status.he_data6 |= value; 272 return true; 273 } 274 default: 275 return false; 276 } 277 } 278 #else 279 static inline bool 280 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, 281 struct hal_rx_ppdu_info *ppdu_info) 282 { 283 return false; 284 } 285 #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */ 286 287 #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) && \ 288 defined(RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 289 290 static inline void 291 hal_rx_handle_mu_ul_info(void *rx_tlv, 292 struct mon_rx_user_status *mon_rx_user_status) 293 { 294 mon_rx_user_status->mu_ul_user_v0_word0 = 295 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_11, 296 SW_RESPONSE_REFERENCE_PTR); 297 298 mon_rx_user_status->mu_ul_user_v0_word1 = 299 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_22, 300 SW_RESPONSE_REFERENCE_PTR_EXT); 301 } 302 303 static inline void 304 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 305 struct mon_rx_user_status *mon_rx_user_status) 306 { 307 uint32_t mpdu_ok_byte_count; 308 uint32_t mpdu_err_byte_count; 309 310 mpdu_ok_byte_count = HAL_RX_GET(rx_tlv, 311 RX_PPDU_END_USER_STATS_17, 312 MPDU_OK_BYTE_COUNT); 313 mpdu_err_byte_count = HAL_RX_GET(rx_tlv, 314 RX_PPDU_END_USER_STATS_19, 315 MPDU_ERR_BYTE_COUNT); 316 317 mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count; 318 mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count; 319 } 320 #else 321 static inline void 322 hal_rx_handle_mu_ul_info(void *rx_tlv, 323 struct mon_rx_user_status *mon_rx_user_status) 324 { 325 } 326 327 static inline void 328 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 329 struct mon_rx_user_status *mon_rx_user_status) 330 { 331 struct hal_rx_ppdu_info *ppdu_info = 332 (struct hal_rx_ppdu_info *)ppduinfo; 333 334 /* HKV1: doesn't support mpdu byte count */ 335 mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len; 336 mon_rx_user_status->mpdu_err_byte_count = 0; 337 } 338 #endif 339 340 static inline void 341 hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id, 342 struct mon_rx_user_status *mon_rx_user_status) 343 { 344 struct mon_rx_info *mon_rx_info; 345 struct mon_rx_user_info *mon_rx_user_info; 346 struct hal_rx_ppdu_info *ppdu_info = 347 (struct hal_rx_ppdu_info *)ppduinfo; 348 349 mon_rx_info = &ppdu_info->rx_info; 350 mon_rx_user_info = &ppdu_info->rx_user_info[user_id]; 351 mon_rx_user_info->qos_control_info_valid = 352 mon_rx_info->qos_control_info_valid; 353 mon_rx_user_info->qos_control = mon_rx_info->qos_control; 354 355 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 356 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 357 mon_rx_user_status->tcp_msdu_count = 358 ppdu_info->rx_status.tcp_msdu_count; 359 mon_rx_user_status->udp_msdu_count = 360 ppdu_info->rx_status.udp_msdu_count; 361 mon_rx_user_status->other_msdu_count = 362 ppdu_info->rx_status.other_msdu_count; 363 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 364 mon_rx_user_status->frame_control_info_valid = 365 ppdu_info->rx_status.frame_control_info_valid; 366 mon_rx_user_status->data_sequence_control_info_valid = 367 ppdu_info->rx_status.data_sequence_control_info_valid; 368 mon_rx_user_status->first_data_seq_ctrl = 369 ppdu_info->rx_status.first_data_seq_ctrl; 370 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 371 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 372 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 373 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 374 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 375 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 376 377 mon_rx_user_status->mpdu_cnt_fcs_ok = 378 ppdu_info->com_info.mpdu_cnt_fcs_ok; 379 mon_rx_user_status->mpdu_cnt_fcs_err = 380 ppdu_info->com_info.mpdu_cnt_fcs_err; 381 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 382 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 383 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 384 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 385 386 hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status); 387 } 388 389 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \ 390 ppdu_info, rssi_info_tlv) \ 391 { \ 392 ppdu_info->rx_status.rssi_chain[chain][0] = \ 393 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 394 RSSI_PRI20_CHAIN##chain); \ 395 ppdu_info->rx_status.rssi_chain[chain][1] = \ 396 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 397 RSSI_EXT20_CHAIN##chain); \ 398 ppdu_info->rx_status.rssi_chain[chain][2] = \ 399 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 400 RSSI_EXT40_LOW20_CHAIN##chain); \ 401 ppdu_info->rx_status.rssi_chain[chain][3] = \ 402 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ 403 RSSI_EXT40_HIGH20_CHAIN##chain); \ 404 ppdu_info->rx_status.rssi_chain[chain][4] = \ 405 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 406 RSSI_EXT80_LOW20_CHAIN##chain); \ 407 ppdu_info->rx_status.rssi_chain[chain][5] = \ 408 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 409 RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \ 410 ppdu_info->rx_status.rssi_chain[chain][6] = \ 411 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 412 RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \ 413 ppdu_info->rx_status.rssi_chain[chain][7] = \ 414 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ 415 RSSI_EXT80_HIGH20_CHAIN##chain); \ 416 } \ 417 418 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 419 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \ 420 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \ 421 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \ 422 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \ 423 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \ 424 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \ 425 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \ 426 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \ 427 428 static inline uint32_t 429 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 430 uint8_t *rssi_info_tlv) 431 { 432 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 433 return 0; 434 } 435 436 #ifdef WLAN_TX_PKT_CAPTURE_ENH 437 static inline void 438 hal_get_qos_control(void *rx_tlv, 439 struct hal_rx_ppdu_info *ppdu_info) 440 { 441 ppdu_info->rx_info.qos_control_info_valid = 442 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 443 QOS_CONTROL_INFO_VALID); 444 445 if (ppdu_info->rx_info.qos_control_info_valid) 446 ppdu_info->rx_info.qos_control = 447 HAL_RX_GET(rx_tlv, 448 RX_PPDU_END_USER_STATS_5, 449 QOS_CONTROL_FIELD); 450 } 451 452 static inline void 453 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 454 struct hal_rx_ppdu_info *ppdu_info) 455 { 456 if ((ppdu_info->sw_frame_group_id 457 == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) || 458 (ppdu_info->sw_frame_group_id == 459 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) { 460 ppdu_info->rx_info.mac_addr1_valid = 461 HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start); 462 463 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] = 464 HAL_RX_GET(rx_mpdu_start, 465 RX_MPDU_INFO_15, 466 MAC_ADDR_AD1_31_0); 467 if (ppdu_info->sw_frame_group_id == 468 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) { 469 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] = 470 HAL_RX_GET(rx_mpdu_start, 471 RX_MPDU_INFO_16, 472 MAC_ADDR_AD1_47_32); 473 } 474 } 475 } 476 #else 477 static inline void 478 hal_get_qos_control(void *rx_tlv, 479 struct hal_rx_ppdu_info *ppdu_info) 480 { 481 } 482 483 static inline void 484 hal_get_mac_addr1(uint8_t *rx_mpdu_start, 485 struct hal_rx_ppdu_info *ppdu_info) 486 { 487 } 488 #endif 489 490 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS 491 static inline void 492 hal_update_frame_type_cnt(uint8_t *rx_mpdu_start, 493 struct hal_rx_ppdu_info *ppdu_info) 494 { 495 uint16_t frame_ctrl; 496 uint8_t fc_type; 497 498 if (HAL_RX_GET_FC_VALID(rx_mpdu_start)) { 499 frame_ctrl = HAL_RX_GET(rx_mpdu_start, 500 RX_MPDU_INFO_14, 501 MPDU_FRAME_CONTROL_FIELD); 502 fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl); 503 if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT) 504 ppdu_info->frm_type_info.rx_mgmt_cnt++; 505 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL) 506 ppdu_info->frm_type_info.rx_ctrl_cnt++; 507 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA) 508 ppdu_info->frm_type_info.rx_data_cnt++; 509 } 510 } 511 #else 512 static inline void 513 hal_update_frame_type_cnt(uint8_t *rx_mpdu_start, 514 struct hal_rx_ppdu_info *ppdu_info) 515 { 516 } 517 #endif 518 519 /** 520 * hal_rx_status_get_tlv_info() - process receive info TLV 521 * @rx_tlv_hdr: pointer to TLV header 522 * @ppdu_info: pointer to ppdu_info 523 * 524 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 525 */ 526 static inline uint32_t 527 hal_rx_status_get_tlv_info_generic_li(void *rx_tlv_hdr, void *ppduinfo, 528 hal_soc_handle_t hal_soc_hdl, 529 qdf_nbuf_t nbuf) 530 { 531 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 532 uint32_t tlv_tag, user_id, tlv_len, value; 533 uint8_t group_id = 0; 534 uint8_t he_dcm = 0; 535 uint8_t he_stbc = 0; 536 uint16_t he_gi = 0; 537 uint16_t he_ltf = 0; 538 void *rx_tlv; 539 bool unhandled = false; 540 struct mon_rx_user_status *mon_rx_user_status; 541 struct hal_rx_ppdu_info *ppdu_info = 542 (struct hal_rx_ppdu_info *)ppduinfo; 543 544 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 545 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 546 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 547 548 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 549 550 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 551 rx_tlv, tlv_len); 552 553 switch (tlv_tag) { 554 case WIFIRX_PPDU_START_E: 555 { 556 if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id == 557 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, PHY_PPDU_ID))) 558 hal_err("Matching ppdu_id(%u) detected", 559 ppdu_info->com_info.last_ppdu_id); 560 561 /* Reset ppdu_info before processing the ppdu */ 562 qdf_mem_zero(ppdu_info, 563 sizeof(struct hal_rx_ppdu_info)); 564 565 ppdu_info->com_info.last_ppdu_id = 566 ppdu_info->com_info.ppdu_id = 567 HAL_RX_GET(rx_tlv, RX_PPDU_START_0, 568 PHY_PPDU_ID); 569 570 /* channel number is set in PHY meta data */ 571 ppdu_info->rx_status.chan_num = 572 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 573 SW_PHY_META_DATA) & 0x0000FFFF); 574 ppdu_info->rx_status.chan_freq = 575 (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, 576 SW_PHY_META_DATA) & 0xFFFF0000) >> 16; 577 if (ppdu_info->rx_status.chan_num) { 578 ppdu_info->rx_status.chan_freq = 579 hal_rx_radiotap_num_to_freq( 580 ppdu_info->rx_status.chan_num, 581 ppdu_info->rx_status.chan_freq); 582 } 583 ppdu_info->com_info.ppdu_timestamp = 584 HAL_RX_GET(rx_tlv, RX_PPDU_START_2, 585 PPDU_START_TIMESTAMP); 586 ppdu_info->rx_status.ppdu_timestamp = 587 ppdu_info->com_info.ppdu_timestamp; 588 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 589 590 break; 591 } 592 593 case WIFIRX_PPDU_START_USER_INFO_E: 594 break; 595 596 case WIFIRX_PPDU_END_E: 597 dp_nofl_debug("[%s][%d] ppdu_end_e len=%d", 598 __func__, __LINE__, tlv_len); 599 /* This is followed by sub-TLVs of PPDU_END */ 600 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 601 break; 602 603 case WIFIPHYRX_PKT_END_E: 604 hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); 605 break; 606 607 case WIFIRXPCU_PPDU_END_INFO_E: 608 ppdu_info->rx_status.rx_antenna = 609 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, RX_ANTENNA); 610 ppdu_info->rx_status.tsft = 611 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, 612 WB_TIMESTAMP_UPPER_32); 613 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 614 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, 615 WB_TIMESTAMP_LOWER_32); 616 ppdu_info->rx_status.duration = 617 HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 618 RX_PPDU_DURATION); 619 hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); 620 break; 621 622 /* 623 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 624 * for MU, based on num users we see this tlv that many times. 625 */ 626 case WIFIRX_PPDU_END_USER_STATS_E: 627 { 628 unsigned long tid = 0; 629 uint16_t seq = 0; 630 631 ppdu_info->rx_status.ast_index = 632 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, 633 AST_INDEX); 634 635 tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, 636 RECEIVED_QOS_DATA_TID_BITMAP); 637 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, 638 sizeof(tid) * 8); 639 640 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 641 ppdu_info->rx_status.tid = HAL_TID_INVALID; 642 643 ppdu_info->rx_status.tcp_msdu_count = 644 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 645 TCP_MSDU_COUNT) + 646 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 647 TCP_ACK_MSDU_COUNT); 648 ppdu_info->rx_status.udp_msdu_count = 649 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, 650 UDP_MSDU_COUNT); 651 ppdu_info->rx_status.other_msdu_count = 652 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, 653 OTHER_MSDU_COUNT); 654 655 if (ppdu_info->sw_frame_group_id 656 != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 657 ppdu_info->rx_status.frame_control_info_valid = 658 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 659 FRAME_CONTROL_INFO_VALID); 660 661 if (ppdu_info->rx_status.frame_control_info_valid) 662 ppdu_info->rx_status.frame_control = 663 HAL_RX_GET(rx_tlv, 664 RX_PPDU_END_USER_STATS_4, 665 FRAME_CONTROL_FIELD); 666 667 hal_get_qos_control(rx_tlv, ppdu_info); 668 } 669 670 ppdu_info->rx_status.data_sequence_control_info_valid = 671 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 672 DATA_SEQUENCE_CONTROL_INFO_VALID); 673 674 seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, 675 FIRST_DATA_SEQ_CTRL); 676 if (ppdu_info->rx_status.data_sequence_control_info_valid) 677 ppdu_info->rx_status.first_data_seq_ctrl = seq; 678 679 ppdu_info->rx_status.preamble_type = 680 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 681 HT_CONTROL_FIELD_PKT_TYPE); 682 switch (ppdu_info->rx_status.preamble_type) { 683 case HAL_RX_PKT_TYPE_11N: 684 ppdu_info->rx_status.ht_flags = 1; 685 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 686 break; 687 case HAL_RX_PKT_TYPE_11AC: 688 ppdu_info->rx_status.vht_flags = 1; 689 break; 690 case HAL_RX_PKT_TYPE_11AX: 691 ppdu_info->rx_status.he_flags = 1; 692 break; 693 default: 694 break; 695 } 696 697 ppdu_info->com_info.mpdu_cnt_fcs_ok = 698 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, 699 MPDU_CNT_FCS_OK); 700 ppdu_info->com_info.mpdu_cnt_fcs_err = 701 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, 702 MPDU_CNT_FCS_ERR); 703 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 704 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 705 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 706 else 707 ppdu_info->rx_status.rs_flags &= 708 (~IEEE80211_AMPDU_FLAG); 709 710 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 711 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_7, 712 FCS_OK_BITMAP_31_0); 713 714 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 715 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_8, 716 FCS_OK_BITMAP_63_32); 717 718 if (user_id < HAL_MAX_UL_MU_USERS) { 719 mon_rx_user_status = 720 &ppdu_info->rx_user_status[user_id]; 721 722 hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status); 723 724 ppdu_info->com_info.num_users++; 725 726 hal_rx_populate_mu_user_info(rx_tlv, ppdu_info, 727 user_id, 728 mon_rx_user_status); 729 } 730 break; 731 } 732 733 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 734 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 735 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_1, 736 FCS_OK_BITMAP_95_64); 737 738 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 739 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_2, 740 FCS_OK_BITMAP_127_96); 741 742 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 743 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_3, 744 FCS_OK_BITMAP_159_128); 745 746 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 747 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_4, 748 FCS_OK_BITMAP_191_160); 749 750 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 751 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_5, 752 FCS_OK_BITMAP_223_192); 753 754 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 755 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_6, 756 FCS_OK_BITMAP_255_224); 757 break; 758 759 case WIFIRX_PPDU_END_STATUS_DONE_E: 760 return HAL_TLV_STATUS_PPDU_DONE; 761 762 case WIFIDUMMY_E: 763 return HAL_TLV_STATUS_BUF_DONE; 764 765 case WIFIPHYRX_HT_SIG_E: 766 { 767 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 768 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 769 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 770 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, 771 FEC_CODING); 772 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 773 1 : 0; 774 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 775 HT_SIG_INFO_0, MCS); 776 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 777 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 778 HT_SIG_INFO_0, CBW); 779 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 780 HT_SIG_INFO_1, SHORT_GI); 781 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 782 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 783 HT_SIG_SU_NSS_SHIFT) + 1; 784 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 785 break; 786 } 787 788 case WIFIPHYRX_L_SIG_B_E: 789 { 790 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 791 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 792 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 793 794 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); 795 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 796 switch (value) { 797 case 1: 798 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 799 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 800 break; 801 case 2: 802 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 803 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 804 break; 805 case 3: 806 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 807 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 808 break; 809 case 4: 810 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 811 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 812 break; 813 case 5: 814 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 815 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 816 break; 817 case 6: 818 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 819 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 820 break; 821 case 7: 822 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 823 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 824 break; 825 default: 826 break; 827 } 828 ppdu_info->rx_status.cck_flag = 1; 829 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 830 break; 831 } 832 833 case WIFIPHYRX_L_SIG_A_E: 834 { 835 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 836 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 837 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 838 839 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); 840 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 841 switch (value) { 842 case 8: 843 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 844 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 845 break; 846 case 9: 847 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 848 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 849 break; 850 case 10: 851 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 852 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 853 break; 854 case 11: 855 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 856 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 857 break; 858 case 12: 859 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 860 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 861 break; 862 case 13: 863 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 864 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 865 break; 866 case 14: 867 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 868 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 869 break; 870 case 15: 871 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 872 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 873 break; 874 default: 875 break; 876 } 877 ppdu_info->rx_status.ofdm_flag = 1; 878 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 879 break; 880 } 881 882 case WIFIPHYRX_VHT_SIG_A_E: 883 { 884 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 885 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 886 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 887 888 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, 889 SU_MU_CODING); 890 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 891 1 : 0; 892 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, 893 GROUP_ID); 894 ppdu_info->rx_status.vht_flag_values5 = group_id; 895 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 896 VHT_SIG_A_INFO_1, MCS); 897 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 898 VHT_SIG_A_INFO_1, GI_SETTING); 899 900 switch (hal->target_type) { 901 case TARGET_TYPE_QCA8074: 902 case TARGET_TYPE_QCA8074V2: 903 case TARGET_TYPE_QCA6018: 904 case TARGET_TYPE_QCA5018: 905 case TARGET_TYPE_QCN9000: 906 case TARGET_TYPE_QCN6122: 907 #ifdef QCA_WIFI_QCA6390 908 case TARGET_TYPE_QCA6390: 909 #endif 910 ppdu_info->rx_status.is_stbc = 911 HAL_RX_GET(vht_sig_a_info, 912 VHT_SIG_A_INFO_0, STBC); 913 value = HAL_RX_GET(vht_sig_a_info, 914 VHT_SIG_A_INFO_0, N_STS); 915 value = value & VHT_SIG_SU_NSS_MASK; 916 if (ppdu_info->rx_status.is_stbc && (value > 0)) 917 value = ((value + 1) >> 1) - 1; 918 ppdu_info->rx_status.nss = 919 ((value & VHT_SIG_SU_NSS_MASK) + 1); 920 921 break; 922 case TARGET_TYPE_QCA6290: 923 #if !defined(QCA_WIFI_QCA6290_11AX) 924 ppdu_info->rx_status.is_stbc = 925 HAL_RX_GET(vht_sig_a_info, 926 VHT_SIG_A_INFO_0, STBC); 927 value = HAL_RX_GET(vht_sig_a_info, 928 VHT_SIG_A_INFO_0, N_STS); 929 value = value & VHT_SIG_SU_NSS_MASK; 930 if (ppdu_info->rx_status.is_stbc && (value > 0)) 931 value = ((value + 1) >> 1) - 1; 932 ppdu_info->rx_status.nss = 933 ((value & VHT_SIG_SU_NSS_MASK) + 1); 934 #else 935 ppdu_info->rx_status.nss = 0; 936 #endif 937 break; 938 case TARGET_TYPE_QCA6490: 939 case TARGET_TYPE_QCA6750: 940 ppdu_info->rx_status.nss = 0; 941 break; 942 default: 943 break; 944 } 945 ppdu_info->rx_status.vht_flag_values3[0] = 946 (((ppdu_info->rx_status.mcs) << 4) 947 | ppdu_info->rx_status.nss); 948 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 949 VHT_SIG_A_INFO_0, BANDWIDTH); 950 ppdu_info->rx_status.vht_flag_values2 = 951 ppdu_info->rx_status.bw; 952 ppdu_info->rx_status.vht_flag_values4 = 953 HAL_RX_GET(vht_sig_a_info, 954 VHT_SIG_A_INFO_1, SU_MU_CODING); 955 956 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 957 VHT_SIG_A_INFO_1, BEAMFORMED); 958 if (group_id == 0 || group_id == 63) 959 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 960 else 961 ppdu_info->rx_status.reception_type = 962 HAL_RX_TYPE_MU_MIMO; 963 964 break; 965 } 966 case WIFIPHYRX_HE_SIG_A_SU_E: 967 { 968 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 969 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 970 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 971 ppdu_info->rx_status.he_flags = 1; 972 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 973 FORMAT_INDICATION); 974 if (value == 0) { 975 ppdu_info->rx_status.he_data1 = 976 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 977 } else { 978 ppdu_info->rx_status.he_data1 = 979 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 980 } 981 982 /* data1 */ 983 ppdu_info->rx_status.he_data1 |= 984 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 985 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 986 QDF_MON_STATUS_HE_DL_UL_KNOWN | 987 QDF_MON_STATUS_HE_MCS_KNOWN | 988 QDF_MON_STATUS_HE_DCM_KNOWN | 989 QDF_MON_STATUS_HE_CODING_KNOWN | 990 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 991 QDF_MON_STATUS_HE_STBC_KNOWN | 992 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 993 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 994 995 /* data2 */ 996 ppdu_info->rx_status.he_data2 = 997 QDF_MON_STATUS_HE_GI_KNOWN; 998 ppdu_info->rx_status.he_data2 |= 999 QDF_MON_STATUS_TXBF_KNOWN | 1000 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1001 QDF_MON_STATUS_TXOP_KNOWN | 1002 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1003 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1004 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1005 1006 /* data3 */ 1007 value = HAL_RX_GET(he_sig_a_su_info, 1008 HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); 1009 ppdu_info->rx_status.he_data3 = value; 1010 value = HAL_RX_GET(he_sig_a_su_info, 1011 HE_SIG_A_SU_INFO_0, BEAM_CHANGE); 1012 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 1013 ppdu_info->rx_status.he_data3 |= value; 1014 value = HAL_RX_GET(he_sig_a_su_info, 1015 HE_SIG_A_SU_INFO_0, DL_UL_FLAG); 1016 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1017 ppdu_info->rx_status.he_data3 |= value; 1018 1019 value = HAL_RX_GET(he_sig_a_su_info, 1020 HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); 1021 ppdu_info->rx_status.mcs = value; 1022 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1023 ppdu_info->rx_status.he_data3 |= value; 1024 1025 value = HAL_RX_GET(he_sig_a_su_info, 1026 HE_SIG_A_SU_INFO_0, DCM); 1027 he_dcm = value; 1028 value = value << QDF_MON_STATUS_DCM_SHIFT; 1029 ppdu_info->rx_status.he_data3 |= value; 1030 value = HAL_RX_GET(he_sig_a_su_info, 1031 HE_SIG_A_SU_INFO_1, CODING); 1032 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 1033 1 : 0; 1034 value = value << QDF_MON_STATUS_CODING_SHIFT; 1035 ppdu_info->rx_status.he_data3 |= value; 1036 value = HAL_RX_GET(he_sig_a_su_info, 1037 HE_SIG_A_SU_INFO_1, 1038 LDPC_EXTRA_SYMBOL); 1039 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1040 ppdu_info->rx_status.he_data3 |= value; 1041 value = HAL_RX_GET(he_sig_a_su_info, 1042 HE_SIG_A_SU_INFO_1, STBC); 1043 he_stbc = value; 1044 value = value << QDF_MON_STATUS_STBC_SHIFT; 1045 ppdu_info->rx_status.he_data3 |= value; 1046 1047 /* data4 */ 1048 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, 1049 SPATIAL_REUSE); 1050 ppdu_info->rx_status.he_data4 = value; 1051 1052 /* data5 */ 1053 value = HAL_RX_GET(he_sig_a_su_info, 1054 HE_SIG_A_SU_INFO_0, TRANSMIT_BW); 1055 ppdu_info->rx_status.he_data5 = value; 1056 ppdu_info->rx_status.bw = value; 1057 value = HAL_RX_GET(he_sig_a_su_info, 1058 HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); 1059 switch (value) { 1060 case 0: 1061 he_gi = HE_GI_0_8; 1062 he_ltf = HE_LTF_1_X; 1063 break; 1064 case 1: 1065 he_gi = HE_GI_0_8; 1066 he_ltf = HE_LTF_2_X; 1067 break; 1068 case 2: 1069 he_gi = HE_GI_1_6; 1070 he_ltf = HE_LTF_2_X; 1071 break; 1072 case 3: 1073 if (he_dcm && he_stbc) { 1074 he_gi = HE_GI_0_8; 1075 he_ltf = HE_LTF_4_X; 1076 } else { 1077 he_gi = HE_GI_3_2; 1078 he_ltf = HE_LTF_4_X; 1079 } 1080 break; 1081 } 1082 ppdu_info->rx_status.sgi = he_gi; 1083 ppdu_info->rx_status.ltf_size = he_ltf; 1084 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 1085 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1086 ppdu_info->rx_status.he_data5 |= value; 1087 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1088 ppdu_info->rx_status.he_data5 |= value; 1089 1090 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 1091 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1092 ppdu_info->rx_status.he_data5 |= value; 1093 1094 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1095 PACKET_EXTENSION_A_FACTOR); 1096 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1097 ppdu_info->rx_status.he_data5 |= value; 1098 1099 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); 1100 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1101 ppdu_info->rx_status.he_data5 |= value; 1102 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1103 PACKET_EXTENSION_PE_DISAMBIGUITY); 1104 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1105 ppdu_info->rx_status.he_data5 |= value; 1106 1107 /* data6 */ 1108 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); 1109 value++; 1110 ppdu_info->rx_status.nss = value; 1111 ppdu_info->rx_status.he_data6 = value; 1112 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1113 DOPPLER_INDICATION); 1114 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1115 ppdu_info->rx_status.he_data6 |= value; 1116 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, 1117 TXOP_DURATION); 1118 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1119 ppdu_info->rx_status.he_data6 |= value; 1120 1121 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 1122 HE_SIG_A_SU_INFO_1, TXBF); 1123 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 1124 break; 1125 } 1126 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 1127 { 1128 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 1129 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 1130 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 1131 1132 ppdu_info->rx_status.he_mu_flags = 1; 1133 1134 /* HE Flags */ 1135 /*data1*/ 1136 ppdu_info->rx_status.he_data1 = 1137 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1138 ppdu_info->rx_status.he_data1 |= 1139 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 1140 QDF_MON_STATUS_HE_DL_UL_KNOWN | 1141 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 1142 QDF_MON_STATUS_HE_STBC_KNOWN | 1143 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 1144 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 1145 1146 /* data2 */ 1147 ppdu_info->rx_status.he_data2 = 1148 QDF_MON_STATUS_HE_GI_KNOWN; 1149 ppdu_info->rx_status.he_data2 |= 1150 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 1151 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 1152 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1153 QDF_MON_STATUS_TXOP_KNOWN | 1154 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 1155 1156 /*data3*/ 1157 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1158 HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); 1159 ppdu_info->rx_status.he_data3 = value; 1160 1161 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1162 HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); 1163 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 1164 ppdu_info->rx_status.he_data3 |= value; 1165 1166 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1167 HE_SIG_A_MU_DL_INFO_1, 1168 LDPC_EXTRA_SYMBOL); 1169 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 1170 ppdu_info->rx_status.he_data3 |= value; 1171 1172 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1173 HE_SIG_A_MU_DL_INFO_1, STBC); 1174 he_stbc = value; 1175 value = value << QDF_MON_STATUS_STBC_SHIFT; 1176 ppdu_info->rx_status.he_data3 |= value; 1177 1178 /*data4*/ 1179 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1180 SPATIAL_REUSE); 1181 ppdu_info->rx_status.he_data4 = value; 1182 1183 /*data5*/ 1184 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1185 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1186 ppdu_info->rx_status.he_data5 = value; 1187 ppdu_info->rx_status.bw = value; 1188 1189 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1190 HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); 1191 switch (value) { 1192 case 0: 1193 he_gi = HE_GI_0_8; 1194 he_ltf = HE_LTF_4_X; 1195 break; 1196 case 1: 1197 he_gi = HE_GI_0_8; 1198 he_ltf = HE_LTF_2_X; 1199 break; 1200 case 2: 1201 he_gi = HE_GI_1_6; 1202 he_ltf = HE_LTF_2_X; 1203 break; 1204 case 3: 1205 he_gi = HE_GI_3_2; 1206 he_ltf = HE_LTF_4_X; 1207 break; 1208 } 1209 ppdu_info->rx_status.sgi = he_gi; 1210 ppdu_info->rx_status.ltf_size = he_ltf; 1211 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 1212 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 1213 ppdu_info->rx_status.he_data5 |= value; 1214 1215 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 1216 ppdu_info->rx_status.he_data5 |= value; 1217 1218 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1219 HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); 1220 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1221 ppdu_info->rx_status.he_data5 |= value; 1222 1223 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1224 PACKET_EXTENSION_A_FACTOR); 1225 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 1226 ppdu_info->rx_status.he_data5 |= value; 1227 1228 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1229 PACKET_EXTENSION_PE_DISAMBIGUITY); 1230 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 1231 ppdu_info->rx_status.he_data5 |= value; 1232 1233 /*data6*/ 1234 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, 1235 DOPPLER_INDICATION); 1236 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 1237 ppdu_info->rx_status.he_data6 |= value; 1238 1239 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, 1240 TXOP_DURATION); 1241 value = value << QDF_MON_STATUS_TXOP_SHIFT; 1242 ppdu_info->rx_status.he_data6 |= value; 1243 1244 /* HE-MU Flags */ 1245 /* HE-MU-flags1 */ 1246 ppdu_info->rx_status.he_flags1 = 1247 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 1248 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 1249 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 1250 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 1251 QDF_MON_STATUS_RU_0_KNOWN; 1252 1253 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1254 HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); 1255 ppdu_info->rx_status.he_flags1 |= value; 1256 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1257 HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); 1258 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 1259 ppdu_info->rx_status.he_flags1 |= value; 1260 1261 /* HE-MU-flags2 */ 1262 ppdu_info->rx_status.he_flags2 = 1263 QDF_MON_STATUS_BW_KNOWN; 1264 1265 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1266 HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); 1267 ppdu_info->rx_status.he_flags2 |= value; 1268 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1269 HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); 1270 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 1271 ppdu_info->rx_status.he_flags2 |= value; 1272 value = HAL_RX_GET(he_sig_a_mu_dl_info, 1273 HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); 1274 value = value - 1; 1275 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 1276 ppdu_info->rx_status.he_flags2 |= value; 1277 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1278 break; 1279 } 1280 case WIFIPHYRX_HE_SIG_B1_MU_E: 1281 { 1282 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 1283 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 1284 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 1285 1286 ppdu_info->rx_status.he_sig_b_common_known |= 1287 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 1288 /* TODO: Check on the availability of other fields in 1289 * sig_b_common 1290 */ 1291 1292 value = HAL_RX_GET(he_sig_b1_mu_info, 1293 HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); 1294 ppdu_info->rx_status.he_RU[0] = value; 1295 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 1296 break; 1297 } 1298 case WIFIPHYRX_HE_SIG_B2_MU_E: 1299 { 1300 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 1301 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 1302 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 1303 /* 1304 * Not all "HE" fields can be updated from 1305 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1306 * to populate rest of the "HE" fields for MU scenarios. 1307 */ 1308 1309 /* HE-data1 */ 1310 ppdu_info->rx_status.he_data1 |= 1311 QDF_MON_STATUS_HE_MCS_KNOWN | 1312 QDF_MON_STATUS_HE_CODING_KNOWN; 1313 1314 /* HE-data2 */ 1315 1316 /* HE-data3 */ 1317 value = HAL_RX_GET(he_sig_b2_mu_info, 1318 HE_SIG_B2_MU_INFO_0, STA_MCS); 1319 ppdu_info->rx_status.mcs = value; 1320 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1321 ppdu_info->rx_status.he_data3 |= value; 1322 1323 value = HAL_RX_GET(he_sig_b2_mu_info, 1324 HE_SIG_B2_MU_INFO_0, STA_CODING); 1325 value = value << QDF_MON_STATUS_CODING_SHIFT; 1326 ppdu_info->rx_status.he_data3 |= value; 1327 1328 /* HE-data4 */ 1329 value = HAL_RX_GET(he_sig_b2_mu_info, 1330 HE_SIG_B2_MU_INFO_0, STA_ID); 1331 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1332 ppdu_info->rx_status.he_data4 |= value; 1333 1334 /* HE-data5 */ 1335 1336 /* HE-data6 */ 1337 value = HAL_RX_GET(he_sig_b2_mu_info, 1338 HE_SIG_B2_MU_INFO_0, NSTS); 1339 /* value n indicates n+1 spatial streams */ 1340 value++; 1341 ppdu_info->rx_status.nss = value; 1342 ppdu_info->rx_status.he_data6 |= value; 1343 1344 break; 1345 } 1346 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 1347 { 1348 uint8_t *he_sig_b2_ofdma_info = 1349 (uint8_t *)rx_tlv + 1350 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 1351 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 1352 1353 /* 1354 * Not all "HE" fields can be updated from 1355 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 1356 * to populate rest of "HE" fields for MU OFDMA scenarios. 1357 */ 1358 1359 /* HE-data1 */ 1360 ppdu_info->rx_status.he_data1 |= 1361 QDF_MON_STATUS_HE_MCS_KNOWN | 1362 QDF_MON_STATUS_HE_DCM_KNOWN | 1363 QDF_MON_STATUS_HE_CODING_KNOWN; 1364 1365 /* HE-data2 */ 1366 ppdu_info->rx_status.he_data2 |= 1367 QDF_MON_STATUS_TXBF_KNOWN; 1368 1369 /* HE-data3 */ 1370 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1371 HE_SIG_B2_OFDMA_INFO_0, STA_MCS); 1372 ppdu_info->rx_status.mcs = value; 1373 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 1374 ppdu_info->rx_status.he_data3 |= value; 1375 1376 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1377 HE_SIG_B2_OFDMA_INFO_0, STA_DCM); 1378 he_dcm = value; 1379 value = value << QDF_MON_STATUS_DCM_SHIFT; 1380 ppdu_info->rx_status.he_data3 |= value; 1381 1382 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1383 HE_SIG_B2_OFDMA_INFO_0, STA_CODING); 1384 value = value << QDF_MON_STATUS_CODING_SHIFT; 1385 ppdu_info->rx_status.he_data3 |= value; 1386 1387 /* HE-data4 */ 1388 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1389 HE_SIG_B2_OFDMA_INFO_0, STA_ID); 1390 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 1391 ppdu_info->rx_status.he_data4 |= value; 1392 1393 /* HE-data5 */ 1394 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1395 HE_SIG_B2_OFDMA_INFO_0, TXBF); 1396 value = value << QDF_MON_STATUS_TXBF_SHIFT; 1397 ppdu_info->rx_status.he_data5 |= value; 1398 1399 /* HE-data6 */ 1400 value = HAL_RX_GET(he_sig_b2_ofdma_info, 1401 HE_SIG_B2_OFDMA_INFO_0, NSTS); 1402 /* value n indicates n+1 spatial streams */ 1403 value++; 1404 ppdu_info->rx_status.nss = value; 1405 ppdu_info->rx_status.he_data6 |= value; 1406 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 1407 break; 1408 } 1409 case WIFIPHYRX_RSSI_LEGACY_E: 1410 { 1411 uint8_t reception_type; 1412 int8_t rssi_value; 1413 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 1414 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 1415 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 1416 1417 ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, 1418 PHYRX_RSSI_LEGACY_35, RSSI_COMB); 1419 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 1420 ppdu_info->rx_status.he_re = 0; 1421 1422 reception_type = HAL_RX_GET(rx_tlv, 1423 PHYRX_RSSI_LEGACY_0, 1424 RECEPTION_TYPE); 1425 switch (reception_type) { 1426 case QDF_RECEPTION_TYPE_ULOFMDA: 1427 ppdu_info->rx_status.reception_type = 1428 HAL_RX_TYPE_MU_OFDMA; 1429 ppdu_info->rx_status.ulofdma_flag = 1; 1430 ppdu_info->rx_status.he_data1 = 1431 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 1432 break; 1433 case QDF_RECEPTION_TYPE_ULMIMO: 1434 ppdu_info->rx_status.reception_type = 1435 HAL_RX_TYPE_MU_MIMO; 1436 ppdu_info->rx_status.he_data1 = 1437 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 1438 break; 1439 default: 1440 ppdu_info->rx_status.reception_type = 1441 HAL_RX_TYPE_SU; 1442 break; 1443 } 1444 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 1445 rssi_value = HAL_RX_GET(rssi_info_tlv, 1446 RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); 1447 ppdu_info->rx_status.rssi[0] = rssi_value; 1448 dp_nofl_debug("RSSI_PRI20_CHAIN0: %d\n", rssi_value); 1449 1450 rssi_value = HAL_RX_GET(rssi_info_tlv, 1451 RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1); 1452 ppdu_info->rx_status.rssi[1] = rssi_value; 1453 dp_nofl_debug("RSSI_PRI20_CHAIN1: %d\n", rssi_value); 1454 1455 rssi_value = HAL_RX_GET(rssi_info_tlv, 1456 RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2); 1457 ppdu_info->rx_status.rssi[2] = rssi_value; 1458 dp_nofl_debug("RSSI_PRI20_CHAIN2: %d\n", rssi_value); 1459 1460 rssi_value = HAL_RX_GET(rssi_info_tlv, 1461 RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3); 1462 ppdu_info->rx_status.rssi[3] = rssi_value; 1463 dp_nofl_debug("RSSI_PRI20_CHAIN3: %d\n", rssi_value); 1464 1465 rssi_value = HAL_RX_GET(rssi_info_tlv, 1466 RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4); 1467 ppdu_info->rx_status.rssi[4] = rssi_value; 1468 dp_nofl_debug("RSSI_PRI20_CHAIN4: %d\n", rssi_value); 1469 1470 rssi_value = HAL_RX_GET(rssi_info_tlv, 1471 RECEIVE_RSSI_INFO_10, 1472 RSSI_PRI20_CHAIN5); 1473 ppdu_info->rx_status.rssi[5] = rssi_value; 1474 dp_nofl_debug("RSSI_PRI20_CHAIN5: %d\n", rssi_value); 1475 1476 rssi_value = HAL_RX_GET(rssi_info_tlv, 1477 RECEIVE_RSSI_INFO_12, 1478 RSSI_PRI20_CHAIN6); 1479 ppdu_info->rx_status.rssi[6] = rssi_value; 1480 dp_nofl_debug("RSSI_PRI20_CHAIN6: %d\n", rssi_value); 1481 1482 rssi_value = HAL_RX_GET(rssi_info_tlv, 1483 RECEIVE_RSSI_INFO_14, 1484 RSSI_PRI20_CHAIN7); 1485 ppdu_info->rx_status.rssi[7] = rssi_value; 1486 dp_nofl_debug("RSSI_PRI20_CHAIN7: %d\n", rssi_value); 1487 break; 1488 } 1489 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 1490 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 1491 ppdu_info); 1492 break; 1493 case WIFIRX_HEADER_E: 1494 { 1495 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 1496 1497 if (ppdu_info->fcs_ok_cnt >= 1498 HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) { 1499 hal_err("Number of MPDUs(%d) per status buff exceeded", 1500 ppdu_info->fcs_ok_cnt); 1501 break; 1502 } 1503 1504 /* Update first_msdu_payload for every mpdu and increment 1505 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 1506 */ 1507 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload = 1508 rx_tlv; 1509 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len; 1510 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 1511 ppdu_info->msdu_info.payload_len = tlv_len; 1512 ppdu_info->user_id = user_id; 1513 ppdu_info->hdr_len = tlv_len; 1514 ppdu_info->data = rx_tlv; 1515 ppdu_info->data += 4; 1516 1517 /* for every RX_HEADER TLV increment mpdu_cnt */ 1518 com_info->mpdu_cnt++; 1519 return HAL_TLV_STATUS_HEADER; 1520 } 1521 case WIFIRX_MPDU_START_E: 1522 { 1523 uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv; 1524 uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_mpdu_start); 1525 uint8_t filter_category = 0; 1526 1527 hal_update_frame_type_cnt(rx_mpdu_start, ppdu_info); 1528 1529 ppdu_info->nac_info.fc_valid = 1530 HAL_RX_GET_FC_VALID(rx_mpdu_start); 1531 1532 ppdu_info->nac_info.to_ds_flag = 1533 HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start); 1534 1535 ppdu_info->nac_info.frame_control = 1536 HAL_RX_GET(rx_mpdu_start, 1537 RX_MPDU_INFO_14, 1538 MPDU_FRAME_CONTROL_FIELD); 1539 1540 ppdu_info->sw_frame_group_id = 1541 HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start); 1542 1543 ppdu_info->rx_user_status[user_id].sw_peer_id = 1544 HAL_RX_GET_SW_PEER_ID(rx_mpdu_start); 1545 1546 if (ppdu_info->sw_frame_group_id == 1547 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 1548 ppdu_info->rx_status.frame_control_info_valid = 1549 ppdu_info->nac_info.fc_valid; 1550 ppdu_info->rx_status.frame_control = 1551 ppdu_info->nac_info.frame_control; 1552 } 1553 1554 hal_get_mac_addr1(rx_mpdu_start, 1555 ppdu_info); 1556 1557 ppdu_info->nac_info.mac_addr2_valid = 1558 HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start); 1559 1560 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 1561 HAL_RX_GET(rx_mpdu_start, 1562 RX_MPDU_INFO_16, 1563 MAC_ADDR_AD2_15_0); 1564 1565 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 1566 HAL_RX_GET(rx_mpdu_start, 1567 RX_MPDU_INFO_17, 1568 MAC_ADDR_AD2_47_16); 1569 1570 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 1571 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 1572 ppdu_info->rx_status.ppdu_len = 1573 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1574 MPDU_LENGTH); 1575 } else { 1576 ppdu_info->rx_status.ppdu_len += 1577 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, 1578 MPDU_LENGTH); 1579 } 1580 1581 filter_category = 1582 HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start); 1583 1584 if (filter_category == 0) 1585 ppdu_info->rx_status.rxpcu_filter_pass = 1; 1586 else if (filter_category == 1) 1587 ppdu_info->rx_status.monitor_direct_used = 1; 1588 1589 ppdu_info->nac_info.mcast_bcast = 1590 HAL_RX_GET(rx_mpdu_start, 1591 RX_MPDU_INFO_13, 1592 MCAST_BCAST); 1593 break; 1594 } 1595 case WIFIRX_MPDU_END_E: 1596 ppdu_info->user_id = user_id; 1597 ppdu_info->fcs_err = 1598 HAL_RX_GET(rx_tlv, RX_MPDU_END_1, 1599 FCS_ERR); 1600 return HAL_TLV_STATUS_MPDU_END; 1601 case WIFIRX_MSDU_END_E: 1602 if (user_id < HAL_MAX_UL_MU_USERS) { 1603 ppdu_info->rx_msdu_info[user_id].cce_metadata = 1604 HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv); 1605 ppdu_info->rx_msdu_info[user_id].fse_metadata = 1606 HAL_RX_MSDU_END_FSE_METADATA_GET(rx_tlv); 1607 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 1608 HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(rx_tlv); 1609 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 1610 HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(rx_tlv); 1611 ppdu_info->rx_msdu_info[user_id].flow_idx = 1612 HAL_RX_MSDU_END_FLOW_IDX_GET(rx_tlv); 1613 } 1614 return HAL_TLV_STATUS_MSDU_END; 1615 case 0: 1616 return HAL_TLV_STATUS_PPDU_DONE; 1617 1618 default: 1619 if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) 1620 unhandled = false; 1621 else 1622 unhandled = true; 1623 break; 1624 } 1625 1626 if (!unhandled) 1627 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1628 "%s TLV type: %d, TLV len:%d %s", 1629 __func__, tlv_tag, tlv_len, 1630 unhandled == true ? "unhandled" : ""); 1631 1632 qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1633 rx_tlv, tlv_len); 1634 1635 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1636 } 1637 1638 /** 1639 * hal_tx_comp_get_release_reason_generic_li() - TQM Release reason 1640 * @hal_desc: completion ring descriptor pointer 1641 * 1642 * This function will return the type of pointer - buffer or descriptor 1643 * 1644 * Return: buffer type 1645 */ 1646 static inline uint8_t hal_tx_comp_get_release_reason_generic_li(void *hal_desc) 1647 { 1648 uint32_t comp_desc = 1649 *(uint32_t *)(((uint8_t *)hal_desc) + 1650 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 1651 1652 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 1653 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 1654 } 1655 1656 /** 1657 * hal_get_wbm_internal_error_generic_li() - is WBM internal error 1658 * @hal_desc: completion ring descriptor pointer 1659 * 1660 * This function will return 0 or 1 - is it WBM internal error or not 1661 * 1662 * Return: uint8_t 1663 */ 1664 static inline uint8_t hal_get_wbm_internal_error_generic_li(void *hal_desc) 1665 { 1666 uint32_t comp_desc = 1667 *(uint32_t *)(((uint8_t *)hal_desc) + 1668 HAL_WBM_INTERNAL_ERROR_OFFSET); 1669 1670 return (comp_desc & HAL_WBM_INTERNAL_ERROR_MASK) >> 1671 HAL_WBM_INTERNAL_ERROR_LSB; 1672 } 1673 1674 /** 1675 * hal_rx_dump_mpdu_start_tlv_generic_li: dump RX mpdu_start TLV in structured 1676 * human readable format. 1677 * @mpdu_start: pointer the rx_attention TLV in pkt. 1678 * @dbg_level: log level. 1679 * 1680 * Return: void 1681 */ 1682 static inline void hal_rx_dump_mpdu_start_tlv_generic_li(void *mpdustart, 1683 uint8_t dbg_level) 1684 { 1685 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 1686 struct rx_mpdu_info *mpdu_info = 1687 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 1688 1689 hal_verbose_debug( 1690 "rx_mpdu_start tlv (1/5) - " 1691 "rxpcu_mpdu_filter_in_category: %x " 1692 "sw_frame_group_id: %x " 1693 "ndp_frame: %x " 1694 "phy_err: %x " 1695 "phy_err_during_mpdu_header: %x " 1696 "protocol_version_err: %x " 1697 "ast_based_lookup_valid: %x " 1698 "phy_ppdu_id: %x " 1699 "ast_index: %x " 1700 "sw_peer_id: %x " 1701 "mpdu_frame_control_valid: %x " 1702 "mpdu_duration_valid: %x " 1703 "mac_addr_ad1_valid: %x " 1704 "mac_addr_ad2_valid: %x " 1705 "mac_addr_ad3_valid: %x " 1706 "mac_addr_ad4_valid: %x " 1707 "mpdu_sequence_control_valid: %x " 1708 "mpdu_qos_control_valid: %x " 1709 "mpdu_ht_control_valid: %x " 1710 "frame_encryption_info_valid: %x ", 1711 mpdu_info->rxpcu_mpdu_filter_in_category, 1712 mpdu_info->sw_frame_group_id, 1713 mpdu_info->ndp_frame, 1714 mpdu_info->phy_err, 1715 mpdu_info->phy_err_during_mpdu_header, 1716 mpdu_info->protocol_version_err, 1717 mpdu_info->ast_based_lookup_valid, 1718 mpdu_info->phy_ppdu_id, 1719 mpdu_info->ast_index, 1720 mpdu_info->sw_peer_id, 1721 mpdu_info->mpdu_frame_control_valid, 1722 mpdu_info->mpdu_duration_valid, 1723 mpdu_info->mac_addr_ad1_valid, 1724 mpdu_info->mac_addr_ad2_valid, 1725 mpdu_info->mac_addr_ad3_valid, 1726 mpdu_info->mac_addr_ad4_valid, 1727 mpdu_info->mpdu_sequence_control_valid, 1728 mpdu_info->mpdu_qos_control_valid, 1729 mpdu_info->mpdu_ht_control_valid, 1730 mpdu_info->frame_encryption_info_valid); 1731 1732 hal_verbose_debug( 1733 "rx_mpdu_start tlv (2/5) - " 1734 "fr_ds: %x " 1735 "to_ds: %x " 1736 "encrypted: %x " 1737 "mpdu_retry: %x " 1738 "mpdu_sequence_number: %x " 1739 "epd_en: %x " 1740 "all_frames_shall_be_encrypted: %x " 1741 "encrypt_type: %x " 1742 "mesh_sta: %x " 1743 "bssid_hit: %x " 1744 "bssid_number: %x " 1745 "tid: %x " 1746 "pn_31_0: %x " 1747 "pn_63_32: %x " 1748 "pn_95_64: %x " 1749 "pn_127_96: %x " 1750 "peer_meta_data: %x " 1751 "rxpt_classify_info.reo_destination_indication: %x " 1752 "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x " 1753 "rx_reo_queue_desc_addr_31_0: %x ", 1754 mpdu_info->fr_ds, 1755 mpdu_info->to_ds, 1756 mpdu_info->encrypted, 1757 mpdu_info->mpdu_retry, 1758 mpdu_info->mpdu_sequence_number, 1759 mpdu_info->epd_en, 1760 mpdu_info->all_frames_shall_be_encrypted, 1761 mpdu_info->encrypt_type, 1762 mpdu_info->mesh_sta, 1763 mpdu_info->bssid_hit, 1764 mpdu_info->bssid_number, 1765 mpdu_info->tid, 1766 mpdu_info->pn_31_0, 1767 mpdu_info->pn_63_32, 1768 mpdu_info->pn_95_64, 1769 mpdu_info->pn_127_96, 1770 mpdu_info->peer_meta_data, 1771 mpdu_info->rxpt_classify_info_details.reo_destination_indication, 1772 mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, 1773 mpdu_info->rx_reo_queue_desc_addr_31_0); 1774 1775 hal_verbose_debug( 1776 "rx_mpdu_start tlv (3/5) - " 1777 "rx_reo_queue_desc_addr_39_32: %x " 1778 "receive_queue_number: %x " 1779 "pre_delim_err_warning: %x " 1780 "first_delim_err: %x " 1781 "key_id_octet: %x " 1782 "new_peer_entry: %x " 1783 "decrypt_needed: %x " 1784 "decap_type: %x " 1785 "rx_insert_vlan_c_tag_padding: %x " 1786 "rx_insert_vlan_s_tag_padding: %x " 1787 "strip_vlan_c_tag_decap: %x " 1788 "strip_vlan_s_tag_decap: %x " 1789 "pre_delim_count: %x " 1790 "ampdu_flag: %x " 1791 "bar_frame: %x " 1792 "mpdu_length: %x " 1793 "first_mpdu: %x " 1794 "mcast_bcast: %x " 1795 "ast_index_not_found: %x " 1796 "ast_index_timeout: %x ", 1797 mpdu_info->rx_reo_queue_desc_addr_39_32, 1798 mpdu_info->receive_queue_number, 1799 mpdu_info->pre_delim_err_warning, 1800 mpdu_info->first_delim_err, 1801 mpdu_info->key_id_octet, 1802 mpdu_info->new_peer_entry, 1803 mpdu_info->decrypt_needed, 1804 mpdu_info->decap_type, 1805 mpdu_info->rx_insert_vlan_c_tag_padding, 1806 mpdu_info->rx_insert_vlan_s_tag_padding, 1807 mpdu_info->strip_vlan_c_tag_decap, 1808 mpdu_info->strip_vlan_s_tag_decap, 1809 mpdu_info->pre_delim_count, 1810 mpdu_info->ampdu_flag, 1811 mpdu_info->bar_frame, 1812 mpdu_info->mpdu_length, 1813 mpdu_info->first_mpdu, 1814 mpdu_info->mcast_bcast, 1815 mpdu_info->ast_index_not_found, 1816 mpdu_info->ast_index_timeout); 1817 1818 hal_verbose_debug( 1819 "rx_mpdu_start tlv (4/5) - " 1820 "power_mgmt: %x " 1821 "non_qos: %x " 1822 "null_data: %x " 1823 "mgmt_type: %x " 1824 "ctrl_type: %x " 1825 "more_data: %x " 1826 "eosp: %x " 1827 "fragment_flag: %x " 1828 "order: %x " 1829 "u_apsd_trigger: %x " 1830 "encrypt_required: %x " 1831 "directed: %x " 1832 "mpdu_frame_control_field: %x " 1833 "mpdu_duration_field: %x " 1834 "mac_addr_ad1_31_0: %x " 1835 "mac_addr_ad1_47_32: %x " 1836 "mac_addr_ad2_15_0: %x " 1837 "mac_addr_ad2_47_16: %x " 1838 "mac_addr_ad3_31_0: %x " 1839 "mac_addr_ad3_47_32: %x ", 1840 mpdu_info->power_mgmt, 1841 mpdu_info->non_qos, 1842 mpdu_info->null_data, 1843 mpdu_info->mgmt_type, 1844 mpdu_info->ctrl_type, 1845 mpdu_info->more_data, 1846 mpdu_info->eosp, 1847 mpdu_info->fragment_flag, 1848 mpdu_info->order, 1849 mpdu_info->u_apsd_trigger, 1850 mpdu_info->encrypt_required, 1851 mpdu_info->directed, 1852 mpdu_info->mpdu_frame_control_field, 1853 mpdu_info->mpdu_duration_field, 1854 mpdu_info->mac_addr_ad1_31_0, 1855 mpdu_info->mac_addr_ad1_47_32, 1856 mpdu_info->mac_addr_ad2_15_0, 1857 mpdu_info->mac_addr_ad2_47_16, 1858 mpdu_info->mac_addr_ad3_31_0, 1859 mpdu_info->mac_addr_ad3_47_32); 1860 1861 hal_verbose_debug( 1862 "rx_mpdu_start tlv (5/5) - " 1863 "mpdu_sequence_control_field: %x " 1864 "mac_addr_ad4_31_0: %x " 1865 "mac_addr_ad4_47_32: %x " 1866 "mpdu_qos_control_field: %x " 1867 "mpdu_ht_control_field: %x ", 1868 mpdu_info->mpdu_sequence_control_field, 1869 mpdu_info->mac_addr_ad4_31_0, 1870 mpdu_info->mac_addr_ad4_47_32, 1871 mpdu_info->mpdu_qos_control_field, 1872 mpdu_info->mpdu_ht_control_field); 1873 } 1874 1875 /** 1876 * hal_tx_set_pcp_tid_map_generic_li() - Configure default PCP to TID map table 1877 * @soc: HAL SoC context 1878 * @map: PCP-TID mapping table 1879 * 1880 * PCP are mapped to 8 TID values using TID values programmed 1881 * in one set of mapping registers PCP_TID_MAP_<0 to 6> 1882 * The mapping register has TID mapping for 8 PCP values 1883 * 1884 * Return: none 1885 */ 1886 static void hal_tx_set_pcp_tid_map_generic_li(struct hal_soc *soc, uint8_t *map) 1887 { 1888 uint32_t addr, value; 1889 1890 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 1891 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 1892 1893 value = (map[0] | 1894 (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | 1895 (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | 1896 (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | 1897 (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | 1898 (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | 1899 (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | 1900 (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); 1901 1902 HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 1903 } 1904 1905 /** 1906 * hal_tx_update_pcp_tid_generic_li() - Update the pcp tid map table with 1907 * value received from user-space 1908 * @soc: HAL SoC context 1909 * @pcp: pcp value 1910 * @tid : tid value 1911 * 1912 * Return: void 1913 */ 1914 static void 1915 hal_tx_update_pcp_tid_generic_li(struct hal_soc *soc, 1916 uint8_t pcp, uint8_t tid) 1917 { 1918 uint32_t addr, value, regval; 1919 1920 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 1921 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 1922 1923 value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); 1924 1925 /* Read back previous PCP TID config and update 1926 * with new config. 1927 */ 1928 regval = HAL_REG_READ(soc, addr); 1929 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); 1930 regval |= value; 1931 1932 HAL_REG_WRITE(soc, addr, 1933 (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 1934 } 1935 1936 /** 1937 * hal_tx_update_tidmap_prty_generic_li() - Update the tid map priority 1938 * @soc: HAL SoC context 1939 * @val: priority value 1940 * 1941 * Return: void 1942 */ 1943 static 1944 void hal_tx_update_tidmap_prty_generic_li(struct hal_soc *soc, uint8_t value) 1945 { 1946 uint32_t addr; 1947 1948 addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( 1949 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 1950 1951 HAL_REG_WRITE(soc, addr, 1952 (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); 1953 } 1954 1955 /** 1956 * hal_rx_msdu_packet_metadata_get(): API to get the 1957 * msdu information from rx_msdu_end TLV 1958 * 1959 * @ buf: pointer to the start of RX PKT TLV headers 1960 * @ hal_rx_msdu_metadata: pointer to the msdu info structure 1961 */ 1962 static void 1963 hal_rx_msdu_packet_metadata_get_generic_li(uint8_t *buf, 1964 void *pkt_msdu_metadata) 1965 { 1966 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1967 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1968 struct hal_rx_msdu_metadata *msdu_metadata = 1969 (struct hal_rx_msdu_metadata *)pkt_msdu_metadata; 1970 1971 msdu_metadata->l3_hdr_pad = 1972 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1973 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1974 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 1975 msdu_metadata->sa_sw_peer_id = 1976 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1977 } 1978 1979 /** 1980 * hal_rx_msdu_end_offset_get_generic(): API to get the 1981 * msdu_end structure offset rx_pkt_tlv structure 1982 * 1983 * NOTE: API returns offset of msdu_end TLV from structure 1984 * rx_pkt_tlvs 1985 */ 1986 static uint32_t hal_rx_msdu_end_offset_get_generic(void) 1987 { 1988 return RX_PKT_TLV_OFFSET(msdu_end_tlv); 1989 } 1990 1991 /** 1992 * hal_rx_attn_offset_get_generic(): API to get the 1993 * msdu_end structure offset rx_pkt_tlv structure 1994 * 1995 * NOTE: API returns offset of attn TLV from structure 1996 * rx_pkt_tlvs 1997 */ 1998 static uint32_t hal_rx_attn_offset_get_generic(void) 1999 { 2000 return RX_PKT_TLV_OFFSET(attn_tlv); 2001 } 2002 2003 /** 2004 * hal_rx_msdu_start_offset_get_generic(): API to get the 2005 * msdu_start structure offset rx_pkt_tlv structure 2006 * 2007 * NOTE: API returns offset of attn TLV from structure 2008 * rx_pkt_tlvs 2009 */ 2010 static uint32_t hal_rx_msdu_start_offset_get_generic(void) 2011 { 2012 return RX_PKT_TLV_OFFSET(msdu_start_tlv); 2013 } 2014 2015 /** 2016 * hal_rx_mpdu_start_offset_get_generic(): API to get the 2017 * mpdu_start structure offset rx_pkt_tlv structure 2018 * 2019 * NOTE: API returns offset of attn TLV from structure 2020 * rx_pkt_tlvs 2021 */ 2022 static uint32_t hal_rx_mpdu_start_offset_get_generic(void) 2023 { 2024 return RX_PKT_TLV_OFFSET(mpdu_start_tlv); 2025 } 2026 2027 /** 2028 * hal_rx_mpdu_end_offset_get_generic(): API to get the 2029 * mpdu_end structure offset rx_pkt_tlv structure 2030 * 2031 * NOTE: API returns offset of attn TLV from structure 2032 * rx_pkt_tlvs 2033 */ 2034 static uint32_t hal_rx_mpdu_end_offset_get_generic(void) 2035 { 2036 return RX_PKT_TLV_OFFSET(mpdu_end_tlv); 2037 } 2038 2039 #ifndef NO_RX_PKT_HDR_TLV 2040 static uint32_t hal_rx_pkt_tlv_offset_get_generic(void) 2041 { 2042 return RX_PKT_TLV_OFFSET(pkt_hdr_tlv); 2043 } 2044 #endif 2045 2046 #if defined(QDF_BIG_ENDIAN_MACHINE) 2047 /** 2048 * hal_setup_reo_swap() - Set the swap flag for big endian machines 2049 * @soc: HAL soc handle 2050 * 2051 * Return: None 2052 */ 2053 static inline void hal_setup_reo_swap(struct hal_soc *soc) 2054 { 2055 uint32_t reg_val; 2056 2057 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR( 2058 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 2059 2060 reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, WRITE_STRUCT_SWAP, 1); 2061 reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, READ_STRUCT_SWAP, 1); 2062 2063 HAL_REG_WRITE(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR( 2064 SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val); 2065 } 2066 #else 2067 static inline void hal_setup_reo_swap(struct hal_soc *soc) 2068 { 2069 } 2070 #endif 2071 2072 /** 2073 * hal_reo_setup_generic_li - Initialize HW REO block 2074 * 2075 * @hal_soc: Opaque HAL SOC handle 2076 * @reo_params: parameters needed by HAL for REO config 2077 */ 2078 static 2079 void hal_reo_setup_generic_li(struct hal_soc *soc, void *reoparams) 2080 { 2081 uint32_t reg_val; 2082 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams; 2083 2084 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR( 2085 SEQ_WCSS_UMAC_REO_REG_OFFSET)); 2086 2087 hal_reo_config(soc, reg_val, reo_params); 2088 /* Other ring enable bits and REO_ENABLE will be set by FW */ 2089 2090 /* TODO: Setup destination ring mapping if enabled */ 2091 2092 /* TODO: Error destination ring setting is left to default. 2093 * Default setting is to send all errors to release ring. 2094 */ 2095 2096 /* Set the reo descriptor swap bits in case of BIG endian platform */ 2097 hal_setup_reo_swap(soc); 2098 2099 HAL_REG_WRITE(soc, 2100 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 2101 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2102 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000); 2103 2104 HAL_REG_WRITE(soc, 2105 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 2106 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2107 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 2108 2109 HAL_REG_WRITE(soc, 2110 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 2111 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2112 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000)); 2113 2114 HAL_REG_WRITE(soc, 2115 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 2116 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2117 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000)); 2118 2119 /* 2120 * When hash based routing is enabled, routing of the rx packet 2121 * is done based on the following value: 1 _ _ _ _ The last 4 2122 * bits are based on hash[3:0]. This means the possible values 2123 * are 0x10 to 0x1f. This value is used to look-up the 2124 * ring ID configured in Destination_Ring_Ctrl_IX_* register. 2125 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3 2126 * registers need to be configured to set-up the 16 entries to 2127 * map the hash values to a ring number. There are 3 bits per 2128 * hash entry – which are mapped as follows: 2129 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI), 2130 * 7: NOT_USED. 2131 */ 2132 if (reo_params->rx_hash_enabled) { 2133 HAL_REG_WRITE(soc, 2134 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 2135 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2136 reo_params->remap1); 2137 2138 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x", 2139 HAL_REG_READ(soc, 2140 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 2141 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 2142 2143 HAL_REG_WRITE(soc, 2144 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 2145 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2146 reo_params->remap2); 2147 2148 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x", 2149 HAL_REG_READ(soc, 2150 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 2151 SEQ_WCSS_UMAC_REO_REG_OFFSET))); 2152 } 2153 2154 /* TODO: Check if the following registers shoould be setup by host: 2155 * AGING_CONTROL 2156 * HIGH_MEMORY_THRESHOLD 2157 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2] 2158 * GLOBAL_LINK_DESC_COUNT_CTRL 2159 */ 2160 } 2161 2162 /** 2163 * hal_setup_link_idle_list_generic_li - Setup scattered idle list using the 2164 * buffer list provided 2165 * 2166 * @hal_soc: Opaque HAL SOC handle 2167 * @scatter_bufs_base_paddr: Array of physical base addresses 2168 * @scatter_bufs_base_vaddr: Array of virtual base addresses 2169 * @num_scatter_bufs: Number of scatter buffers in the above lists 2170 * @scatter_buf_size: Size of each scatter buffer 2171 * @last_buf_end_offset: Offset to the last entry 2172 * @num_entries: Total entries of all scatter bufs 2173 * 2174 * Return: None 2175 */ 2176 static void 2177 hal_setup_link_idle_list_generic_li(struct hal_soc *soc, 2178 qdf_dma_addr_t scatter_bufs_base_paddr[], 2179 void *scatter_bufs_base_vaddr[], 2180 uint32_t num_scatter_bufs, 2181 uint32_t scatter_buf_size, 2182 uint32_t last_buf_end_offset, 2183 uint32_t num_entries) 2184 { 2185 int i; 2186 uint32_t *prev_buf_link_ptr = NULL; 2187 uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size; 2188 uint32_t val; 2189 2190 /* Link the scatter buffers */ 2191 for (i = 0; i < num_scatter_bufs; i++) { 2192 if (i > 0) { 2193 prev_buf_link_ptr[0] = 2194 scatter_bufs_base_paddr[i] & 0xffffffff; 2195 prev_buf_link_ptr[1] = HAL_SM( 2196 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2197 BASE_ADDRESS_39_32, 2198 ((uint64_t)(scatter_bufs_base_paddr[i]) 2199 >> 32)) | HAL_SM( 2200 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2201 ADDRESS_MATCH_TAG, 2202 ADDRESS_MATCH_TAG_VAL); 2203 } 2204 prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] + 2205 scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE); 2206 } 2207 2208 /* TBD: Register programming partly based on MLD & the rest based on 2209 * inputs from HW team. Not complete yet. 2210 */ 2211 2212 reg_scatter_buf_size = (scatter_buf_size - 2213 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64; 2214 reg_tot_scatter_buf_size = ((scatter_buf_size - 2215 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64; 2216 2217 HAL_REG_WRITE(soc, 2218 HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR 2219 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2220 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, 2221 SCATTER_BUFFER_SIZE, 2222 reg_scatter_buf_size) | 2223 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, 2224 LINK_DESC_IDLE_LIST_MODE, 0x1)); 2225 2226 HAL_REG_WRITE(soc, 2227 HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR 2228 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2229 HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE, 2230 SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST, 2231 reg_tot_scatter_buf_size)); 2232 2233 HAL_REG_WRITE(soc, 2234 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR 2235 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2236 scatter_bufs_base_paddr[0] & 0xffffffff); 2237 2238 HAL_REG_WRITE(soc, 2239 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR 2240 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2241 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) & 2242 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK); 2243 2244 HAL_REG_WRITE(soc, 2245 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR 2246 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2247 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2248 BASE_ADDRESS_39_32, 2249 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32)) | 2250 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 2251 ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL)); 2252 2253 /* ADDRESS_MATCH_TAG field in the above register is expected to match 2254 * with the upper bits of link pointer. The above write sets this field 2255 * to zero and we are also setting the upper bits of link pointers to 2256 * zero while setting up the link list of scatter buffers above 2257 */ 2258 2259 /* Setup head and tail pointers for the idle list */ 2260 HAL_REG_WRITE(soc, 2261 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR 2262 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2263 scatter_bufs_base_paddr[num_scatter_bufs - 1] & 2264 0xffffffff); 2265 HAL_REG_WRITE(soc, 2266 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR 2267 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2268 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 2269 BUFFER_ADDRESS_39_32, 2270 ((uint64_t)(scatter_bufs_base_paddr 2271 [num_scatter_bufs - 1]) >> 32)) | 2272 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 2273 HEAD_POINTER_OFFSET, last_buf_end_offset >> 2)); 2274 2275 HAL_REG_WRITE(soc, 2276 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR 2277 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2278 scatter_bufs_base_paddr[0] & 0xffffffff); 2279 2280 HAL_REG_WRITE(soc, 2281 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR 2282 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2283 scatter_bufs_base_paddr[0] & 0xffffffff); 2284 HAL_REG_WRITE(soc, 2285 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR 2286 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2287 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 2288 BUFFER_ADDRESS_39_32, 2289 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32)) | 2290 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 2291 TAIL_POINTER_OFFSET, 0)); 2292 2293 HAL_REG_WRITE(soc, 2294 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR 2295 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2 * num_entries); 2296 2297 /* Set RING_ID_DISABLE */ 2298 val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1); 2299 2300 /* 2301 * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence 2302 * check the presence of the bit before toggling it. 2303 */ 2304 #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK 2305 val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1); 2306 #endif 2307 HAL_REG_WRITE(soc, 2308 HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR 2309 (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2310 val); 2311 } 2312 2313 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 2314 /** 2315 * hal_tx_desc_set_search_type_generic_li - Set the search type value 2316 * @desc: Handle to Tx Descriptor 2317 * @search_type: search type 2318 * 0 – Normal search 2319 * 1 – Index based address search 2320 * 2 – Index based flow search 2321 * 2322 * Return: void 2323 */ 2324 static inline 2325 void hal_tx_desc_set_search_type_generic_li(void *desc, uint8_t search_type) 2326 { 2327 HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= 2328 HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); 2329 } 2330 #else 2331 static inline 2332 void hal_tx_desc_set_search_type_generic_li(void *desc, uint8_t search_type) 2333 { 2334 } 2335 2336 #endif 2337 2338 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 2339 /** 2340 * hal_tx_desc_set_search_index_generic_li - Set the search index value 2341 * @desc: Handle to Tx Descriptor 2342 * @search_index: The index that will be used for index based address or 2343 * flow search. The field is valid when 'search_type' is 2344 * 1 0r 2 2345 * 2346 * Return: void 2347 */ 2348 static inline 2349 void hal_tx_desc_set_search_index_generic_li(void *desc, uint32_t search_index) 2350 { 2351 HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= 2352 HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); 2353 } 2354 #else 2355 static inline 2356 void hal_tx_desc_set_search_index_generic_li(void *desc, uint32_t search_index) 2357 { 2358 } 2359 #endif 2360 2361 #ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 2362 /** 2363 * hal_tx_desc_set_cache_set_num_generic_li - Set the cache-set-num value 2364 * @desc: Handle to Tx Descriptor 2365 * @cache_num: Cache set number that should be used to cache the index 2366 * based search results, for address and flow search. 2367 * This value should be equal to LSB four bits of the hash value 2368 * of match data, in case of search index points to an entry 2369 * which may be used in content based search also. The value can 2370 * be anything when the entry pointed by search index will not be 2371 * used for content based search. 2372 * 2373 * Return: void 2374 */ 2375 static inline 2376 void hal_tx_desc_set_cache_set_num_generic_li(void *desc, uint8_t cache_num) 2377 { 2378 HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |= 2379 HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num); 2380 } 2381 #else 2382 static inline 2383 void hal_tx_desc_set_cache_set_num_generic_li(void *desc, uint8_t cache_num) 2384 { 2385 } 2386 #endif 2387 #endif /* _HAL_LI_GENERIC_API_H_ */ 2388