1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "hal_li_api.h" 21 #include "hal_li_hw_headers.h" 22 #include "hal_li_reo.h" 23 24 #include "hal_rx.h" 25 #include "hal_li_rx.h" 26 #include "hal_tx.h" 27 #include <hal_api_mon.h> 28 29 static uint16_t hal_get_rx_max_ba_window_li(int tid) 30 { 31 return HAL_RX_BA_WINDOW_256; 32 } 33 34 static uint32_t hal_get_reo_qdesc_size_li(uint32_t ba_window_size, int tid) 35 { 36 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 37 * NON_QOS_TID until HW issues are resolved. 38 */ 39 if (tid != HAL_NON_QOS_TID) 40 ba_window_size = hal_get_rx_max_ba_window_li(tid); 41 42 /* Return descriptor size corresponding to window size of 2 since 43 * we set ba_window_size to 2 while setting up REO descriptors as 44 * a WAR to get 2k jump exception aggregates are received without 45 * a BA session. 46 */ 47 if (ba_window_size <= 1) { 48 if (tid != HAL_NON_QOS_TID) 49 return sizeof(struct rx_reo_queue) + 50 sizeof(struct rx_reo_queue_ext); 51 else 52 return sizeof(struct rx_reo_queue); 53 } 54 55 if (ba_window_size <= 105) 56 return sizeof(struct rx_reo_queue) + 57 sizeof(struct rx_reo_queue_ext); 58 59 if (ba_window_size <= 210) 60 return sizeof(struct rx_reo_queue) + 61 (2 * sizeof(struct rx_reo_queue_ext)); 62 63 return sizeof(struct rx_reo_queue) + 64 (3 * sizeof(struct rx_reo_queue_ext)); 65 } 66 67 void hal_set_link_desc_addr_li(void *desc, uint32_t cookie, 68 qdf_dma_addr_t link_desc_paddr, 69 uint8_t bm_id) 70 { 71 uint32_t *buf_addr = (uint32_t *)desc; 72 73 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, 74 link_desc_paddr & 0xffffffff); 75 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 76 (uint64_t)link_desc_paddr >> 32); 77 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, RETURN_BUFFER_MANAGER, 78 bm_id); 79 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, 80 cookie); 81 } 82 83 void hal_tx_init_data_ring_li(hal_soc_handle_t hal_soc_hdl, 84 hal_ring_handle_t hal_ring_hdl) 85 { 86 uint8_t *desc_addr; 87 struct hal_srng_params srng_params; 88 uint32_t desc_size; 89 uint32_t num_desc; 90 91 hal_get_srng_params(hal_soc_hdl, hal_ring_hdl, &srng_params); 92 93 desc_addr = (uint8_t *)srng_params.ring_base_vaddr; 94 desc_size = sizeof(struct tcl_data_cmd); 95 num_desc = srng_params.num_entries; 96 97 while (num_desc) { 98 HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, 99 desc_size); 100 desc_addr += (desc_size + sizeof(struct tlv_32_hdr)); 101 num_desc--; 102 } 103 } 104 105 /* 106 * hal_rx_msdu_is_wlan_mcast_generic_li(): Check if the buffer is for multicast 107 * address 108 * @nbuf: Network buffer 109 * 110 * Returns: flag to indicate whether the nbuf has MC/BC address 111 */ 112 static uint32_t hal_rx_msdu_is_wlan_mcast_generic_li(qdf_nbuf_t nbuf) 113 { 114 uint8_t *buf = qdf_nbuf_data(nbuf); 115 116 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 117 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 118 119 return rx_attn->mcast_bcast; 120 } 121 122 /** 123 * hal_rx_tlv_decap_format_get_li() - Get packet decap format from the TLV 124 * @hw_desc_addr: rx tlv desc 125 * 126 * Return: pkt decap format 127 */ 128 static uint32_t hal_rx_tlv_decap_format_get_li(void *hw_desc_addr) 129 { 130 struct rx_msdu_start *rx_msdu_start; 131 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 132 133 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 134 135 return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); 136 } 137 138 /** 139 * hal_rx_dump_pkt_tlvs_li(): API to print all member elements of 140 * RX TLVs 141 * @ buf: pointer the pkt buffer. 142 * @ dbg_level: log level. 143 * 144 * Return: void 145 */ 146 static void hal_rx_dump_pkt_tlvs_li(hal_soc_handle_t hal_soc_hdl, 147 uint8_t *buf, uint8_t dbg_level) 148 { 149 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 150 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 151 struct rx_mpdu_start *mpdu_start = 152 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 153 struct rx_msdu_start *msdu_start = 154 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 155 struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 156 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 157 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 158 159 hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level); 160 hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc); 161 hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level); 162 hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level); 163 hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level); 164 hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level); 165 } 166 167 /** 168 * hal_rx_tlv_get_offload_info_li() - Get the offload info from TLV 169 * @rx_tlv: RX tlv start address in buffer 170 * @offload_info: Buffer to store the offload info 171 * 172 * Return: 0 on success, -EINVAL on failure. 173 */ 174 static int 175 hal_rx_tlv_get_offload_info_li(uint8_t *rx_tlv, 176 struct hal_offload_info *offload_info) 177 { 178 offload_info->flow_id = HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(rx_tlv); 179 offload_info->ipv6_proto = HAL_RX_TLV_GET_IPV6(rx_tlv); 180 offload_info->lro_eligible = HAL_RX_TLV_GET_LRO_ELIGIBLE(rx_tlv); 181 offload_info->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(rx_tlv); 182 183 if (offload_info->tcp_proto) { 184 offload_info->tcp_pure_ack = 185 HAL_RX_TLV_GET_TCP_PURE_ACK(rx_tlv); 186 offload_info->tcp_offset = HAL_RX_TLV_GET_TCP_OFFSET(rx_tlv); 187 offload_info->tcp_win = HAL_RX_TLV_GET_TCP_WIN(rx_tlv); 188 offload_info->tcp_seq_num = HAL_RX_TLV_GET_TCP_SEQ(rx_tlv); 189 offload_info->tcp_ack_num = HAL_RX_TLV_GET_TCP_ACK(rx_tlv); 190 } 191 return 0; 192 } 193 194 /* 195 * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value 196 * from rx attention 197 * @buf: pointer to rx_pkt_tlvs 198 * 199 * Return: phy_ppdu_id 200 */ 201 static uint16_t hal_rx_attn_phy_ppdu_id_get_li(uint8_t *buf) 202 { 203 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 204 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 205 uint16_t phy_ppdu_id; 206 207 phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn); 208 209 return phy_ppdu_id; 210 } 211 212 /** 213 * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length 214 * from rx_msdu_start TLV 215 * 216 * @ buf: pointer to the start of RX PKT TLV headers 217 * Return: msdu length 218 */ 219 static uint32_t hal_rx_msdu_start_msdu_len_get_li(uint8_t *buf) 220 { 221 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 222 struct rx_msdu_start *msdu_start = 223 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 224 uint32_t msdu_len; 225 226 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 227 228 return msdu_len; 229 } 230 231 /** 232 * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field 233 * 234 * @nbuf: Network buffer 235 * Returns: rx more fragment bit 236 * 237 */ 238 static uint16_t hal_rx_get_frame_ctrl_field_li(uint8_t *buf) 239 { 240 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 241 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 242 uint16_t frame_ctrl = 0; 243 244 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 245 246 return frame_ctrl; 247 } 248 249 /** 250 * hal_rx_get_proto_params_li() - Get l4 proto values from TLV 251 * @buf: rx tlv address 252 * @proto_params: Buffer to store proto parameters 253 * 254 * Return: 0 on success. 255 */ 256 static int hal_rx_get_proto_params_li(uint8_t *buf, void *proto_params) 257 { 258 struct hal_proto_params *param = 259 (struct hal_proto_params *)proto_params; 260 261 param->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(buf); 262 param->udp_proto = HAL_RX_TLV_GET_UDP_PROTO(buf); 263 param->ipv6_proto = HAL_RX_TLV_GET_IPV6(buf); 264 265 return 0; 266 } 267 268 /** 269 * hal_rx_get_l3_l4_offsets_li() - Get l3/l4 header offset from TLV 270 * @buf: rx tlv start address 271 * @l3_hdr_offset: buffer to store l3 offset 272 * @l4_hdr_offset: buffer to store l4 offset 273 * 274 * Return: 0 on success. 275 */ 276 static int hal_rx_get_l3_l4_offsets_li(uint8_t *buf, uint32_t *l3_hdr_offset, 277 uint32_t *l4_hdr_offset) 278 { 279 *l3_hdr_offset = HAL_RX_TLV_GET_IP_OFFSET(buf); 280 *l4_hdr_offset = HAL_RX_TLV_GET_TCP_OFFSET(buf); 281 282 return 0; 283 } 284 285 /** 286 * hal_rx_tlv_get_pn_num_li() - Get packet number from RX TLV 287 * @buf: rx tlv address 288 * @pn_num: buffer to store packet number 289 * 290 * Return: None 291 */ 292 static inline void hal_rx_tlv_get_pn_num_li(uint8_t *buf, uint64_t *pn_num) 293 { 294 struct rx_pkt_tlvs *rx_pkt_tlv = 295 (struct rx_pkt_tlvs *)buf; 296 struct rx_mpdu_info *rx_mpdu_info_details = 297 &rx_pkt_tlv->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 298 299 pn_num[0] = rx_mpdu_info_details->pn_31_0; 300 pn_num[0] |= 301 ((uint64_t)rx_mpdu_info_details->pn_63_32 << 32); 302 pn_num[1] = rx_mpdu_info_details->pn_95_64; 303 pn_num[1] |= 304 ((uint64_t)rx_mpdu_info_details->pn_127_96 << 32); 305 } 306 307 #ifdef NO_RX_PKT_HDR_TLV 308 /** 309 * hal_rx_pkt_hdr_get_li() - Get rx packet header start address. 310 * @buf: packet start address 311 * 312 * Return: packet data start address. 313 */ 314 static inline uint8_t *hal_rx_pkt_hdr_get_li(uint8_t *buf) 315 { 316 return buf + RX_PKT_TLVS_LEN; 317 } 318 #else 319 static inline uint8_t *hal_rx_pkt_hdr_get_li(uint8_t *buf) 320 { 321 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 322 323 return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr; 324 } 325 #endif 326 327 /** 328 * hal_rx_priv_info_set_in_tlv_li(): Save the private info to 329 * the reserved bytes of rx_tlv_hdr 330 * @buf: start of rx_tlv_hdr 331 * @priv_data: hal_wbm_err_desc_info structure 332 * @len: length of the private data 333 * Return: void 334 */ 335 static inline void 336 hal_rx_priv_info_set_in_tlv_li(uint8_t *buf, uint8_t *priv_data, 337 uint32_t len) 338 { 339 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 340 uint32_t copy_len = (len > RX_PADDING0_BYTES) ? 341 RX_PADDING0_BYTES : len; 342 343 qdf_mem_copy(pkt_tlvs->rx_padding0, priv_data, copy_len); 344 } 345 346 /** 347 * hal_rx_priv_info_get_from_tlv_li(): retrieve the private data from 348 * the reserved bytes of rx_tlv_hdr. 349 * @buf: start of rx_tlv_hdr 350 * @priv_data: hal_wbm_err_desc_info structure 351 * @len: length of the private data 352 * Return: void 353 */ 354 static inline void 355 hal_rx_priv_info_get_from_tlv_li(uint8_t *buf, uint8_t *priv_data, 356 uint32_t len) 357 { 358 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 359 uint32_t copy_len = (len > RX_PADDING0_BYTES) ? 360 RX_PADDING0_BYTES : len; 361 362 qdf_mem_copy(priv_data, pkt_tlvs->rx_padding0, copy_len); 363 } 364 365 /** 366 * hal_rx_get_tlv_size_generic_li() - Get rx packet tlv size 367 * @rx_pkt_tlv_size: TLV size for regular RX packets 368 * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets 369 * 370 * Return: size of rx pkt tlv before the actual data 371 */ 372 static void hal_rx_get_tlv_size_generic_li(uint16_t *rx_pkt_tlv_size, 373 uint16_t *rx_mon_pkt_tlv_size) 374 { 375 *rx_pkt_tlv_size = RX_PKT_TLVS_LEN; 376 *rx_mon_pkt_tlv_size = SIZE_OF_MONITOR_TLV; 377 } 378 379 /** 380 * hal_rx_wbm_err_src_get_li() - Get WBM error source from descriptor 381 * @ring_desc: ring descriptor 382 * 383 * Return: wbm error source 384 */ 385 uint32_t hal_rx_wbm_err_src_get_li(hal_ring_desc_t ring_desc) 386 { 387 return HAL_WBM2SW_RELEASE_SRC_GET(ring_desc); 388 } 389 390 /** 391 * hal_rx_ret_buf_manager_get_li() - Get return buffer manager from ring desc 392 * @ring_desc: ring descriptor 393 * 394 * Return: rbm 395 */ 396 uint8_t hal_rx_ret_buf_manager_get_li(hal_ring_desc_t ring_desc) 397 { 398 /* 399 * The following macro takes buf_addr_info as argument, 400 * but since buf_addr_info is the first field in ring_desc 401 * Hence the following call is OK 402 */ 403 return HAL_RX_BUF_RBM_GET(ring_desc); 404 } 405 406 /** 407 * hal_rx_reo_buf_paddr_get_li: Gets the physical address and 408 * cookie from the REO destination ring element 409 * 410 * @ rx_desc: Opaque cookie pointer used by HAL to get to 411 * the current descriptor 412 * @ buf_info: structure to return the buffer information 413 * Return: void 414 */ 415 static void hal_rx_reo_buf_paddr_get_li(hal_ring_desc_t rx_desc, 416 struct hal_buf_info *buf_info) 417 { 418 struct reo_destination_ring *reo_ring = 419 (struct reo_destination_ring *)rx_desc; 420 421 buf_info->paddr = 422 (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) | 423 ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32)); 424 buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring); 425 } 426 427 /** 428 * hal_rx_msdu_link_desc_set_li: Retrieves MSDU Link Descriptor to WBM 429 * 430 * @ hal_soc_hdl : HAL version of the SOC pointer 431 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 432 * @ buf_addr_info : void pointer to the buffer_addr_info 433 * @ bm_action : put in IDLE list or release to MSDU_LIST 434 * 435 * Return: void 436 */ 437 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 438 static void hal_rx_msdu_link_desc_set_li(hal_soc_handle_t hal_soc_hdl, 439 void *src_srng_desc, 440 hal_buff_addrinfo_t buf_addr_info, 441 uint8_t bm_action) 442 { 443 /* 444 * The offsets for fields used in this function are same in 445 * wbm_release_ring for Lithium and wbm_release_ring_tx 446 * for Beryllium. hence we can use wbm_release_ring directly. 447 */ 448 struct wbm_release_ring *wbm_rel_srng = 449 (struct wbm_release_ring *)src_srng_desc; 450 uint32_t addr_31_0; 451 uint8_t addr_39_32; 452 453 /* Structure copy !!! */ 454 wbm_rel_srng->released_buff_or_desc_addr_info = 455 *(struct buffer_addr_info *)buf_addr_info; 456 457 addr_31_0 = 458 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0; 459 addr_39_32 = 460 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32; 461 462 HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, 463 RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW); 464 HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, BM_ACTION, 465 bm_action); 466 HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, 467 BUFFER_OR_DESC_TYPE, 468 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC); 469 470 /* WBM error is indicated when any of the link descriptors given to 471 * WBM has a NULL address, and one those paths is the link descriptors 472 * released from host after processing RXDMA errors, 473 * or from Rx defrag path, and we want to add an assert here to ensure 474 * host is not releasing descriptors with NULL address. 475 */ 476 477 if (qdf_unlikely(!addr_31_0 && !addr_39_32)) { 478 hal_dump_wbm_rel_desc(src_srng_desc); 479 qdf_assert_always(0); 480 } 481 } 482 483 static 484 void hal_rx_buf_cookie_rbm_get_li(uint32_t *buf_addr_info_hdl, 485 hal_buf_info_t buf_info_hdl) 486 { 487 struct hal_buf_info *buf_info = 488 (struct hal_buf_info *)buf_info_hdl; 489 struct buffer_addr_info *buf_addr_info = 490 (struct buffer_addr_info *)buf_addr_info_hdl; 491 492 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 493 /* 494 * buffer addr info is the first member of ring desc, so the typecast 495 * can be done. 496 */ 497 buf_info->rbm = hal_rx_ret_buf_manager_get_li 498 ((hal_ring_desc_t)buf_addr_info); 499 } 500 501 /** 502 * hal_rx_msdu_link_desc_get(): API to get the MSDU information 503 * from the MSDU link descriptor 504 * 505 * @ hal_soc_hdl : HAL version of the SOC pointer 506 * @msdu_link_desc: Opaque pointer used by HAL to get to the 507 * MSDU link descriptor (struct rx_msdu_link) 508 * 509 * @msdu_list: Return the list of MSDUs contained in this link descriptor 510 * 511 * @num_msdus: Number of MSDUs in the MPDU 512 * 513 * Return: void 514 */ 515 static inline void hal_rx_msdu_list_get_li(hal_soc_handle_t hal_soc_hdl, 516 void *msdu_link_desc, 517 void *hal_msdu_list, 518 uint16_t *num_msdus) 519 { 520 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 521 struct rx_msdu_details *msdu_details; 522 struct rx_msdu_desc_info *msdu_desc_info; 523 struct hal_rx_msdu_list *msdu_list = hal_msdu_list; 524 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 525 int i; 526 struct hal_buf_info buf_info; 527 528 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 529 530 hal_debug("msdu_link=%pK msdu_details=%pK", msdu_link, msdu_details); 531 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 532 /* num_msdus received in mpdu descriptor may be incorrect 533 * sometimes due to HW issue. Check msdu buffer address also 534 */ 535 if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET( 536 &msdu_details[i].buffer_addr_info_details) == 0)) 537 break; 538 if (HAL_RX_BUFFER_ADDR_31_0_GET( 539 &msdu_details[i].buffer_addr_info_details) == 0) { 540 /* set the last msdu bit in the prev msdu_desc_info */ 541 msdu_desc_info = 542 hal_rx_msdu_desc_info_get_ptr 543 (&msdu_details[i - 1], hal_soc); 544 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 545 break; 546 } 547 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 548 hal_soc); 549 550 /* set first MSDU bit or the last MSDU bit */ 551 if (!i) 552 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 553 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 554 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 555 556 msdu_list->msdu_info[i].msdu_flags = 557 hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info); 558 msdu_list->msdu_info[i].msdu_len = 559 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 560 561 /* addr field in buf_info will not be valid */ 562 hal_rx_buf_cookie_rbm_get_li( 563 (uint32_t *) 564 &msdu_details[i].buffer_addr_info_details, 565 &buf_info); 566 msdu_list->sw_cookie[i] = buf_info.sw_cookie; 567 msdu_list->rbm[i] = buf_info.rbm; 568 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 569 &msdu_details[i].buffer_addr_info_details) | 570 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 571 &msdu_details[i].buffer_addr_info_details) << 32; 572 hal_debug("i=%d sw_cookie=%d", i, msdu_list->sw_cookie[i]); 573 } 574 *num_msdus = i; 575 } 576 577 /* 578 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 579 * rxdma ring entry. 580 * @rxdma_entry: descriptor entry 581 * @paddr: physical address of nbuf data pointer. 582 * @cookie: SW cookie used as a index to SW rx desc. 583 * @manager: who owns the nbuf (host, NSS, etc...). 584 * 585 */ 586 static void hal_rxdma_buff_addr_info_set_li(void *rxdma_entry, 587 qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager) 588 { 589 uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff); 590 uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32; 591 592 HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo); 593 HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi); 594 HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie); 595 HAL_RXDMA_MANAGER_SET(rxdma_entry, manager); 596 } 597 598 /** 599 * hal_rx_get_reo_error_code_li() - Get REO error code from ring desc 600 * @rx_desc: rx descriptor 601 * 602 * Return: REO error code 603 */ 604 static uint32_t hal_rx_get_reo_error_code_li(hal_ring_desc_t rx_desc) 605 { 606 struct reo_destination_ring *reo_desc = 607 (struct reo_destination_ring *)rx_desc; 608 609 return HAL_RX_REO_ERROR_GET(reo_desc); 610 } 611 612 /** 613 * hal_gen_reo_remap_val_generic_li() - Generate the reo map value 614 * @ix0_map: mapping values for reo 615 * 616 * Return: IX0 reo remap register value to be written 617 */ 618 static uint32_t 619 hal_gen_reo_remap_val_generic_li(enum hal_reo_remap_reg remap_reg, 620 uint8_t *ix0_map) 621 { 622 uint32_t ix_val = 0; 623 624 switch (remap_reg) { 625 case HAL_REO_REMAP_REG_IX0: 626 ix_val = HAL_REO_REMAP_IX0(ix0_map[0], 0) | 627 HAL_REO_REMAP_IX0(ix0_map[1], 1) | 628 HAL_REO_REMAP_IX0(ix0_map[2], 2) | 629 HAL_REO_REMAP_IX0(ix0_map[3], 3) | 630 HAL_REO_REMAP_IX0(ix0_map[4], 4) | 631 HAL_REO_REMAP_IX0(ix0_map[5], 5) | 632 HAL_REO_REMAP_IX0(ix0_map[6], 6) | 633 HAL_REO_REMAP_IX0(ix0_map[7], 7); 634 break; 635 case HAL_REO_REMAP_REG_IX2: 636 ix_val = HAL_REO_REMAP_IX2(ix0_map[0], 16) | 637 HAL_REO_REMAP_IX2(ix0_map[1], 17) | 638 HAL_REO_REMAP_IX2(ix0_map[2], 18) | 639 HAL_REO_REMAP_IX2(ix0_map[3], 19) | 640 HAL_REO_REMAP_IX2(ix0_map[4], 20) | 641 HAL_REO_REMAP_IX2(ix0_map[5], 21) | 642 HAL_REO_REMAP_IX2(ix0_map[6], 22) | 643 HAL_REO_REMAP_IX2(ix0_map[7], 23); 644 break; 645 default: 646 break; 647 } 648 649 return ix_val; 650 } 651 652 /** 653 * hal_rx_tlv_csum_err_get_li() - Get IP and tcp-udp checksum fail flag 654 * @rx_tlv_hdr: start address of rx_tlv_hdr 655 * @ip_csum_err: buffer to return ip_csum_fail flag 656 * @tcp_udp_csum_fail: placeholder to return tcp-udp checksum fail flag 657 * 658 * Return: None 659 */ 660 static inline void 661 hal_rx_tlv_csum_err_get_li(uint8_t *rx_tlv_hdr, uint32_t *ip_csum_err, 662 uint32_t *tcp_udp_csum_err) 663 { 664 *ip_csum_err = hal_rx_attn_ip_cksum_fail_get(rx_tlv_hdr); 665 *tcp_udp_csum_err = hal_rx_attn_tcp_udp_cksum_fail_get(rx_tlv_hdr); 666 } 667 668 static 669 void hal_rx_tlv_get_pkt_capture_flags_li(uint8_t *rx_tlv_pkt_hdr, 670 struct hal_rx_pkt_capture_flags *flags) 671 { 672 struct rx_pkt_tlvs *rx_tlv_hdr = (struct rx_pkt_tlvs *)rx_tlv_pkt_hdr; 673 struct rx_attention *rx_attn = &rx_tlv_hdr->attn_tlv.rx_attn; 674 struct rx_mpdu_start *mpdu_start = 675 &rx_tlv_hdr->mpdu_start_tlv.rx_mpdu_start; 676 struct rx_mpdu_end *mpdu_end = &rx_tlv_hdr->mpdu_end_tlv.rx_mpdu_end; 677 struct rx_msdu_start *msdu_start = 678 &rx_tlv_hdr->msdu_start_tlv.rx_msdu_start; 679 680 flags->encrypt_type = mpdu_start->rx_mpdu_info_details.encrypt_type; 681 flags->fcs_err = mpdu_end->fcs_err; 682 flags->fragment_flag = rx_attn->fragment_flag; 683 flags->chan_freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 684 flags->rssi_comb = HAL_RX_MSDU_START_RSSI_GET(msdu_start); 685 flags->tsft = msdu_start->ppdu_start_timestamp; 686 } 687 688 static uint8_t hal_rx_err_status_get_li(hal_ring_desc_t rx_desc) 689 { 690 return HAL_RX_ERROR_STATUS_GET(rx_desc); 691 } 692 693 static uint8_t hal_rx_reo_buf_type_get_li(hal_ring_desc_t rx_desc) 694 { 695 return HAL_RX_REO_BUF_TYPE_GET(rx_desc); 696 } 697 698 static inline bool 699 hal_rx_mpdu_info_ampdu_flag_get_li(uint8_t *buf) 700 { 701 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 702 struct rx_mpdu_start *mpdu_start = 703 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 704 705 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 706 bool ampdu_flag; 707 708 ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info); 709 710 return ampdu_flag; 711 } 712 713 static 714 uint32_t hal_rx_tlv_mpdu_len_err_get_li(void *hw_desc_addr) 715 { 716 struct rx_attention *rx_attn; 717 struct rx_mon_pkt_tlvs *rx_desc = 718 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 719 720 rx_attn = &rx_desc->attn_tlv.rx_attn; 721 722 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR); 723 } 724 725 static 726 uint32_t hal_rx_tlv_mpdu_fcs_err_get_li(void *hw_desc_addr) 727 { 728 struct rx_attention *rx_attn; 729 struct rx_mon_pkt_tlvs *rx_desc = 730 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 731 732 rx_attn = &rx_desc->attn_tlv.rx_attn; 733 734 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR); 735 } 736 737 #ifdef NO_RX_PKT_HDR_TLV 738 static uint8_t *hal_rx_desc_get_80211_hdr_li(void *hw_desc_addr) 739 { 740 uint8_t *rx_pkt_hdr; 741 struct rx_mon_pkt_tlvs *rx_desc = 742 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 743 744 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 745 746 return rx_pkt_hdr; 747 } 748 #else 749 static uint8_t *hal_rx_desc_get_80211_hdr_li(void *hw_desc_addr) 750 { 751 uint8_t *rx_pkt_hdr; 752 753 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 754 755 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 756 757 return rx_pkt_hdr; 758 } 759 #endif 760 761 static uint32_t hal_rx_hw_desc_mpdu_user_id_li(void *hw_desc_addr) 762 { 763 struct rx_mon_pkt_tlvs *rx_desc = 764 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 765 uint32_t user_id; 766 767 user_id = HAL_RX_GET_USER_TLV32_USERID( 768 &rx_desc->mpdu_start_tlv); 769 770 return user_id; 771 } 772 773 /** 774 * hal_rx_msdu_start_msdu_len_set_li(): API to set the MSDU length 775 * from rx_msdu_start TLV 776 * 777 * @buf: pointer to the start of RX PKT TLV headers 778 * @len: msdu length 779 * 780 * Return: none 781 */ 782 static inline void 783 hal_rx_msdu_start_msdu_len_set_li(uint8_t *buf, uint32_t len) 784 { 785 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 786 struct rx_msdu_start *msdu_start = 787 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 788 void *wrd1; 789 790 wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET; 791 *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK); 792 *(uint32_t *)wrd1 |= len; 793 } 794 795 /* 796 * hal_rx_tlv_bw_get_li(): API to get the Bandwidth 797 * Interval from rx_msdu_start 798 * 799 * @buf: pointer to the start of RX PKT TLV header 800 * Return: uint32_t(bw) 801 */ 802 static inline uint32_t hal_rx_tlv_bw_get_li(uint8_t *buf) 803 { 804 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 805 struct rx_msdu_start *msdu_start = 806 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 807 uint32_t bw; 808 809 bw = HAL_RX_MSDU_START_BW_GET(msdu_start); 810 811 return bw; 812 } 813 814 /* 815 * hal_rx_tlv_get_freq_li(): API to get the frequency of operating channel 816 * from rx_msdu_start 817 * 818 * @buf: pointer to the start of RX PKT TLV header 819 * Return: uint32_t(frequency) 820 */ 821 static inline uint32_t 822 hal_rx_tlv_get_freq_li(uint8_t *buf) 823 { 824 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 825 struct rx_msdu_start *msdu_start = 826 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 827 uint32_t freq; 828 829 freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 830 831 return freq; 832 } 833 834 /** 835 * hal_rx_tlv_sgi_get_li(): API to get the Short Gaurd 836 * Interval from rx_msdu_start TLV 837 * 838 * @buf: pointer to the start of RX PKT TLV headers 839 * Return: uint32_t(sgi) 840 */ 841 static inline uint32_t 842 hal_rx_tlv_sgi_get_li(uint8_t *buf) 843 { 844 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 845 struct rx_msdu_start *msdu_start = 846 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 847 uint32_t sgi; 848 849 sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start); 850 851 return sgi; 852 } 853 854 /** 855 * hal_rx_tlv_rate_mcs_get_li(): API to get the MCS rate 856 * from rx_msdu_start TLV 857 * 858 * @buf: pointer to the start of RX PKT TLV headers 859 * Return: uint32_t(rate_mcs) 860 */ 861 static inline uint32_t 862 hal_rx_tlv_rate_mcs_get_li(uint8_t *buf) 863 { 864 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 865 struct rx_msdu_start *msdu_start = 866 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 867 uint32_t rate_mcs; 868 869 rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start); 870 871 return rate_mcs; 872 } 873 874 /* 875 * hal_rx_tlv_get_pkt_type_li(): API to get the pkt type 876 * from rx_msdu_start 877 * 878 * @buf: pointer to the start of RX PKT TLV header 879 * Return: uint32_t(pkt type) 880 */ 881 882 static inline uint32_t hal_rx_tlv_get_pkt_type_li(uint8_t *buf) 883 { 884 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 885 struct rx_msdu_start *msdu_start = 886 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 887 uint32_t pkt_type; 888 889 pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start); 890 891 return pkt_type; 892 } 893 894 /** 895 * hal_rx_tlv_mic_err_get_li(): API to get the MIC ERR 896 * from rx_mpdu_end TLV 897 * 898 * @buf: pointer to the start of RX PKT TLV headers 899 * Return: uint32_t(mic_err) 900 */ 901 static inline uint32_t 902 hal_rx_tlv_mic_err_get_li(uint8_t *buf) 903 { 904 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 905 struct rx_mpdu_end *mpdu_end = 906 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 907 uint32_t mic_err; 908 909 mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end); 910 911 return mic_err; 912 } 913 914 /** 915 * hal_rx_tlv_decrypt_err_get_li(): API to get the Decrypt ERR 916 * from rx_mpdu_end TLV 917 * 918 * @buf: pointer to the start of RX PKT TLV headers 919 * Return: uint32_t(decrypt_err) 920 */ 921 static inline uint32_t 922 hal_rx_tlv_decrypt_err_get_li(uint8_t *buf) 923 { 924 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 925 struct rx_mpdu_end *mpdu_end = 926 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 927 uint32_t decrypt_err; 928 929 decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end); 930 931 return decrypt_err; 932 } 933 934 /* 935 * hal_rx_tlv_first_mpdu_get_li(): get fist_mpdu bit from rx attention 936 * @buf: pointer to rx_pkt_tlvs 937 * 938 * reutm: uint32_t(first_msdu) 939 */ 940 static inline uint32_t 941 hal_rx_tlv_first_mpdu_get_li(uint8_t *buf) 942 { 943 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 944 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 945 uint32_t first_mpdu; 946 947 first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn); 948 949 return first_mpdu; 950 } 951 952 /* 953 * hal_rx_msdu_get_keyid_li(): API to get the key id if the decrypted packet 954 * from rx_msdu_end 955 * 956 * @buf: pointer to the start of RX PKT TLV header 957 * Return: uint32_t(key id) 958 */ 959 static inline uint8_t 960 hal_rx_msdu_get_keyid_li(uint8_t *buf) 961 { 962 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 963 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 964 uint32_t keyid_octet; 965 966 keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end); 967 968 return keyid_octet & 0x3; 969 } 970 971 /* 972 * hal_rx_tlv_get_is_decrypted_li(): API to get the decrypt status of the 973 * packet from rx_attention 974 * 975 * @buf: pointer to the start of RX PKT TLV header 976 * Return: uint32_t(decryt status) 977 */ 978 static inline uint32_t 979 hal_rx_tlv_get_is_decrypted_li(uint8_t *buf) 980 { 981 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 982 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 983 uint32_t is_decrypt = 0; 984 uint32_t decrypt_status; 985 986 decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn); 987 988 if (!decrypt_status) 989 is_decrypt = 1; 990 991 return is_decrypt; 992 } 993 994 /** 995 * hal_rx_msdu_reo_dst_ind_get_li: Gets the REO 996 * destination ring ID from the msdu desc info 997 * 998 * @ hal_soc_hdl : HAL version of the SOC pointer 999 * @msdu_link_desc : Opaque cookie pointer used by HAL to get to 1000 * the current descriptor 1001 * 1002 * Return: dst_ind (REO destination ring ID) 1003 */ 1004 static inline uint32_t 1005 hal_rx_msdu_reo_dst_ind_get_li(hal_soc_handle_t hal_soc_hdl, 1006 void *msdu_link_desc) 1007 { 1008 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1009 struct rx_msdu_details *msdu_details; 1010 struct rx_msdu_desc_info *msdu_desc_info; 1011 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 1012 uint32_t dst_ind; 1013 1014 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1015 1016 /* The first msdu in the link should exsist */ 1017 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0], 1018 hal_soc); 1019 dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info); 1020 return dst_ind; 1021 } 1022 1023 static inline void 1024 hal_mpdu_desc_info_set_li(hal_soc_handle_t hal_soc_hdl, 1025 void *mpdu_desc, uint32_t seq_no) 1026 { 1027 struct rx_mpdu_desc_info *mpdu_desc_info = 1028 (struct rx_mpdu_desc_info *)mpdu_desc; 1029 1030 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1031 MSDU_COUNT, 0x1); 1032 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1033 MPDU_SEQUENCE_NUMBER, seq_no); 1034 /* unset frag bit */ 1035 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1036 FRAGMENT_FLAG, 0x0); 1037 /* set sa/da valid bits */ 1038 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1039 SA_IS_VALID, 0x1); 1040 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1041 DA_IS_VALID, 0x1); 1042 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1043 RAW_MPDU, 0x0); 1044 } 1045 1046 static inline void 1047 hal_msdu_desc_info_set_li(hal_soc_handle_t hal_soc_hdl, 1048 void *msdu_desc, uint32_t dst_ind, 1049 uint32_t nbuf_len) 1050 { 1051 struct rx_msdu_desc_info *msdu_desc_info = 1052 (struct rx_msdu_desc_info *)msdu_desc; 1053 1054 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1055 FIRST_MSDU_IN_MPDU_FLAG, 1); 1056 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1057 LAST_MSDU_IN_MPDU_FLAG, 1); 1058 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1059 MSDU_CONTINUATION, 0x0); 1060 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1061 REO_DESTINATION_INDICATION, 1062 dst_ind); 1063 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1064 MSDU_LENGTH, nbuf_len); 1065 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1066 SA_IS_VALID, 1); 1067 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1068 DA_IS_VALID, 1); 1069 } 1070 1071 static inline 1072 uint8_t *hal_get_reo_ent_desc_qdesc_addr_li(uint8_t *desc) 1073 { 1074 return desc + REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET; 1075 } 1076 1077 static inline 1078 void hal_set_reo_ent_desc_reo_dest_ind_li(uint8_t *desc, uint32_t dst_ind) 1079 { 1080 HAL_RX_FLD_SET(desc, REO_ENTRANCE_RING_5, 1081 REO_DESTINATION_INDICATION, dst_ind); 1082 } 1083 1084 static inline void 1085 hal_rx_wbm_rel_buf_paddr_get_li(hal_ring_desc_t rx_desc, 1086 struct hal_buf_info *buf_info) 1087 { 1088 struct wbm_release_ring *wbm_rel_ring = 1089 (struct wbm_release_ring *)rx_desc; 1090 1091 buf_info->paddr = 1092 (HAL_RX_WBM_BUF_ADDR_31_0_GET(wbm_rel_ring) | 1093 ((uint64_t)(HAL_RX_WBM_BUF_ADDR_39_32_GET(wbm_rel_ring)) << 32)); 1094 1095 buf_info->sw_cookie = HAL_RX_WBM_BUF_COOKIE_GET(wbm_rel_ring); 1096 } 1097 1098 static QDF_STATUS hal_reo_status_update_li(hal_soc_handle_t hal_soc_hdl, 1099 hal_ring_desc_t reo_desc, 1100 void *st_handle, 1101 uint32_t tlv, int *num_ref) 1102 { 1103 union hal_reo_status *reo_status_ref; 1104 1105 reo_status_ref = (union hal_reo_status *)st_handle; 1106 1107 switch (tlv) { 1108 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1109 hal_reo_queue_stats_status_li(reo_desc, 1110 &reo_status_ref->queue_status, 1111 hal_soc_hdl); 1112 *num_ref = reo_status_ref->queue_status.header.cmd_num; 1113 break; 1114 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1115 hal_reo_flush_queue_status_li(reo_desc, 1116 &reo_status_ref->fl_queue_status, 1117 hal_soc_hdl); 1118 *num_ref = reo_status_ref->fl_queue_status.header.cmd_num; 1119 break; 1120 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1121 hal_reo_flush_cache_status_li(reo_desc, 1122 &reo_status_ref->fl_cache_status, 1123 hal_soc_hdl); 1124 *num_ref = reo_status_ref->fl_cache_status.header.cmd_num; 1125 break; 1126 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1127 hal_reo_unblock_cache_status_li( 1128 reo_desc, hal_soc_hdl, 1129 &reo_status_ref->unblk_cache_status); 1130 *num_ref = reo_status_ref->unblk_cache_status.header.cmd_num; 1131 break; 1132 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1133 hal_reo_flush_timeout_list_status_li( 1134 reo_desc, 1135 &reo_status_ref->fl_timeout_status, 1136 hal_soc_hdl); 1137 *num_ref = reo_status_ref->fl_timeout_status.header.cmd_num; 1138 break; 1139 case HAL_REO_DESC_THRES_STATUS_TLV: 1140 hal_reo_desc_thres_reached_status_li( 1141 reo_desc, 1142 &reo_status_ref->thres_status, 1143 hal_soc_hdl); 1144 *num_ref = reo_status_ref->thres_status.header.cmd_num; 1145 break; 1146 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1147 hal_reo_rx_update_queue_status_li( 1148 reo_desc, 1149 &reo_status_ref->rx_queue_status, 1150 hal_soc_hdl); 1151 *num_ref = reo_status_ref->rx_queue_status.header.cmd_num; 1152 break; 1153 default: 1154 QDF_TRACE(QDF_MODULE_ID_DP_REO, QDF_TRACE_LEVEL_WARN, 1155 "hal_soc %pK: no handler for TLV:%d", 1156 hal_soc_hdl, tlv); 1157 return QDF_STATUS_E_FAILURE; 1158 } /* switch */ 1159 1160 return QDF_STATUS_SUCCESS; 1161 } 1162 1163 /** 1164 * hal_get_idle_link_bm_id_li() - Get idle link BM id from chid_id 1165 * @chip_id: mlo chip_id 1166 * 1167 * Returns: RBM ID 1168 */ 1169 static uint8_t hal_get_idle_link_bm_id_li(uint8_t chip_id) 1170 { 1171 return WBM_IDLE_DESC_LIST; 1172 } 1173 1174 /** 1175 * hal_hw_txrx_default_ops_attach_li() - Attach the default hal ops for 1176 * lithium chipsets. 1177 * @hal_soc_hdl: HAL soc handle 1178 * 1179 * Return: None 1180 */ 1181 void hal_hw_txrx_default_ops_attach_li(struct hal_soc *hal_soc) 1182 { 1183 hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_li; 1184 hal_soc->ops->hal_get_rx_max_ba_window = 1185 hal_get_rx_max_ba_window_li; 1186 hal_soc->ops->hal_set_link_desc_addr = hal_set_link_desc_addr_li; 1187 hal_soc->ops->hal_tx_init_data_ring = hal_tx_init_data_ring_li; 1188 hal_soc->ops->hal_get_ba_aging_timeout = hal_get_ba_aging_timeout_li; 1189 hal_soc->ops->hal_set_ba_aging_timeout = hal_set_ba_aging_timeout_li; 1190 hal_soc->ops->hal_get_reo_reg_base_offset = 1191 hal_get_reo_reg_base_offset_li; 1192 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_li; 1193 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 1194 hal_rx_msdu_is_wlan_mcast_generic_li; 1195 hal_soc->ops->hal_rx_tlv_decap_format_get = 1196 hal_rx_tlv_decap_format_get_li; 1197 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_li; 1198 hal_soc->ops->hal_rx_tlv_get_offload_info = 1199 hal_rx_tlv_get_offload_info_li; 1200 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 1201 hal_rx_attn_phy_ppdu_id_get_li; 1202 hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_attn_msdu_done_get_li; 1203 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1204 hal_rx_msdu_start_msdu_len_get_li; 1205 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1206 hal_rx_get_frame_ctrl_field_li; 1207 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_li; 1208 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_li; 1209 1210 hal_soc->ops->hal_rx_reo_buf_paddr_get = hal_rx_reo_buf_paddr_get_li; 1211 hal_soc->ops->hal_rx_msdu_link_desc_set = hal_rx_msdu_link_desc_set_li; 1212 hal_soc->ops->hal_rx_buf_cookie_rbm_get = hal_rx_buf_cookie_rbm_get_li; 1213 hal_soc->ops->hal_rx_ret_buf_manager_get = 1214 hal_rx_ret_buf_manager_get_li; 1215 hal_soc->ops->hal_rxdma_buff_addr_info_set = 1216 hal_rxdma_buff_addr_info_set_li; 1217 hal_soc->ops->hal_rx_msdu_flags_get = hal_rx_msdu_flags_get_li; 1218 hal_soc->ops->hal_rx_get_reo_error_code = hal_rx_get_reo_error_code_li; 1219 hal_soc->ops->hal_gen_reo_remap_val = 1220 hal_gen_reo_remap_val_generic_li; 1221 hal_soc->ops->hal_rx_tlv_csum_err_get = 1222 hal_rx_tlv_csum_err_get_li; 1223 hal_soc->ops->hal_rx_mpdu_desc_info_get = 1224 hal_rx_mpdu_desc_info_get_li; 1225 hal_soc->ops->hal_rx_err_status_get = hal_rx_err_status_get_li; 1226 hal_soc->ops->hal_rx_reo_buf_type_get = hal_rx_reo_buf_type_get_li; 1227 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_li; 1228 hal_soc->ops->hal_rx_wbm_err_src_get = hal_rx_wbm_err_src_get_li; 1229 hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get = 1230 hal_rx_wbm_rel_buf_paddr_get_li; 1231 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1232 hal_rx_priv_info_set_in_tlv_li; 1233 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1234 hal_rx_priv_info_get_from_tlv_li; 1235 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1236 hal_rx_mpdu_info_ampdu_flag_get_li; 1237 hal_soc->ops->hal_rx_tlv_mpdu_len_err_get = 1238 hal_rx_tlv_mpdu_len_err_get_li; 1239 hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get = 1240 hal_rx_tlv_mpdu_fcs_err_get_li; 1241 hal_soc->ops->hal_reo_send_cmd = hal_reo_send_cmd_li; 1242 hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags = 1243 hal_rx_tlv_get_pkt_capture_flags_li; 1244 hal_soc->ops->hal_rx_desc_get_80211_hdr = hal_rx_desc_get_80211_hdr_li; 1245 hal_soc->ops->hal_rx_hw_desc_mpdu_user_id = 1246 hal_rx_hw_desc_mpdu_user_id_li; 1247 hal_soc->ops->hal_reo_qdesc_setup = hal_reo_qdesc_setup_li; 1248 hal_soc->ops->hal_rx_tlv_msdu_len_set = 1249 hal_rx_msdu_start_msdu_len_set_li; 1250 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_li; 1251 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_li; 1252 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_li; 1253 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_li; 1254 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_li; 1255 hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_li; 1256 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_li; 1257 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1258 hal_rx_tlv_decrypt_err_get_li; 1259 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_li; 1260 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 1261 hal_rx_tlv_get_is_decrypted_li; 1262 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_li; 1263 hal_soc->ops->hal_rx_msdu_reo_dst_ind_get = 1264 hal_rx_msdu_reo_dst_ind_get_li; 1265 hal_soc->ops->hal_msdu_desc_info_set = hal_msdu_desc_info_set_li; 1266 hal_soc->ops->hal_mpdu_desc_info_set = hal_mpdu_desc_info_set_li; 1267 hal_soc->ops->hal_reo_status_update = hal_reo_status_update_li; 1268 hal_soc->ops->hal_get_tlv_hdr_size = hal_get_tlv_hdr_size_li; 1269 hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr = 1270 hal_get_reo_ent_desc_qdesc_addr_li; 1271 hal_soc->ops->hal_rx_get_qdesc_addr = hal_rx_get_qdesc_addr_li; 1272 hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind = 1273 hal_set_reo_ent_desc_reo_dest_ind_li; 1274 hal_soc->ops->hal_get_idle_link_bm_id = hal_get_idle_link_bm_id_li; 1275 } 1276