1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "hal_li_api.h" 21 #include "hal_li_hw_headers.h" 22 #include "hal_li_reo.h" 23 24 #include "hal_rx.h" 25 #include "hal_li_rx.h" 26 #include "hal_tx.h" 27 #include <hal_api_mon.h> 28 29 static uint16_t hal_get_rx_max_ba_window_li(int tid) 30 { 31 return HAL_RX_BA_WINDOW_256; 32 } 33 34 static uint32_t hal_get_reo_qdesc_size_li(uint32_t ba_window_size, int tid) 35 { 36 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 37 * NON_QOS_TID until HW issues are resolved. 38 */ 39 if (tid != HAL_NON_QOS_TID) 40 ba_window_size = hal_get_rx_max_ba_window_li(tid); 41 42 /* Return descriptor size corresponding to window size of 2 since 43 * we set ba_window_size to 2 while setting up REO descriptors as 44 * a WAR to get 2k jump exception aggregates are received without 45 * a BA session. 46 */ 47 if (ba_window_size <= 1) { 48 if (tid != HAL_NON_QOS_TID) 49 return sizeof(struct rx_reo_queue) + 50 sizeof(struct rx_reo_queue_ext); 51 else 52 return sizeof(struct rx_reo_queue); 53 } 54 55 if (ba_window_size <= 105) 56 return sizeof(struct rx_reo_queue) + 57 sizeof(struct rx_reo_queue_ext); 58 59 if (ba_window_size <= 210) 60 return sizeof(struct rx_reo_queue) + 61 (2 * sizeof(struct rx_reo_queue_ext)); 62 63 return sizeof(struct rx_reo_queue) + 64 (3 * sizeof(struct rx_reo_queue_ext)); 65 } 66 67 void hal_set_link_desc_addr_li(void *desc, uint32_t cookie, 68 qdf_dma_addr_t link_desc_paddr, 69 uint8_t bm_id) 70 { 71 uint32_t *buf_addr = (uint32_t *)desc; 72 73 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, 74 link_desc_paddr & 0xffffffff); 75 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 76 (uint64_t)link_desc_paddr >> 32); 77 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, RETURN_BUFFER_MANAGER, 78 bm_id); 79 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, 80 cookie); 81 } 82 83 void hal_tx_init_data_ring_li(hal_soc_handle_t hal_soc_hdl, 84 hal_ring_handle_t hal_ring_hdl) 85 { 86 uint8_t *desc_addr; 87 struct hal_srng_params srng_params; 88 uint32_t desc_size; 89 uint32_t num_desc; 90 91 hal_get_srng_params(hal_soc_hdl, hal_ring_hdl, &srng_params); 92 93 desc_addr = (uint8_t *)srng_params.ring_base_vaddr; 94 desc_size = sizeof(struct tcl_data_cmd); 95 num_desc = srng_params.num_entries; 96 97 while (num_desc) { 98 HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, 99 desc_size); 100 desc_addr += (desc_size + sizeof(struct tlv_32_hdr)); 101 num_desc--; 102 } 103 } 104 105 /** 106 * hal_rx_msdu_is_wlan_mcast_generic_li(): Check if the buffer is for multicast 107 * address 108 * @nbuf: Network buffer 109 * 110 * Returns: flag to indicate whether the nbuf has MC/BC address 111 */ 112 static uint32_t hal_rx_msdu_is_wlan_mcast_generic_li(qdf_nbuf_t nbuf) 113 { 114 uint8_t *buf = qdf_nbuf_data(nbuf); 115 116 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 117 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 118 119 return rx_attn->mcast_bcast; 120 } 121 122 /** 123 * hal_rx_tlv_decap_format_get_li() - Get packet decap format from the TLV 124 * @hw_desc_addr: rx tlv desc 125 * 126 * Return: pkt decap format 127 */ 128 static uint32_t hal_rx_tlv_decap_format_get_li(void *hw_desc_addr) 129 { 130 struct rx_msdu_start *rx_msdu_start; 131 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 132 133 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 134 135 return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); 136 } 137 138 /** 139 * hal_rx_dump_pkt_tlvs_li(): API to print all member elements of 140 * RX TLVs 141 * @hal_soc_hdl: hal_soc handle 142 * @buf: pointer the pkt buffer. 143 * @dbg_level: log level. 144 * 145 * Return: void 146 */ 147 static void hal_rx_dump_pkt_tlvs_li(hal_soc_handle_t hal_soc_hdl, 148 uint8_t *buf, uint8_t dbg_level) 149 { 150 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 151 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 152 struct rx_mpdu_start *mpdu_start = 153 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 154 struct rx_msdu_start *msdu_start = 155 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 156 struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 157 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 158 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 159 160 hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level); 161 hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc); 162 hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level); 163 hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level); 164 hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level); 165 hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level); 166 } 167 168 /** 169 * hal_rx_tlv_get_offload_info_li() - Get the offload info from TLV 170 * @rx_tlv: RX tlv start address in buffer 171 * @offload_info: Buffer to store the offload info 172 * 173 * Return: 0 on success, -EINVAL on failure. 174 */ 175 static int 176 hal_rx_tlv_get_offload_info_li(uint8_t *rx_tlv, 177 struct hal_offload_info *offload_info) 178 { 179 offload_info->flow_id = HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(rx_tlv); 180 offload_info->ipv6_proto = HAL_RX_TLV_GET_IPV6(rx_tlv); 181 offload_info->lro_eligible = HAL_RX_TLV_GET_LRO_ELIGIBLE(rx_tlv); 182 offload_info->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(rx_tlv); 183 184 if (offload_info->tcp_proto) { 185 offload_info->tcp_pure_ack = 186 HAL_RX_TLV_GET_TCP_PURE_ACK(rx_tlv); 187 offload_info->tcp_offset = HAL_RX_TLV_GET_TCP_OFFSET(rx_tlv); 188 offload_info->tcp_win = HAL_RX_TLV_GET_TCP_WIN(rx_tlv); 189 offload_info->tcp_seq_num = HAL_RX_TLV_GET_TCP_SEQ(rx_tlv); 190 offload_info->tcp_ack_num = HAL_RX_TLV_GET_TCP_ACK(rx_tlv); 191 } 192 return 0; 193 } 194 195 /** 196 * hal_rx_attn_phy_ppdu_id_get_li(): get phy_ppdu_id value 197 * from rx attention 198 * @buf: pointer to rx_pkt_tlvs 199 * 200 * Return: phy_ppdu_id 201 */ 202 static uint16_t hal_rx_attn_phy_ppdu_id_get_li(uint8_t *buf) 203 { 204 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 205 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 206 uint16_t phy_ppdu_id; 207 208 phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn); 209 210 return phy_ppdu_id; 211 } 212 213 /** 214 * hal_rx_msdu_start_msdu_len_get_li(): API to get the MSDU length 215 * from rx_msdu_start TLV 216 * 217 * @buf: pointer to the start of RX PKT TLV headers 218 * 219 * Return: msdu length 220 */ 221 static uint32_t hal_rx_msdu_start_msdu_len_get_li(uint8_t *buf) 222 { 223 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 224 struct rx_msdu_start *msdu_start = 225 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 226 uint32_t msdu_len; 227 228 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 229 230 return msdu_len; 231 } 232 233 /** 234 * hal_rx_get_proto_params_li() - Get l4 proto values from TLV 235 * @buf: rx tlv address 236 * @proto_params: Buffer to store proto parameters 237 * 238 * Return: 0 on success. 239 */ 240 static int hal_rx_get_proto_params_li(uint8_t *buf, void *proto_params) 241 { 242 struct hal_proto_params *param = 243 (struct hal_proto_params *)proto_params; 244 245 param->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(buf); 246 param->udp_proto = HAL_RX_TLV_GET_UDP_PROTO(buf); 247 param->ipv6_proto = HAL_RX_TLV_GET_IPV6(buf); 248 249 return 0; 250 } 251 252 /** 253 * hal_rx_get_l3_l4_offsets_li() - Get l3/l4 header offset from TLV 254 * @buf: rx tlv start address 255 * @l3_hdr_offset: buffer to store l3 offset 256 * @l4_hdr_offset: buffer to store l4 offset 257 * 258 * Return: 0 on success. 259 */ 260 static int hal_rx_get_l3_l4_offsets_li(uint8_t *buf, uint32_t *l3_hdr_offset, 261 uint32_t *l4_hdr_offset) 262 { 263 *l3_hdr_offset = HAL_RX_TLV_GET_IP_OFFSET(buf); 264 *l4_hdr_offset = HAL_RX_TLV_GET_TCP_OFFSET(buf); 265 266 return 0; 267 } 268 269 /** 270 * hal_rx_tlv_get_pn_num_li() - Get packet number from RX TLV 271 * @buf: rx tlv address 272 * @pn_num: buffer to store packet number 273 * 274 * Return: None 275 */ 276 static inline void hal_rx_tlv_get_pn_num_li(uint8_t *buf, uint64_t *pn_num) 277 { 278 struct rx_pkt_tlvs *rx_pkt_tlv = 279 (struct rx_pkt_tlvs *)buf; 280 struct rx_mpdu_info *rx_mpdu_info_details = 281 &rx_pkt_tlv->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 282 283 pn_num[0] = rx_mpdu_info_details->pn_31_0; 284 pn_num[0] |= 285 ((uint64_t)rx_mpdu_info_details->pn_63_32 << 32); 286 pn_num[1] = rx_mpdu_info_details->pn_95_64; 287 pn_num[1] |= 288 ((uint64_t)rx_mpdu_info_details->pn_127_96 << 32); 289 } 290 291 #ifdef NO_RX_PKT_HDR_TLV 292 /** 293 * hal_rx_pkt_hdr_get_li() - Get rx packet header start address. 294 * @buf: packet start address 295 * 296 * Return: packet data start address. 297 */ 298 static inline uint8_t *hal_rx_pkt_hdr_get_li(uint8_t *buf) 299 { 300 return buf + RX_PKT_TLVS_LEN; 301 } 302 #else 303 static inline uint8_t *hal_rx_pkt_hdr_get_li(uint8_t *buf) 304 { 305 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 306 307 return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr; 308 } 309 #endif 310 311 /** 312 * hal_rx_priv_info_set_in_tlv_li(): Save the private info to 313 * the reserved bytes of rx_tlv_hdr 314 * @buf: start of rx_tlv_hdr 315 * @priv_data: hal_wbm_err_desc_info structure 316 * @len: length of the private data 317 * Return: void 318 */ 319 static inline void 320 hal_rx_priv_info_set_in_tlv_li(uint8_t *buf, uint8_t *priv_data, 321 uint32_t len) 322 { 323 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 324 uint32_t copy_len = (len > RX_PADDING0_BYTES) ? 325 RX_PADDING0_BYTES : len; 326 327 qdf_mem_copy(pkt_tlvs->rx_padding0, priv_data, copy_len); 328 } 329 330 /** 331 * hal_rx_priv_info_get_from_tlv_li(): retrieve the private data from 332 * the reserved bytes of rx_tlv_hdr. 333 * @buf: start of rx_tlv_hdr 334 * @priv_data: hal_wbm_err_desc_info structure 335 * @len: length of the private data 336 * Return: void 337 */ 338 static inline void 339 hal_rx_priv_info_get_from_tlv_li(uint8_t *buf, uint8_t *priv_data, 340 uint32_t len) 341 { 342 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 343 uint32_t copy_len = (len > RX_PADDING0_BYTES) ? 344 RX_PADDING0_BYTES : len; 345 346 qdf_mem_copy(priv_data, pkt_tlvs->rx_padding0, copy_len); 347 } 348 349 /** 350 * hal_rx_get_tlv_size_generic_li() - Get rx packet tlv size 351 * @rx_pkt_tlv_size: TLV size for regular RX packets 352 * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets 353 * 354 * Return: size of rx pkt tlv before the actual data 355 */ 356 static void hal_rx_get_tlv_size_generic_li(uint16_t *rx_pkt_tlv_size, 357 uint16_t *rx_mon_pkt_tlv_size) 358 { 359 *rx_pkt_tlv_size = RX_PKT_TLVS_LEN; 360 *rx_mon_pkt_tlv_size = SIZE_OF_MONITOR_TLV; 361 } 362 363 /** 364 * hal_rx_wbm_err_src_get_li() - Get WBM error source from descriptor 365 * @ring_desc: ring descriptor 366 * 367 * Return: wbm error source 368 */ 369 uint32_t hal_rx_wbm_err_src_get_li(hal_ring_desc_t ring_desc) 370 { 371 return HAL_WBM2SW_RELEASE_SRC_GET(ring_desc); 372 } 373 374 /** 375 * hal_rx_ret_buf_manager_get_li() - Get return buffer manager from ring desc 376 * @ring_desc: ring descriptor 377 * 378 * Return: rbm 379 */ 380 uint8_t hal_rx_ret_buf_manager_get_li(hal_ring_desc_t ring_desc) 381 { 382 /* 383 * The following macro takes buf_addr_info as argument, 384 * but since buf_addr_info is the first field in ring_desc 385 * Hence the following call is OK 386 */ 387 return HAL_RX_BUF_RBM_GET(ring_desc); 388 } 389 390 /** 391 * hal_rx_reo_buf_paddr_get_li() - Gets the physical address and 392 * cookie from the REO destination ring element 393 * 394 * @rx_desc: Opaque cookie pointer used by HAL to get to 395 * the current descriptor 396 * @buf_info: structure to return the buffer information 397 * 398 * Return: void 399 */ 400 static void hal_rx_reo_buf_paddr_get_li(hal_ring_desc_t rx_desc, 401 struct hal_buf_info *buf_info) 402 { 403 struct reo_destination_ring *reo_ring = 404 (struct reo_destination_ring *)rx_desc; 405 406 buf_info->paddr = 407 (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) | 408 ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32)); 409 buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring); 410 } 411 412 /** 413 * hal_rx_msdu_link_desc_set_li() - Retrieves MSDU Link Descriptor to WBM 414 * 415 * @hal_soc_hdl: HAL version of the SOC pointer 416 * @src_srng_desc: void pointer to the WBM Release Ring descriptor 417 * @buf_addr_info: void pointer to the buffer_addr_info 418 * @bm_action: put in IDLE list or release to MSDU_LIST 419 * 420 * Return: void 421 */ 422 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 423 static void hal_rx_msdu_link_desc_set_li(hal_soc_handle_t hal_soc_hdl, 424 void *src_srng_desc, 425 hal_buff_addrinfo_t buf_addr_info, 426 uint8_t bm_action) 427 { 428 /* 429 * The offsets for fields used in this function are same in 430 * wbm_release_ring for Lithium and wbm_release_ring_tx 431 * for Beryllium. hence we can use wbm_release_ring directly. 432 */ 433 struct wbm_release_ring *wbm_rel_srng = 434 (struct wbm_release_ring *)src_srng_desc; 435 uint32_t addr_31_0; 436 uint8_t addr_39_32; 437 438 /* Structure copy !!! */ 439 wbm_rel_srng->released_buff_or_desc_addr_info = 440 *(struct buffer_addr_info *)buf_addr_info; 441 442 addr_31_0 = 443 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0; 444 addr_39_32 = 445 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32; 446 447 HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, 448 RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW); 449 HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, BM_ACTION, 450 bm_action); 451 HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, 452 BUFFER_OR_DESC_TYPE, 453 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC); 454 455 /* WBM error is indicated when any of the link descriptors given to 456 * WBM has a NULL address, and one those paths is the link descriptors 457 * released from host after processing RXDMA errors, 458 * or from Rx defrag path, and we want to add an assert here to ensure 459 * host is not releasing descriptors with NULL address. 460 */ 461 462 if (qdf_unlikely(!addr_31_0 && !addr_39_32)) { 463 hal_dump_wbm_rel_desc(src_srng_desc); 464 qdf_assert_always(0); 465 } 466 } 467 468 static 469 void hal_rx_buf_cookie_rbm_get_li(uint32_t *buf_addr_info_hdl, 470 hal_buf_info_t buf_info_hdl) 471 { 472 struct hal_buf_info *buf_info = 473 (struct hal_buf_info *)buf_info_hdl; 474 struct buffer_addr_info *buf_addr_info = 475 (struct buffer_addr_info *)buf_addr_info_hdl; 476 477 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 478 /* 479 * buffer addr info is the first member of ring desc, so the typecast 480 * can be done. 481 */ 482 buf_info->rbm = hal_rx_ret_buf_manager_get_li 483 ((hal_ring_desc_t)buf_addr_info); 484 } 485 486 /** 487 * hal_rx_msdu_list_get_li(): API to get the MSDU information 488 * from the MSDU link descriptor 489 * 490 * @hal_soc_hdl: HAL version of the SOC pointer 491 * @msdu_link_desc: Opaque pointer used by HAL to get to the 492 * MSDU link descriptor (struct rx_msdu_link) 493 * 494 * @hal_msdu_list: Return the list of MSDUs contained in this link descriptor 495 * 496 * @num_msdus: Number of MSDUs in the MPDU 497 * 498 * Return: void 499 */ 500 static inline void hal_rx_msdu_list_get_li(hal_soc_handle_t hal_soc_hdl, 501 void *msdu_link_desc, 502 void *hal_msdu_list, 503 uint16_t *num_msdus) 504 { 505 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 506 struct rx_msdu_details *msdu_details; 507 struct rx_msdu_desc_info *msdu_desc_info; 508 struct hal_rx_msdu_list *msdu_list = hal_msdu_list; 509 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 510 int i; 511 struct hal_buf_info buf_info; 512 513 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 514 515 hal_debug("msdu_link=%pK msdu_details=%pK", msdu_link, msdu_details); 516 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 517 /* num_msdus received in mpdu descriptor may be incorrect 518 * sometimes due to HW issue. Check msdu buffer address also 519 */ 520 if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET( 521 &msdu_details[i].buffer_addr_info_details) == 0)) 522 break; 523 if (HAL_RX_BUFFER_ADDR_31_0_GET( 524 &msdu_details[i].buffer_addr_info_details) == 0) { 525 /* set the last msdu bit in the prev msdu_desc_info */ 526 msdu_desc_info = 527 hal_rx_msdu_desc_info_get_ptr 528 (&msdu_details[i - 1], hal_soc); 529 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 530 break; 531 } 532 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 533 hal_soc); 534 535 /* set first MSDU bit or the last MSDU bit */ 536 if (!i) 537 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 538 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 539 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 540 541 msdu_list->msdu_info[i].msdu_flags = 542 hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info); 543 msdu_list->msdu_info[i].msdu_len = 544 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 545 546 /* addr field in buf_info will not be valid */ 547 hal_rx_buf_cookie_rbm_get_li( 548 (uint32_t *) 549 &msdu_details[i].buffer_addr_info_details, 550 &buf_info); 551 msdu_list->sw_cookie[i] = buf_info.sw_cookie; 552 msdu_list->rbm[i] = buf_info.rbm; 553 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 554 &msdu_details[i].buffer_addr_info_details) | 555 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 556 &msdu_details[i].buffer_addr_info_details) << 32; 557 hal_debug("i=%d sw_cookie=%d", i, msdu_list->sw_cookie[i]); 558 } 559 *num_msdus = i; 560 } 561 562 /* 563 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 564 * rxdma ring entry. 565 * @rxdma_entry: descriptor entry 566 * @paddr: physical address of nbuf data pointer. 567 * @cookie: SW cookie used as a index to SW rx desc. 568 * @manager: who owns the nbuf (host, NSS, etc...). 569 * 570 */ 571 static void hal_rxdma_buff_addr_info_set_li(void *rxdma_entry, 572 qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager) 573 { 574 uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff); 575 uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32; 576 577 HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo); 578 HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi); 579 HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie); 580 HAL_RXDMA_MANAGER_SET(rxdma_entry, manager); 581 } 582 583 /** 584 * hal_rx_get_reo_error_code_li() - Get REO error code from ring desc 585 * @rx_desc: rx descriptor 586 * 587 * Return: REO error code 588 */ 589 static uint32_t hal_rx_get_reo_error_code_li(hal_ring_desc_t rx_desc) 590 { 591 struct reo_destination_ring *reo_desc = 592 (struct reo_destination_ring *)rx_desc; 593 594 return HAL_RX_REO_ERROR_GET(reo_desc); 595 } 596 597 /** 598 * hal_gen_reo_remap_val_generic_li() - Generate the reo map value 599 * @remap_reg: remap register 600 * @ix0_map: mapping values for reo 601 * 602 * Return: IX0 reo remap register value to be written 603 */ 604 static uint32_t 605 hal_gen_reo_remap_val_generic_li(enum hal_reo_remap_reg remap_reg, 606 uint8_t *ix0_map) 607 { 608 uint32_t ix_val = 0; 609 610 switch (remap_reg) { 611 case HAL_REO_REMAP_REG_IX0: 612 ix_val = HAL_REO_REMAP_IX0(ix0_map[0], 0) | 613 HAL_REO_REMAP_IX0(ix0_map[1], 1) | 614 HAL_REO_REMAP_IX0(ix0_map[2], 2) | 615 HAL_REO_REMAP_IX0(ix0_map[3], 3) | 616 HAL_REO_REMAP_IX0(ix0_map[4], 4) | 617 HAL_REO_REMAP_IX0(ix0_map[5], 5) | 618 HAL_REO_REMAP_IX0(ix0_map[6], 6) | 619 HAL_REO_REMAP_IX0(ix0_map[7], 7); 620 break; 621 case HAL_REO_REMAP_REG_IX2: 622 ix_val = HAL_REO_REMAP_IX2(ix0_map[0], 16) | 623 HAL_REO_REMAP_IX2(ix0_map[1], 17) | 624 HAL_REO_REMAP_IX2(ix0_map[2], 18) | 625 HAL_REO_REMAP_IX2(ix0_map[3], 19) | 626 HAL_REO_REMAP_IX2(ix0_map[4], 20) | 627 HAL_REO_REMAP_IX2(ix0_map[5], 21) | 628 HAL_REO_REMAP_IX2(ix0_map[6], 22) | 629 HAL_REO_REMAP_IX2(ix0_map[7], 23); 630 break; 631 default: 632 break; 633 } 634 635 return ix_val; 636 } 637 638 /** 639 * hal_rx_tlv_csum_err_get_li() - Get IP and tcp-udp checksum fail flag 640 * @rx_tlv_hdr: start address of rx_tlv_hdr 641 * @ip_csum_err: buffer to return ip_csum_fail flag 642 * @tcp_udp_csum_err: placeholder to return tcp-udp checksum fail flag 643 * 644 * Return: None 645 */ 646 static inline void 647 hal_rx_tlv_csum_err_get_li(uint8_t *rx_tlv_hdr, uint32_t *ip_csum_err, 648 uint32_t *tcp_udp_csum_err) 649 { 650 *ip_csum_err = hal_rx_attn_ip_cksum_fail_get(rx_tlv_hdr); 651 *tcp_udp_csum_err = hal_rx_attn_tcp_udp_cksum_fail_get(rx_tlv_hdr); 652 } 653 654 static 655 void hal_rx_tlv_get_pkt_capture_flags_li(uint8_t *rx_tlv_pkt_hdr, 656 struct hal_rx_pkt_capture_flags *flags) 657 { 658 struct rx_pkt_tlvs *rx_tlv_hdr = (struct rx_pkt_tlvs *)rx_tlv_pkt_hdr; 659 struct rx_attention *rx_attn = &rx_tlv_hdr->attn_tlv.rx_attn; 660 struct rx_mpdu_start *mpdu_start = 661 &rx_tlv_hdr->mpdu_start_tlv.rx_mpdu_start; 662 struct rx_mpdu_end *mpdu_end = &rx_tlv_hdr->mpdu_end_tlv.rx_mpdu_end; 663 struct rx_msdu_start *msdu_start = 664 &rx_tlv_hdr->msdu_start_tlv.rx_msdu_start; 665 666 flags->encrypt_type = mpdu_start->rx_mpdu_info_details.encrypt_type; 667 flags->fcs_err = mpdu_end->fcs_err; 668 flags->fragment_flag = rx_attn->fragment_flag; 669 flags->chan_freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 670 flags->rssi_comb = HAL_RX_MSDU_START_RSSI_GET(msdu_start); 671 flags->tsft = msdu_start->ppdu_start_timestamp; 672 } 673 674 static uint8_t hal_rx_err_status_get_li(hal_ring_desc_t rx_desc) 675 { 676 return HAL_RX_ERROR_STATUS_GET(rx_desc); 677 } 678 679 static uint8_t hal_rx_reo_buf_type_get_li(hal_ring_desc_t rx_desc) 680 { 681 return HAL_RX_REO_BUF_TYPE_GET(rx_desc); 682 } 683 684 static inline bool 685 hal_rx_mpdu_info_ampdu_flag_get_li(uint8_t *buf) 686 { 687 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 688 struct rx_mpdu_start *mpdu_start = 689 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 690 691 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 692 bool ampdu_flag; 693 694 ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info); 695 696 return ampdu_flag; 697 } 698 699 static 700 uint32_t hal_rx_tlv_mpdu_len_err_get_li(void *hw_desc_addr) 701 { 702 struct rx_attention *rx_attn; 703 struct rx_mon_pkt_tlvs *rx_desc = 704 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 705 706 rx_attn = &rx_desc->attn_tlv.rx_attn; 707 708 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR); 709 } 710 711 static 712 uint32_t hal_rx_tlv_mpdu_fcs_err_get_li(void *hw_desc_addr) 713 { 714 struct rx_attention *rx_attn; 715 struct rx_mon_pkt_tlvs *rx_desc = 716 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 717 718 rx_attn = &rx_desc->attn_tlv.rx_attn; 719 720 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR); 721 } 722 723 #ifdef NO_RX_PKT_HDR_TLV 724 static uint8_t *hal_rx_desc_get_80211_hdr_li(void *hw_desc_addr) 725 { 726 uint8_t *rx_pkt_hdr; 727 struct rx_mon_pkt_tlvs *rx_desc = 728 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 729 730 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 731 732 return rx_pkt_hdr; 733 } 734 #else 735 static uint8_t *hal_rx_desc_get_80211_hdr_li(void *hw_desc_addr) 736 { 737 uint8_t *rx_pkt_hdr; 738 739 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 740 741 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 742 743 return rx_pkt_hdr; 744 } 745 #endif 746 747 static uint32_t hal_rx_hw_desc_mpdu_user_id_li(void *hw_desc_addr) 748 { 749 struct rx_mon_pkt_tlvs *rx_desc = 750 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 751 uint32_t user_id; 752 753 user_id = HAL_RX_GET_USER_TLV32_USERID( 754 &rx_desc->mpdu_start_tlv); 755 756 return user_id; 757 } 758 759 /** 760 * hal_rx_msdu_start_msdu_len_set_li(): API to set the MSDU length 761 * from rx_msdu_start TLV 762 * 763 * @buf: pointer to the start of RX PKT TLV headers 764 * @len: msdu length 765 * 766 * Return: none 767 */ 768 static inline void 769 hal_rx_msdu_start_msdu_len_set_li(uint8_t *buf, uint32_t len) 770 { 771 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 772 struct rx_msdu_start *msdu_start = 773 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 774 void *wrd1; 775 776 wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET; 777 *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK); 778 *(uint32_t *)wrd1 |= len; 779 } 780 781 /* 782 * hal_rx_tlv_bw_get_li(): API to get the Bandwidth 783 * Interval from rx_msdu_start 784 * 785 * @buf: pointer to the start of RX PKT TLV header 786 * Return: uint32_t(bw) 787 */ 788 static inline uint32_t hal_rx_tlv_bw_get_li(uint8_t *buf) 789 { 790 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 791 struct rx_msdu_start *msdu_start = 792 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 793 uint32_t bw; 794 795 bw = HAL_RX_MSDU_START_BW_GET(msdu_start); 796 797 return bw; 798 } 799 800 /* 801 * hal_rx_tlv_get_freq_li(): API to get the frequency of operating channel 802 * from rx_msdu_start 803 * 804 * @buf: pointer to the start of RX PKT TLV header 805 * Return: uint32_t(frequency) 806 */ 807 static inline uint32_t 808 hal_rx_tlv_get_freq_li(uint8_t *buf) 809 { 810 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 811 struct rx_msdu_start *msdu_start = 812 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 813 uint32_t freq; 814 815 freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 816 817 return freq; 818 } 819 820 /** 821 * hal_rx_tlv_sgi_get_li(): API to get the Short Guard 822 * Interval from rx_msdu_start TLV 823 * 824 * @buf: pointer to the start of RX PKT TLV headers 825 * Return: uint32_t(sgi) 826 */ 827 static inline uint32_t 828 hal_rx_tlv_sgi_get_li(uint8_t *buf) 829 { 830 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 831 struct rx_msdu_start *msdu_start = 832 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 833 uint32_t sgi; 834 835 sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start); 836 837 return sgi; 838 } 839 840 /** 841 * hal_rx_tlv_rate_mcs_get_li(): API to get the MCS rate 842 * from rx_msdu_start TLV 843 * 844 * @buf: pointer to the start of RX PKT TLV headers 845 * Return: uint32_t(rate_mcs) 846 */ 847 static inline uint32_t 848 hal_rx_tlv_rate_mcs_get_li(uint8_t *buf) 849 { 850 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 851 struct rx_msdu_start *msdu_start = 852 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 853 uint32_t rate_mcs; 854 855 rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start); 856 857 return rate_mcs; 858 } 859 860 /* 861 * hal_rx_tlv_get_pkt_type_li(): API to get the pkt type 862 * from rx_msdu_start 863 * 864 * @buf: pointer to the start of RX PKT TLV header 865 * Return: uint32_t(pkt type) 866 */ 867 868 static inline uint32_t hal_rx_tlv_get_pkt_type_li(uint8_t *buf) 869 { 870 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 871 struct rx_msdu_start *msdu_start = 872 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 873 uint32_t pkt_type; 874 875 pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start); 876 877 return pkt_type; 878 } 879 880 /** 881 * hal_rx_tlv_mic_err_get_li(): API to get the MIC ERR 882 * from rx_mpdu_end TLV 883 * 884 * @buf: pointer to the start of RX PKT TLV headers 885 * Return: uint32_t(mic_err) 886 */ 887 static inline uint32_t 888 hal_rx_tlv_mic_err_get_li(uint8_t *buf) 889 { 890 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 891 struct rx_mpdu_end *mpdu_end = 892 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 893 uint32_t mic_err; 894 895 mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end); 896 897 return mic_err; 898 } 899 900 /** 901 * hal_rx_tlv_decrypt_err_get_li(): API to get the Decrypt ERR 902 * from rx_mpdu_end TLV 903 * 904 * @buf: pointer to the start of RX PKT TLV headers 905 * Return: uint32_t(decrypt_err) 906 */ 907 static inline uint32_t 908 hal_rx_tlv_decrypt_err_get_li(uint8_t *buf) 909 { 910 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 911 struct rx_mpdu_end *mpdu_end = 912 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 913 uint32_t decrypt_err; 914 915 decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end); 916 917 return decrypt_err; 918 } 919 920 /* 921 * hal_rx_tlv_first_mpdu_get_li(): get fist_mpdu bit from rx attention 922 * @buf: pointer to rx_pkt_tlvs 923 * 924 * reutm: uint32_t(first_msdu) 925 */ 926 static inline uint32_t 927 hal_rx_tlv_first_mpdu_get_li(uint8_t *buf) 928 { 929 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 930 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 931 uint32_t first_mpdu; 932 933 first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn); 934 935 return first_mpdu; 936 } 937 938 /* 939 * hal_rx_msdu_get_keyid_li(): API to get the key id if the decrypted packet 940 * from rx_msdu_end 941 * 942 * @buf: pointer to the start of RX PKT TLV header 943 * Return: uint32_t(key id) 944 */ 945 static inline uint8_t 946 hal_rx_msdu_get_keyid_li(uint8_t *buf) 947 { 948 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 949 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 950 uint32_t keyid_octet; 951 952 keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end); 953 954 return keyid_octet & 0x3; 955 } 956 957 /* 958 * hal_rx_tlv_get_is_decrypted_li(): API to get the decrypt status of the 959 * packet from rx_attention 960 * 961 * @buf: pointer to the start of RX PKT TLV header 962 * Return: uint32_t(decryt status) 963 */ 964 static inline uint32_t 965 hal_rx_tlv_get_is_decrypted_li(uint8_t *buf) 966 { 967 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 968 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 969 uint32_t is_decrypt = 0; 970 uint32_t decrypt_status; 971 972 decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn); 973 974 if (!decrypt_status) 975 is_decrypt = 1; 976 977 return is_decrypt; 978 } 979 980 /** 981 * hal_rx_msdu_reo_dst_ind_get_li() - Gets the REO 982 * destination ring ID from the msdu desc info 983 * 984 * @hal_soc_hdl: HAL version of the SOC pointer 985 * @msdu_link_desc: Opaque cookie pointer used by HAL to get to 986 * the current descriptor 987 * 988 * Return: dst_ind (REO destination ring ID) 989 */ 990 static inline uint32_t 991 hal_rx_msdu_reo_dst_ind_get_li(hal_soc_handle_t hal_soc_hdl, 992 void *msdu_link_desc) 993 { 994 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 995 struct rx_msdu_details *msdu_details; 996 struct rx_msdu_desc_info *msdu_desc_info; 997 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 998 uint32_t dst_ind; 999 1000 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1001 1002 /* The first msdu in the link should exist */ 1003 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0], 1004 hal_soc); 1005 dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info); 1006 return dst_ind; 1007 } 1008 1009 static inline void 1010 hal_mpdu_desc_info_set_li(hal_soc_handle_t hal_soc_hdl, 1011 void *ent_desc, 1012 void *mpdu_desc, 1013 uint32_t seq_no) 1014 { 1015 struct rx_mpdu_desc_info *mpdu_desc_info = 1016 (struct rx_mpdu_desc_info *)mpdu_desc; 1017 1018 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1019 MSDU_COUNT, 0x1); 1020 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1021 MPDU_SEQUENCE_NUMBER, seq_no); 1022 /* unset frag bit */ 1023 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1024 FRAGMENT_FLAG, 0x0); 1025 /* set sa/da valid bits */ 1026 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1027 SA_IS_VALID, 0x1); 1028 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1029 DA_IS_VALID, 0x1); 1030 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1031 RAW_MPDU, 0x0); 1032 } 1033 1034 static inline void 1035 hal_msdu_desc_info_set_li(hal_soc_handle_t hal_soc_hdl, 1036 void *msdu_desc, uint32_t dst_ind, 1037 uint32_t nbuf_len) 1038 { 1039 struct rx_msdu_desc_info *msdu_desc_info = 1040 (struct rx_msdu_desc_info *)msdu_desc; 1041 1042 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1043 FIRST_MSDU_IN_MPDU_FLAG, 1); 1044 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1045 LAST_MSDU_IN_MPDU_FLAG, 1); 1046 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1047 MSDU_CONTINUATION, 0x0); 1048 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1049 REO_DESTINATION_INDICATION, 1050 dst_ind); 1051 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1052 MSDU_LENGTH, nbuf_len); 1053 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1054 SA_IS_VALID, 1); 1055 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1056 DA_IS_VALID, 1); 1057 } 1058 1059 static inline 1060 uint8_t *hal_get_reo_ent_desc_qdesc_addr_li(uint8_t *desc) 1061 { 1062 return desc + REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET; 1063 } 1064 1065 static inline 1066 void hal_set_reo_ent_desc_reo_dest_ind_li(uint8_t *desc, uint32_t dst_ind) 1067 { 1068 HAL_RX_FLD_SET(desc, REO_ENTRANCE_RING_5, 1069 REO_DESTINATION_INDICATION, dst_ind); 1070 } 1071 1072 static inline void 1073 hal_rx_wbm_rel_buf_paddr_get_li(hal_ring_desc_t rx_desc, 1074 struct hal_buf_info *buf_info) 1075 { 1076 struct wbm_release_ring *wbm_rel_ring = 1077 (struct wbm_release_ring *)rx_desc; 1078 1079 buf_info->paddr = 1080 (HAL_RX_WBM_BUF_ADDR_31_0_GET(wbm_rel_ring) | 1081 ((uint64_t)(HAL_RX_WBM_BUF_ADDR_39_32_GET(wbm_rel_ring)) << 32)); 1082 1083 buf_info->sw_cookie = HAL_RX_WBM_BUF_COOKIE_GET(wbm_rel_ring); 1084 } 1085 1086 static QDF_STATUS hal_reo_status_update_li(hal_soc_handle_t hal_soc_hdl, 1087 hal_ring_desc_t reo_desc, 1088 void *st_handle, 1089 uint32_t tlv, int *num_ref) 1090 { 1091 union hal_reo_status *reo_status_ref; 1092 1093 reo_status_ref = (union hal_reo_status *)st_handle; 1094 1095 switch (tlv) { 1096 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1097 hal_reo_queue_stats_status_li(reo_desc, 1098 &reo_status_ref->queue_status, 1099 hal_soc_hdl); 1100 *num_ref = reo_status_ref->queue_status.header.cmd_num; 1101 break; 1102 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1103 hal_reo_flush_queue_status_li(reo_desc, 1104 &reo_status_ref->fl_queue_status, 1105 hal_soc_hdl); 1106 *num_ref = reo_status_ref->fl_queue_status.header.cmd_num; 1107 break; 1108 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1109 hal_reo_flush_cache_status_li(reo_desc, 1110 &reo_status_ref->fl_cache_status, 1111 hal_soc_hdl); 1112 *num_ref = reo_status_ref->fl_cache_status.header.cmd_num; 1113 break; 1114 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1115 hal_reo_unblock_cache_status_li( 1116 reo_desc, hal_soc_hdl, 1117 &reo_status_ref->unblk_cache_status); 1118 *num_ref = reo_status_ref->unblk_cache_status.header.cmd_num; 1119 break; 1120 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1121 hal_reo_flush_timeout_list_status_li( 1122 reo_desc, 1123 &reo_status_ref->fl_timeout_status, 1124 hal_soc_hdl); 1125 *num_ref = reo_status_ref->fl_timeout_status.header.cmd_num; 1126 break; 1127 case HAL_REO_DESC_THRES_STATUS_TLV: 1128 hal_reo_desc_thres_reached_status_li( 1129 reo_desc, 1130 &reo_status_ref->thres_status, 1131 hal_soc_hdl); 1132 *num_ref = reo_status_ref->thres_status.header.cmd_num; 1133 break; 1134 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1135 hal_reo_rx_update_queue_status_li( 1136 reo_desc, 1137 &reo_status_ref->rx_queue_status, 1138 hal_soc_hdl); 1139 *num_ref = reo_status_ref->rx_queue_status.header.cmd_num; 1140 break; 1141 default: 1142 QDF_TRACE(QDF_MODULE_ID_DP_REO, QDF_TRACE_LEVEL_WARN, 1143 "hal_soc %pK: no handler for TLV:%d", 1144 hal_soc_hdl, tlv); 1145 return QDF_STATUS_E_FAILURE; 1146 } /* switch */ 1147 1148 return QDF_STATUS_SUCCESS; 1149 } 1150 1151 /** 1152 * hal_get_idle_link_bm_id_li() - Get idle link BM id from chid_id 1153 * @chip_id: mlo chip_id 1154 * 1155 * Returns: RBM ID 1156 */ 1157 static uint8_t hal_get_idle_link_bm_id_li(uint8_t chip_id) 1158 { 1159 return WBM_IDLE_DESC_LIST; 1160 } 1161 1162 void hal_hw_txrx_default_ops_attach_li(struct hal_soc *hal_soc) 1163 { 1164 hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_li; 1165 hal_soc->ops->hal_get_rx_max_ba_window = 1166 hal_get_rx_max_ba_window_li; 1167 hal_soc->ops->hal_set_link_desc_addr = hal_set_link_desc_addr_li; 1168 hal_soc->ops->hal_tx_init_data_ring = hal_tx_init_data_ring_li; 1169 hal_soc->ops->hal_get_ba_aging_timeout = hal_get_ba_aging_timeout_li; 1170 hal_soc->ops->hal_set_ba_aging_timeout = hal_set_ba_aging_timeout_li; 1171 hal_soc->ops->hal_get_reo_reg_base_offset = 1172 hal_get_reo_reg_base_offset_li; 1173 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_li; 1174 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 1175 hal_rx_msdu_is_wlan_mcast_generic_li; 1176 hal_soc->ops->hal_rx_tlv_decap_format_get = 1177 hal_rx_tlv_decap_format_get_li; 1178 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_li; 1179 hal_soc->ops->hal_rx_tlv_get_offload_info = 1180 hal_rx_tlv_get_offload_info_li; 1181 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 1182 hal_rx_attn_phy_ppdu_id_get_li; 1183 hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_attn_msdu_done_get_li; 1184 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1185 hal_rx_msdu_start_msdu_len_get_li; 1186 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_li; 1187 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_li; 1188 1189 hal_soc->ops->hal_rx_reo_buf_paddr_get = hal_rx_reo_buf_paddr_get_li; 1190 hal_soc->ops->hal_rx_msdu_link_desc_set = hal_rx_msdu_link_desc_set_li; 1191 hal_soc->ops->hal_rx_buf_cookie_rbm_get = hal_rx_buf_cookie_rbm_get_li; 1192 hal_soc->ops->hal_rx_ret_buf_manager_get = 1193 hal_rx_ret_buf_manager_get_li; 1194 hal_soc->ops->hal_rxdma_buff_addr_info_set = 1195 hal_rxdma_buff_addr_info_set_li; 1196 hal_soc->ops->hal_rx_msdu_flags_get = hal_rx_msdu_flags_get_li; 1197 hal_soc->ops->hal_rx_get_reo_error_code = hal_rx_get_reo_error_code_li; 1198 hal_soc->ops->hal_gen_reo_remap_val = 1199 hal_gen_reo_remap_val_generic_li; 1200 hal_soc->ops->hal_rx_tlv_csum_err_get = 1201 hal_rx_tlv_csum_err_get_li; 1202 hal_soc->ops->hal_rx_mpdu_desc_info_get = 1203 hal_rx_mpdu_desc_info_get_li; 1204 hal_soc->ops->hal_rx_err_status_get = hal_rx_err_status_get_li; 1205 hal_soc->ops->hal_rx_reo_buf_type_get = hal_rx_reo_buf_type_get_li; 1206 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_li; 1207 hal_soc->ops->hal_rx_wbm_err_src_get = hal_rx_wbm_err_src_get_li; 1208 hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get = 1209 hal_rx_wbm_rel_buf_paddr_get_li; 1210 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1211 hal_rx_priv_info_set_in_tlv_li; 1212 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1213 hal_rx_priv_info_get_from_tlv_li; 1214 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1215 hal_rx_mpdu_info_ampdu_flag_get_li; 1216 hal_soc->ops->hal_rx_tlv_mpdu_len_err_get = 1217 hal_rx_tlv_mpdu_len_err_get_li; 1218 hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get = 1219 hal_rx_tlv_mpdu_fcs_err_get_li; 1220 hal_soc->ops->hal_reo_send_cmd = hal_reo_send_cmd_li; 1221 hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags = 1222 hal_rx_tlv_get_pkt_capture_flags_li; 1223 hal_soc->ops->hal_rx_desc_get_80211_hdr = hal_rx_desc_get_80211_hdr_li; 1224 hal_soc->ops->hal_rx_hw_desc_mpdu_user_id = 1225 hal_rx_hw_desc_mpdu_user_id_li; 1226 hal_soc->ops->hal_reo_qdesc_setup = hal_reo_qdesc_setup_li; 1227 hal_soc->ops->hal_rx_tlv_msdu_len_set = 1228 hal_rx_msdu_start_msdu_len_set_li; 1229 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_li; 1230 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_li; 1231 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_li; 1232 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_li; 1233 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_li; 1234 hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_li; 1235 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_li; 1236 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1237 hal_rx_tlv_decrypt_err_get_li; 1238 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_li; 1239 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 1240 hal_rx_tlv_get_is_decrypted_li; 1241 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_li; 1242 hal_soc->ops->hal_rx_msdu_reo_dst_ind_get = 1243 hal_rx_msdu_reo_dst_ind_get_li; 1244 hal_soc->ops->hal_msdu_desc_info_set = hal_msdu_desc_info_set_li; 1245 hal_soc->ops->hal_mpdu_desc_info_set = hal_mpdu_desc_info_set_li; 1246 hal_soc->ops->hal_reo_status_update = hal_reo_status_update_li; 1247 hal_soc->ops->hal_get_tlv_hdr_size = hal_get_tlv_hdr_size_li; 1248 hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr = 1249 hal_get_reo_ent_desc_qdesc_addr_li; 1250 hal_soc->ops->hal_rx_get_qdesc_addr = hal_rx_get_qdesc_addr_li; 1251 hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind = 1252 hal_set_reo_ent_desc_reo_dest_ind_li; 1253 hal_soc->ops->hal_get_idle_link_bm_id = hal_get_idle_link_bm_id_li; 1254 } 1255