1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "hal_li_api.h" 21 #include "hal_li_hw_headers.h" 22 #include "hal_li_reo.h" 23 24 #include "hal_rx.h" 25 #include "hal_li_rx.h" 26 #include "hal_tx.h" 27 #include <hal_api_mon.h> 28 29 static uint16_t hal_get_rx_max_ba_window_li(int tid) 30 { 31 return HAL_RX_BA_WINDOW_256; 32 } 33 34 static uint32_t hal_get_reo_qdesc_size_li(uint32_t ba_window_size, int tid) 35 { 36 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 37 * NON_QOS_TID until HW issues are resolved. 38 */ 39 if (tid != HAL_NON_QOS_TID) 40 ba_window_size = hal_get_rx_max_ba_window_li(tid); 41 42 /* Return descriptor size corresponding to window size of 2 since 43 * we set ba_window_size to 2 while setting up REO descriptors as 44 * a WAR to get 2k jump exception aggregates are received without 45 * a BA session. 46 */ 47 if (ba_window_size <= 1) { 48 if (tid != HAL_NON_QOS_TID) 49 return sizeof(struct rx_reo_queue) + 50 sizeof(struct rx_reo_queue_ext); 51 else 52 return sizeof(struct rx_reo_queue); 53 } 54 55 if (ba_window_size <= 105) 56 return sizeof(struct rx_reo_queue) + 57 sizeof(struct rx_reo_queue_ext); 58 59 if (ba_window_size <= 210) 60 return sizeof(struct rx_reo_queue) + 61 (2 * sizeof(struct rx_reo_queue_ext)); 62 63 return sizeof(struct rx_reo_queue) + 64 (3 * sizeof(struct rx_reo_queue_ext)); 65 } 66 67 void hal_set_link_desc_addr_li(void *desc, uint32_t cookie, 68 qdf_dma_addr_t link_desc_paddr, 69 uint8_t bm_id) 70 { 71 uint32_t *buf_addr = (uint32_t *)desc; 72 73 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, 74 link_desc_paddr & 0xffffffff); 75 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 76 (uint64_t)link_desc_paddr >> 32); 77 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, RETURN_BUFFER_MANAGER, 78 bm_id); 79 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, 80 cookie); 81 } 82 83 void hal_tx_init_data_ring_li(hal_soc_handle_t hal_soc_hdl, 84 hal_ring_handle_t hal_ring_hdl) 85 { 86 uint8_t *desc_addr; 87 struct hal_srng_params srng_params; 88 uint32_t desc_size; 89 uint32_t num_desc; 90 91 hal_get_srng_params(hal_soc_hdl, hal_ring_hdl, &srng_params); 92 93 desc_addr = (uint8_t *)srng_params.ring_base_vaddr; 94 desc_size = sizeof(struct tcl_data_cmd); 95 num_desc = srng_params.num_entries; 96 97 while (num_desc) { 98 HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, 99 desc_size); 100 desc_addr += (desc_size + sizeof(struct tlv_32_hdr)); 101 num_desc--; 102 } 103 } 104 105 /* 106 * hal_rx_msdu_is_wlan_mcast_generic_li(): Check if the buffer is for multicast 107 * address 108 * @nbuf: Network buffer 109 * 110 * Returns: flag to indicate whether the nbuf has MC/BC address 111 */ 112 static uint32_t hal_rx_msdu_is_wlan_mcast_generic_li(qdf_nbuf_t nbuf) 113 { 114 uint8_t *buf = qdf_nbuf_data(nbuf); 115 116 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 117 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 118 119 return rx_attn->mcast_bcast; 120 } 121 122 /** 123 * hal_rx_tlv_decap_format_get_li() - Get packet decap format from the TLV 124 * @hw_desc_addr: rx tlv desc 125 * 126 * Return: pkt decap format 127 */ 128 static uint32_t hal_rx_tlv_decap_format_get_li(void *hw_desc_addr) 129 { 130 struct rx_msdu_start *rx_msdu_start; 131 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 132 133 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 134 135 return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); 136 } 137 138 /** 139 * hal_rx_dump_pkt_tlvs_li(): API to print all member elements of 140 * RX TLVs 141 * @ buf: pointer the pkt buffer. 142 * @ dbg_level: log level. 143 * 144 * Return: void 145 */ 146 static void hal_rx_dump_pkt_tlvs_li(hal_soc_handle_t hal_soc_hdl, 147 uint8_t *buf, uint8_t dbg_level) 148 { 149 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 150 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 151 struct rx_mpdu_start *mpdu_start = 152 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 153 struct rx_msdu_start *msdu_start = 154 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 155 struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 156 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 157 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 158 159 hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level); 160 hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc); 161 hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level); 162 hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level); 163 hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level); 164 hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level); 165 } 166 167 /** 168 * hal_rx_tlv_get_offload_info_li() - Get the offload info from TLV 169 * @rx_tlv: RX tlv start address in buffer 170 * @offload_info: Buffer to store the offload info 171 * 172 * Return: 0 on success, -EINVAL on failure. 173 */ 174 static int 175 hal_rx_tlv_get_offload_info_li(uint8_t *rx_tlv, 176 struct hal_offload_info *offload_info) 177 { 178 offload_info->flow_id = HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(rx_tlv); 179 offload_info->ipv6_proto = HAL_RX_TLV_GET_IPV6(rx_tlv); 180 offload_info->lro_eligible = HAL_RX_TLV_GET_LRO_ELIGIBLE(rx_tlv); 181 offload_info->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(rx_tlv); 182 183 if (offload_info->tcp_proto) { 184 offload_info->tcp_pure_ack = 185 HAL_RX_TLV_GET_TCP_PURE_ACK(rx_tlv); 186 offload_info->tcp_offset = HAL_RX_TLV_GET_TCP_OFFSET(rx_tlv); 187 offload_info->tcp_win = HAL_RX_TLV_GET_TCP_WIN(rx_tlv); 188 offload_info->tcp_seq_num = HAL_RX_TLV_GET_TCP_SEQ(rx_tlv); 189 offload_info->tcp_ack_num = HAL_RX_TLV_GET_TCP_ACK(rx_tlv); 190 } 191 return 0; 192 } 193 194 /* 195 * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value 196 * from rx attention 197 * @buf: pointer to rx_pkt_tlvs 198 * 199 * Return: phy_ppdu_id 200 */ 201 static uint16_t hal_rx_attn_phy_ppdu_id_get_li(uint8_t *buf) 202 { 203 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 204 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 205 uint16_t phy_ppdu_id; 206 207 phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn); 208 209 return phy_ppdu_id; 210 } 211 212 /** 213 * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length 214 * from rx_msdu_start TLV 215 * 216 * @ buf: pointer to the start of RX PKT TLV headers 217 * Return: msdu length 218 */ 219 static uint32_t hal_rx_msdu_start_msdu_len_get_li(uint8_t *buf) 220 { 221 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 222 struct rx_msdu_start *msdu_start = 223 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 224 uint32_t msdu_len; 225 226 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 227 228 return msdu_len; 229 } 230 231 /** 232 * hal_rx_get_proto_params_li() - Get l4 proto values from TLV 233 * @buf: rx tlv address 234 * @proto_params: Buffer to store proto parameters 235 * 236 * Return: 0 on success. 237 */ 238 static int hal_rx_get_proto_params_li(uint8_t *buf, void *proto_params) 239 { 240 struct hal_proto_params *param = 241 (struct hal_proto_params *)proto_params; 242 243 param->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(buf); 244 param->udp_proto = HAL_RX_TLV_GET_UDP_PROTO(buf); 245 param->ipv6_proto = HAL_RX_TLV_GET_IPV6(buf); 246 247 return 0; 248 } 249 250 /** 251 * hal_rx_get_l3_l4_offsets_li() - Get l3/l4 header offset from TLV 252 * @buf: rx tlv start address 253 * @l3_hdr_offset: buffer to store l3 offset 254 * @l4_hdr_offset: buffer to store l4 offset 255 * 256 * Return: 0 on success. 257 */ 258 static int hal_rx_get_l3_l4_offsets_li(uint8_t *buf, uint32_t *l3_hdr_offset, 259 uint32_t *l4_hdr_offset) 260 { 261 *l3_hdr_offset = HAL_RX_TLV_GET_IP_OFFSET(buf); 262 *l4_hdr_offset = HAL_RX_TLV_GET_TCP_OFFSET(buf); 263 264 return 0; 265 } 266 267 /** 268 * hal_rx_tlv_get_pn_num_li() - Get packet number from RX TLV 269 * @buf: rx tlv address 270 * @pn_num: buffer to store packet number 271 * 272 * Return: None 273 */ 274 static inline void hal_rx_tlv_get_pn_num_li(uint8_t *buf, uint64_t *pn_num) 275 { 276 struct rx_pkt_tlvs *rx_pkt_tlv = 277 (struct rx_pkt_tlvs *)buf; 278 struct rx_mpdu_info *rx_mpdu_info_details = 279 &rx_pkt_tlv->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 280 281 pn_num[0] = rx_mpdu_info_details->pn_31_0; 282 pn_num[0] |= 283 ((uint64_t)rx_mpdu_info_details->pn_63_32 << 32); 284 pn_num[1] = rx_mpdu_info_details->pn_95_64; 285 pn_num[1] |= 286 ((uint64_t)rx_mpdu_info_details->pn_127_96 << 32); 287 } 288 289 #ifdef NO_RX_PKT_HDR_TLV 290 /** 291 * hal_rx_pkt_hdr_get_li() - Get rx packet header start address. 292 * @buf: packet start address 293 * 294 * Return: packet data start address. 295 */ 296 static inline uint8_t *hal_rx_pkt_hdr_get_li(uint8_t *buf) 297 { 298 return buf + RX_PKT_TLVS_LEN; 299 } 300 #else 301 static inline uint8_t *hal_rx_pkt_hdr_get_li(uint8_t *buf) 302 { 303 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 304 305 return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr; 306 } 307 #endif 308 309 /** 310 * hal_rx_priv_info_set_in_tlv_li(): Save the private info to 311 * the reserved bytes of rx_tlv_hdr 312 * @buf: start of rx_tlv_hdr 313 * @priv_data: hal_wbm_err_desc_info structure 314 * @len: length of the private data 315 * Return: void 316 */ 317 static inline void 318 hal_rx_priv_info_set_in_tlv_li(uint8_t *buf, uint8_t *priv_data, 319 uint32_t len) 320 { 321 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 322 uint32_t copy_len = (len > RX_PADDING0_BYTES) ? 323 RX_PADDING0_BYTES : len; 324 325 qdf_mem_copy(pkt_tlvs->rx_padding0, priv_data, copy_len); 326 } 327 328 /** 329 * hal_rx_priv_info_get_from_tlv_li(): retrieve the private data from 330 * the reserved bytes of rx_tlv_hdr. 331 * @buf: start of rx_tlv_hdr 332 * @priv_data: hal_wbm_err_desc_info structure 333 * @len: length of the private data 334 * Return: void 335 */ 336 static inline void 337 hal_rx_priv_info_get_from_tlv_li(uint8_t *buf, uint8_t *priv_data, 338 uint32_t len) 339 { 340 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 341 uint32_t copy_len = (len > RX_PADDING0_BYTES) ? 342 RX_PADDING0_BYTES : len; 343 344 qdf_mem_copy(priv_data, pkt_tlvs->rx_padding0, copy_len); 345 } 346 347 /** 348 * hal_rx_get_tlv_size_generic_li() - Get rx packet tlv size 349 * @rx_pkt_tlv_size: TLV size for regular RX packets 350 * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets 351 * 352 * Return: size of rx pkt tlv before the actual data 353 */ 354 static void hal_rx_get_tlv_size_generic_li(uint16_t *rx_pkt_tlv_size, 355 uint16_t *rx_mon_pkt_tlv_size) 356 { 357 *rx_pkt_tlv_size = RX_PKT_TLVS_LEN; 358 *rx_mon_pkt_tlv_size = SIZE_OF_MONITOR_TLV; 359 } 360 361 /** 362 * hal_rx_wbm_err_src_get_li() - Get WBM error source from descriptor 363 * @ring_desc: ring descriptor 364 * 365 * Return: wbm error source 366 */ 367 uint32_t hal_rx_wbm_err_src_get_li(hal_ring_desc_t ring_desc) 368 { 369 return HAL_WBM2SW_RELEASE_SRC_GET(ring_desc); 370 } 371 372 /** 373 * hal_rx_ret_buf_manager_get_li() - Get return buffer manager from ring desc 374 * @ring_desc: ring descriptor 375 * 376 * Return: rbm 377 */ 378 uint8_t hal_rx_ret_buf_manager_get_li(hal_ring_desc_t ring_desc) 379 { 380 /* 381 * The following macro takes buf_addr_info as argument, 382 * but since buf_addr_info is the first field in ring_desc 383 * Hence the following call is OK 384 */ 385 return HAL_RX_BUF_RBM_GET(ring_desc); 386 } 387 388 /** 389 * hal_rx_reo_buf_paddr_get_li: Gets the physical address and 390 * cookie from the REO destination ring element 391 * 392 * @ rx_desc: Opaque cookie pointer used by HAL to get to 393 * the current descriptor 394 * @ buf_info: structure to return the buffer information 395 * Return: void 396 */ 397 static void hal_rx_reo_buf_paddr_get_li(hal_ring_desc_t rx_desc, 398 struct hal_buf_info *buf_info) 399 { 400 struct reo_destination_ring *reo_ring = 401 (struct reo_destination_ring *)rx_desc; 402 403 buf_info->paddr = 404 (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) | 405 ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32)); 406 buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring); 407 } 408 409 /** 410 * hal_rx_msdu_link_desc_set_li: Retrieves MSDU Link Descriptor to WBM 411 * 412 * @ hal_soc_hdl : HAL version of the SOC pointer 413 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 414 * @ buf_addr_info : void pointer to the buffer_addr_info 415 * @ bm_action : put in IDLE list or release to MSDU_LIST 416 * 417 * Return: void 418 */ 419 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 420 static void hal_rx_msdu_link_desc_set_li(hal_soc_handle_t hal_soc_hdl, 421 void *src_srng_desc, 422 hal_buff_addrinfo_t buf_addr_info, 423 uint8_t bm_action) 424 { 425 /* 426 * The offsets for fields used in this function are same in 427 * wbm_release_ring for Lithium and wbm_release_ring_tx 428 * for Beryllium. hence we can use wbm_release_ring directly. 429 */ 430 struct wbm_release_ring *wbm_rel_srng = 431 (struct wbm_release_ring *)src_srng_desc; 432 uint32_t addr_31_0; 433 uint8_t addr_39_32; 434 435 /* Structure copy !!! */ 436 wbm_rel_srng->released_buff_or_desc_addr_info = 437 *(struct buffer_addr_info *)buf_addr_info; 438 439 addr_31_0 = 440 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0; 441 addr_39_32 = 442 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32; 443 444 HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, 445 RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW); 446 HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, BM_ACTION, 447 bm_action); 448 HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, 449 BUFFER_OR_DESC_TYPE, 450 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC); 451 452 /* WBM error is indicated when any of the link descriptors given to 453 * WBM has a NULL address, and one those paths is the link descriptors 454 * released from host after processing RXDMA errors, 455 * or from Rx defrag path, and we want to add an assert here to ensure 456 * host is not releasing descriptors with NULL address. 457 */ 458 459 if (qdf_unlikely(!addr_31_0 && !addr_39_32)) { 460 hal_dump_wbm_rel_desc(src_srng_desc); 461 qdf_assert_always(0); 462 } 463 } 464 465 static 466 void hal_rx_buf_cookie_rbm_get_li(uint32_t *buf_addr_info_hdl, 467 hal_buf_info_t buf_info_hdl) 468 { 469 struct hal_buf_info *buf_info = 470 (struct hal_buf_info *)buf_info_hdl; 471 struct buffer_addr_info *buf_addr_info = 472 (struct buffer_addr_info *)buf_addr_info_hdl; 473 474 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 475 /* 476 * buffer addr info is the first member of ring desc, so the typecast 477 * can be done. 478 */ 479 buf_info->rbm = hal_rx_ret_buf_manager_get_li 480 ((hal_ring_desc_t)buf_addr_info); 481 } 482 483 /** 484 * hal_rx_msdu_link_desc_get(): API to get the MSDU information 485 * from the MSDU link descriptor 486 * 487 * @ hal_soc_hdl : HAL version of the SOC pointer 488 * @msdu_link_desc: Opaque pointer used by HAL to get to the 489 * MSDU link descriptor (struct rx_msdu_link) 490 * 491 * @msdu_list: Return the list of MSDUs contained in this link descriptor 492 * 493 * @num_msdus: Number of MSDUs in the MPDU 494 * 495 * Return: void 496 */ 497 static inline void hal_rx_msdu_list_get_li(hal_soc_handle_t hal_soc_hdl, 498 void *msdu_link_desc, 499 void *hal_msdu_list, 500 uint16_t *num_msdus) 501 { 502 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 503 struct rx_msdu_details *msdu_details; 504 struct rx_msdu_desc_info *msdu_desc_info; 505 struct hal_rx_msdu_list *msdu_list = hal_msdu_list; 506 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 507 int i; 508 struct hal_buf_info buf_info; 509 510 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 511 512 hal_debug("msdu_link=%pK msdu_details=%pK", msdu_link, msdu_details); 513 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 514 /* num_msdus received in mpdu descriptor may be incorrect 515 * sometimes due to HW issue. Check msdu buffer address also 516 */ 517 if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET( 518 &msdu_details[i].buffer_addr_info_details) == 0)) 519 break; 520 if (HAL_RX_BUFFER_ADDR_31_0_GET( 521 &msdu_details[i].buffer_addr_info_details) == 0) { 522 /* set the last msdu bit in the prev msdu_desc_info */ 523 msdu_desc_info = 524 hal_rx_msdu_desc_info_get_ptr 525 (&msdu_details[i - 1], hal_soc); 526 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 527 break; 528 } 529 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 530 hal_soc); 531 532 /* set first MSDU bit or the last MSDU bit */ 533 if (!i) 534 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 535 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 536 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 537 538 msdu_list->msdu_info[i].msdu_flags = 539 hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info); 540 msdu_list->msdu_info[i].msdu_len = 541 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 542 543 /* addr field in buf_info will not be valid */ 544 hal_rx_buf_cookie_rbm_get_li( 545 (uint32_t *) 546 &msdu_details[i].buffer_addr_info_details, 547 &buf_info); 548 msdu_list->sw_cookie[i] = buf_info.sw_cookie; 549 msdu_list->rbm[i] = buf_info.rbm; 550 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 551 &msdu_details[i].buffer_addr_info_details) | 552 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 553 &msdu_details[i].buffer_addr_info_details) << 32; 554 hal_debug("i=%d sw_cookie=%d", i, msdu_list->sw_cookie[i]); 555 } 556 *num_msdus = i; 557 } 558 559 /* 560 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 561 * rxdma ring entry. 562 * @rxdma_entry: descriptor entry 563 * @paddr: physical address of nbuf data pointer. 564 * @cookie: SW cookie used as a index to SW rx desc. 565 * @manager: who owns the nbuf (host, NSS, etc...). 566 * 567 */ 568 static void hal_rxdma_buff_addr_info_set_li(void *rxdma_entry, 569 qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager) 570 { 571 uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff); 572 uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32; 573 574 HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo); 575 HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi); 576 HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie); 577 HAL_RXDMA_MANAGER_SET(rxdma_entry, manager); 578 } 579 580 /** 581 * hal_rx_get_reo_error_code_li() - Get REO error code from ring desc 582 * @rx_desc: rx descriptor 583 * 584 * Return: REO error code 585 */ 586 static uint32_t hal_rx_get_reo_error_code_li(hal_ring_desc_t rx_desc) 587 { 588 struct reo_destination_ring *reo_desc = 589 (struct reo_destination_ring *)rx_desc; 590 591 return HAL_RX_REO_ERROR_GET(reo_desc); 592 } 593 594 /** 595 * hal_gen_reo_remap_val_generic_li() - Generate the reo map value 596 * @ix0_map: mapping values for reo 597 * 598 * Return: IX0 reo remap register value to be written 599 */ 600 static uint32_t 601 hal_gen_reo_remap_val_generic_li(enum hal_reo_remap_reg remap_reg, 602 uint8_t *ix0_map) 603 { 604 uint32_t ix_val = 0; 605 606 switch (remap_reg) { 607 case HAL_REO_REMAP_REG_IX0: 608 ix_val = HAL_REO_REMAP_IX0(ix0_map[0], 0) | 609 HAL_REO_REMAP_IX0(ix0_map[1], 1) | 610 HAL_REO_REMAP_IX0(ix0_map[2], 2) | 611 HAL_REO_REMAP_IX0(ix0_map[3], 3) | 612 HAL_REO_REMAP_IX0(ix0_map[4], 4) | 613 HAL_REO_REMAP_IX0(ix0_map[5], 5) | 614 HAL_REO_REMAP_IX0(ix0_map[6], 6) | 615 HAL_REO_REMAP_IX0(ix0_map[7], 7); 616 break; 617 case HAL_REO_REMAP_REG_IX2: 618 ix_val = HAL_REO_REMAP_IX2(ix0_map[0], 16) | 619 HAL_REO_REMAP_IX2(ix0_map[1], 17) | 620 HAL_REO_REMAP_IX2(ix0_map[2], 18) | 621 HAL_REO_REMAP_IX2(ix0_map[3], 19) | 622 HAL_REO_REMAP_IX2(ix0_map[4], 20) | 623 HAL_REO_REMAP_IX2(ix0_map[5], 21) | 624 HAL_REO_REMAP_IX2(ix0_map[6], 22) | 625 HAL_REO_REMAP_IX2(ix0_map[7], 23); 626 break; 627 default: 628 break; 629 } 630 631 return ix_val; 632 } 633 634 /** 635 * hal_rx_tlv_csum_err_get_li() - Get IP and tcp-udp checksum fail flag 636 * @rx_tlv_hdr: start address of rx_tlv_hdr 637 * @ip_csum_err: buffer to return ip_csum_fail flag 638 * @tcp_udp_csum_fail: placeholder to return tcp-udp checksum fail flag 639 * 640 * Return: None 641 */ 642 static inline void 643 hal_rx_tlv_csum_err_get_li(uint8_t *rx_tlv_hdr, uint32_t *ip_csum_err, 644 uint32_t *tcp_udp_csum_err) 645 { 646 *ip_csum_err = hal_rx_attn_ip_cksum_fail_get(rx_tlv_hdr); 647 *tcp_udp_csum_err = hal_rx_attn_tcp_udp_cksum_fail_get(rx_tlv_hdr); 648 } 649 650 static 651 void hal_rx_tlv_get_pkt_capture_flags_li(uint8_t *rx_tlv_pkt_hdr, 652 struct hal_rx_pkt_capture_flags *flags) 653 { 654 struct rx_pkt_tlvs *rx_tlv_hdr = (struct rx_pkt_tlvs *)rx_tlv_pkt_hdr; 655 struct rx_attention *rx_attn = &rx_tlv_hdr->attn_tlv.rx_attn; 656 struct rx_mpdu_start *mpdu_start = 657 &rx_tlv_hdr->mpdu_start_tlv.rx_mpdu_start; 658 struct rx_mpdu_end *mpdu_end = &rx_tlv_hdr->mpdu_end_tlv.rx_mpdu_end; 659 struct rx_msdu_start *msdu_start = 660 &rx_tlv_hdr->msdu_start_tlv.rx_msdu_start; 661 662 flags->encrypt_type = mpdu_start->rx_mpdu_info_details.encrypt_type; 663 flags->fcs_err = mpdu_end->fcs_err; 664 flags->fragment_flag = rx_attn->fragment_flag; 665 flags->chan_freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 666 flags->rssi_comb = HAL_RX_MSDU_START_RSSI_GET(msdu_start); 667 flags->tsft = msdu_start->ppdu_start_timestamp; 668 } 669 670 static uint8_t hal_rx_err_status_get_li(hal_ring_desc_t rx_desc) 671 { 672 return HAL_RX_ERROR_STATUS_GET(rx_desc); 673 } 674 675 static uint8_t hal_rx_reo_buf_type_get_li(hal_ring_desc_t rx_desc) 676 { 677 return HAL_RX_REO_BUF_TYPE_GET(rx_desc); 678 } 679 680 static inline bool 681 hal_rx_mpdu_info_ampdu_flag_get_li(uint8_t *buf) 682 { 683 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 684 struct rx_mpdu_start *mpdu_start = 685 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 686 687 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 688 bool ampdu_flag; 689 690 ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info); 691 692 return ampdu_flag; 693 } 694 695 static 696 uint32_t hal_rx_tlv_mpdu_len_err_get_li(void *hw_desc_addr) 697 { 698 struct rx_attention *rx_attn; 699 struct rx_mon_pkt_tlvs *rx_desc = 700 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 701 702 rx_attn = &rx_desc->attn_tlv.rx_attn; 703 704 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR); 705 } 706 707 static 708 uint32_t hal_rx_tlv_mpdu_fcs_err_get_li(void *hw_desc_addr) 709 { 710 struct rx_attention *rx_attn; 711 struct rx_mon_pkt_tlvs *rx_desc = 712 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 713 714 rx_attn = &rx_desc->attn_tlv.rx_attn; 715 716 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR); 717 } 718 719 #ifdef NO_RX_PKT_HDR_TLV 720 static uint8_t *hal_rx_desc_get_80211_hdr_li(void *hw_desc_addr) 721 { 722 uint8_t *rx_pkt_hdr; 723 struct rx_mon_pkt_tlvs *rx_desc = 724 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 725 726 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 727 728 return rx_pkt_hdr; 729 } 730 #else 731 static uint8_t *hal_rx_desc_get_80211_hdr_li(void *hw_desc_addr) 732 { 733 uint8_t *rx_pkt_hdr; 734 735 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 736 737 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 738 739 return rx_pkt_hdr; 740 } 741 #endif 742 743 static uint32_t hal_rx_hw_desc_mpdu_user_id_li(void *hw_desc_addr) 744 { 745 struct rx_mon_pkt_tlvs *rx_desc = 746 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 747 uint32_t user_id; 748 749 user_id = HAL_RX_GET_USER_TLV32_USERID( 750 &rx_desc->mpdu_start_tlv); 751 752 return user_id; 753 } 754 755 /** 756 * hal_rx_msdu_start_msdu_len_set_li(): API to set the MSDU length 757 * from rx_msdu_start TLV 758 * 759 * @buf: pointer to the start of RX PKT TLV headers 760 * @len: msdu length 761 * 762 * Return: none 763 */ 764 static inline void 765 hal_rx_msdu_start_msdu_len_set_li(uint8_t *buf, uint32_t len) 766 { 767 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 768 struct rx_msdu_start *msdu_start = 769 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 770 void *wrd1; 771 772 wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET; 773 *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK); 774 *(uint32_t *)wrd1 |= len; 775 } 776 777 /* 778 * hal_rx_tlv_bw_get_li(): API to get the Bandwidth 779 * Interval from rx_msdu_start 780 * 781 * @buf: pointer to the start of RX PKT TLV header 782 * Return: uint32_t(bw) 783 */ 784 static inline uint32_t hal_rx_tlv_bw_get_li(uint8_t *buf) 785 { 786 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 787 struct rx_msdu_start *msdu_start = 788 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 789 uint32_t bw; 790 791 bw = HAL_RX_MSDU_START_BW_GET(msdu_start); 792 793 return bw; 794 } 795 796 /* 797 * hal_rx_tlv_get_freq_li(): API to get the frequency of operating channel 798 * from rx_msdu_start 799 * 800 * @buf: pointer to the start of RX PKT TLV header 801 * Return: uint32_t(frequency) 802 */ 803 static inline uint32_t 804 hal_rx_tlv_get_freq_li(uint8_t *buf) 805 { 806 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 807 struct rx_msdu_start *msdu_start = 808 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 809 uint32_t freq; 810 811 freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 812 813 return freq; 814 } 815 816 /** 817 * hal_rx_tlv_sgi_get_li(): API to get the Short Gaurd 818 * Interval from rx_msdu_start TLV 819 * 820 * @buf: pointer to the start of RX PKT TLV headers 821 * Return: uint32_t(sgi) 822 */ 823 static inline uint32_t 824 hal_rx_tlv_sgi_get_li(uint8_t *buf) 825 { 826 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 827 struct rx_msdu_start *msdu_start = 828 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 829 uint32_t sgi; 830 831 sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start); 832 833 return sgi; 834 } 835 836 /** 837 * hal_rx_tlv_rate_mcs_get_li(): API to get the MCS rate 838 * from rx_msdu_start TLV 839 * 840 * @buf: pointer to the start of RX PKT TLV headers 841 * Return: uint32_t(rate_mcs) 842 */ 843 static inline uint32_t 844 hal_rx_tlv_rate_mcs_get_li(uint8_t *buf) 845 { 846 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 847 struct rx_msdu_start *msdu_start = 848 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 849 uint32_t rate_mcs; 850 851 rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start); 852 853 return rate_mcs; 854 } 855 856 /* 857 * hal_rx_tlv_get_pkt_type_li(): API to get the pkt type 858 * from rx_msdu_start 859 * 860 * @buf: pointer to the start of RX PKT TLV header 861 * Return: uint32_t(pkt type) 862 */ 863 864 static inline uint32_t hal_rx_tlv_get_pkt_type_li(uint8_t *buf) 865 { 866 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 867 struct rx_msdu_start *msdu_start = 868 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 869 uint32_t pkt_type; 870 871 pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start); 872 873 return pkt_type; 874 } 875 876 /** 877 * hal_rx_tlv_mic_err_get_li(): API to get the MIC ERR 878 * from rx_mpdu_end TLV 879 * 880 * @buf: pointer to the start of RX PKT TLV headers 881 * Return: uint32_t(mic_err) 882 */ 883 static inline uint32_t 884 hal_rx_tlv_mic_err_get_li(uint8_t *buf) 885 { 886 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 887 struct rx_mpdu_end *mpdu_end = 888 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 889 uint32_t mic_err; 890 891 mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end); 892 893 return mic_err; 894 } 895 896 /** 897 * hal_rx_tlv_decrypt_err_get_li(): API to get the Decrypt ERR 898 * from rx_mpdu_end TLV 899 * 900 * @buf: pointer to the start of RX PKT TLV headers 901 * Return: uint32_t(decrypt_err) 902 */ 903 static inline uint32_t 904 hal_rx_tlv_decrypt_err_get_li(uint8_t *buf) 905 { 906 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 907 struct rx_mpdu_end *mpdu_end = 908 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 909 uint32_t decrypt_err; 910 911 decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end); 912 913 return decrypt_err; 914 } 915 916 /* 917 * hal_rx_tlv_first_mpdu_get_li(): get fist_mpdu bit from rx attention 918 * @buf: pointer to rx_pkt_tlvs 919 * 920 * reutm: uint32_t(first_msdu) 921 */ 922 static inline uint32_t 923 hal_rx_tlv_first_mpdu_get_li(uint8_t *buf) 924 { 925 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 926 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 927 uint32_t first_mpdu; 928 929 first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn); 930 931 return first_mpdu; 932 } 933 934 /* 935 * hal_rx_msdu_get_keyid_li(): API to get the key id if the decrypted packet 936 * from rx_msdu_end 937 * 938 * @buf: pointer to the start of RX PKT TLV header 939 * Return: uint32_t(key id) 940 */ 941 static inline uint8_t 942 hal_rx_msdu_get_keyid_li(uint8_t *buf) 943 { 944 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 945 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 946 uint32_t keyid_octet; 947 948 keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end); 949 950 return keyid_octet & 0x3; 951 } 952 953 /* 954 * hal_rx_tlv_get_is_decrypted_li(): API to get the decrypt status of the 955 * packet from rx_attention 956 * 957 * @buf: pointer to the start of RX PKT TLV header 958 * Return: uint32_t(decryt status) 959 */ 960 static inline uint32_t 961 hal_rx_tlv_get_is_decrypted_li(uint8_t *buf) 962 { 963 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 964 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 965 uint32_t is_decrypt = 0; 966 uint32_t decrypt_status; 967 968 decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn); 969 970 if (!decrypt_status) 971 is_decrypt = 1; 972 973 return is_decrypt; 974 } 975 976 /** 977 * hal_rx_msdu_reo_dst_ind_get_li: Gets the REO 978 * destination ring ID from the msdu desc info 979 * 980 * @ hal_soc_hdl : HAL version of the SOC pointer 981 * @msdu_link_desc : Opaque cookie pointer used by HAL to get to 982 * the current descriptor 983 * 984 * Return: dst_ind (REO destination ring ID) 985 */ 986 static inline uint32_t 987 hal_rx_msdu_reo_dst_ind_get_li(hal_soc_handle_t hal_soc_hdl, 988 void *msdu_link_desc) 989 { 990 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 991 struct rx_msdu_details *msdu_details; 992 struct rx_msdu_desc_info *msdu_desc_info; 993 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 994 uint32_t dst_ind; 995 996 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 997 998 /* The first msdu in the link should exsist */ 999 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0], 1000 hal_soc); 1001 dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info); 1002 return dst_ind; 1003 } 1004 1005 static inline void 1006 hal_mpdu_desc_info_set_li(hal_soc_handle_t hal_soc_hdl, 1007 void *ent_desc, 1008 void *mpdu_desc, 1009 uint32_t seq_no) 1010 { 1011 struct rx_mpdu_desc_info *mpdu_desc_info = 1012 (struct rx_mpdu_desc_info *)mpdu_desc; 1013 1014 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1015 MSDU_COUNT, 0x1); 1016 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1017 MPDU_SEQUENCE_NUMBER, seq_no); 1018 /* unset frag bit */ 1019 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1020 FRAGMENT_FLAG, 0x0); 1021 /* set sa/da valid bits */ 1022 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1023 SA_IS_VALID, 0x1); 1024 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1025 DA_IS_VALID, 0x1); 1026 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1027 RAW_MPDU, 0x0); 1028 } 1029 1030 static inline void 1031 hal_msdu_desc_info_set_li(hal_soc_handle_t hal_soc_hdl, 1032 void *msdu_desc, uint32_t dst_ind, 1033 uint32_t nbuf_len) 1034 { 1035 struct rx_msdu_desc_info *msdu_desc_info = 1036 (struct rx_msdu_desc_info *)msdu_desc; 1037 1038 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1039 FIRST_MSDU_IN_MPDU_FLAG, 1); 1040 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1041 LAST_MSDU_IN_MPDU_FLAG, 1); 1042 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1043 MSDU_CONTINUATION, 0x0); 1044 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1045 REO_DESTINATION_INDICATION, 1046 dst_ind); 1047 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1048 MSDU_LENGTH, nbuf_len); 1049 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1050 SA_IS_VALID, 1); 1051 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1052 DA_IS_VALID, 1); 1053 } 1054 1055 static inline 1056 uint8_t *hal_get_reo_ent_desc_qdesc_addr_li(uint8_t *desc) 1057 { 1058 return desc + REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET; 1059 } 1060 1061 static inline 1062 void hal_set_reo_ent_desc_reo_dest_ind_li(uint8_t *desc, uint32_t dst_ind) 1063 { 1064 HAL_RX_FLD_SET(desc, REO_ENTRANCE_RING_5, 1065 REO_DESTINATION_INDICATION, dst_ind); 1066 } 1067 1068 static inline void 1069 hal_rx_wbm_rel_buf_paddr_get_li(hal_ring_desc_t rx_desc, 1070 struct hal_buf_info *buf_info) 1071 { 1072 struct wbm_release_ring *wbm_rel_ring = 1073 (struct wbm_release_ring *)rx_desc; 1074 1075 buf_info->paddr = 1076 (HAL_RX_WBM_BUF_ADDR_31_0_GET(wbm_rel_ring) | 1077 ((uint64_t)(HAL_RX_WBM_BUF_ADDR_39_32_GET(wbm_rel_ring)) << 32)); 1078 1079 buf_info->sw_cookie = HAL_RX_WBM_BUF_COOKIE_GET(wbm_rel_ring); 1080 } 1081 1082 static QDF_STATUS hal_reo_status_update_li(hal_soc_handle_t hal_soc_hdl, 1083 hal_ring_desc_t reo_desc, 1084 void *st_handle, 1085 uint32_t tlv, int *num_ref) 1086 { 1087 union hal_reo_status *reo_status_ref; 1088 1089 reo_status_ref = (union hal_reo_status *)st_handle; 1090 1091 switch (tlv) { 1092 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1093 hal_reo_queue_stats_status_li(reo_desc, 1094 &reo_status_ref->queue_status, 1095 hal_soc_hdl); 1096 *num_ref = reo_status_ref->queue_status.header.cmd_num; 1097 break; 1098 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1099 hal_reo_flush_queue_status_li(reo_desc, 1100 &reo_status_ref->fl_queue_status, 1101 hal_soc_hdl); 1102 *num_ref = reo_status_ref->fl_queue_status.header.cmd_num; 1103 break; 1104 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1105 hal_reo_flush_cache_status_li(reo_desc, 1106 &reo_status_ref->fl_cache_status, 1107 hal_soc_hdl); 1108 *num_ref = reo_status_ref->fl_cache_status.header.cmd_num; 1109 break; 1110 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1111 hal_reo_unblock_cache_status_li( 1112 reo_desc, hal_soc_hdl, 1113 &reo_status_ref->unblk_cache_status); 1114 *num_ref = reo_status_ref->unblk_cache_status.header.cmd_num; 1115 break; 1116 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1117 hal_reo_flush_timeout_list_status_li( 1118 reo_desc, 1119 &reo_status_ref->fl_timeout_status, 1120 hal_soc_hdl); 1121 *num_ref = reo_status_ref->fl_timeout_status.header.cmd_num; 1122 break; 1123 case HAL_REO_DESC_THRES_STATUS_TLV: 1124 hal_reo_desc_thres_reached_status_li( 1125 reo_desc, 1126 &reo_status_ref->thres_status, 1127 hal_soc_hdl); 1128 *num_ref = reo_status_ref->thres_status.header.cmd_num; 1129 break; 1130 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1131 hal_reo_rx_update_queue_status_li( 1132 reo_desc, 1133 &reo_status_ref->rx_queue_status, 1134 hal_soc_hdl); 1135 *num_ref = reo_status_ref->rx_queue_status.header.cmd_num; 1136 break; 1137 default: 1138 QDF_TRACE(QDF_MODULE_ID_DP_REO, QDF_TRACE_LEVEL_WARN, 1139 "hal_soc %pK: no handler for TLV:%d", 1140 hal_soc_hdl, tlv); 1141 return QDF_STATUS_E_FAILURE; 1142 } /* switch */ 1143 1144 return QDF_STATUS_SUCCESS; 1145 } 1146 1147 /** 1148 * hal_get_idle_link_bm_id_li() - Get idle link BM id from chid_id 1149 * @chip_id: mlo chip_id 1150 * 1151 * Returns: RBM ID 1152 */ 1153 static uint8_t hal_get_idle_link_bm_id_li(uint8_t chip_id) 1154 { 1155 return WBM_IDLE_DESC_LIST; 1156 } 1157 1158 /** 1159 * hal_hw_txrx_default_ops_attach_li() - Attach the default hal ops for 1160 * lithium chipsets. 1161 * @hal_soc_hdl: HAL soc handle 1162 * 1163 * Return: None 1164 */ 1165 void hal_hw_txrx_default_ops_attach_li(struct hal_soc *hal_soc) 1166 { 1167 hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_li; 1168 hal_soc->ops->hal_get_rx_max_ba_window = 1169 hal_get_rx_max_ba_window_li; 1170 hal_soc->ops->hal_set_link_desc_addr = hal_set_link_desc_addr_li; 1171 hal_soc->ops->hal_tx_init_data_ring = hal_tx_init_data_ring_li; 1172 hal_soc->ops->hal_get_ba_aging_timeout = hal_get_ba_aging_timeout_li; 1173 hal_soc->ops->hal_set_ba_aging_timeout = hal_set_ba_aging_timeout_li; 1174 hal_soc->ops->hal_get_reo_reg_base_offset = 1175 hal_get_reo_reg_base_offset_li; 1176 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_li; 1177 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 1178 hal_rx_msdu_is_wlan_mcast_generic_li; 1179 hal_soc->ops->hal_rx_tlv_decap_format_get = 1180 hal_rx_tlv_decap_format_get_li; 1181 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_li; 1182 hal_soc->ops->hal_rx_tlv_get_offload_info = 1183 hal_rx_tlv_get_offload_info_li; 1184 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 1185 hal_rx_attn_phy_ppdu_id_get_li; 1186 hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_attn_msdu_done_get_li; 1187 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1188 hal_rx_msdu_start_msdu_len_get_li; 1189 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_li; 1190 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_li; 1191 1192 hal_soc->ops->hal_rx_reo_buf_paddr_get = hal_rx_reo_buf_paddr_get_li; 1193 hal_soc->ops->hal_rx_msdu_link_desc_set = hal_rx_msdu_link_desc_set_li; 1194 hal_soc->ops->hal_rx_buf_cookie_rbm_get = hal_rx_buf_cookie_rbm_get_li; 1195 hal_soc->ops->hal_rx_ret_buf_manager_get = 1196 hal_rx_ret_buf_manager_get_li; 1197 hal_soc->ops->hal_rxdma_buff_addr_info_set = 1198 hal_rxdma_buff_addr_info_set_li; 1199 hal_soc->ops->hal_rx_msdu_flags_get = hal_rx_msdu_flags_get_li; 1200 hal_soc->ops->hal_rx_get_reo_error_code = hal_rx_get_reo_error_code_li; 1201 hal_soc->ops->hal_gen_reo_remap_val = 1202 hal_gen_reo_remap_val_generic_li; 1203 hal_soc->ops->hal_rx_tlv_csum_err_get = 1204 hal_rx_tlv_csum_err_get_li; 1205 hal_soc->ops->hal_rx_mpdu_desc_info_get = 1206 hal_rx_mpdu_desc_info_get_li; 1207 hal_soc->ops->hal_rx_err_status_get = hal_rx_err_status_get_li; 1208 hal_soc->ops->hal_rx_reo_buf_type_get = hal_rx_reo_buf_type_get_li; 1209 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_li; 1210 hal_soc->ops->hal_rx_wbm_err_src_get = hal_rx_wbm_err_src_get_li; 1211 hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get = 1212 hal_rx_wbm_rel_buf_paddr_get_li; 1213 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1214 hal_rx_priv_info_set_in_tlv_li; 1215 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1216 hal_rx_priv_info_get_from_tlv_li; 1217 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1218 hal_rx_mpdu_info_ampdu_flag_get_li; 1219 hal_soc->ops->hal_rx_tlv_mpdu_len_err_get = 1220 hal_rx_tlv_mpdu_len_err_get_li; 1221 hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get = 1222 hal_rx_tlv_mpdu_fcs_err_get_li; 1223 hal_soc->ops->hal_reo_send_cmd = hal_reo_send_cmd_li; 1224 hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags = 1225 hal_rx_tlv_get_pkt_capture_flags_li; 1226 hal_soc->ops->hal_rx_desc_get_80211_hdr = hal_rx_desc_get_80211_hdr_li; 1227 hal_soc->ops->hal_rx_hw_desc_mpdu_user_id = 1228 hal_rx_hw_desc_mpdu_user_id_li; 1229 hal_soc->ops->hal_reo_qdesc_setup = hal_reo_qdesc_setup_li; 1230 hal_soc->ops->hal_rx_tlv_msdu_len_set = 1231 hal_rx_msdu_start_msdu_len_set_li; 1232 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_li; 1233 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_li; 1234 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_li; 1235 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_li; 1236 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_li; 1237 hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_li; 1238 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_li; 1239 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1240 hal_rx_tlv_decrypt_err_get_li; 1241 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_li; 1242 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 1243 hal_rx_tlv_get_is_decrypted_li; 1244 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_li; 1245 hal_soc->ops->hal_rx_msdu_reo_dst_ind_get = 1246 hal_rx_msdu_reo_dst_ind_get_li; 1247 hal_soc->ops->hal_msdu_desc_info_set = hal_msdu_desc_info_set_li; 1248 hal_soc->ops->hal_mpdu_desc_info_set = hal_mpdu_desc_info_set_li; 1249 hal_soc->ops->hal_reo_status_update = hal_reo_status_update_li; 1250 hal_soc->ops->hal_get_tlv_hdr_size = hal_get_tlv_hdr_size_li; 1251 hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr = 1252 hal_get_reo_ent_desc_qdesc_addr_li; 1253 hal_soc->ops->hal_rx_get_qdesc_addr = hal_rx_get_qdesc_addr_li; 1254 hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind = 1255 hal_set_reo_ent_desc_reo_dest_ind_li; 1256 hal_soc->ops->hal_get_idle_link_bm_id = hal_get_idle_link_bm_id_li; 1257 } 1258