1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include "hal_li_api.h" 20 #include "hal_li_hw_headers.h" 21 #include "hal_li_reo.h" 22 23 #include "hal_rx.h" 24 #include "hal_li_rx.h" 25 #include "hal_tx.h" 26 #include <hal_api_mon.h> 27 28 static uint32_t hal_get_reo_qdesc_size_li(uint32_t ba_window_size, int tid) 29 { 30 /* Return descriptor size corresponding to window size of 2 since 31 * we set ba_window_size to 2 while setting up REO descriptors as 32 * a WAR to get 2k jump exception aggregates are received without 33 * a BA session. 34 */ 35 if (ba_window_size <= 1) { 36 if (tid != HAL_NON_QOS_TID) 37 return sizeof(struct rx_reo_queue) + 38 sizeof(struct rx_reo_queue_ext); 39 else 40 return sizeof(struct rx_reo_queue); 41 } 42 43 if (ba_window_size <= 105) 44 return sizeof(struct rx_reo_queue) + 45 sizeof(struct rx_reo_queue_ext); 46 47 if (ba_window_size <= 210) 48 return sizeof(struct rx_reo_queue) + 49 (2 * sizeof(struct rx_reo_queue_ext)); 50 51 return sizeof(struct rx_reo_queue) + 52 (3 * sizeof(struct rx_reo_queue_ext)); 53 } 54 55 void hal_set_link_desc_addr_li(void *desc, uint32_t cookie, 56 qdf_dma_addr_t link_desc_paddr) 57 { 58 uint32_t *buf_addr = (uint32_t *)desc; 59 60 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, 61 link_desc_paddr & 0xffffffff); 62 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 63 (uint64_t)link_desc_paddr >> 32); 64 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, RETURN_BUFFER_MANAGER, 65 WBM_IDLE_DESC_LIST); 66 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, 67 cookie); 68 } 69 70 void hal_tx_init_data_ring_li(hal_soc_handle_t hal_soc_hdl, 71 hal_ring_handle_t hal_ring_hdl) 72 { 73 uint8_t *desc_addr; 74 struct hal_srng_params srng_params; 75 uint32_t desc_size; 76 uint32_t num_desc; 77 78 hal_get_srng_params(hal_soc_hdl, hal_ring_hdl, &srng_params); 79 80 desc_addr = (uint8_t *)srng_params.ring_base_vaddr; 81 desc_size = sizeof(struct tcl_data_cmd); 82 num_desc = srng_params.num_entries; 83 84 while (num_desc) { 85 HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, 86 desc_size); 87 desc_addr += (desc_size + sizeof(struct tlv_32_hdr)); 88 num_desc--; 89 } 90 } 91 92 /* 93 * hal_rx_msdu_is_wlan_mcast_generic_li(): Check if the buffer is for multicast 94 * address 95 * @nbuf: Network buffer 96 * 97 * Returns: flag to indicate whether the nbuf has MC/BC address 98 */ 99 static uint32_t hal_rx_msdu_is_wlan_mcast_generic_li(qdf_nbuf_t nbuf) 100 { 101 uint8_t *buf = qdf_nbuf_data(nbuf); 102 103 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 104 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 105 106 return rx_attn->mcast_bcast; 107 } 108 109 /** 110 * hal_rx_tlv_decap_format_get_li() - Get packet decap format from the TLV 111 * @hw_desc_addr: rx tlv desc 112 * 113 * Return: pkt decap format 114 */ 115 static uint32_t hal_rx_tlv_decap_format_get_li(void *hw_desc_addr) 116 { 117 struct rx_msdu_start *rx_msdu_start; 118 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 119 120 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 121 122 return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); 123 } 124 125 /** 126 * hal_rx_dump_pkt_tlvs_li(): API to print all member elements of 127 * RX TLVs 128 * @ buf: pointer the pkt buffer. 129 * @ dbg_level: log level. 130 * 131 * Return: void 132 */ 133 static void hal_rx_dump_pkt_tlvs_li(hal_soc_handle_t hal_soc_hdl, 134 uint8_t *buf, uint8_t dbg_level) 135 { 136 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 137 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 138 struct rx_mpdu_start *mpdu_start = 139 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 140 struct rx_msdu_start *msdu_start = 141 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 142 struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 143 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 144 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 145 146 hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level); 147 hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc); 148 hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level); 149 hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level); 150 hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level); 151 hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level); 152 } 153 154 /** 155 * hal_rx_tlv_get_offload_info_li() - Get the offload info from TLV 156 * @rx_tlv: RX tlv start address in buffer 157 * @offload_info: Buffer to store the offload info 158 * 159 * Return: 0 on success, -EINVAL on failure. 160 */ 161 static int 162 hal_rx_tlv_get_offload_info_li(uint8_t *rx_tlv, 163 struct hal_offload_info *offload_info) 164 { 165 offload_info->flow_id = HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(rx_tlv); 166 offload_info->ipv6_proto = HAL_RX_TLV_GET_IPV6(rx_tlv); 167 offload_info->lro_eligible = HAL_RX_TLV_GET_LRO_ELIGIBLE(rx_tlv); 168 offload_info->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(rx_tlv); 169 170 if (offload_info->tcp_proto) { 171 offload_info->tcp_pure_ack = 172 HAL_RX_TLV_GET_TCP_PURE_ACK(rx_tlv); 173 offload_info->tcp_offset = HAL_RX_TLV_GET_TCP_OFFSET(rx_tlv); 174 offload_info->tcp_win = HAL_RX_TLV_GET_TCP_WIN(rx_tlv); 175 offload_info->tcp_seq_num = HAL_RX_TLV_GET_TCP_SEQ(rx_tlv); 176 offload_info->tcp_ack_num = HAL_RX_TLV_GET_TCP_ACK(rx_tlv); 177 } 178 return 0; 179 } 180 181 /* 182 * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value 183 * from rx attention 184 * @buf: pointer to rx_pkt_tlvs 185 * 186 * Return: phy_ppdu_id 187 */ 188 static uint16_t hal_rx_attn_phy_ppdu_id_get_li(uint8_t *buf) 189 { 190 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 191 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 192 uint16_t phy_ppdu_id; 193 194 phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn); 195 196 return phy_ppdu_id; 197 } 198 199 /** 200 * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length 201 * from rx_msdu_start TLV 202 * 203 * @ buf: pointer to the start of RX PKT TLV headers 204 * Return: msdu length 205 */ 206 static uint32_t hal_rx_msdu_start_msdu_len_get_li(uint8_t *buf) 207 { 208 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 209 struct rx_msdu_start *msdu_start = 210 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 211 uint32_t msdu_len; 212 213 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 214 215 return msdu_len; 216 } 217 218 /** 219 * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field 220 * 221 * @nbuf: Network buffer 222 * Returns: rx more fragment bit 223 * 224 */ 225 static uint16_t hal_rx_get_frame_ctrl_field_li(uint8_t *buf) 226 { 227 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 228 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 229 uint16_t frame_ctrl = 0; 230 231 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 232 233 return frame_ctrl; 234 } 235 236 /** 237 * hal_rx_get_proto_params_li() - Get l4 proto values from TLV 238 * @buf: rx tlv address 239 * @proto_params: Buffer to store proto parameters 240 * 241 * Return: 0 on success. 242 */ 243 static int hal_rx_get_proto_params_li(uint8_t *buf, void *proto_params) 244 { 245 struct hal_proto_params *param = 246 (struct hal_proto_params *)proto_params; 247 248 param->tcp_proto = HAL_RX_TLV_GET_IP_OFFSET(buf); 249 param->udp_proto = HAL_RX_TLV_GET_UDP_PROTO(buf); 250 param->ipv6_proto = HAL_RX_TLV_GET_IPV6(buf); 251 252 return 0; 253 } 254 255 /** 256 * hal_rx_get_l3_l4_offsets_li() - Get l3/l4 header offset from TLV 257 * @buf: rx tlv start address 258 * @l3_hdr_offset: buffer to store l3 offset 259 * @l4_hdr_offset: buffer to store l4 offset 260 * 261 * Return: 0 on success. 262 */ 263 static int hal_rx_get_l3_l4_offsets_li(uint8_t *buf, uint32_t *l3_hdr_offset, 264 uint32_t *l4_hdr_offset) 265 { 266 *l3_hdr_offset = HAL_RX_TLV_GET_IP_OFFSET(buf); 267 *l4_hdr_offset = HAL_RX_TLV_GET_TCP_OFFSET(buf); 268 269 return 0; 270 } 271 272 /** 273 * hal_rx_tlv_get_pn_num_li() - Get packet number from RX TLV 274 * @buf: rx tlv address 275 * @pn_num: buffer to store packet number 276 * 277 * Return: None 278 */ 279 static inline void hal_rx_tlv_get_pn_num_li(uint8_t *buf, uint64_t *pn_num) 280 { 281 struct rx_pkt_tlvs *rx_pkt_tlv = 282 (struct rx_pkt_tlvs *)buf; 283 struct rx_mpdu_info *rx_mpdu_info_details = 284 &rx_pkt_tlv->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 285 286 pn_num[0] = rx_mpdu_info_details->pn_31_0; 287 pn_num[0] |= 288 ((uint64_t)rx_mpdu_info_details->pn_63_32 << 32); 289 pn_num[1] = rx_mpdu_info_details->pn_95_64; 290 pn_num[1] |= 291 ((uint64_t)rx_mpdu_info_details->pn_127_96 << 32); 292 } 293 294 #ifdef NO_RX_PKT_HDR_TLV 295 /** 296 * hal_rx_pkt_hdr_get_li() - Get rx packet header start address. 297 * @buf: packet start address 298 * 299 * Return: packet data start address. 300 */ 301 static inline uint8_t *hal_rx_pkt_hdr_get_li(uint8_t *buf) 302 { 303 return buf + RX_PKT_TLVS_LEN; 304 } 305 #else 306 static inline uint8_t *hal_rx_pkt_hdr_get_li(uint8_t *buf) 307 { 308 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 309 310 return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr; 311 } 312 #endif 313 314 /** 315 * hal_rx_priv_info_set_in_tlv_li(): Save the private info to 316 * the reserved bytes of rx_tlv_hdr 317 * @buf: start of rx_tlv_hdr 318 * @priv_data: hal_wbm_err_desc_info structure 319 * @len: length of the private data 320 * Return: void 321 */ 322 static inline void 323 hal_rx_priv_info_set_in_tlv_li(uint8_t *buf, uint8_t *priv_data, 324 uint32_t len) 325 { 326 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 327 uint32_t copy_len = (len > RX_PADDING0_BYTES) ? 328 RX_PADDING0_BYTES : len; 329 330 qdf_mem_copy(pkt_tlvs->rx_padding0, priv_data, copy_len); 331 } 332 333 /** 334 * hal_rx_priv_info_get_from_tlv_li(): retrieve the private data from 335 * the reserved bytes of rx_tlv_hdr. 336 * @buf: start of rx_tlv_hdr 337 * @priv_data: hal_wbm_err_desc_info structure 338 * @len: length of the private data 339 * Return: void 340 */ 341 static inline void 342 hal_rx_priv_info_get_from_tlv_li(uint8_t *buf, uint8_t *priv_data, 343 uint32_t len) 344 { 345 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 346 uint32_t copy_len = (len > RX_PADDING0_BYTES) ? 347 RX_PADDING0_BYTES : len; 348 349 qdf_mem_copy(priv_data, pkt_tlvs->rx_padding0, copy_len); 350 } 351 352 /** 353 * hal_rx_get_tlv_size_generic_li() - Get rx packet tlv size 354 * @rx_pkt_tlv_size: TLV size for regular RX packets 355 * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets 356 * 357 * Return: size of rx pkt tlv before the actual data 358 */ 359 static void hal_rx_get_tlv_size_generic_li(uint16_t *rx_pkt_tlv_size, 360 uint16_t *rx_mon_pkt_tlv_size) 361 { 362 *rx_pkt_tlv_size = RX_PKT_TLVS_LEN; 363 *rx_mon_pkt_tlv_size = SIZE_OF_MONITOR_TLV; 364 } 365 366 /** 367 * hal_rx_wbm_err_src_get_li() - Get WBM error source from descriptor 368 * @ring_desc: ring descriptor 369 * 370 * Return: wbm error source 371 */ 372 uint32_t hal_rx_wbm_err_src_get_li(hal_ring_desc_t ring_desc) 373 { 374 return HAL_WBM2SW_RELEASE_SRC_GET(ring_desc); 375 } 376 377 /** 378 * hal_rx_ret_buf_manager_get_li() - Get return buffer manager from ring desc 379 * @ring_desc: ring descriptor 380 * 381 * Return: rbm 382 */ 383 uint8_t hal_rx_ret_buf_manager_get_li(hal_ring_desc_t ring_desc) 384 { 385 /* 386 * The following macro takes buf_addr_info as argument, 387 * but since buf_addr_info is the first field in ring_desc 388 * Hence the following call is OK 389 */ 390 return HAL_RX_BUF_RBM_GET(ring_desc); 391 } 392 393 /** 394 * hal_rx_reo_buf_paddr_get_li: Gets the physical address and 395 * cookie from the REO destination ring element 396 * 397 * @ rx_desc: Opaque cookie pointer used by HAL to get to 398 * the current descriptor 399 * @ buf_info: structure to return the buffer information 400 * Return: void 401 */ 402 static void hal_rx_reo_buf_paddr_get_li(hal_ring_desc_t rx_desc, 403 struct hal_buf_info *buf_info) 404 { 405 struct reo_destination_ring *reo_ring = 406 (struct reo_destination_ring *)rx_desc; 407 408 buf_info->paddr = 409 (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) | 410 ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32)); 411 buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring); 412 } 413 414 /** 415 * hal_rx_msdu_link_desc_set_li: Retrieves MSDU Link Descriptor to WBM 416 * 417 * @ hal_soc_hdl : HAL version of the SOC pointer 418 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor 419 * @ buf_addr_info : void pointer to the buffer_addr_info 420 * @ bm_action : put in IDLE list or release to MSDU_LIST 421 * 422 * Return: void 423 */ 424 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 425 static void hal_rx_msdu_link_desc_set_li(hal_soc_handle_t hal_soc_hdl, 426 void *src_srng_desc, 427 hal_buff_addrinfo_t buf_addr_info, 428 uint8_t bm_action) 429 { 430 /* 431 * The offsets for fields used in this function are same in 432 * wbm_release_ring for Lithium and wbm_release_ring_tx 433 * for Beryllium. hence we can use wbm_release_ring directly. 434 */ 435 struct wbm_release_ring *wbm_rel_srng = 436 (struct wbm_release_ring *)src_srng_desc; 437 uint32_t addr_31_0; 438 uint8_t addr_39_32; 439 440 /* Structure copy !!! */ 441 wbm_rel_srng->released_buff_or_desc_addr_info = 442 *(struct buffer_addr_info *)buf_addr_info; 443 444 addr_31_0 = 445 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0; 446 addr_39_32 = 447 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32; 448 449 HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, 450 RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW); 451 HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, BM_ACTION, 452 bm_action); 453 HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, 454 BUFFER_OR_DESC_TYPE, 455 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC); 456 457 /* WBM error is indicated when any of the link descriptors given to 458 * WBM has a NULL address, and one those paths is the link descriptors 459 * released from host after processing RXDMA errors, 460 * or from Rx defrag path, and we want to add an assert here to ensure 461 * host is not releasing descriptors with NULL address. 462 */ 463 464 if (qdf_unlikely(!addr_31_0 && !addr_39_32)) { 465 hal_dump_wbm_rel_desc(src_srng_desc); 466 qdf_assert_always(0); 467 } 468 } 469 470 static 471 void hal_rx_buf_cookie_rbm_get_li(uint32_t *buf_addr_info_hdl, 472 hal_buf_info_t buf_info_hdl) 473 { 474 struct hal_buf_info *buf_info = 475 (struct hal_buf_info *)buf_info_hdl; 476 struct buffer_addr_info *buf_addr_info = 477 (struct buffer_addr_info *)buf_addr_info_hdl; 478 479 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 480 /* 481 * buffer addr info is the first member of ring desc, so the typecast 482 * can be done. 483 */ 484 buf_info->rbm = hal_rx_ret_buf_manager_get_li 485 ((hal_ring_desc_t)buf_addr_info); 486 } 487 488 /** 489 * hal_rx_msdu_link_desc_get(): API to get the MSDU information 490 * from the MSDU link descriptor 491 * 492 * @ hal_soc_hdl : HAL version of the SOC pointer 493 * @msdu_link_desc: Opaque pointer used by HAL to get to the 494 * MSDU link descriptor (struct rx_msdu_link) 495 * 496 * @msdu_list: Return the list of MSDUs contained in this link descriptor 497 * 498 * @num_msdus: Number of MSDUs in the MPDU 499 * 500 * Return: void 501 */ 502 static inline void hal_rx_msdu_list_get_li(hal_soc_handle_t hal_soc_hdl, 503 void *msdu_link_desc, 504 void *hal_msdu_list, 505 uint16_t *num_msdus) 506 { 507 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 508 struct rx_msdu_details *msdu_details; 509 struct rx_msdu_desc_info *msdu_desc_info; 510 struct hal_rx_msdu_list *msdu_list = hal_msdu_list; 511 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 512 int i; 513 struct hal_buf_info buf_info; 514 515 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 516 517 hal_debug("msdu_link=%pK msdu_details=%pK", msdu_link, msdu_details); 518 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 519 /* num_msdus received in mpdu descriptor may be incorrect 520 * sometimes due to HW issue. Check msdu buffer address also 521 */ 522 if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET( 523 &msdu_details[i].buffer_addr_info_details) == 0)) 524 break; 525 if (HAL_RX_BUFFER_ADDR_31_0_GET( 526 &msdu_details[i].buffer_addr_info_details) == 0) { 527 /* set the last msdu bit in the prev msdu_desc_info */ 528 msdu_desc_info = 529 hal_rx_msdu_desc_info_get_ptr 530 (&msdu_details[i - 1], hal_soc); 531 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 532 break; 533 } 534 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 535 hal_soc); 536 537 /* set first MSDU bit or the last MSDU bit */ 538 if (!i) 539 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 540 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 541 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 542 543 msdu_list->msdu_info[i].msdu_flags = 544 hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info); 545 msdu_list->msdu_info[i].msdu_len = 546 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 547 548 /* addr field in buf_info will not be valid */ 549 hal_rx_buf_cookie_rbm_get_li( 550 (uint32_t *) 551 &msdu_details[i].buffer_addr_info_details, 552 &buf_info); 553 msdu_list->sw_cookie[i] = buf_info.sw_cookie; 554 msdu_list->rbm[i] = buf_info.rbm; 555 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 556 &msdu_details[i].buffer_addr_info_details) | 557 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 558 &msdu_details[i].buffer_addr_info_details) << 32; 559 hal_debug("i=%d sw_cookie=%d", i, msdu_list->sw_cookie[i]); 560 } 561 *num_msdus = i; 562 } 563 564 /* 565 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 566 * rxdma ring entry. 567 * @rxdma_entry: descriptor entry 568 * @paddr: physical address of nbuf data pointer. 569 * @cookie: SW cookie used as a index to SW rx desc. 570 * @manager: who owns the nbuf (host, NSS, etc...). 571 * 572 */ 573 static void hal_rxdma_buff_addr_info_set_li(void *rxdma_entry, 574 qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager) 575 { 576 uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff); 577 uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32; 578 579 HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo); 580 HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi); 581 HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie); 582 HAL_RXDMA_MANAGER_SET(rxdma_entry, manager); 583 } 584 585 /** 586 * hal_rx_get_reo_error_code_li() - Get REO error code from ring desc 587 * @rx_desc: rx descriptor 588 * 589 * Return: REO error code 590 */ 591 static uint32_t hal_rx_get_reo_error_code_li(hal_ring_desc_t rx_desc) 592 { 593 struct reo_destination_ring *reo_desc = 594 (struct reo_destination_ring *)rx_desc; 595 596 return HAL_RX_REO_ERROR_GET(reo_desc); 597 } 598 599 /** 600 * hal_gen_reo_remap_val_generic_li() - Generate the reo map value 601 * @ix0_map: mapping values for reo 602 * 603 * Return: IX0 reo remap register value to be written 604 */ 605 static uint32_t 606 hal_gen_reo_remap_val_generic_li(enum hal_reo_remap_reg remap_reg, 607 uint8_t *ix0_map) 608 { 609 uint32_t ix_val = 0; 610 611 switch (remap_reg) { 612 case HAL_REO_REMAP_REG_IX0: 613 ix_val = HAL_REO_REMAP_IX0(ix0_map[0], 0) | 614 HAL_REO_REMAP_IX0(ix0_map[1], 1) | 615 HAL_REO_REMAP_IX0(ix0_map[2], 2) | 616 HAL_REO_REMAP_IX0(ix0_map[3], 3) | 617 HAL_REO_REMAP_IX0(ix0_map[4], 4) | 618 HAL_REO_REMAP_IX0(ix0_map[5], 5) | 619 HAL_REO_REMAP_IX0(ix0_map[6], 6) | 620 HAL_REO_REMAP_IX0(ix0_map[7], 7); 621 break; 622 case HAL_REO_REMAP_REG_IX2: 623 ix_val = HAL_REO_REMAP_IX2(ix0_map[0], 16) | 624 HAL_REO_REMAP_IX2(ix0_map[1], 17) | 625 HAL_REO_REMAP_IX2(ix0_map[2], 18) | 626 HAL_REO_REMAP_IX2(ix0_map[3], 19) | 627 HAL_REO_REMAP_IX2(ix0_map[4], 20) | 628 HAL_REO_REMAP_IX2(ix0_map[5], 21) | 629 HAL_REO_REMAP_IX2(ix0_map[6], 22) | 630 HAL_REO_REMAP_IX2(ix0_map[7], 23); 631 break; 632 default: 633 break; 634 } 635 636 return ix_val; 637 } 638 639 /** 640 * hal_rx_tlv_csum_err_get_li() - Get IP and tcp-udp checksum fail flag 641 * @rx_tlv_hdr: start address of rx_tlv_hdr 642 * @ip_csum_err: buffer to return ip_csum_fail flag 643 * @tcp_udp_csum_fail: placeholder to return tcp-udp checksum fail flag 644 * 645 * Return: None 646 */ 647 static inline void 648 hal_rx_tlv_csum_err_get_li(uint8_t *rx_tlv_hdr, uint32_t *ip_csum_err, 649 uint32_t *tcp_udp_csum_err) 650 { 651 *ip_csum_err = hal_rx_attn_ip_cksum_fail_get(rx_tlv_hdr); 652 *tcp_udp_csum_err = hal_rx_attn_tcp_udp_cksum_fail_get(rx_tlv_hdr); 653 } 654 655 static 656 void hal_rx_tlv_get_pkt_capture_flags_li(uint8_t *rx_tlv_pkt_hdr, 657 struct hal_rx_pkt_capture_flags *flags) 658 { 659 struct rx_pkt_tlvs *rx_tlv_hdr = (struct rx_pkt_tlvs *)rx_tlv_pkt_hdr; 660 struct rx_attention *rx_attn = &rx_tlv_hdr->attn_tlv.rx_attn; 661 struct rx_mpdu_start *mpdu_start = 662 &rx_tlv_hdr->mpdu_start_tlv.rx_mpdu_start; 663 struct rx_mpdu_end *mpdu_end = &rx_tlv_hdr->mpdu_end_tlv.rx_mpdu_end; 664 struct rx_msdu_start *msdu_start = 665 &rx_tlv_hdr->msdu_start_tlv.rx_msdu_start; 666 667 flags->encrypt_type = mpdu_start->rx_mpdu_info_details.encrypt_type; 668 flags->fcs_err = mpdu_end->fcs_err; 669 flags->fragment_flag = rx_attn->fragment_flag; 670 flags->chan_freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 671 flags->rssi_comb = HAL_RX_MSDU_START_RSSI_GET(msdu_start); 672 flags->tsft = msdu_start->ppdu_start_timestamp; 673 } 674 675 static uint8_t hal_rx_err_status_get_li(hal_ring_desc_t rx_desc) 676 { 677 return HAL_RX_ERROR_STATUS_GET(rx_desc); 678 } 679 680 static uint8_t hal_rx_reo_buf_type_get_li(hal_ring_desc_t rx_desc) 681 { 682 return HAL_RX_REO_BUF_TYPE_GET(rx_desc); 683 } 684 685 static inline bool 686 hal_rx_mpdu_info_ampdu_flag_get_li(uint8_t *buf) 687 { 688 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 689 struct rx_mpdu_start *mpdu_start = 690 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 691 692 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 693 bool ampdu_flag; 694 695 ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info); 696 697 return ampdu_flag; 698 } 699 700 static 701 uint32_t hal_rx_tlv_mpdu_len_err_get_li(void *hw_desc_addr) 702 { 703 struct rx_attention *rx_attn; 704 struct rx_mon_pkt_tlvs *rx_desc = 705 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 706 707 rx_attn = &rx_desc->attn_tlv.rx_attn; 708 709 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR); 710 } 711 712 static 713 uint32_t hal_rx_tlv_mpdu_fcs_err_get_li(void *hw_desc_addr) 714 { 715 struct rx_attention *rx_attn; 716 struct rx_mon_pkt_tlvs *rx_desc = 717 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 718 719 rx_attn = &rx_desc->attn_tlv.rx_attn; 720 721 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR); 722 } 723 724 #ifdef NO_RX_PKT_HDR_TLV 725 static uint8_t *hal_rx_desc_get_80211_hdr_li(void *hw_desc_addr) 726 { 727 uint8_t *rx_pkt_hdr; 728 struct rx_mon_pkt_tlvs *rx_desc = 729 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 730 731 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 732 733 return rx_pkt_hdr; 734 } 735 #else 736 static uint8_t *hal_rx_desc_get_80211_hdr_li(void *hw_desc_addr) 737 { 738 uint8_t *rx_pkt_hdr; 739 740 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 741 742 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 743 744 return rx_pkt_hdr; 745 } 746 #endif 747 748 static uint32_t hal_rx_hw_desc_mpdu_user_id_li(void *hw_desc_addr) 749 { 750 struct rx_mon_pkt_tlvs *rx_desc = 751 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 752 uint32_t user_id; 753 754 user_id = HAL_RX_GET_USER_TLV32_USERID( 755 &rx_desc->mpdu_start_tlv); 756 757 return user_id; 758 } 759 760 /** 761 * hal_rx_msdu_start_msdu_len_set_li(): API to set the MSDU length 762 * from rx_msdu_start TLV 763 * 764 * @buf: pointer to the start of RX PKT TLV headers 765 * @len: msdu length 766 * 767 * Return: none 768 */ 769 static inline void 770 hal_rx_msdu_start_msdu_len_set_li(uint8_t *buf, uint32_t len) 771 { 772 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 773 struct rx_msdu_start *msdu_start = 774 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 775 void *wrd1; 776 777 wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET; 778 *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK); 779 *(uint32_t *)wrd1 |= len; 780 } 781 782 /* 783 * hal_rx_tlv_bw_get_li(): API to get the Bandwidth 784 * Interval from rx_msdu_start 785 * 786 * @buf: pointer to the start of RX PKT TLV header 787 * Return: uint32_t(bw) 788 */ 789 static inline uint32_t hal_rx_tlv_bw_get_li(uint8_t *buf) 790 { 791 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 792 struct rx_msdu_start *msdu_start = 793 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 794 uint32_t bw; 795 796 bw = HAL_RX_MSDU_START_BW_GET(msdu_start); 797 798 return bw; 799 } 800 801 /* 802 * hal_rx_tlv_get_freq_li(): API to get the frequency of operating channel 803 * from rx_msdu_start 804 * 805 * @buf: pointer to the start of RX PKT TLV header 806 * Return: uint32_t(frequency) 807 */ 808 static inline uint32_t 809 hal_rx_tlv_get_freq_li(uint8_t *buf) 810 { 811 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 812 struct rx_msdu_start *msdu_start = 813 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 814 uint32_t freq; 815 816 freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 817 818 return freq; 819 } 820 821 /** 822 * hal_rx_tlv_sgi_get_li(): API to get the Short Gaurd 823 * Interval from rx_msdu_start TLV 824 * 825 * @buf: pointer to the start of RX PKT TLV headers 826 * Return: uint32_t(sgi) 827 */ 828 static inline uint32_t 829 hal_rx_tlv_sgi_get_li(uint8_t *buf) 830 { 831 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 832 struct rx_msdu_start *msdu_start = 833 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 834 uint32_t sgi; 835 836 sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start); 837 838 return sgi; 839 } 840 841 /** 842 * hal_rx_tlv_rate_mcs_get_li(): API to get the MCS rate 843 * from rx_msdu_start TLV 844 * 845 * @buf: pointer to the start of RX PKT TLV headers 846 * Return: uint32_t(rate_mcs) 847 */ 848 static inline uint32_t 849 hal_rx_tlv_rate_mcs_get_li(uint8_t *buf) 850 { 851 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 852 struct rx_msdu_start *msdu_start = 853 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 854 uint32_t rate_mcs; 855 856 rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start); 857 858 return rate_mcs; 859 } 860 861 /* 862 * hal_rx_tlv_get_pkt_type_li(): API to get the pkt type 863 * from rx_msdu_start 864 * 865 * @buf: pointer to the start of RX PKT TLV header 866 * Return: uint32_t(pkt type) 867 */ 868 869 static inline uint32_t hal_rx_tlv_get_pkt_type_li(uint8_t *buf) 870 { 871 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 872 struct rx_msdu_start *msdu_start = 873 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 874 uint32_t pkt_type; 875 876 pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start); 877 878 return pkt_type; 879 } 880 881 /** 882 * hal_rx_tlv_mic_err_get_li(): API to get the MIC ERR 883 * from rx_mpdu_end TLV 884 * 885 * @buf: pointer to the start of RX PKT TLV headers 886 * Return: uint32_t(mic_err) 887 */ 888 static inline uint32_t 889 hal_rx_tlv_mic_err_get_li(uint8_t *buf) 890 { 891 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 892 struct rx_mpdu_end *mpdu_end = 893 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 894 uint32_t mic_err; 895 896 mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end); 897 898 return mic_err; 899 } 900 901 /** 902 * hal_rx_tlv_decrypt_err_get_li(): API to get the Decrypt ERR 903 * from rx_mpdu_end TLV 904 * 905 * @buf: pointer to the start of RX PKT TLV headers 906 * Return: uint32_t(decrypt_err) 907 */ 908 static inline uint32_t 909 hal_rx_tlv_decrypt_err_get_li(uint8_t *buf) 910 { 911 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 912 struct rx_mpdu_end *mpdu_end = 913 &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; 914 uint32_t decrypt_err; 915 916 decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end); 917 918 return decrypt_err; 919 } 920 921 /* 922 * hal_rx_tlv_first_mpdu_get_li(): get fist_mpdu bit from rx attention 923 * @buf: pointer to rx_pkt_tlvs 924 * 925 * reutm: uint32_t(first_msdu) 926 */ 927 static inline uint32_t 928 hal_rx_tlv_first_mpdu_get_li(uint8_t *buf) 929 { 930 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 931 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 932 uint32_t first_mpdu; 933 934 first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn); 935 936 return first_mpdu; 937 } 938 939 /* 940 * hal_rx_msdu_get_keyid_li(): API to get the key id if the decrypted packet 941 * from rx_msdu_end 942 * 943 * @buf: pointer to the start of RX PKT TLV header 944 * Return: uint32_t(key id) 945 */ 946 static inline uint8_t 947 hal_rx_msdu_get_keyid_li(uint8_t *buf) 948 { 949 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 950 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 951 uint32_t keyid_octet; 952 953 keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end); 954 955 return keyid_octet & 0x3; 956 } 957 958 /* 959 * hal_rx_tlv_get_is_decrypted_li(): API to get the decrypt status of the 960 * packet from rx_attention 961 * 962 * @buf: pointer to the start of RX PKT TLV header 963 * Return: uint32_t(decryt status) 964 */ 965 static inline uint32_t 966 hal_rx_tlv_get_is_decrypted_li(uint8_t *buf) 967 { 968 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 969 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 970 uint32_t is_decrypt = 0; 971 uint32_t decrypt_status; 972 973 decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn); 974 975 if (!decrypt_status) 976 is_decrypt = 1; 977 978 return is_decrypt; 979 } 980 981 /** 982 * hal_rx_msdu_reo_dst_ind_get_li: Gets the REO 983 * destination ring ID from the msdu desc info 984 * 985 * @ hal_soc_hdl : HAL version of the SOC pointer 986 * @msdu_link_desc : Opaque cookie pointer used by HAL to get to 987 * the current descriptor 988 * 989 * Return: dst_ind (REO destination ring ID) 990 */ 991 static inline uint32_t 992 hal_rx_msdu_reo_dst_ind_get_li(hal_soc_handle_t hal_soc_hdl, 993 void *msdu_link_desc) 994 { 995 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 996 struct rx_msdu_details *msdu_details; 997 struct rx_msdu_desc_info *msdu_desc_info; 998 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 999 uint32_t dst_ind; 1000 1001 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 1002 1003 /* The first msdu in the link should exsist */ 1004 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0], 1005 hal_soc); 1006 dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info); 1007 return dst_ind; 1008 } 1009 1010 static inline void 1011 hal_mpdu_desc_info_set_li(hal_soc_handle_t hal_soc_hdl, 1012 void *mpdu_desc, uint32_t seq_no) 1013 { 1014 struct rx_mpdu_desc_info *mpdu_desc_info = 1015 (struct rx_mpdu_desc_info *)mpdu_desc; 1016 1017 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1018 MSDU_COUNT, 0x1); 1019 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1020 MPDU_SEQUENCE_NUMBER, seq_no); 1021 /* unset frag bit */ 1022 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1023 FRAGMENT_FLAG, 0x0); 1024 /* set sa/da valid bits */ 1025 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1026 SA_IS_VALID, 0x1); 1027 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1028 DA_IS_VALID, 0x1); 1029 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 1030 RAW_MPDU, 0x0); 1031 } 1032 1033 static inline void 1034 hal_msdu_desc_info_set_li(hal_soc_handle_t hal_soc_hdl, 1035 void *msdu_desc, uint32_t dst_ind, 1036 uint32_t nbuf_len) 1037 { 1038 struct rx_msdu_desc_info *msdu_desc_info = 1039 (struct rx_msdu_desc_info *)msdu_desc; 1040 1041 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1042 FIRST_MSDU_IN_MPDU_FLAG, 1); 1043 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1044 LAST_MSDU_IN_MPDU_FLAG, 1); 1045 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1046 MSDU_CONTINUATION, 0x0); 1047 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1048 REO_DESTINATION_INDICATION, 1049 dst_ind); 1050 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1051 MSDU_LENGTH, nbuf_len); 1052 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1053 SA_IS_VALID, 1); 1054 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 1055 DA_IS_VALID, 1); 1056 } 1057 1058 static QDF_STATUS hal_reo_status_update_li(hal_soc_handle_t hal_soc_hdl, 1059 hal_ring_desc_t reo_desc, 1060 void *st_handle, 1061 uint32_t tlv, int *num_ref) 1062 { 1063 union hal_reo_status *reo_status_ref; 1064 1065 reo_status_ref = (union hal_reo_status *)st_handle; 1066 1067 switch (tlv) { 1068 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1069 hal_reo_queue_stats_status_li(reo_desc, 1070 &reo_status_ref->queue_status, 1071 hal_soc_hdl); 1072 *num_ref = reo_status_ref->queue_status.header.cmd_num; 1073 break; 1074 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1075 hal_reo_flush_queue_status_li(reo_desc, 1076 &reo_status_ref->fl_queue_status, 1077 hal_soc_hdl); 1078 *num_ref = reo_status_ref->fl_queue_status.header.cmd_num; 1079 break; 1080 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1081 hal_reo_flush_cache_status_li(reo_desc, 1082 &reo_status_ref->fl_cache_status, 1083 hal_soc_hdl); 1084 *num_ref = reo_status_ref->fl_cache_status.header.cmd_num; 1085 break; 1086 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1087 hal_reo_unblock_cache_status_li( 1088 reo_desc, hal_soc_hdl, 1089 &reo_status_ref->unblk_cache_status); 1090 *num_ref = reo_status_ref->unblk_cache_status.header.cmd_num; 1091 break; 1092 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1093 hal_reo_flush_timeout_list_status_li( 1094 reo_desc, 1095 &reo_status_ref->fl_timeout_status, 1096 hal_soc_hdl); 1097 *num_ref = reo_status_ref->fl_timeout_status.header.cmd_num; 1098 break; 1099 case HAL_REO_DESC_THRES_STATUS_TLV: 1100 hal_reo_desc_thres_reached_status_li( 1101 reo_desc, 1102 &reo_status_ref->thres_status, 1103 hal_soc_hdl); 1104 *num_ref = reo_status_ref->thres_status.header.cmd_num; 1105 break; 1106 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1107 hal_reo_rx_update_queue_status_li( 1108 reo_desc, 1109 &reo_status_ref->rx_queue_status, 1110 hal_soc_hdl); 1111 *num_ref = reo_status_ref->rx_queue_status.header.cmd_num; 1112 break; 1113 default: 1114 QDF_TRACE(QDF_MODULE_ID_DP_REO, QDF_TRACE_LEVEL_WARN, 1115 "hal_soc %pK: no handler for TLV:%d", 1116 hal_soc_hdl, tlv); 1117 return QDF_STATUS_E_FAILURE; 1118 } /* switch */ 1119 1120 return QDF_STATUS_SUCCESS; 1121 } 1122 1123 /** 1124 * hal_hw_txrx_default_ops_attach_li() - Attach the default hal ops for 1125 * lithium chipsets. 1126 * @hal_soc_hdl: HAL soc handle 1127 * 1128 * Return: None 1129 */ 1130 void hal_hw_txrx_default_ops_attach_li(struct hal_soc *hal_soc) 1131 { 1132 hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_li; 1133 hal_soc->ops->hal_set_link_desc_addr = hal_set_link_desc_addr_li; 1134 hal_soc->ops->hal_tx_init_data_ring = hal_tx_init_data_ring_li; 1135 hal_soc->ops->hal_get_ba_aging_timeout = hal_get_ba_aging_timeout_li; 1136 hal_soc->ops->hal_set_ba_aging_timeout = hal_set_ba_aging_timeout_li; 1137 hal_soc->ops->hal_get_reo_reg_base_offset = 1138 hal_get_reo_reg_base_offset_li; 1139 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_li; 1140 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 1141 hal_rx_msdu_is_wlan_mcast_generic_li; 1142 hal_soc->ops->hal_rx_tlv_decap_format_get = 1143 hal_rx_tlv_decap_format_get_li; 1144 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_li; 1145 hal_soc->ops->hal_rx_tlv_get_offload_info = 1146 hal_rx_tlv_get_offload_info_li; 1147 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 1148 hal_rx_attn_phy_ppdu_id_get_li; 1149 hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_attn_msdu_done_get_li; 1150 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1151 hal_rx_msdu_start_msdu_len_get_li; 1152 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1153 hal_rx_get_frame_ctrl_field_li; 1154 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_li; 1155 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_li; 1156 1157 hal_soc->ops->hal_rx_reo_buf_paddr_get = hal_rx_reo_buf_paddr_get_li; 1158 hal_soc->ops->hal_rx_msdu_link_desc_set = hal_rx_msdu_link_desc_set_li; 1159 hal_soc->ops->hal_rx_buf_cookie_rbm_get = hal_rx_buf_cookie_rbm_get_li; 1160 hal_soc->ops->hal_rx_ret_buf_manager_get = 1161 hal_rx_ret_buf_manager_get_li; 1162 hal_soc->ops->hal_rxdma_buff_addr_info_set = 1163 hal_rxdma_buff_addr_info_set_li; 1164 hal_soc->ops->hal_rx_msdu_flags_get = hal_rx_msdu_flags_get_li; 1165 hal_soc->ops->hal_rx_get_reo_error_code = hal_rx_get_reo_error_code_li; 1166 hal_soc->ops->hal_gen_reo_remap_val = 1167 hal_gen_reo_remap_val_generic_li; 1168 hal_soc->ops->hal_rx_tlv_csum_err_get = 1169 hal_rx_tlv_csum_err_get_li; 1170 hal_soc->ops->hal_rx_mpdu_desc_info_get = 1171 hal_rx_mpdu_desc_info_get_li; 1172 hal_soc->ops->hal_rx_err_status_get = hal_rx_err_status_get_li; 1173 hal_soc->ops->hal_rx_reo_buf_type_get = hal_rx_reo_buf_type_get_li; 1174 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_li; 1175 hal_soc->ops->hal_rx_wbm_err_src_get = hal_rx_wbm_err_src_get_li; 1176 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1177 hal_rx_priv_info_set_in_tlv_li; 1178 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1179 hal_rx_priv_info_get_from_tlv_li; 1180 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1181 hal_rx_mpdu_info_ampdu_flag_get_li; 1182 hal_soc->ops->hal_rx_tlv_mpdu_len_err_get = 1183 hal_rx_tlv_mpdu_len_err_get_li; 1184 hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get = 1185 hal_rx_tlv_mpdu_fcs_err_get_li; 1186 hal_soc->ops->hal_reo_send_cmd = hal_reo_send_cmd_li; 1187 hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags = 1188 hal_rx_tlv_get_pkt_capture_flags_li; 1189 hal_soc->ops->hal_rx_desc_get_80211_hdr = hal_rx_desc_get_80211_hdr_li; 1190 hal_soc->ops->hal_rx_hw_desc_mpdu_user_id = 1191 hal_rx_hw_desc_mpdu_user_id_li; 1192 hal_soc->ops->hal_reo_qdesc_setup = hal_reo_qdesc_setup_li; 1193 hal_soc->ops->hal_rx_tlv_msdu_len_set = 1194 hal_rx_msdu_start_msdu_len_set_li; 1195 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_li; 1196 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_li; 1197 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_li; 1198 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_li; 1199 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_li; 1200 hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_li; 1201 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_li; 1202 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1203 hal_rx_tlv_decrypt_err_get_li; 1204 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_li; 1205 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 1206 hal_rx_tlv_get_is_decrypted_li; 1207 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_li; 1208 hal_soc->ops->hal_rx_msdu_reo_dst_ind_get = 1209 hal_rx_msdu_reo_dst_ind_get_li; 1210 hal_soc->ops->hal_msdu_desc_info_set = hal_msdu_desc_info_set_li; 1211 hal_soc->ops->hal_mpdu_desc_info_set = hal_mpdu_desc_info_set_li; 1212 hal_soc->ops->hal_reo_status_update = hal_reo_status_update_li; 1213 hal_soc->ops->hal_get_tlv_hdr_size = hal_get_tlv_hdr_size_li; 1214 } 1215