1 /* 2 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "qdf_types.h" 21 #include "qdf_util.h" 22 #include "qdf_types.h" 23 #include "qdf_lock.h" 24 #include "qdf_mem.h" 25 #include "qdf_nbuf.h" 26 #include "hal_hw_headers.h" 27 #include "hal_internal.h" 28 #include "hal_api.h" 29 #include "target_type.h" 30 #include "wcss_version.h" 31 #include "qdf_module.h" 32 #include "hal_flow.h" 33 #include "rx_flow_search_entry.h" 34 #include "hal_rx_flow_info.h" 35 #include "hal_be_api.h" 36 #include "reo_destination_ring_with_pn.h" 37 #include "rx_reo_queue_1k.h" 38 39 #include <hal_be_rx.h> 40 41 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 42 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 43 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 44 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 45 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 46 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 47 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 48 PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 49 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 50 PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 51 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 52 PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 53 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 54 PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 59 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 60 PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 61 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 62 PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 63 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 64 PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 65 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 66 PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 67 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 68 PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 69 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 70 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 71 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 72 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 73 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 74 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 75 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 76 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 77 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 78 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 79 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 80 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 81 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 82 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 83 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 84 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 85 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 86 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 87 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 88 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 89 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 90 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 91 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 92 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 94 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 95 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 96 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 97 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 98 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 99 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 100 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 101 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 102 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 103 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 104 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 105 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 106 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 107 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 108 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 109 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 110 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 112 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 113 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 114 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 115 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 116 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 117 118 #include "hal_kiwi_tx.h" 119 #include "hal_kiwi_rx.h" 120 121 #include "hal_be_rx_tlv.h" 122 123 #include <hal_generic_api.h> 124 #include <hal_be_generic_api.h> 125 #include "hal_be_api_mon.h" 126 127 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 128 129 static uint32_t hal_get_link_desc_size_kiwi(void) 130 { 131 return LINK_DESC_SIZE; 132 } 133 134 /** 135 * hal_rx_dump_msdu_end_tlv_kiwi: dump RX msdu_end TLV in structured 136 * human readable format. 137 * @ msdu_end: pointer the msdu_end TLV in pkt. 138 * @ dbg_level: log level. 139 * 140 * Return: void 141 */ 142 #ifdef QCA_WIFI_KIWI_V2 143 static void hal_rx_dump_msdu_end_tlv_kiwi(void *msduend, 144 uint8_t dbg_level) 145 { 146 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 147 148 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 149 "rx_msdu_end tlv (1/5)- " 150 "rxpcu_mpdu_filter_in_category :%x " 151 "sw_frame_group_id :%x " 152 "reserved_0 :%x " 153 "phy_ppdu_id :%x " 154 "ip_hdr_chksum :%x " 155 "reported_mpdu_length :%x " 156 "reserved_1a :%x " 157 "reserved_2a :%x " 158 "cce_super_rule :%x " 159 "cce_classify_not_done_truncate :%x " 160 "cce_classify_not_done_cce_dis :%x " 161 "cumulative_l3_checksum :%x " 162 "rule_indication_31_0 :%x " 163 "ipv6_options_crc :%x " 164 "da_offset :%x " 165 "sa_offset :%x " 166 "da_offset_valid :%x " 167 "sa_offset_valid :%x " 168 "reserved_5a :%x " 169 "l3_type :%x", 170 msdu_end->rxpcu_mpdu_filter_in_category, 171 msdu_end->sw_frame_group_id, 172 msdu_end->reserved_0, 173 msdu_end->phy_ppdu_id, 174 msdu_end->ip_hdr_chksum, 175 msdu_end->reported_mpdu_length, 176 msdu_end->reserved_1a, 177 msdu_end->reserved_2a, 178 msdu_end->cce_super_rule, 179 msdu_end->cce_classify_not_done_truncate, 180 msdu_end->cce_classify_not_done_cce_dis, 181 msdu_end->cumulative_l3_checksum, 182 msdu_end->rule_indication_31_0, 183 msdu_end->ipv6_options_crc, 184 msdu_end->da_offset, 185 msdu_end->sa_offset, 186 msdu_end->da_offset_valid, 187 msdu_end->sa_offset_valid, 188 msdu_end->reserved_5a, 189 msdu_end->l3_type); 190 191 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 192 "rx_msdu_end tlv (2/5)- " 193 "rule_indication_63_32 :%x " 194 "tcp_seq_number :%x " 195 "tcp_ack_number :%x " 196 "tcp_flag :%x " 197 "lro_eligible :%x " 198 "reserved_9a :%x " 199 "window_size :%x " 200 "sa_sw_peer_id :%x " 201 "sa_idx_timeout :%x " 202 "da_idx_timeout :%x " 203 "to_ds :%x " 204 "tid :%x " 205 "sa_is_valid :%x " 206 "da_is_valid :%x " 207 "da_is_mcbc :%x " 208 "l3_header_padding :%x " 209 "first_msdu :%x " 210 "last_msdu :%x " 211 "fr_ds :%x " 212 "ip_chksum_fail_copy :%x " 213 "sa_idx :%x " 214 "da_idx_or_sw_peer_id :%x", 215 msdu_end->rule_indication_63_32, 216 msdu_end->tcp_seq_number, 217 msdu_end->tcp_ack_number, 218 msdu_end->tcp_flag, 219 msdu_end->lro_eligible, 220 msdu_end->reserved_9a, 221 msdu_end->window_size, 222 msdu_end->sa_sw_peer_id, 223 msdu_end->sa_idx_timeout, 224 msdu_end->da_idx_timeout, 225 msdu_end->to_ds, 226 msdu_end->tid, 227 msdu_end->sa_is_valid, 228 msdu_end->da_is_valid, 229 msdu_end->da_is_mcbc, 230 msdu_end->l3_header_padding, 231 msdu_end->first_msdu, 232 msdu_end->last_msdu, 233 msdu_end->fr_ds, 234 msdu_end->ip_chksum_fail_copy, 235 msdu_end->sa_idx, 236 msdu_end->da_idx_or_sw_peer_id); 237 238 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 239 "rx_msdu_end tlv (3/5)- " 240 "msdu_drop :%x " 241 "reo_destination_indication :%x " 242 "flow_idx :%x " 243 "use_ppe :%x " 244 "__reserved_g_0003 :%x " 245 "vlan_ctag_stripped :%x " 246 "vlan_stag_stripped :%x " 247 "fragment_flag :%x " 248 "fse_metadata :%x " 249 "cce_metadata :%x " 250 "tcp_udp_chksum :%x " 251 "aggregation_count :%x " 252 "flow_aggregation_continuation :%x " 253 "fisa_timeout :%x " 254 "tcp_udp_chksum_fail_copy :%x " 255 "msdu_limit_error :%x " 256 "flow_idx_timeout :%x " 257 "flow_idx_invalid :%x " 258 "cce_match :%x " 259 "amsdu_parser_error :%x " 260 "cumulative_ip_length :%x " 261 "key_id_octet :%x " 262 "reserved_16a :%x " 263 "reserved_17a :%x " 264 "service_code :%x " 265 "priority_valid :%x " 266 "intra_bss :%x " 267 "dest_chip_id :%x " 268 "multicast_echo :%x " 269 "wds_learning_event :%x " 270 "wds_roaming_event :%x " 271 "wds_keep_alive_event :%x " 272 "reserved_17b :%x", 273 msdu_end->msdu_drop, 274 msdu_end->reo_destination_indication, 275 msdu_end->flow_idx, 276 msdu_end->use_ppe, 277 msdu_end->__reserved_g_0003, 278 msdu_end->vlan_ctag_stripped, 279 msdu_end->vlan_stag_stripped, 280 msdu_end->fragment_flag, 281 msdu_end->fse_metadata, 282 msdu_end->cce_metadata, 283 msdu_end->tcp_udp_chksum, 284 msdu_end->aggregation_count, 285 msdu_end->flow_aggregation_continuation, 286 msdu_end->fisa_timeout, 287 msdu_end->tcp_udp_chksum_fail_copy, 288 msdu_end->msdu_limit_error, 289 msdu_end->flow_idx_timeout, 290 msdu_end->flow_idx_invalid, 291 msdu_end->cce_match, 292 msdu_end->amsdu_parser_error, 293 msdu_end->cumulative_ip_length, 294 msdu_end->key_id_octet, 295 msdu_end->reserved_16a, 296 msdu_end->reserved_17a, 297 msdu_end->service_code, 298 msdu_end->priority_valid, 299 msdu_end->intra_bss, 300 msdu_end->dest_chip_id, 301 msdu_end->multicast_echo, 302 msdu_end->wds_learning_event, 303 msdu_end->wds_roaming_event, 304 msdu_end->wds_keep_alive_event, 305 msdu_end->reserved_17b); 306 307 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 308 "rx_msdu_end tlv (4/5)- " 309 "msdu_length :%x " 310 "stbc :%x " 311 "ipsec_esp :%x " 312 "l3_offset :%x " 313 "ipsec_ah :%x " 314 "l4_offset :%x " 315 "msdu_number :%x " 316 "decap_format :%x " 317 "ipv4_proto :%x " 318 "ipv6_proto :%x " 319 "tcp_proto :%x " 320 "udp_proto :%x " 321 "ip_frag :%x " 322 "tcp_only_ack :%x " 323 "da_is_bcast_mcast :%x " 324 "toeplitz_hash_sel :%x " 325 "ip_fixed_header_valid :%x " 326 "ip_extn_header_valid :%x " 327 "tcp_udp_header_valid :%x " 328 "mesh_control_present :%x " 329 "ldpc :%x " 330 "ip4_protocol_ip6_next_header :%x " 331 "vlan_ctag_ci :%x " 332 "vlan_stag_ci :%x " 333 "peer_meta_data :%x " 334 "user_rssi :%x " 335 "pkt_type :%x " 336 "sgi :%x " 337 "rate_mcs :%x " 338 "receive_bandwidth :%x " 339 "reception_type :%x " 340 "mimo_ss_bitmap :%x " 341 "msdu_done_copy :%x " 342 "flow_id_toeplitz :%x", 343 msdu_end->msdu_length, 344 msdu_end->stbc, 345 msdu_end->ipsec_esp, 346 msdu_end->l3_offset, 347 msdu_end->ipsec_ah, 348 msdu_end->l4_offset, 349 msdu_end->msdu_number, 350 msdu_end->decap_format, 351 msdu_end->ipv4_proto, 352 msdu_end->ipv6_proto, 353 msdu_end->tcp_proto, 354 msdu_end->udp_proto, 355 msdu_end->ip_frag, 356 msdu_end->tcp_only_ack, 357 msdu_end->da_is_bcast_mcast, 358 msdu_end->toeplitz_hash_sel, 359 msdu_end->ip_fixed_header_valid, 360 msdu_end->ip_extn_header_valid, 361 msdu_end->tcp_udp_header_valid, 362 msdu_end->mesh_control_present, 363 msdu_end->ldpc, 364 msdu_end->ip4_protocol_ip6_next_header, 365 msdu_end->vlan_ctag_ci, 366 msdu_end->vlan_stag_ci, 367 msdu_end->peer_meta_data, 368 msdu_end->user_rssi, 369 msdu_end->pkt_type, 370 msdu_end->sgi, 371 msdu_end->rate_mcs, 372 msdu_end->receive_bandwidth, 373 msdu_end->reception_type, 374 msdu_end->mimo_ss_bitmap, 375 msdu_end->msdu_done_copy, 376 msdu_end->flow_id_toeplitz); 377 378 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 379 "rx_msdu_end tlv (5/5)- " 380 "ppdu_start_timestamp_63_32 :%x " 381 "sw_phy_meta_data :%x " 382 "ppdu_start_timestamp_31_0 :%x " 383 "toeplitz_hash_2_or_4 :%x " 384 "reserved_28a :%x " 385 "sa_15_0 :%x " 386 "sa_47_16 :%x " 387 "first_mpdu :%x " 388 "reserved_30a :%x " 389 "mcast_bcast :%x " 390 "ast_index_not_found :%x " 391 "ast_index_timeout :%x " 392 "power_mgmt :%x " 393 "non_qos :%x " 394 "null_data :%x " 395 "mgmt_type :%x " 396 "ctrl_type :%x " 397 "more_data :%x " 398 "eosp :%x " 399 "a_msdu_error :%x " 400 "reserved_30b :%x " 401 "order :%x " 402 "wifi_parser_error :%x " 403 "overflow_err :%x " 404 "msdu_length_err :%x " 405 "tcp_udp_chksum_fail :%x " 406 "ip_chksum_fail :%x " 407 "sa_idx_invalid :%x " 408 "da_idx_invalid :%x " 409 "amsdu_addr_mismatch :%x " 410 "rx_in_tx_decrypt_byp :%x " 411 "encrypt_required :%x " 412 "directed :%x " 413 "buffer_fragment :%x " 414 "mpdu_length_err :%x " 415 "tkip_mic_err :%x " 416 "decrypt_err :%x " 417 "unencrypted_frame_err :%x " 418 "fcs_err :%x " 419 "reserved_31a :%x " 420 "decrypt_status_code :%x " 421 "rx_bitmap_not_updated :%x " 422 "reserved_31b :%x " 423 "msdu_done :%x", 424 msdu_end->ppdu_start_timestamp_63_32, 425 msdu_end->sw_phy_meta_data, 426 msdu_end->ppdu_start_timestamp_31_0, 427 msdu_end->toeplitz_hash_2_or_4, 428 msdu_end->reserved_28a, 429 msdu_end->sa_15_0, 430 msdu_end->sa_47_16, 431 msdu_end->first_mpdu, 432 msdu_end->reserved_30a, 433 msdu_end->mcast_bcast, 434 msdu_end->ast_index_not_found, 435 msdu_end->ast_index_timeout, 436 msdu_end->power_mgmt, 437 msdu_end->non_qos, 438 msdu_end->null_data, 439 msdu_end->mgmt_type, 440 msdu_end->ctrl_type, 441 msdu_end->more_data, 442 msdu_end->eosp, 443 msdu_end->a_msdu_error, 444 msdu_end->reserved_30b, 445 msdu_end->order, 446 msdu_end->wifi_parser_error, 447 msdu_end->overflow_err, 448 msdu_end->msdu_length_err, 449 msdu_end->tcp_udp_chksum_fail, 450 msdu_end->ip_chksum_fail, 451 msdu_end->sa_idx_invalid, 452 msdu_end->da_idx_invalid, 453 msdu_end->amsdu_addr_mismatch, 454 msdu_end->rx_in_tx_decrypt_byp, 455 msdu_end->encrypt_required, 456 msdu_end->directed, 457 msdu_end->buffer_fragment, 458 msdu_end->mpdu_length_err, 459 msdu_end->tkip_mic_err, 460 msdu_end->decrypt_err, 461 msdu_end->unencrypted_frame_err, 462 msdu_end->fcs_err, 463 msdu_end->reserved_31a, 464 msdu_end->decrypt_status_code, 465 msdu_end->rx_bitmap_not_updated, 466 msdu_end->reserved_31b, 467 msdu_end->msdu_done); 468 } 469 #else 470 static void hal_rx_dump_msdu_end_tlv_kiwi(void *msduend, 471 uint8_t dbg_level) 472 { 473 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 474 475 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 476 "rx_msdu_end tlv (1/7)- " 477 "rxpcu_mpdu_filter_in_category :%x" 478 "sw_frame_group_id :%x" 479 "reserved_0 :%x" 480 "phy_ppdu_id :%x" 481 "ip_hdr_chksum:%x" 482 "reported_mpdu_length :%x" 483 "reserved_1a :%x" 484 "key_id_octet :%x" 485 "cce_super_rule :%x" 486 "cce_classify_not_done_truncate :%x" 487 "cce_classify_not_done_cce_dis:%x" 488 "cumulative_l3_checksum :%x" 489 "rule_indication_31_0 :%x" 490 "rule_indication_63_32:%x" 491 "da_offset :%x" 492 "sa_offset :%x" 493 "da_offset_valid :%x" 494 "sa_offset_valid :%x" 495 "reserved_5a :%x" 496 "l3_type :%x", 497 msdu_end->rxpcu_mpdu_filter_in_category, 498 msdu_end->sw_frame_group_id, 499 msdu_end->reserved_0, 500 msdu_end->phy_ppdu_id, 501 msdu_end->ip_hdr_chksum, 502 msdu_end->reported_mpdu_length, 503 msdu_end->reserved_1a, 504 msdu_end->key_id_octet, 505 msdu_end->cce_super_rule, 506 msdu_end->cce_classify_not_done_truncate, 507 msdu_end->cce_classify_not_done_cce_dis, 508 msdu_end->cumulative_l3_checksum, 509 msdu_end->rule_indication_31_0, 510 msdu_end->rule_indication_63_32, 511 msdu_end->da_offset, 512 msdu_end->sa_offset, 513 msdu_end->da_offset_valid, 514 msdu_end->sa_offset_valid, 515 msdu_end->reserved_5a, 516 msdu_end->l3_type); 517 518 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 519 "rx_msdu_end tlv (2/7)- " 520 "ipv6_options_crc :%x" 521 "tcp_seq_number :%x" 522 "tcp_ack_number :%x" 523 "tcp_flag :%x" 524 "lro_eligible :%x" 525 "reserved_9a :%x" 526 "window_size :%x" 527 "tcp_udp_chksum :%x" 528 "sa_idx_timeout :%x" 529 "da_idx_timeout :%x" 530 "msdu_limit_error :%x" 531 "flow_idx_timeout :%x" 532 "flow_idx_invalid :%x" 533 "wifi_parser_error :%x" 534 "amsdu_parser_error :%x" 535 "sa_is_valid :%x" 536 "da_is_valid :%x" 537 "da_is_mcbc :%x" 538 "l3_header_padding :%x" 539 "first_msdu :%x" 540 "last_msdu :%x", 541 msdu_end->ipv6_options_crc, 542 msdu_end->tcp_seq_number, 543 msdu_end->tcp_ack_number, 544 msdu_end->tcp_flag, 545 msdu_end->lro_eligible, 546 msdu_end->reserved_9a, 547 msdu_end->window_size, 548 msdu_end->tcp_udp_chksum, 549 msdu_end->sa_idx_timeout, 550 msdu_end->da_idx_timeout, 551 msdu_end->msdu_limit_error, 552 msdu_end->flow_idx_timeout, 553 msdu_end->flow_idx_invalid, 554 msdu_end->wifi_parser_error, 555 msdu_end->amsdu_parser_error, 556 msdu_end->sa_is_valid, 557 msdu_end->da_is_valid, 558 msdu_end->da_is_mcbc, 559 msdu_end->l3_header_padding, 560 msdu_end->first_msdu, 561 msdu_end->last_msdu); 562 563 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 564 "rx_msdu_end tlv (3/7)" 565 "tcp_udp_chksum_fail_copy :%x" 566 "ip_chksum_fail_copy :%x" 567 "sa_idx :%x" 568 "da_idx_or_sw_peer_id :%x" 569 "msdu_drop :%x" 570 "reo_destination_indication :%x" 571 "flow_idx :%x" 572 "reserved_12a :%x" 573 "fse_metadata :%x" 574 "cce_metadata :%x" 575 "sa_sw_peer_id:%x" 576 "aggregation_count :%x" 577 "flow_aggregation_continuation:%x" 578 "fisa_timeout :%x" 579 "reserved_15a :%x" 580 "cumulative_l4_checksum :%x" 581 "cumulative_ip_length :%x" 582 "service_code :%x" 583 "priority_valid :%x", 584 msdu_end->tcp_udp_chksum_fail_copy, 585 msdu_end->ip_chksum_fail_copy, 586 msdu_end->sa_idx, 587 msdu_end->da_idx_or_sw_peer_id, 588 msdu_end->msdu_drop, 589 msdu_end->reo_destination_indication, 590 msdu_end->flow_idx, 591 msdu_end->reserved_12a, 592 msdu_end->fse_metadata, 593 msdu_end->cce_metadata, 594 msdu_end->sa_sw_peer_id, 595 msdu_end->aggregation_count, 596 msdu_end->flow_aggregation_continuation, 597 msdu_end->fisa_timeout, 598 msdu_end->reserved_15a, 599 msdu_end->cumulative_l4_checksum, 600 msdu_end->cumulative_ip_length, 601 msdu_end->service_code, 602 msdu_end->priority_valid); 603 604 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 605 "rx_msdu_end tlv (4/7)" 606 "reserved_17a :%x" 607 "msdu_length :%x" 608 "ipsec_esp :%x" 609 "l3_offset :%x" 610 "ipsec_ah :%x" 611 "l4_offset :%x" 612 "msdu_number :%x" 613 "decap_format :%x" 614 "ipv4_proto :%x" 615 "ipv6_proto :%x" 616 "tcp_proto :%x" 617 "udp_proto :%x" 618 "ip_frag :%x" 619 "tcp_only_ack :%x" 620 "da_is_bcast_mcast :%x" 621 "toeplitz_hash_sel :%x" 622 "ip_fixed_header_valid:%x" 623 "ip_extn_header_valid :%x" 624 "tcp_udp_header_valid :%x", 625 msdu_end->reserved_17a, 626 msdu_end->msdu_length, 627 msdu_end->ipsec_esp, 628 msdu_end->l3_offset, 629 msdu_end->ipsec_ah, 630 msdu_end->l4_offset, 631 msdu_end->msdu_number, 632 msdu_end->decap_format, 633 msdu_end->ipv4_proto, 634 msdu_end->ipv6_proto, 635 msdu_end->tcp_proto, 636 msdu_end->udp_proto, 637 msdu_end->ip_frag, 638 msdu_end->tcp_only_ack, 639 msdu_end->da_is_bcast_mcast, 640 msdu_end->toeplitz_hash_sel, 641 msdu_end->ip_fixed_header_valid, 642 msdu_end->ip_extn_header_valid, 643 msdu_end->tcp_udp_header_valid); 644 645 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 646 "rx_msdu_end tlv (5/7)" 647 "mesh_control_present :%x" 648 "ldpc :%x" 649 "ip4_protocol_ip6_next_header :%x" 650 "toeplitz_hash_2_or_4 :%x" 651 "flow_id_toeplitz :%x" 652 "user_rssi :%x" 653 "pkt_type :%x" 654 "stbc :%x" 655 "sgi :%x" 656 "rate_mcs :%x" 657 "receive_bandwidth :%x" 658 "reception_type :%x" 659 "mimo_ss_bitmap :%x" 660 "ppdu_start_timestamp_31_0 :%x" 661 "ppdu_start_timestamp_63_32 :%x" 662 "sw_phy_meta_data :%x" 663 "vlan_ctag_ci :%x" 664 "vlan_stag_ci :%x" 665 "first_mpdu :%x" 666 "reserved_30a :%x" 667 "mcast_bcast :%x", 668 msdu_end->mesh_control_present, 669 msdu_end->ldpc, 670 msdu_end->ip4_protocol_ip6_next_header, 671 msdu_end->toeplitz_hash_2_or_4, 672 msdu_end->flow_id_toeplitz, 673 msdu_end->user_rssi, 674 msdu_end->pkt_type, 675 msdu_end->stbc, 676 msdu_end->sgi, 677 msdu_end->rate_mcs, 678 msdu_end->receive_bandwidth, 679 msdu_end->reception_type, 680 msdu_end->mimo_ss_bitmap, 681 msdu_end->ppdu_start_timestamp_31_0, 682 msdu_end->ppdu_start_timestamp_63_32, 683 msdu_end->sw_phy_meta_data, 684 msdu_end->vlan_ctag_ci, 685 msdu_end->vlan_stag_ci, 686 msdu_end->first_mpdu, 687 msdu_end->reserved_30a, 688 msdu_end->mcast_bcast); 689 690 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 691 "rx_msdu_end tlv (6/7)" 692 "ast_index_not_found :%x" 693 "ast_index_timeout :%x" 694 "power_mgmt :%x" 695 "non_qos :%x" 696 "null_data :%x" 697 "mgmt_type :%x" 698 "ctrl_type :%x" 699 "more_data :%x" 700 "eosp :%x" 701 "a_msdu_error :%x" 702 "fragment_flag:%x" 703 "order:%x" 704 "cce_match :%x" 705 "overflow_err :%x" 706 "msdu_length_err :%x" 707 "tcp_udp_chksum_fail :%x" 708 "ip_chksum_fail :%x" 709 "sa_idx_invalid :%x" 710 "da_idx_invalid :%x" 711 "reserved_30b :%x", 712 msdu_end->ast_index_not_found, 713 msdu_end->ast_index_timeout, 714 msdu_end->power_mgmt, 715 msdu_end->non_qos, 716 msdu_end->null_data, 717 msdu_end->mgmt_type, 718 msdu_end->ctrl_type, 719 msdu_end->more_data, 720 msdu_end->eosp, 721 msdu_end->a_msdu_error, 722 msdu_end->fragment_flag, 723 msdu_end->order, 724 msdu_end->cce_match, 725 msdu_end->overflow_err, 726 msdu_end->msdu_length_err, 727 msdu_end->tcp_udp_chksum_fail, 728 msdu_end->ip_chksum_fail, 729 msdu_end->sa_idx_invalid, 730 msdu_end->da_idx_invalid, 731 msdu_end->reserved_30b); 732 733 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 734 "rx_msdu_end tlv (7/7)" 735 "rx_in_tx_decrypt_byp :%x" 736 "encrypt_required :%x" 737 "directed :%x" 738 "buffer_fragment :%x" 739 "mpdu_length_err :%x" 740 "tkip_mic_err :%x" 741 "decrypt_err :%x" 742 "unencrypted_frame_err:%x" 743 "fcs_err :%x" 744 "reserved_31a :%x" 745 "decrypt_status_code :%x" 746 "rx_bitmap_not_updated:%x" 747 "reserved_31b :%x" 748 "msdu_done :%x", 749 msdu_end->rx_in_tx_decrypt_byp, 750 msdu_end->encrypt_required, 751 msdu_end->directed, 752 msdu_end->buffer_fragment, 753 msdu_end->mpdu_length_err, 754 msdu_end->tkip_mic_err, 755 msdu_end->decrypt_err, 756 msdu_end->unencrypted_frame_err, 757 msdu_end->fcs_err, 758 msdu_end->reserved_31a, 759 msdu_end->decrypt_status_code, 760 msdu_end->rx_bitmap_not_updated, 761 msdu_end->reserved_31b, 762 msdu_end->msdu_done); 763 } 764 #endif 765 766 /** 767 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 768 * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 769 * @ dbg_level: log level. 770 * 771 * Return: void 772 */ 773 static inline void hal_rx_dump_pkt_hdr_tlv_kiwi(struct rx_pkt_tlvs *pkt_tlvs, 774 uint8_t dbg_level) 775 { 776 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 777 778 hal_verbose_debug("\n---------------\n" 779 "rx_pkt_hdr_tlv\n" 780 "---------------\n" 781 "phy_ppdu_id %lld ", 782 pkt_hdr_tlv->phy_ppdu_id); 783 784 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 785 sizeof(pkt_hdr_tlv->rx_pkt_hdr)); 786 } 787 788 /** 789 * hal_rx_dump_mpdu_start_tlv_generic_be: dump RX mpdu_start TLV in structured 790 * human readable format. 791 * @mpdu_start: pointer the rx_attention TLV in pkt. 792 * @dbg_level: log level. 793 * 794 * Return: void 795 */ 796 static inline void hal_rx_dump_mpdu_start_tlv_kiwi(void *mpdustart, 797 uint8_t dbg_level) 798 { 799 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 800 struct rx_mpdu_info *mpdu_info = 801 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 802 803 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 804 "rx_mpdu_start tlv (1/5) - " 805 "rx_reo_queue_desc_addr_31_0 :%x" 806 "rx_reo_queue_desc_addr_39_32 :%x" 807 "receive_queue_number:%x " 808 "pre_delim_err_warning:%x " 809 "first_delim_err:%x " 810 "reserved_2a:%x " 811 "pn_31_0:%x " 812 "pn_63_32:%x " 813 "pn_95_64:%x " 814 "pn_127_96:%x " 815 "epd_en:%x " 816 "all_frames_shall_be_encrypted :%x" 817 "encrypt_type:%x " 818 "wep_key_width_for_variable_key :%x" 819 "bssid_hit:%x " 820 "bssid_number:%x " 821 "tid:%x " 822 "reserved_7a:%x " 823 "peer_meta_data:%x ", 824 mpdu_info->rx_reo_queue_desc_addr_31_0, 825 mpdu_info->rx_reo_queue_desc_addr_39_32, 826 mpdu_info->receive_queue_number, 827 mpdu_info->pre_delim_err_warning, 828 mpdu_info->first_delim_err, 829 mpdu_info->reserved_2a, 830 mpdu_info->pn_31_0, 831 mpdu_info->pn_63_32, 832 mpdu_info->pn_95_64, 833 mpdu_info->pn_127_96, 834 mpdu_info->epd_en, 835 mpdu_info->all_frames_shall_be_encrypted, 836 mpdu_info->encrypt_type, 837 mpdu_info->wep_key_width_for_variable_key, 838 mpdu_info->bssid_hit, 839 mpdu_info->bssid_number, 840 mpdu_info->tid, 841 mpdu_info->reserved_7a, 842 mpdu_info->peer_meta_data); 843 844 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 845 "rx_mpdu_start tlv (2/5) - " 846 "rxpcu_mpdu_filter_in_category :%x" 847 "sw_frame_group_id:%x " 848 "ndp_frame:%x " 849 "phy_err:%x " 850 "phy_err_during_mpdu_header :%x" 851 "protocol_version_err:%x " 852 "ast_based_lookup_valid:%x " 853 "reserved_9a:%x " 854 "phy_ppdu_id:%x " 855 "ast_index:%x " 856 "sw_peer_id:%x " 857 "mpdu_frame_control_valid:%x " 858 "mpdu_duration_valid:%x " 859 "mac_addr_ad1_valid:%x " 860 "mac_addr_ad2_valid:%x " 861 "mac_addr_ad3_valid:%x " 862 "mac_addr_ad4_valid:%x " 863 "mpdu_sequence_control_valid :%x" 864 "mpdu_qos_control_valid:%x " 865 "mpdu_ht_control_valid:%x " 866 "frame_encryption_info_valid :%x", 867 mpdu_info->rxpcu_mpdu_filter_in_category, 868 mpdu_info->sw_frame_group_id, 869 mpdu_info->ndp_frame, 870 mpdu_info->phy_err, 871 mpdu_info->phy_err_during_mpdu_header, 872 mpdu_info->protocol_version_err, 873 mpdu_info->ast_based_lookup_valid, 874 mpdu_info->reserved_9a, 875 mpdu_info->phy_ppdu_id, 876 mpdu_info->ast_index, 877 mpdu_info->sw_peer_id, 878 mpdu_info->mpdu_frame_control_valid, 879 mpdu_info->mpdu_duration_valid, 880 mpdu_info->mac_addr_ad1_valid, 881 mpdu_info->mac_addr_ad2_valid, 882 mpdu_info->mac_addr_ad3_valid, 883 mpdu_info->mac_addr_ad4_valid, 884 mpdu_info->mpdu_sequence_control_valid, 885 mpdu_info->mpdu_qos_control_valid, 886 mpdu_info->mpdu_ht_control_valid, 887 mpdu_info->frame_encryption_info_valid); 888 889 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 890 "rx_mpdu_start tlv (3/5) - " 891 "mpdu_fragment_number:%x " 892 "more_fragment_flag:%x " 893 "reserved_11a:%x " 894 "fr_ds:%x " 895 "to_ds:%x " 896 "encrypted:%x " 897 "mpdu_retry:%x " 898 "mpdu_sequence_number:%x " 899 "key_id_octet:%x " 900 "new_peer_entry:%x " 901 "decrypt_needed:%x " 902 "decap_type:%x " 903 "rx_insert_vlan_c_tag_padding :%x" 904 "rx_insert_vlan_s_tag_padding :%x" 905 "strip_vlan_c_tag_decap:%x " 906 "strip_vlan_s_tag_decap:%x " 907 "pre_delim_count:%x " 908 "ampdu_flag:%x " 909 "bar_frame:%x " 910 "raw_mpdu:%x " 911 "reserved_12:%x " 912 "mpdu_length:%x ", 913 mpdu_info->mpdu_fragment_number, 914 mpdu_info->more_fragment_flag, 915 mpdu_info->reserved_11a, 916 mpdu_info->fr_ds, 917 mpdu_info->to_ds, 918 mpdu_info->encrypted, 919 mpdu_info->mpdu_retry, 920 mpdu_info->mpdu_sequence_number, 921 mpdu_info->key_id_octet, 922 mpdu_info->new_peer_entry, 923 mpdu_info->decrypt_needed, 924 mpdu_info->decap_type, 925 mpdu_info->rx_insert_vlan_c_tag_padding, 926 mpdu_info->rx_insert_vlan_s_tag_padding, 927 mpdu_info->strip_vlan_c_tag_decap, 928 mpdu_info->strip_vlan_s_tag_decap, 929 mpdu_info->pre_delim_count, 930 mpdu_info->ampdu_flag, 931 mpdu_info->bar_frame, 932 mpdu_info->raw_mpdu, 933 mpdu_info->reserved_12, 934 mpdu_info->mpdu_length); 935 936 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 937 "rx_mpdu_start tlv (4/5) - " 938 "mpdu_length:%x " 939 "first_mpdu:%x " 940 "mcast_bcast:%x " 941 "ast_index_not_found:%x " 942 "ast_index_timeout:%x " 943 "power_mgmt:%x " 944 "non_qos:%x " 945 "null_data:%x " 946 "mgmt_type:%x " 947 "ctrl_type:%x " 948 "more_data:%x " 949 "eosp:%x " 950 "fragment_flag:%x " 951 "order:%x " 952 "u_apsd_trigger:%x " 953 "encrypt_required:%x " 954 "directed:%x " 955 "amsdu_present:%x " 956 "reserved_13:%x " 957 "mpdu_frame_control_field:%x " 958 "mpdu_duration_field:%x ", 959 mpdu_info->mpdu_length, 960 mpdu_info->first_mpdu, 961 mpdu_info->mcast_bcast, 962 mpdu_info->ast_index_not_found, 963 mpdu_info->ast_index_timeout, 964 mpdu_info->power_mgmt, 965 mpdu_info->non_qos, 966 mpdu_info->null_data, 967 mpdu_info->mgmt_type, 968 mpdu_info->ctrl_type, 969 mpdu_info->more_data, 970 mpdu_info->eosp, 971 mpdu_info->fragment_flag, 972 mpdu_info->order, 973 mpdu_info->u_apsd_trigger, 974 mpdu_info->encrypt_required, 975 mpdu_info->directed, 976 mpdu_info->amsdu_present, 977 mpdu_info->reserved_13, 978 mpdu_info->mpdu_frame_control_field, 979 mpdu_info->mpdu_duration_field); 980 981 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 982 "rx_mpdu_start tlv (5/5) - " 983 "mac_addr_ad1_31_0:%x " 984 "mac_addr_ad1_47_32:%x " 985 "mac_addr_ad2_15_0:%x " 986 "mac_addr_ad2_47_16:%x " 987 "mac_addr_ad3_31_0:%x " 988 "mac_addr_ad3_47_32:%x " 989 "mpdu_sequence_control_field :%x" 990 "mac_addr_ad4_31_0:%x " 991 "mac_addr_ad4_47_32:%x " 992 "mpdu_qos_control_field:%x " 993 "mpdu_ht_control_field:%x " 994 "vdev_id:%x " 995 "service_code:%x " 996 "priority_valid:%x " 997 "reserved_23a:%x ", 998 mpdu_info->mac_addr_ad1_31_0, 999 mpdu_info->mac_addr_ad1_47_32, 1000 mpdu_info->mac_addr_ad2_15_0, 1001 mpdu_info->mac_addr_ad2_47_16, 1002 mpdu_info->mac_addr_ad3_31_0, 1003 mpdu_info->mac_addr_ad3_47_32, 1004 mpdu_info->mpdu_sequence_control_field, 1005 mpdu_info->mac_addr_ad4_31_0, 1006 mpdu_info->mac_addr_ad4_47_32, 1007 mpdu_info->mpdu_qos_control_field, 1008 mpdu_info->mpdu_ht_control_field, 1009 mpdu_info->vdev_id, 1010 mpdu_info->service_code, 1011 mpdu_info->priority_valid, 1012 mpdu_info->reserved_23a); 1013 } 1014 1015 /** 1016 * hal_rx_dump_pkt_tlvs_kiwi(): API to print RX Pkt TLVS for kiwi 1017 * @hal_soc_hdl: hal_soc handle 1018 * @buf: pointer the pkt buffer 1019 * @dbg_level: log level 1020 * 1021 * Return: void 1022 */ 1023 static void hal_rx_dump_pkt_tlvs_kiwi(hal_soc_handle_t hal_soc_hdl, 1024 uint8_t *buf, uint8_t dbg_level) 1025 { 1026 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1027 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1028 struct rx_mpdu_start *mpdu_start = 1029 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1030 1031 hal_rx_dump_msdu_end_tlv_kiwi(msdu_end, dbg_level); 1032 hal_rx_dump_mpdu_start_tlv_kiwi(mpdu_start, dbg_level); 1033 hal_rx_dump_pkt_hdr_tlv_kiwi(pkt_tlvs, dbg_level); 1034 } 1035 1036 /** 1037 * hal_rx_tlv_populate_mpdu_desc_info_kiwi() - Populate the local mpdu_desc_info 1038 * elements from the rx tlvs 1039 * @buf: start address of rx tlvs [Validated by caller] 1040 * @mpdu_desc_info_hdl: Buffer to populate the mpdu_dsc_info 1041 * [To be validated by caller] 1042 * 1043 * Return: None 1044 */ 1045 static void 1046 hal_rx_tlv_populate_mpdu_desc_info_kiwi(uint8_t *buf, 1047 void *mpdu_desc_info_hdl) 1048 { 1049 struct hal_rx_mpdu_desc_info *mpdu_desc_info = 1050 (struct hal_rx_mpdu_desc_info *)mpdu_desc_info_hdl; 1051 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1052 struct rx_mpdu_start *mpdu_start = 1053 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1054 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1055 1056 mpdu_desc_info->mpdu_seq = mpdu_info->mpdu_sequence_number; 1057 mpdu_desc_info->mpdu_flags = hal_rx_get_mpdu_flags((uint32_t *) 1058 mpdu_info); 1059 mpdu_desc_info->peer_meta_data = mpdu_info->peer_meta_data; 1060 mpdu_desc_info->bar_frame = mpdu_info->bar_frame; 1061 } 1062 1063 /** 1064 * hal_reo_status_get_header_kiwi - Process reo desc info 1065 * @d - Pointer to reo descriptior 1066 * @b - tlv type info 1067 * @h1 - Pointer to hal_reo_status_header where info to be stored 1068 * 1069 * Return - none. 1070 * 1071 */ 1072 static void hal_reo_status_get_header_kiwi(hal_ring_desc_t ring_desc, int b, 1073 void *h1) 1074 { 1075 uint64_t *d = (uint64_t *)ring_desc; 1076 uint64_t val1 = 0; 1077 struct hal_reo_status_header *h = 1078 (struct hal_reo_status_header *)h1; 1079 1080 /* Offsets of descriptor fields defined in HW headers start 1081 * from the field after TLV header 1082 */ 1083 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr)); 1084 1085 switch (b) { 1086 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1087 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1088 STATUS_HEADER_REO_STATUS_NUMBER)]; 1089 break; 1090 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1091 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1092 STATUS_HEADER_REO_STATUS_NUMBER)]; 1093 break; 1094 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1095 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1096 STATUS_HEADER_REO_STATUS_NUMBER)]; 1097 break; 1098 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1099 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1100 STATUS_HEADER_REO_STATUS_NUMBER)]; 1101 break; 1102 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1103 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1104 STATUS_HEADER_REO_STATUS_NUMBER)]; 1105 break; 1106 case HAL_REO_DESC_THRES_STATUS_TLV: 1107 val1 = 1108 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1109 STATUS_HEADER_REO_STATUS_NUMBER)]; 1110 break; 1111 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1112 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1113 STATUS_HEADER_REO_STATUS_NUMBER)]; 1114 break; 1115 default: 1116 qdf_nofl_err("ERROR: Unknown tlv\n"); 1117 break; 1118 } 1119 h->cmd_num = 1120 HAL_GET_FIELD( 1121 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER, 1122 val1); 1123 h->exec_time = 1124 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1125 CMD_EXECUTION_TIME, val1); 1126 h->status = 1127 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1128 REO_CMD_EXECUTION_STATUS, val1); 1129 switch (b) { 1130 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1131 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1132 STATUS_HEADER_TIMESTAMP)]; 1133 break; 1134 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1135 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1136 STATUS_HEADER_TIMESTAMP)]; 1137 break; 1138 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1139 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1140 STATUS_HEADER_TIMESTAMP)]; 1141 break; 1142 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1143 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1144 STATUS_HEADER_TIMESTAMP)]; 1145 break; 1146 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1147 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1148 STATUS_HEADER_TIMESTAMP)]; 1149 break; 1150 case HAL_REO_DESC_THRES_STATUS_TLV: 1151 val1 = 1152 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1153 STATUS_HEADER_TIMESTAMP)]; 1154 break; 1155 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1156 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1157 STATUS_HEADER_TIMESTAMP)]; 1158 break; 1159 default: 1160 qdf_nofl_err("ERROR: Unknown tlv\n"); 1161 break; 1162 } 1163 h->tstamp = 1164 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1); 1165 } 1166 1167 static 1168 void *hal_rx_msdu0_buffer_addr_lsb_kiwi(void *link_desc_va) 1169 { 1170 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1171 } 1172 1173 static 1174 void *hal_rx_msdu_desc_info_ptr_get_kiwi(void *msdu0) 1175 { 1176 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1177 } 1178 1179 static 1180 void *hal_ent_mpdu_desc_info_kiwi(void *ent_ring_desc) 1181 { 1182 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1183 } 1184 1185 static 1186 void *hal_dst_mpdu_desc_info_kiwi(void *dst_ring_desc) 1187 { 1188 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1189 } 1190 1191 /* 1192 * hal_rx_get_tlv_kiwi(): API to get the tlv 1193 * 1194 * @rx_tlv: TLV data extracted from the rx packet 1195 * Return: uint8_t 1196 */ 1197 static uint8_t hal_rx_get_tlv_kiwi(void *rx_tlv) 1198 { 1199 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH); 1200 } 1201 1202 /** 1203 * hal_rx_proc_phyrx_other_receive_info_tlv_kiwi() 1204 * - process other receive info TLV 1205 * @rx_tlv_hdr: pointer to TLV header 1206 * @ppdu_info: pointer to ppdu_info 1207 * 1208 * Return: None 1209 */ 1210 static 1211 void hal_rx_proc_phyrx_other_receive_info_tlv_kiwi(void *rx_tlv_hdr, 1212 void *ppdu_info_handle) 1213 { 1214 uint32_t tlv_tag, tlv_len; 1215 uint32_t temp_len, other_tlv_len, other_tlv_tag; 1216 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 1217 void *other_tlv_hdr = NULL; 1218 void *other_tlv = NULL; 1219 1220 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 1221 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 1222 temp_len = 0; 1223 1224 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 1225 1226 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 1227 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 1228 temp_len += other_tlv_len; 1229 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 1230 1231 switch (other_tlv_tag) { 1232 default: 1233 hal_err_rl("unhandled TLV type: %d, TLV len:%d", 1234 other_tlv_tag, other_tlv_len); 1235 break; 1236 } 1237 } 1238 1239 /** 1240 * hal_reo_config_kiwi(): Set reo config parameters 1241 * @soc: hal soc handle 1242 * @reg_val: value to be set 1243 * @reo_params: reo parameters 1244 * 1245 * Return: void 1246 */ 1247 static 1248 void hal_reo_config_kiwi(struct hal_soc *soc, 1249 uint32_t reg_val, 1250 struct hal_reo_params *reo_params) 1251 { 1252 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1253 } 1254 1255 /** 1256 * hal_rx_msdu_desc_info_get_ptr_kiwi() - Get msdu desc info ptr 1257 * @msdu_details_ptr - Pointer to msdu_details_ptr 1258 * 1259 * Return - Pointer to rx_msdu_desc_info structure. 1260 * 1261 */ 1262 static void *hal_rx_msdu_desc_info_get_ptr_kiwi(void *msdu_details_ptr) 1263 { 1264 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1265 } 1266 1267 /** 1268 * hal_rx_link_desc_msdu0_ptr_kiwi - Get pointer to rx_msdu details 1269 * @link_desc - Pointer to link desc 1270 * 1271 * Return - Pointer to rx_msdu_details structure 1272 * 1273 */ 1274 static void *hal_rx_link_desc_msdu0_ptr_kiwi(void *link_desc) 1275 { 1276 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1277 } 1278 1279 /** 1280 * hal_get_window_address_kiwi(): Function to get hp/tp address 1281 * @hal_soc: Pointer to hal_soc 1282 * @addr: address offset of register 1283 * 1284 * Return: modified address offset of register 1285 */ 1286 static inline qdf_iomem_t hal_get_window_address_kiwi(struct hal_soc *hal_soc, 1287 qdf_iomem_t addr) 1288 { 1289 return addr; 1290 } 1291 1292 /** 1293 * hal_reo_set_err_dst_remap_kiwi(): Function to set REO error destination 1294 * ring remap register 1295 * @hal_soc: Pointer to hal_soc 1296 * 1297 * Return: none. 1298 */ 1299 static void 1300 hal_reo_set_err_dst_remap_kiwi(void *hal_soc) 1301 { 1302 /* 1303 * Set REO error 2k jump (error code 5) / OOR (error code 7) 1304 * frame routed to REO2SW0 ring. 1305 */ 1306 uint32_t dst_remap_ix0 = 1307 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 0) | 1308 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 1) | 1309 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 2) | 1310 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 3) | 1311 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 4) | 1312 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) | 1313 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) | 1314 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7); 1315 1316 uint32_t dst_remap_ix1 = 1317 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 14) | 1318 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 13) | 1319 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 12) | 1320 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 11) | 1321 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 10) | 1322 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 9) | 1323 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 8); 1324 1325 HAL_REG_WRITE(hal_soc, 1326 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1327 REO_REG_REG_BASE), 1328 dst_remap_ix0); 1329 1330 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x", 1331 HAL_REG_READ( 1332 hal_soc, 1333 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1334 REO_REG_REG_BASE))); 1335 1336 HAL_REG_WRITE(hal_soc, 1337 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1338 REO_REG_REG_BASE), 1339 dst_remap_ix1); 1340 1341 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1 0x%x", 1342 HAL_REG_READ( 1343 hal_soc, 1344 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1345 REO_REG_REG_BASE))); 1346 } 1347 1348 /** 1349 * hal_reo_enable_pn_in_dest_kiwi() - Set the REO register to enable previous PN 1350 * for OOR and 2K-jump frames 1351 * @hal_soc: HAL SoC handle 1352 * 1353 * Return: 1, since the register is set. 1354 */ 1355 static uint8_t hal_reo_enable_pn_in_dest_kiwi(void *hal_soc) 1356 { 1357 HAL_REG_WRITE(hal_soc, HWIO_REO_R0_PN_IN_DEST_ADDR(REO_REG_REG_BASE), 1358 1); 1359 return 1; 1360 } 1361 1362 /** 1363 * hal_rx_flow_setup_fse_kiwi() - Setup a flow search entry in HW FST 1364 * @fst: Pointer to the Rx Flow Search Table 1365 * @table_offset: offset into the table where the flow is to be setup 1366 * @flow: Flow Parameters 1367 * 1368 * Flow table entry fields are updated in host byte order, little endian order. 1369 * 1370 * Return: Success/Failure 1371 */ 1372 static void * 1373 hal_rx_flow_setup_fse_kiwi(uint8_t *rx_fst, uint32_t table_offset, 1374 uint8_t *rx_flow) 1375 { 1376 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1377 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1378 uint8_t *fse; 1379 bool fse_valid; 1380 1381 if (table_offset >= fst->max_entries) { 1382 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1383 "HAL FSE table offset %u exceeds max entries %u", 1384 table_offset, fst->max_entries); 1385 return NULL; 1386 } 1387 1388 fse = (uint8_t *)fst->base_vaddr + 1389 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1390 1391 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1392 1393 if (fse_valid) { 1394 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1395 "HAL FSE %pK already valid", fse); 1396 return NULL; 1397 } 1398 1399 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) = 1400 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1401 (flow->tuple_info.src_ip_127_96)); 1402 1403 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) = 1404 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1405 (flow->tuple_info.src_ip_95_64)); 1406 1407 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) = 1408 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1409 (flow->tuple_info.src_ip_63_32)); 1410 1411 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) = 1412 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1413 (flow->tuple_info.src_ip_31_0)); 1414 1415 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) = 1416 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1417 (flow->tuple_info.dest_ip_127_96)); 1418 1419 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) = 1420 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1421 (flow->tuple_info.dest_ip_95_64)); 1422 1423 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) = 1424 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1425 (flow->tuple_info.dest_ip_63_32)); 1426 1427 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) = 1428 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1429 (flow->tuple_info.dest_ip_31_0)); 1430 1431 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT); 1432 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |= 1433 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1434 (flow->tuple_info.dest_port)); 1435 1436 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT); 1437 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |= 1438 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1439 (flow->tuple_info.src_port)); 1440 1441 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL); 1442 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |= 1443 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1444 flow->tuple_info.l4_protocol); 1445 1446 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER); 1447 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |= 1448 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1449 flow->reo_destination_handler); 1450 1451 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1452 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |= 1453 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1454 1455 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA); 1456 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) = 1457 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1458 (flow->fse_metadata)); 1459 1460 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION); 1461 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |= 1462 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1463 REO_DESTINATION_INDICATION, 1464 flow->reo_destination_indication); 1465 1466 /* Reset all the other fields in FSE */ 1467 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9); 1468 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP); 1469 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT); 1470 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT); 1471 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP); 1472 1473 return fse; 1474 } 1475 1476 /* 1477 * hal_rx_flow_setup_cmem_fse_kiwi() - Setup a flow search entry in HW CMEM FST 1478 * @hal_soc: hal_soc reference 1479 * @cmem_ba: CMEM base address 1480 * @table_offset: offset into the table where the flow is to be setup 1481 * @flow: Flow Parameters 1482 * 1483 * Return: Success/Failure 1484 */ 1485 static uint32_t 1486 hal_rx_flow_setup_cmem_fse_kiwi(struct hal_soc *hal_soc, uint32_t cmem_ba, 1487 uint32_t table_offset, uint8_t *rx_flow) 1488 { 1489 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1490 uint32_t fse_offset; 1491 uint32_t value; 1492 1493 fse_offset = cmem_ba + (table_offset * HAL_RX_FST_ENTRY_SIZE); 1494 1495 /* Reset the Valid bit */ 1496 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1497 VALID), 0); 1498 1499 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1500 (flow->tuple_info.src_ip_127_96)); 1501 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1502 SRC_IP_127_96), value); 1503 1504 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1505 (flow->tuple_info.src_ip_95_64)); 1506 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1507 SRC_IP_95_64), value); 1508 1509 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1510 (flow->tuple_info.src_ip_63_32)); 1511 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1512 SRC_IP_63_32), value); 1513 1514 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1515 (flow->tuple_info.src_ip_31_0)); 1516 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1517 SRC_IP_31_0), value); 1518 1519 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1520 (flow->tuple_info.dest_ip_127_96)); 1521 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1522 DEST_IP_127_96), value); 1523 1524 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1525 (flow->tuple_info.dest_ip_95_64)); 1526 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1527 DEST_IP_95_64), value); 1528 1529 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1530 (flow->tuple_info.dest_ip_63_32)); 1531 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1532 DEST_IP_63_32), value); 1533 1534 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1535 (flow->tuple_info.dest_ip_31_0)); 1536 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1537 DEST_IP_31_0), value); 1538 1539 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1540 (flow->tuple_info.dest_port)); 1541 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1542 (flow->tuple_info.src_port)); 1543 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1544 SRC_PORT), value); 1545 1546 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1547 (flow->fse_metadata)); 1548 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1549 METADATA), value); 1550 1551 /* Reset all the other fields in FSE */ 1552 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1553 MSDU_COUNT), 0); 1554 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1555 MSDU_BYTE_COUNT), 0); 1556 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1557 TIMESTAMP), 0); 1558 1559 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1560 flow->tuple_info.l4_protocol); 1561 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1562 flow->reo_destination_handler); 1563 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1564 REO_DESTINATION_INDICATION, 1565 flow->reo_destination_indication); 1566 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1567 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1568 L4_PROTOCOL), value); 1569 1570 return fse_offset; 1571 } 1572 1573 /** 1574 * hal_rx_flow_get_cmem_fse_ts_kiwi() - Get timestamp field from CMEM FSE 1575 * @hal_soc: hal_soc reference 1576 * @fse_offset: CMEM FSE offset 1577 * 1578 * Return: Timestamp 1579 */ 1580 static uint32_t hal_rx_flow_get_cmem_fse_ts_kiwi(struct hal_soc *hal_soc, 1581 uint32_t fse_offset) 1582 { 1583 return HAL_CMEM_READ(hal_soc, fse_offset + 1584 HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, TIMESTAMP)); 1585 } 1586 1587 /** 1588 * hal_rx_flow_get_cmem_fse_kiwi() - Get FSE from CMEM 1589 * @hal_soc: hal_soc reference 1590 * @fse_offset: CMEM FSE offset 1591 * @fse: referece where FSE will be copied 1592 * @len: length of FSE 1593 * 1594 * Return: If read is succesfull or not 1595 */ 1596 static void 1597 hal_rx_flow_get_cmem_fse_kiwi(struct hal_soc *hal_soc, uint32_t fse_offset, 1598 uint32_t *fse, qdf_size_t len) 1599 { 1600 int i; 1601 1602 if (len != HAL_RX_FST_ENTRY_SIZE) 1603 return; 1604 1605 for (i = 0; i < NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY; i++) 1606 fse[i] = HAL_CMEM_READ(hal_soc, fse_offset + i * 4); 1607 } 1608 1609 static 1610 void hal_compute_reo_remap_ix2_ix3_kiwi(uint32_t *ring_map, 1611 uint32_t num_rings, uint32_t *remap1, 1612 uint32_t *remap2) 1613 { 1614 1615 switch (num_rings) { 1616 /* should we have all the different possible ring configs */ 1617 default: 1618 case 3: 1619 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1620 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1621 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1622 HAL_REO_REMAP_IX2(ring_map[0], 19) | 1623 HAL_REO_REMAP_IX2(ring_map[1], 20) | 1624 HAL_REO_REMAP_IX2(ring_map[2], 21) | 1625 HAL_REO_REMAP_IX2(ring_map[0], 22) | 1626 HAL_REO_REMAP_IX2(ring_map[1], 23); 1627 1628 *remap2 = HAL_REO_REMAP_IX3(ring_map[2], 24) | 1629 HAL_REO_REMAP_IX3(ring_map[0], 25) | 1630 HAL_REO_REMAP_IX3(ring_map[1], 26) | 1631 HAL_REO_REMAP_IX3(ring_map[2], 27) | 1632 HAL_REO_REMAP_IX3(ring_map[0], 28) | 1633 HAL_REO_REMAP_IX3(ring_map[1], 29) | 1634 HAL_REO_REMAP_IX3(ring_map[2], 30) | 1635 HAL_REO_REMAP_IX3(ring_map[0], 31); 1636 break; 1637 case 4: 1638 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1639 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1640 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1641 HAL_REO_REMAP_IX2(ring_map[3], 19) | 1642 HAL_REO_REMAP_IX2(ring_map[0], 20) | 1643 HAL_REO_REMAP_IX2(ring_map[1], 21) | 1644 HAL_REO_REMAP_IX2(ring_map[2], 22) | 1645 HAL_REO_REMAP_IX2(ring_map[3], 23); 1646 1647 *remap2 = HAL_REO_REMAP_IX3(ring_map[0], 24) | 1648 HAL_REO_REMAP_IX3(ring_map[1], 25) | 1649 HAL_REO_REMAP_IX3(ring_map[2], 26) | 1650 HAL_REO_REMAP_IX3(ring_map[3], 27) | 1651 HAL_REO_REMAP_IX3(ring_map[0], 28) | 1652 HAL_REO_REMAP_IX3(ring_map[1], 29) | 1653 HAL_REO_REMAP_IX3(ring_map[2], 30) | 1654 HAL_REO_REMAP_IX3(ring_map[3], 31); 1655 break; 1656 case 6: 1657 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1658 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1659 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1660 HAL_REO_REMAP_IX2(ring_map[3], 19) | 1661 HAL_REO_REMAP_IX2(ring_map[4], 20) | 1662 HAL_REO_REMAP_IX2(ring_map[5], 21) | 1663 HAL_REO_REMAP_IX2(ring_map[0], 22) | 1664 HAL_REO_REMAP_IX2(ring_map[1], 23); 1665 1666 *remap2 = HAL_REO_REMAP_IX3(ring_map[2], 24) | 1667 HAL_REO_REMAP_IX3(ring_map[3], 25) | 1668 HAL_REO_REMAP_IX3(ring_map[4], 26) | 1669 HAL_REO_REMAP_IX3(ring_map[5], 27) | 1670 HAL_REO_REMAP_IX3(ring_map[0], 28) | 1671 HAL_REO_REMAP_IX3(ring_map[1], 29) | 1672 HAL_REO_REMAP_IX3(ring_map[2], 30) | 1673 HAL_REO_REMAP_IX3(ring_map[3], 31); 1674 break; 1675 case 8: 1676 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1677 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1678 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1679 HAL_REO_REMAP_IX2(ring_map[3], 19) | 1680 HAL_REO_REMAP_IX2(ring_map[4], 20) | 1681 HAL_REO_REMAP_IX2(ring_map[5], 21) | 1682 HAL_REO_REMAP_IX2(ring_map[6], 22) | 1683 HAL_REO_REMAP_IX2(ring_map[7], 23); 1684 1685 *remap2 = HAL_REO_REMAP_IX3(ring_map[0], 24) | 1686 HAL_REO_REMAP_IX3(ring_map[1], 25) | 1687 HAL_REO_REMAP_IX3(ring_map[2], 26) | 1688 HAL_REO_REMAP_IX3(ring_map[3], 27) | 1689 HAL_REO_REMAP_IX3(ring_map[4], 28) | 1690 HAL_REO_REMAP_IX3(ring_map[5], 29) | 1691 HAL_REO_REMAP_IX3(ring_map[6], 30) | 1692 HAL_REO_REMAP_IX3(ring_map[7], 31); 1693 break; 1694 } 1695 } 1696 1697 /* NUM TCL Bank registers in KIWI */ 1698 #define HAL_NUM_TCL_BANKS_KIWI 8 1699 1700 /** 1701 * hal_tx_get_num_tcl_banks_kiwi() - Get number of banks in target 1702 * 1703 * Returns: number of bank 1704 */ 1705 static uint8_t hal_tx_get_num_tcl_banks_kiwi(void) 1706 { 1707 return HAL_NUM_TCL_BANKS_KIWI; 1708 } 1709 1710 /** 1711 * hal_rx_reo_prev_pn_get_kiwi() - Get the previous PN from the REO ring desc. 1712 * @ring_desc: REO ring descriptor [To be validated by caller ] 1713 * @prev_pn: Buffer where the previous PN is to be populated. 1714 * [To be validated by caller] 1715 * 1716 * Return: None 1717 */ 1718 static void hal_rx_reo_prev_pn_get_kiwi(void *ring_desc, 1719 uint64_t *prev_pn) 1720 { 1721 struct reo_destination_ring_with_pn *reo_desc = 1722 (struct reo_destination_ring_with_pn *)ring_desc; 1723 1724 *prev_pn = reo_desc->prev_pn_23_0; 1725 *prev_pn |= ((uint64_t)reo_desc->prev_pn_55_24 << 24); 1726 } 1727 1728 /** 1729 * hal_cmem_write_kiwi() - function for CMEM buffer writing 1730 * @hal_soc_hdl: HAL SOC handle 1731 * @offset: CMEM address 1732 * @value: value to write 1733 * 1734 * Return: None. 1735 */ 1736 static inline void hal_cmem_write_kiwi(hal_soc_handle_t hal_soc_hdl, 1737 uint32_t offset, 1738 uint32_t value) 1739 { 1740 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1741 1742 hal_write32_mb(hal, offset, value); 1743 } 1744 1745 /** 1746 * hal_get_idle_link_bm_id_kiwi() - Get idle link BM id from chid_id 1747 * @chip_id: mlo chip_id 1748 * 1749 * Returns: RBM ID 1750 */ 1751 static uint8_t hal_get_idle_link_bm_id_kiwi(uint8_t chip_id) 1752 { 1753 return WBM_IDLE_DESC_LIST; 1754 } 1755 1756 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1757 /** 1758 * hal_get_first_wow_wakeup_packet_kiwi(): Function to get if the buffer 1759 * is the first one that wakes up host from WoW. 1760 * 1761 * @buf: network buffer 1762 * 1763 * Dummy function for KIWI 1764 * 1765 * Returns: 1 to indicate it is first packet received that wakes up host from 1766 * WoW. Otherwise 0 1767 */ 1768 static inline uint8_t hal_get_first_wow_wakeup_packet_kiwi(uint8_t *buf) 1769 { 1770 return 0; 1771 } 1772 #endif 1773 1774 static uint16_t hal_get_rx_max_ba_window_kiwi(int tid) 1775 { 1776 return HAL_RX_BA_WINDOW_1024; 1777 } 1778 1779 /** 1780 * hal_get_reo_qdesc_size_kiwi()- Get the reo queue descriptor size 1781 * from the give Block-Ack window size 1782 * Return: reo queue descriptor size 1783 */ 1784 static uint32_t hal_get_reo_qdesc_size_kiwi(uint32_t ba_window_size, int tid) 1785 { 1786 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 1787 * NON_QOS_TID until HW issues are resolved. 1788 */ 1789 if (tid != HAL_NON_QOS_TID) 1790 ba_window_size = hal_get_rx_max_ba_window_kiwi(tid); 1791 1792 /* Return descriptor size corresponding to window size of 2 since 1793 * we set ba_window_size to 2 while setting up REO descriptors as 1794 * a WAR to get 2k jump exception aggregates are received without 1795 * a BA session. 1796 */ 1797 if (ba_window_size <= 1) { 1798 if (tid != HAL_NON_QOS_TID) 1799 return sizeof(struct rx_reo_queue) + 1800 sizeof(struct rx_reo_queue_ext); 1801 else 1802 return sizeof(struct rx_reo_queue); 1803 } 1804 1805 if (ba_window_size <= 105) 1806 return sizeof(struct rx_reo_queue) + 1807 sizeof(struct rx_reo_queue_ext); 1808 1809 if (ba_window_size <= 210) 1810 return sizeof(struct rx_reo_queue) + 1811 (2 * sizeof(struct rx_reo_queue_ext)); 1812 1813 if (ba_window_size <= 256) 1814 return sizeof(struct rx_reo_queue) + 1815 (3 * sizeof(struct rx_reo_queue_ext)); 1816 1817 return sizeof(struct rx_reo_queue) + 1818 (10 * sizeof(struct rx_reo_queue_ext)) + 1819 sizeof(struct rx_reo_queue_1k); 1820 } 1821 1822 static void hal_hw_txrx_ops_attach_kiwi(struct hal_soc *hal_soc) 1823 { 1824 /* init and setup */ 1825 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1826 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1827 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1828 hal_soc->ops->hal_get_window_address = hal_get_window_address_kiwi; 1829 hal_soc->ops->hal_reo_set_err_dst_remap = 1830 hal_reo_set_err_dst_remap_kiwi; 1831 hal_soc->ops->hal_reo_enable_pn_in_dest = 1832 hal_reo_enable_pn_in_dest_kiwi; 1833 /* Overwrite the default BE ops */ 1834 hal_soc->ops->hal_get_rx_max_ba_window = hal_get_rx_max_ba_window_kiwi; 1835 hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_kiwi; 1836 1837 /* tx */ 1838 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_kiwi; 1839 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_kiwi; 1840 hal_soc->ops->hal_tx_comp_get_status = 1841 hal_tx_comp_get_status_generic_be; 1842 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1843 hal_tx_init_cmd_credit_ring_kiwi; 1844 hal_soc->ops->hal_tx_config_rbm_mapping_be = 1845 hal_tx_config_rbm_mapping_be_kiwi; 1846 1847 /* rx */ 1848 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; 1849 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1850 hal_rx_mon_hw_desc_get_mpdu_status_be; 1851 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_kiwi; 1852 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be; 1853 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1854 hal_rx_proc_phyrx_other_receive_info_tlv_kiwi; 1855 1856 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_kiwi; 1857 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1858 hal_rx_dump_mpdu_start_tlv_kiwi; 1859 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_kiwi; 1860 1861 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_kiwi; 1862 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be; 1863 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1864 hal_rx_tlv_reception_type_get_be; 1865 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1866 hal_rx_msdu_end_da_idx_get_be; 1867 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1868 hal_rx_msdu_desc_info_get_ptr_kiwi; 1869 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1870 hal_rx_link_desc_msdu0_ptr_kiwi; 1871 hal_soc->ops->hal_reo_status_get_header = 1872 hal_reo_status_get_header_kiwi; 1873 hal_soc->ops->hal_rx_status_get_tlv_info = 1874 hal_rx_status_get_tlv_info_wrapper_be; 1875 hal_soc->ops->hal_rx_wbm_err_info_get = 1876 hal_rx_wbm_err_info_get_generic_be; 1877 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1878 hal_rx_priv_info_set_in_tlv_be; 1879 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1880 hal_rx_priv_info_get_from_tlv_be; 1881 1882 hal_soc->ops->hal_tx_set_pcp_tid_map = 1883 hal_tx_set_pcp_tid_map_generic_be; 1884 hal_soc->ops->hal_tx_update_pcp_tid_map = 1885 hal_tx_update_pcp_tid_generic_be; 1886 hal_soc->ops->hal_tx_set_tidmap_prty = 1887 hal_tx_update_tidmap_prty_generic_be; 1888 hal_soc->ops->hal_rx_get_rx_fragment_number = 1889 hal_rx_get_rx_fragment_number_be; 1890 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1891 hal_rx_tlv_da_is_mcbc_get_be; 1892 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1893 hal_rx_tlv_sa_is_valid_get_be; 1894 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be, 1895 hal_soc->ops->hal_rx_desc_is_first_msdu = 1896 hal_rx_desc_is_first_msdu_be; 1897 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1898 hal_rx_tlv_l3_hdr_padding_get_be; 1899 hal_soc->ops->hal_rx_encryption_info_valid = 1900 hal_rx_encryption_info_valid_be; 1901 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; 1902 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1903 hal_rx_tlv_first_msdu_get_be; 1904 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1905 hal_rx_tlv_da_is_valid_get_be; 1906 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1907 hal_rx_tlv_last_msdu_get_be; 1908 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1909 hal_rx_get_mpdu_mac_ad4_valid_be; 1910 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1911 hal_rx_mpdu_start_sw_peer_id_get_be; 1912 hal_soc->ops->hal_rx_mpdu_peer_meta_data_get = 1913 hal_rx_mpdu_peer_meta_data_get_be; 1914 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be; 1915 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be; 1916 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1917 hal_rx_get_mpdu_frame_control_valid_be; 1918 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; 1919 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; 1920 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; 1921 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; 1922 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1923 hal_rx_get_mpdu_sequence_control_valid_be; 1924 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; 1925 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; 1926 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1927 hal_rx_hw_desc_get_ppduid_get_be; 1928 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1929 hal_rx_msdu0_buffer_addr_lsb_kiwi; 1930 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1931 hal_rx_msdu_desc_info_ptr_get_kiwi; 1932 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_kiwi; 1933 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_kiwi; 1934 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; 1935 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; 1936 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1937 hal_rx_get_mac_addr2_valid_be; 1938 hal_soc->ops->hal_rx_get_filter_category = 1939 hal_rx_get_filter_category_be; 1940 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be; 1941 hal_soc->ops->hal_reo_config = hal_reo_config_kiwi; 1942 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; 1943 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1944 hal_rx_msdu_flow_idx_invalid_be; 1945 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1946 hal_rx_msdu_flow_idx_timeout_be; 1947 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1948 hal_rx_msdu_fse_metadata_get_be; 1949 hal_soc->ops->hal_rx_msdu_cce_match_get = 1950 hal_rx_msdu_cce_match_get_be; 1951 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1952 hal_rx_msdu_cce_metadata_get_be; 1953 hal_soc->ops->hal_rx_msdu_get_flow_params = 1954 hal_rx_msdu_get_flow_params_be; 1955 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1956 hal_rx_tlv_get_tcp_chksum_be; 1957 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be; 1958 #if defined(QCA_WIFI_KIWI) && defined(WLAN_CFR_ENABLE) && \ 1959 defined(WLAN_ENH_CFR_ENABLE) 1960 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_kiwi; 1961 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_kiwi; 1962 #else 1963 hal_soc->ops->hal_rx_get_bb_info = NULL; 1964 hal_soc->ops->hal_rx_get_rtt_info = NULL; 1965 #endif 1966 /* rx - msdu end fast path info fields */ 1967 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1968 hal_rx_msdu_packet_metadata_get_generic_be; 1969 hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum = 1970 hal_rx_get_fisa_cumulative_l4_checksum_be; 1971 hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length = 1972 hal_rx_get_fisa_cumulative_ip_length_be; 1973 hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_be; 1974 hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation = 1975 hal_rx_get_flow_agg_continuation_be; 1976 hal_soc->ops->hal_rx_get_fisa_flow_agg_count = 1977 hal_rx_get_flow_agg_count_be; 1978 hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_be; 1979 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1980 hal_rx_mpdu_start_tlv_tag_valid_be; 1981 hal_soc->ops->hal_rx_reo_prev_pn_get = hal_rx_reo_prev_pn_get_kiwi; 1982 1983 /* rx - TLV struct offsets */ 1984 hal_soc->ops->hal_rx_msdu_end_offset_get = 1985 hal_rx_msdu_end_offset_get_generic; 1986 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1987 hal_rx_mpdu_start_offset_get_generic; 1988 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1989 hal_rx_pkt_tlv_offset_get_generic; 1990 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_kiwi; 1991 hal_soc->ops->hal_rx_flow_get_tuple_info = 1992 hal_rx_flow_get_tuple_info_be; 1993 hal_soc->ops->hal_rx_flow_delete_entry = 1994 hal_rx_flow_delete_entry_be; 1995 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be; 1996 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1997 hal_compute_reo_remap_ix2_ix3_kiwi; 1998 hal_soc->ops->hal_rx_flow_setup_cmem_fse = 1999 hal_rx_flow_setup_cmem_fse_kiwi; 2000 hal_soc->ops->hal_rx_flow_get_cmem_fse_ts = 2001 hal_rx_flow_get_cmem_fse_ts_kiwi; 2002 hal_soc->ops->hal_rx_flow_get_cmem_fse = hal_rx_flow_get_cmem_fse_kiwi; 2003 hal_soc->ops->hal_cmem_write = hal_cmem_write_kiwi; 2004 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 2005 hal_rx_msdu_get_reo_destination_indication_be; 2006 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_kiwi; 2007 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; 2008 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 2009 hal_rx_msdu_is_wlan_mcast_generic_be; 2010 hal_soc->ops->hal_rx_tlv_bw_get = 2011 hal_rx_tlv_bw_get_be; 2012 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 2013 hal_rx_tlv_get_is_decrypted_be; 2014 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be; 2015 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be; 2016 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 2017 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 2018 hal_soc->ops->hal_rx_tlv_mpdu_len_err_get = 2019 hal_rx_tlv_mpdu_len_err_get_be; 2020 hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get = 2021 hal_rx_tlv_mpdu_fcs_err_get_be; 2022 2023 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be; 2024 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 2025 hal_rx_tlv_decrypt_err_get_be; 2026 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; 2027 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; 2028 hal_soc->ops->hal_rx_tlv_decap_format_get = 2029 hal_rx_tlv_decap_format_get_be; 2030 hal_soc->ops->hal_rx_tlv_get_offload_info = 2031 hal_rx_tlv_get_offload_info_be; 2032 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 2033 hal_rx_attn_phy_ppdu_id_get_be; 2034 hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_tlv_msdu_done_get_be; 2035 hal_soc->ops->hal_rx_tlv_msdu_len_get = 2036 hal_rx_msdu_start_msdu_len_get_be; 2037 hal_soc->ops->hal_rx_get_frame_ctrl_field = 2038 hal_rx_get_frame_ctrl_field_be; 2039 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; 2040 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; 2041 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; 2042 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 2043 hal_rx_mpdu_info_ampdu_flag_get_be; 2044 hal_soc->ops->hal_rx_tlv_msdu_len_set = 2045 hal_rx_msdu_start_msdu_len_set_be; 2046 hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info = 2047 hal_rx_tlv_populate_mpdu_desc_info_kiwi; 2048 hal_soc->ops->hal_rx_tlv_get_pn_num = 2049 hal_rx_tlv_get_pn_num_be; 2050 hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr = 2051 hal_get_reo_ent_desc_qdesc_addr_be; 2052 hal_soc->ops->hal_rx_get_qdesc_addr = 2053 hal_rx_get_qdesc_addr_be; 2054 hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind = 2055 hal_set_reo_ent_desc_reo_dest_ind_be; 2056 hal_soc->ops->hal_get_idle_link_bm_id = hal_get_idle_link_bm_id_kiwi; 2057 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 2058 hal_soc->ops->hal_get_first_wow_wakeup_packet = 2059 hal_get_first_wow_wakeup_packet_kiwi; 2060 #endif 2061 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 2062 2063 hal_soc->ops->hal_rx_tlv_l3_type_get = hal_rx_tlv_l3_type_get_be; 2064 hal_soc->ops->hal_tx_vdev_mismatch_routing_set = 2065 hal_tx_vdev_mismatch_routing_set_generic_be; 2066 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = 2067 hal_tx_mcast_mlo_reinject_routing_set_generic_be; 2068 hal_soc->ops->hal_get_ba_aging_timeout = 2069 hal_get_ba_aging_timeout_be_generic; 2070 hal_soc->ops->hal_setup_link_idle_list = 2071 hal_setup_link_idle_list_generic_be; 2072 hal_soc->ops->hal_cookie_conversion_reg_cfg_be = 2073 hal_cookie_conversion_reg_cfg_generic_be; 2074 hal_soc->ops->hal_set_ba_aging_timeout = 2075 hal_set_ba_aging_timeout_be_generic; 2076 hal_soc->ops->hal_tx_populate_bank_register = 2077 hal_tx_populate_bank_register_be; 2078 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = 2079 hal_tx_vdev_mcast_ctrl_set_be; 2080 }; 2081 2082 struct hal_hw_srng_config hw_srng_table_kiwi[] = { 2083 /* TODO: max_rings can populated by querying HW capabilities */ 2084 { /* REO_DST */ 2085 .start_ring_id = HAL_SRNG_REO2SW1, 2086 .max_rings = 8, 2087 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2088 .lmac_ring = FALSE, 2089 .ring_dir = HAL_SRNG_DST_RING, 2090 .nf_irq_support = true, 2091 .reg_start = { 2092 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 2093 REO_REG_REG_BASE), 2094 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 2095 REO_REG_REG_BASE) 2096 }, 2097 .reg_size = { 2098 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 2099 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 2100 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 2101 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 2102 }, 2103 .max_size = 2104 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 2105 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 2106 }, 2107 { /* REO_EXCEPTION */ 2108 /* Designating REO2SW0 ring as exception ring. */ 2109 .start_ring_id = HAL_SRNG_REO2SW0, 2110 .max_rings = 1, 2111 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2112 .lmac_ring = FALSE, 2113 .ring_dir = HAL_SRNG_DST_RING, 2114 .reg_start = { 2115 HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR( 2116 REO_REG_REG_BASE), 2117 HWIO_REO_R2_REO2SW0_RING_HP_ADDR( 2118 REO_REG_REG_BASE) 2119 }, 2120 /* Single ring - provide ring size if multiple rings of this 2121 * type are supported 2122 */ 2123 .reg_size = {}, 2124 .max_size = 2125 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >> 2126 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT, 2127 }, 2128 { /* REO_REINJECT */ 2129 .start_ring_id = HAL_SRNG_SW2REO, 2130 .max_rings = 1, 2131 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2132 .lmac_ring = FALSE, 2133 .ring_dir = HAL_SRNG_SRC_RING, 2134 .reg_start = { 2135 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 2136 REO_REG_REG_BASE), 2137 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 2138 REO_REG_REG_BASE) 2139 }, 2140 /* Single ring - provide ring size if multiple rings of this 2141 * type are supported 2142 */ 2143 .reg_size = {}, 2144 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 2145 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 2146 }, 2147 { /* REO_CMD */ 2148 .start_ring_id = HAL_SRNG_REO_CMD, 2149 .max_rings = 1, 2150 .entry_size = (sizeof(struct tlv_32_hdr) + 2151 sizeof(struct reo_get_queue_stats)) >> 2, 2152 .lmac_ring = FALSE, 2153 .ring_dir = HAL_SRNG_SRC_RING, 2154 .reg_start = { 2155 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 2156 REO_REG_REG_BASE), 2157 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 2158 REO_REG_REG_BASE), 2159 }, 2160 /* Single ring - provide ring size if multiple rings of this 2161 * type are supported 2162 */ 2163 .reg_size = {}, 2164 .max_size = 2165 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 2166 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 2167 }, 2168 { /* REO_STATUS */ 2169 .start_ring_id = HAL_SRNG_REO_STATUS, 2170 .max_rings = 1, 2171 .entry_size = (sizeof(struct tlv_32_hdr) + 2172 sizeof(struct reo_get_queue_stats_status)) >> 2, 2173 .lmac_ring = FALSE, 2174 .ring_dir = HAL_SRNG_DST_RING, 2175 .reg_start = { 2176 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2177 REO_REG_REG_BASE), 2178 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2179 REO_REG_REG_BASE), 2180 }, 2181 /* Single ring - provide ring size if multiple rings of this 2182 * type are supported 2183 */ 2184 .reg_size = {}, 2185 .max_size = 2186 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2187 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2188 }, 2189 { /* TCL_DATA */ 2190 .start_ring_id = HAL_SRNG_SW2TCL1, 2191 .max_rings = 5, 2192 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 2193 .lmac_ring = FALSE, 2194 .ring_dir = HAL_SRNG_SRC_RING, 2195 .reg_start = { 2196 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2197 MAC_TCL_REG_REG_BASE), 2198 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2199 MAC_TCL_REG_REG_BASE), 2200 }, 2201 .reg_size = { 2202 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2203 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2204 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2205 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2206 }, 2207 .max_size = 2208 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2209 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2210 }, 2211 { /* TCL_CMD */ 2212 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2213 #ifndef WLAN_DP_DISABLE_TCL_CMD_CRED_SRNG 2214 .max_rings = 1, 2215 #else 2216 .max_rings = 0, 2217 #endif 2218 .entry_size = sizeof(struct tcl_gse_cmd) >> 2, 2219 .lmac_ring = FALSE, 2220 .ring_dir = HAL_SRNG_SRC_RING, 2221 .reg_start = { 2222 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2223 MAC_TCL_REG_REG_BASE), 2224 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2225 MAC_TCL_REG_REG_BASE), 2226 }, 2227 /* Single ring - provide ring size if multiple rings of this 2228 * type are supported 2229 */ 2230 .reg_size = {}, 2231 .max_size = 2232 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2233 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2234 }, 2235 { /* TCL_STATUS */ 2236 .start_ring_id = HAL_SRNG_TCL_STATUS, 2237 #ifndef WLAN_DP_DISABLE_TCL_CMD_CRED_SRNG 2238 .max_rings = 1, 2239 #else 2240 .max_rings = 0, 2241 #endif 2242 /* confirm that TLV header is needed */ 2243 .entry_size = sizeof(struct tcl_status_ring) >> 2, 2244 .lmac_ring = FALSE, 2245 .ring_dir = HAL_SRNG_DST_RING, 2246 .reg_start = { 2247 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2248 MAC_TCL_REG_REG_BASE), 2249 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2250 MAC_TCL_REG_REG_BASE), 2251 }, 2252 /* Single ring - provide ring size if multiple rings of this 2253 * type are supported 2254 */ 2255 .reg_size = {}, 2256 .max_size = 2257 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2258 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2259 }, 2260 { /* CE_SRC */ 2261 .start_ring_id = HAL_SRNG_CE_0_SRC, 2262 .max_rings = 12, 2263 .entry_size = sizeof(struct ce_src_desc) >> 2, 2264 .lmac_ring = FALSE, 2265 .ring_dir = HAL_SRNG_SRC_RING, 2266 .reg_start = { 2267 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, 2268 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, 2269 }, 2270 .reg_size = { 2271 SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 2272 SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 2273 SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 2274 SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 2275 }, 2276 .max_size = 2277 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >> 2278 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT, 2279 }, 2280 { /* CE_DST */ 2281 .start_ring_id = HAL_SRNG_CE_0_DST, 2282 .max_rings = 12, 2283 .entry_size = 8 >> 2, 2284 /*TODO: entry_size above should actually be 2285 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2286 * of struct ce_dst_desc in HW header files 2287 */ 2288 .lmac_ring = FALSE, 2289 .ring_dir = HAL_SRNG_SRC_RING, 2290 .reg_start = { 2291 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, 2292 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, 2293 }, 2294 .reg_size = { 2295 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2296 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2297 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2298 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2299 }, 2300 .max_size = 2301 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2302 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2303 }, 2304 { /* CE_DST_STATUS */ 2305 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2306 .max_rings = 12, 2307 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2308 .lmac_ring = FALSE, 2309 .ring_dir = HAL_SRNG_DST_RING, 2310 .reg_start = { 2311 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, 2312 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, 2313 }, 2314 .reg_size = { 2315 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2316 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2317 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2318 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2319 }, 2320 .max_size = 2321 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2322 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2323 }, 2324 { /* WBM_IDLE_LINK */ 2325 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2326 .max_rings = 1, 2327 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2328 .lmac_ring = FALSE, 2329 .ring_dir = HAL_SRNG_SRC_RING, 2330 .reg_start = { 2331 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2332 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE), 2333 }, 2334 /* Single ring - provide ring size if multiple rings of this 2335 * type are supported 2336 */ 2337 .reg_size = {}, 2338 .max_size = 2339 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2340 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2341 }, 2342 { /* SW2WBM_RELEASE */ 2343 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2344 .max_rings = 1, 2345 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2346 .lmac_ring = FALSE, 2347 .ring_dir = HAL_SRNG_SRC_RING, 2348 .reg_start = { 2349 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2350 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2351 }, 2352 /* Single ring - provide ring size if multiple rings of this 2353 * type are supported 2354 */ 2355 .reg_size = {}, 2356 .max_size = 2357 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2358 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2359 }, 2360 { /* WBM2SW_RELEASE */ 2361 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2362 .max_rings = 8, 2363 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2364 .lmac_ring = FALSE, 2365 .ring_dir = HAL_SRNG_DST_RING, 2366 .nf_irq_support = true, 2367 .reg_start = { 2368 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2369 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2370 }, 2371 .reg_size = { 2372 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE) - 2373 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2374 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE) - 2375 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2376 }, 2377 .max_size = 2378 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2379 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2380 }, 2381 { /* RXDMA_BUF */ 2382 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2383 #ifdef IPA_OFFLOAD 2384 .max_rings = 3, 2385 #else 2386 .max_rings = 2, 2387 #endif 2388 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2389 .lmac_ring = TRUE, 2390 .ring_dir = HAL_SRNG_SRC_RING, 2391 /* reg_start is not set because LMAC rings are not accessed 2392 * from host 2393 */ 2394 .reg_start = {}, 2395 .reg_size = {}, 2396 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2397 }, 2398 { /* RXDMA_DST */ 2399 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2400 .max_rings = 1, 2401 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2402 .lmac_ring = TRUE, 2403 .ring_dir = HAL_SRNG_DST_RING, 2404 /* reg_start is not set because LMAC rings are not accessed 2405 * from host 2406 */ 2407 .reg_start = {}, 2408 .reg_size = {}, 2409 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2410 }, 2411 { /* RXDMA_MONITOR_BUF */ 2412 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2413 .max_rings = 1, 2414 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2415 .lmac_ring = TRUE, 2416 .ring_dir = HAL_SRNG_SRC_RING, 2417 /* reg_start is not set because LMAC rings are not accessed 2418 * from host 2419 */ 2420 .reg_start = {}, 2421 .reg_size = {}, 2422 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2423 }, 2424 { /* RXDMA_MONITOR_STATUS */ 2425 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2426 .max_rings = 1, 2427 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2428 .lmac_ring = TRUE, 2429 .ring_dir = HAL_SRNG_SRC_RING, 2430 /* reg_start is not set because LMAC rings are not accessed 2431 * from host 2432 */ 2433 .reg_start = {}, 2434 .reg_size = {}, 2435 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2436 }, 2437 { /* RXDMA_MONITOR_DST */ 2438 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2439 .max_rings = 1, 2440 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2441 .lmac_ring = TRUE, 2442 .ring_dir = HAL_SRNG_DST_RING, 2443 /* reg_start is not set because LMAC rings are not accessed 2444 * from host 2445 */ 2446 .reg_start = {}, 2447 .reg_size = {}, 2448 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2449 }, 2450 { /* RXDMA_MONITOR_DESC */ 2451 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2452 .max_rings = 1, 2453 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2454 .lmac_ring = TRUE, 2455 .ring_dir = HAL_SRNG_SRC_RING, 2456 /* reg_start is not set because LMAC rings are not accessed 2457 * from host 2458 */ 2459 .reg_start = {}, 2460 .reg_size = {}, 2461 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2462 }, 2463 { /* DIR_BUF_RX_DMA_SRC */ 2464 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2465 /* 2466 * one ring is for spectral scan 2467 * the other is for cfr 2468 */ 2469 .max_rings = 2, 2470 .entry_size = 2, 2471 .lmac_ring = TRUE, 2472 .ring_dir = HAL_SRNG_SRC_RING, 2473 /* reg_start is not set because LMAC rings are not accessed 2474 * from host 2475 */ 2476 .reg_start = {}, 2477 .reg_size = {}, 2478 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2479 }, 2480 #ifdef WLAN_FEATURE_CIF_CFR 2481 { /* WIFI_POS_SRC */ 2482 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2483 .max_rings = 1, 2484 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2485 .lmac_ring = TRUE, 2486 .ring_dir = HAL_SRNG_SRC_RING, 2487 /* reg_start is not set because LMAC rings are not accessed 2488 * from host 2489 */ 2490 .reg_start = {}, 2491 .reg_size = {}, 2492 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2493 }, 2494 #endif 2495 { /* REO2PPE */ 0}, 2496 { /* PPE2TCL */ 0}, 2497 { /* PPE_RELEASE */ 0}, 2498 { /* TX_MONITOR_BUF */ 0}, 2499 { /* TX_MONITOR_DST */ 0}, 2500 { /* SW2RXDMA_NEW */ 0}, 2501 }; 2502 2503 /** 2504 * hal_srng_hw_reg_offset_init_kiwi() - Initialize the HW srng reg offset 2505 * applicable only for KIWI 2506 * @hal_soc: HAL Soc handle 2507 * 2508 * Return: None 2509 */ 2510 static inline void hal_srng_hw_reg_offset_init_kiwi(struct hal_soc *hal_soc) 2511 { 2512 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 2513 2514 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB), 2515 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB), 2516 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA), 2517 hw_reg_offset[DST_PRODUCER_INT2_SETUP] = 2518 REG_OFFSET(DST, PRODUCER_INT2_SETUP); 2519 } 2520 2521 /** 2522 * hal_kiwi_attach() - Attach kiwi target specific hal_soc ops, 2523 * offset and srng table 2524 */ 2525 void hal_kiwi_attach(struct hal_soc *hal_soc) 2526 { 2527 hal_soc->hw_srng_table = hw_srng_table_kiwi; 2528 2529 hal_srng_hw_reg_offset_init_generic(hal_soc); 2530 hal_srng_hw_reg_offset_init_kiwi(hal_soc); 2531 hal_hw_txrx_default_ops_attach_be(hal_soc); 2532 hal_hw_txrx_ops_attach_kiwi(hal_soc); 2533 } 2534