1 /* 2 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "qdf_types.h" 21 #include "qdf_util.h" 22 #include "qdf_types.h" 23 #include "qdf_lock.h" 24 #include "qdf_mem.h" 25 #include "qdf_nbuf.h" 26 #include "hal_hw_headers.h" 27 #include "hal_internal.h" 28 #include "hal_api.h" 29 #include "target_type.h" 30 #include "wcss_version.h" 31 #include "qdf_module.h" 32 #include "hal_flow.h" 33 #include "rx_flow_search_entry.h" 34 #include "hal_rx_flow_info.h" 35 #include "hal_be_api.h" 36 #include "reo_destination_ring_with_pn.h" 37 #include "rx_reo_queue_1k.h" 38 39 #include <hal_be_rx.h> 40 41 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 42 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 43 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 44 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 45 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 46 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 47 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 48 PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 49 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 50 PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 51 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 52 PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 53 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 54 PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 59 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 60 PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 61 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 62 PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 63 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 64 PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 65 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 66 PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 67 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 68 PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 69 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 70 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 71 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 72 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 73 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 74 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 75 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 76 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 77 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 78 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 79 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 80 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 81 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 82 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 83 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 84 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 85 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 86 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 87 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 88 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 89 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 90 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 91 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 92 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 94 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 95 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 96 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 97 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 98 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 99 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 100 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 101 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 102 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 103 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 104 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 105 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 106 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 107 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 108 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 109 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 110 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 112 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 113 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 114 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 115 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 116 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 117 118 #include "hal_kiwi_tx.h" 119 #include "hal_kiwi_rx.h" 120 121 #include "hal_be_rx_tlv.h" 122 123 #include <hal_generic_api.h> 124 #include <hal_be_generic_api.h> 125 #include "hal_be_api_mon.h" 126 127 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 128 129 #ifdef QCA_GET_TSF_VIA_REG 130 #define PCIE_PCIE_MHI_TIME_LOW 0xA28 131 #define PCIE_PCIE_MHI_TIME_HIGH 0xA2C 132 133 #define PMM_REG_BASE 0xB500FC 134 135 #define FW_QTIME_CYCLES_PER_10_USEC 192 136 #endif 137 138 static uint32_t hal_get_link_desc_size_kiwi(void) 139 { 140 return LINK_DESC_SIZE; 141 } 142 143 /** 144 * hal_rx_dump_msdu_end_tlv_kiwi() - dump RX msdu_end TLV in structured 145 * human readable format. 146 * @msduend: pointer the msdu_end TLV in pkt. 147 * @dbg_level: log level. 148 * 149 * Return: void 150 */ 151 #ifdef QCA_WIFI_KIWI_V2 152 static void hal_rx_dump_msdu_end_tlv_kiwi(void *msduend, 153 uint8_t dbg_level) 154 { 155 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 156 157 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 158 "rx_msdu_end tlv (1/5)- " 159 "rxpcu_mpdu_filter_in_category :%x " 160 "sw_frame_group_id :%x " 161 "reserved_0 :%x " 162 "phy_ppdu_id :%x " 163 "ip_hdr_chksum :%x " 164 "reported_mpdu_length :%x " 165 "reserved_1a :%x " 166 "reserved_2a :%x " 167 "cce_super_rule :%x " 168 "cce_classify_not_done_truncate :%x " 169 "cce_classify_not_done_cce_dis :%x " 170 "cumulative_l3_checksum :%x " 171 "rule_indication_31_0 :%x " 172 "ipv6_options_crc :%x " 173 "da_offset :%x " 174 "sa_offset :%x " 175 "da_offset_valid :%x " 176 "sa_offset_valid :%x " 177 "reserved_5a :%x " 178 "l3_type :%x", 179 msdu_end->rxpcu_mpdu_filter_in_category, 180 msdu_end->sw_frame_group_id, 181 msdu_end->reserved_0, 182 msdu_end->phy_ppdu_id, 183 msdu_end->ip_hdr_chksum, 184 msdu_end->reported_mpdu_length, 185 msdu_end->reserved_1a, 186 msdu_end->reserved_2a, 187 msdu_end->cce_super_rule, 188 msdu_end->cce_classify_not_done_truncate, 189 msdu_end->cce_classify_not_done_cce_dis, 190 msdu_end->cumulative_l3_checksum, 191 msdu_end->rule_indication_31_0, 192 msdu_end->ipv6_options_crc, 193 msdu_end->da_offset, 194 msdu_end->sa_offset, 195 msdu_end->da_offset_valid, 196 msdu_end->sa_offset_valid, 197 msdu_end->reserved_5a, 198 msdu_end->l3_type); 199 200 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 201 "rx_msdu_end tlv (2/5)- " 202 "rule_indication_63_32 :%x " 203 "tcp_seq_number :%x " 204 "tcp_ack_number :%x " 205 "tcp_flag :%x " 206 "lro_eligible :%x " 207 "reserved_9a :%x " 208 "window_size :%x " 209 "sa_sw_peer_id :%x " 210 "sa_idx_timeout :%x " 211 "da_idx_timeout :%x " 212 "to_ds :%x " 213 "tid :%x " 214 "sa_is_valid :%x " 215 "da_is_valid :%x " 216 "da_is_mcbc :%x " 217 "l3_header_padding :%x " 218 "first_msdu :%x " 219 "last_msdu :%x " 220 "fr_ds :%x " 221 "ip_chksum_fail_copy :%x " 222 "sa_idx :%x " 223 "da_idx_or_sw_peer_id :%x", 224 msdu_end->rule_indication_63_32, 225 msdu_end->tcp_seq_number, 226 msdu_end->tcp_ack_number, 227 msdu_end->tcp_flag, 228 msdu_end->lro_eligible, 229 msdu_end->reserved_9a, 230 msdu_end->window_size, 231 msdu_end->sa_sw_peer_id, 232 msdu_end->sa_idx_timeout, 233 msdu_end->da_idx_timeout, 234 msdu_end->to_ds, 235 msdu_end->tid, 236 msdu_end->sa_is_valid, 237 msdu_end->da_is_valid, 238 msdu_end->da_is_mcbc, 239 msdu_end->l3_header_padding, 240 msdu_end->first_msdu, 241 msdu_end->last_msdu, 242 msdu_end->fr_ds, 243 msdu_end->ip_chksum_fail_copy, 244 msdu_end->sa_idx, 245 msdu_end->da_idx_or_sw_peer_id); 246 247 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 248 "rx_msdu_end tlv (3/5)- " 249 "msdu_drop :%x " 250 "reo_destination_indication :%x " 251 "flow_idx :%x " 252 "use_ppe :%x " 253 "__reserved_g_0003 :%x " 254 "vlan_ctag_stripped :%x " 255 "vlan_stag_stripped :%x " 256 "fragment_flag :%x " 257 "fse_metadata :%x " 258 "cce_metadata :%x " 259 "tcp_udp_chksum :%x " 260 "aggregation_count :%x " 261 "flow_aggregation_continuation :%x " 262 "fisa_timeout :%x " 263 "tcp_udp_chksum_fail_copy :%x " 264 "msdu_limit_error :%x " 265 "flow_idx_timeout :%x " 266 "flow_idx_invalid :%x " 267 "cce_match :%x " 268 "amsdu_parser_error :%x " 269 "cumulative_ip_length :%x " 270 "key_id_octet :%x " 271 "reserved_16a :%x " 272 "reserved_17a :%x " 273 "service_code :%x " 274 "priority_valid :%x " 275 "intra_bss :%x " 276 "dest_chip_id :%x " 277 "multicast_echo :%x " 278 "wds_learning_event :%x " 279 "wds_roaming_event :%x " 280 "wds_keep_alive_event :%x " 281 "reserved_17b :%x", 282 msdu_end->msdu_drop, 283 msdu_end->reo_destination_indication, 284 msdu_end->flow_idx, 285 msdu_end->use_ppe, 286 msdu_end->__reserved_g_0003, 287 msdu_end->vlan_ctag_stripped, 288 msdu_end->vlan_stag_stripped, 289 msdu_end->fragment_flag, 290 msdu_end->fse_metadata, 291 msdu_end->cce_metadata, 292 msdu_end->tcp_udp_chksum, 293 msdu_end->aggregation_count, 294 msdu_end->flow_aggregation_continuation, 295 msdu_end->fisa_timeout, 296 msdu_end->tcp_udp_chksum_fail_copy, 297 msdu_end->msdu_limit_error, 298 msdu_end->flow_idx_timeout, 299 msdu_end->flow_idx_invalid, 300 msdu_end->cce_match, 301 msdu_end->amsdu_parser_error, 302 msdu_end->cumulative_ip_length, 303 msdu_end->key_id_octet, 304 msdu_end->reserved_16a, 305 msdu_end->reserved_17a, 306 msdu_end->service_code, 307 msdu_end->priority_valid, 308 msdu_end->intra_bss, 309 msdu_end->dest_chip_id, 310 msdu_end->multicast_echo, 311 msdu_end->wds_learning_event, 312 msdu_end->wds_roaming_event, 313 msdu_end->wds_keep_alive_event, 314 msdu_end->reserved_17b); 315 316 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 317 "rx_msdu_end tlv (4/5)- " 318 "msdu_length :%x " 319 "stbc :%x " 320 "ipsec_esp :%x " 321 "l3_offset :%x " 322 "ipsec_ah :%x " 323 "l4_offset :%x " 324 "msdu_number :%x " 325 "decap_format :%x " 326 "ipv4_proto :%x " 327 "ipv6_proto :%x " 328 "tcp_proto :%x " 329 "udp_proto :%x " 330 "ip_frag :%x " 331 "tcp_only_ack :%x " 332 "da_is_bcast_mcast :%x " 333 "toeplitz_hash_sel :%x " 334 "ip_fixed_header_valid :%x " 335 "ip_extn_header_valid :%x " 336 "tcp_udp_header_valid :%x " 337 "mesh_control_present :%x " 338 "ldpc :%x " 339 "ip4_protocol_ip6_next_header :%x " 340 "vlan_ctag_ci :%x " 341 "vlan_stag_ci :%x " 342 "peer_meta_data :%x " 343 "user_rssi :%x " 344 "pkt_type :%x " 345 "sgi :%x " 346 "rate_mcs :%x " 347 "receive_bandwidth :%x " 348 "reception_type :%x " 349 "mimo_ss_bitmap :%x " 350 "msdu_done_copy :%x " 351 "flow_id_toeplitz :%x", 352 msdu_end->msdu_length, 353 msdu_end->stbc, 354 msdu_end->ipsec_esp, 355 msdu_end->l3_offset, 356 msdu_end->ipsec_ah, 357 msdu_end->l4_offset, 358 msdu_end->msdu_number, 359 msdu_end->decap_format, 360 msdu_end->ipv4_proto, 361 msdu_end->ipv6_proto, 362 msdu_end->tcp_proto, 363 msdu_end->udp_proto, 364 msdu_end->ip_frag, 365 msdu_end->tcp_only_ack, 366 msdu_end->da_is_bcast_mcast, 367 msdu_end->toeplitz_hash_sel, 368 msdu_end->ip_fixed_header_valid, 369 msdu_end->ip_extn_header_valid, 370 msdu_end->tcp_udp_header_valid, 371 msdu_end->mesh_control_present, 372 msdu_end->ldpc, 373 msdu_end->ip4_protocol_ip6_next_header, 374 msdu_end->vlan_ctag_ci, 375 msdu_end->vlan_stag_ci, 376 msdu_end->peer_meta_data, 377 msdu_end->user_rssi, 378 msdu_end->pkt_type, 379 msdu_end->sgi, 380 msdu_end->rate_mcs, 381 msdu_end->receive_bandwidth, 382 msdu_end->reception_type, 383 msdu_end->mimo_ss_bitmap, 384 msdu_end->msdu_done_copy, 385 msdu_end->flow_id_toeplitz); 386 387 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 388 "rx_msdu_end tlv (5/5)- " 389 "ppdu_start_timestamp_63_32 :%x " 390 "sw_phy_meta_data :%x " 391 "ppdu_start_timestamp_31_0 :%x " 392 "toeplitz_hash_2_or_4 :%x " 393 "reserved_28a :%x " 394 "sa_15_0 :%x " 395 "sa_47_16 :%x " 396 "first_mpdu :%x " 397 "reserved_30a :%x " 398 "mcast_bcast :%x " 399 "ast_index_not_found :%x " 400 "ast_index_timeout :%x " 401 "power_mgmt :%x " 402 "non_qos :%x " 403 "null_data :%x " 404 "mgmt_type :%x " 405 "ctrl_type :%x " 406 "more_data :%x " 407 "eosp :%x " 408 "a_msdu_error :%x " 409 "reserved_30b :%x " 410 "order :%x " 411 "wifi_parser_error :%x " 412 "overflow_err :%x " 413 "msdu_length_err :%x " 414 "tcp_udp_chksum_fail :%x " 415 "ip_chksum_fail :%x " 416 "sa_idx_invalid :%x " 417 "da_idx_invalid :%x " 418 "amsdu_addr_mismatch :%x " 419 "rx_in_tx_decrypt_byp :%x " 420 "encrypt_required :%x " 421 "directed :%x " 422 "buffer_fragment :%x " 423 "mpdu_length_err :%x " 424 "tkip_mic_err :%x " 425 "decrypt_err :%x " 426 "unencrypted_frame_err :%x " 427 "fcs_err :%x " 428 "reserved_31a :%x " 429 "decrypt_status_code :%x " 430 "rx_bitmap_not_updated :%x " 431 "reserved_31b :%x " 432 "msdu_done :%x", 433 msdu_end->ppdu_start_timestamp_63_32, 434 msdu_end->sw_phy_meta_data, 435 msdu_end->ppdu_start_timestamp_31_0, 436 msdu_end->toeplitz_hash_2_or_4, 437 msdu_end->reserved_28a, 438 msdu_end->sa_15_0, 439 msdu_end->sa_47_16, 440 msdu_end->first_mpdu, 441 msdu_end->reserved_30a, 442 msdu_end->mcast_bcast, 443 msdu_end->ast_index_not_found, 444 msdu_end->ast_index_timeout, 445 msdu_end->power_mgmt, 446 msdu_end->non_qos, 447 msdu_end->null_data, 448 msdu_end->mgmt_type, 449 msdu_end->ctrl_type, 450 msdu_end->more_data, 451 msdu_end->eosp, 452 msdu_end->a_msdu_error, 453 msdu_end->reserved_30b, 454 msdu_end->order, 455 msdu_end->wifi_parser_error, 456 msdu_end->overflow_err, 457 msdu_end->msdu_length_err, 458 msdu_end->tcp_udp_chksum_fail, 459 msdu_end->ip_chksum_fail, 460 msdu_end->sa_idx_invalid, 461 msdu_end->da_idx_invalid, 462 msdu_end->amsdu_addr_mismatch, 463 msdu_end->rx_in_tx_decrypt_byp, 464 msdu_end->encrypt_required, 465 msdu_end->directed, 466 msdu_end->buffer_fragment, 467 msdu_end->mpdu_length_err, 468 msdu_end->tkip_mic_err, 469 msdu_end->decrypt_err, 470 msdu_end->unencrypted_frame_err, 471 msdu_end->fcs_err, 472 msdu_end->reserved_31a, 473 msdu_end->decrypt_status_code, 474 msdu_end->rx_bitmap_not_updated, 475 msdu_end->reserved_31b, 476 msdu_end->msdu_done); 477 } 478 #else 479 static void hal_rx_dump_msdu_end_tlv_kiwi(void *msduend, 480 uint8_t dbg_level) 481 { 482 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 483 484 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 485 "rx_msdu_end tlv (1/7)- " 486 "rxpcu_mpdu_filter_in_category :%x" 487 "sw_frame_group_id :%x" 488 "reserved_0 :%x" 489 "phy_ppdu_id :%x" 490 "ip_hdr_chksum:%x" 491 "reported_mpdu_length :%x" 492 "reserved_1a :%x" 493 "key_id_octet :%x" 494 "cce_super_rule :%x" 495 "cce_classify_not_done_truncate :%x" 496 "cce_classify_not_done_cce_dis:%x" 497 "cumulative_l3_checksum :%x" 498 "rule_indication_31_0 :%x" 499 "rule_indication_63_32:%x" 500 "da_offset :%x" 501 "sa_offset :%x" 502 "da_offset_valid :%x" 503 "sa_offset_valid :%x" 504 "reserved_5a :%x" 505 "l3_type :%x", 506 msdu_end->rxpcu_mpdu_filter_in_category, 507 msdu_end->sw_frame_group_id, 508 msdu_end->reserved_0, 509 msdu_end->phy_ppdu_id, 510 msdu_end->ip_hdr_chksum, 511 msdu_end->reported_mpdu_length, 512 msdu_end->reserved_1a, 513 msdu_end->key_id_octet, 514 msdu_end->cce_super_rule, 515 msdu_end->cce_classify_not_done_truncate, 516 msdu_end->cce_classify_not_done_cce_dis, 517 msdu_end->cumulative_l3_checksum, 518 msdu_end->rule_indication_31_0, 519 msdu_end->rule_indication_63_32, 520 msdu_end->da_offset, 521 msdu_end->sa_offset, 522 msdu_end->da_offset_valid, 523 msdu_end->sa_offset_valid, 524 msdu_end->reserved_5a, 525 msdu_end->l3_type); 526 527 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 528 "rx_msdu_end tlv (2/7)- " 529 "ipv6_options_crc :%x" 530 "tcp_seq_number :%x" 531 "tcp_ack_number :%x" 532 "tcp_flag :%x" 533 "lro_eligible :%x" 534 "reserved_9a :%x" 535 "window_size :%x" 536 "tcp_udp_chksum :%x" 537 "sa_idx_timeout :%x" 538 "da_idx_timeout :%x" 539 "msdu_limit_error :%x" 540 "flow_idx_timeout :%x" 541 "flow_idx_invalid :%x" 542 "wifi_parser_error :%x" 543 "amsdu_parser_error :%x" 544 "sa_is_valid :%x" 545 "da_is_valid :%x" 546 "da_is_mcbc :%x" 547 "l3_header_padding :%x" 548 "first_msdu :%x" 549 "last_msdu :%x", 550 msdu_end->ipv6_options_crc, 551 msdu_end->tcp_seq_number, 552 msdu_end->tcp_ack_number, 553 msdu_end->tcp_flag, 554 msdu_end->lro_eligible, 555 msdu_end->reserved_9a, 556 msdu_end->window_size, 557 msdu_end->tcp_udp_chksum, 558 msdu_end->sa_idx_timeout, 559 msdu_end->da_idx_timeout, 560 msdu_end->msdu_limit_error, 561 msdu_end->flow_idx_timeout, 562 msdu_end->flow_idx_invalid, 563 msdu_end->wifi_parser_error, 564 msdu_end->amsdu_parser_error, 565 msdu_end->sa_is_valid, 566 msdu_end->da_is_valid, 567 msdu_end->da_is_mcbc, 568 msdu_end->l3_header_padding, 569 msdu_end->first_msdu, 570 msdu_end->last_msdu); 571 572 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 573 "rx_msdu_end tlv (3/7)" 574 "tcp_udp_chksum_fail_copy :%x" 575 "ip_chksum_fail_copy :%x" 576 "sa_idx :%x" 577 "da_idx_or_sw_peer_id :%x" 578 "msdu_drop :%x" 579 "reo_destination_indication :%x" 580 "flow_idx :%x" 581 "reserved_12a :%x" 582 "fse_metadata :%x" 583 "cce_metadata :%x" 584 "sa_sw_peer_id:%x" 585 "aggregation_count :%x" 586 "flow_aggregation_continuation:%x" 587 "fisa_timeout :%x" 588 "reserved_15a :%x" 589 "cumulative_l4_checksum :%x" 590 "cumulative_ip_length :%x" 591 "service_code :%x" 592 "priority_valid :%x", 593 msdu_end->tcp_udp_chksum_fail_copy, 594 msdu_end->ip_chksum_fail_copy, 595 msdu_end->sa_idx, 596 msdu_end->da_idx_or_sw_peer_id, 597 msdu_end->msdu_drop, 598 msdu_end->reo_destination_indication, 599 msdu_end->flow_idx, 600 msdu_end->reserved_12a, 601 msdu_end->fse_metadata, 602 msdu_end->cce_metadata, 603 msdu_end->sa_sw_peer_id, 604 msdu_end->aggregation_count, 605 msdu_end->flow_aggregation_continuation, 606 msdu_end->fisa_timeout, 607 msdu_end->reserved_15a, 608 msdu_end->cumulative_l4_checksum, 609 msdu_end->cumulative_ip_length, 610 msdu_end->service_code, 611 msdu_end->priority_valid); 612 613 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 614 "rx_msdu_end tlv (4/7)" 615 "reserved_17a :%x" 616 "msdu_length :%x" 617 "ipsec_esp :%x" 618 "l3_offset :%x" 619 "ipsec_ah :%x" 620 "l4_offset :%x" 621 "msdu_number :%x" 622 "decap_format :%x" 623 "ipv4_proto :%x" 624 "ipv6_proto :%x" 625 "tcp_proto :%x" 626 "udp_proto :%x" 627 "ip_frag :%x" 628 "tcp_only_ack :%x" 629 "da_is_bcast_mcast :%x" 630 "toeplitz_hash_sel :%x" 631 "ip_fixed_header_valid:%x" 632 "ip_extn_header_valid :%x" 633 "tcp_udp_header_valid :%x", 634 msdu_end->reserved_17a, 635 msdu_end->msdu_length, 636 msdu_end->ipsec_esp, 637 msdu_end->l3_offset, 638 msdu_end->ipsec_ah, 639 msdu_end->l4_offset, 640 msdu_end->msdu_number, 641 msdu_end->decap_format, 642 msdu_end->ipv4_proto, 643 msdu_end->ipv6_proto, 644 msdu_end->tcp_proto, 645 msdu_end->udp_proto, 646 msdu_end->ip_frag, 647 msdu_end->tcp_only_ack, 648 msdu_end->da_is_bcast_mcast, 649 msdu_end->toeplitz_hash_sel, 650 msdu_end->ip_fixed_header_valid, 651 msdu_end->ip_extn_header_valid, 652 msdu_end->tcp_udp_header_valid); 653 654 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 655 "rx_msdu_end tlv (5/7)" 656 "mesh_control_present :%x" 657 "ldpc :%x" 658 "ip4_protocol_ip6_next_header :%x" 659 "toeplitz_hash_2_or_4 :%x" 660 "flow_id_toeplitz :%x" 661 "user_rssi :%x" 662 "pkt_type :%x" 663 "stbc :%x" 664 "sgi :%x" 665 "rate_mcs :%x" 666 "receive_bandwidth :%x" 667 "reception_type :%x" 668 "mimo_ss_bitmap :%x" 669 "ppdu_start_timestamp_31_0 :%x" 670 "ppdu_start_timestamp_63_32 :%x" 671 "sw_phy_meta_data :%x" 672 "vlan_ctag_ci :%x" 673 "vlan_stag_ci :%x" 674 "first_mpdu :%x" 675 "reserved_30a :%x" 676 "mcast_bcast :%x", 677 msdu_end->mesh_control_present, 678 msdu_end->ldpc, 679 msdu_end->ip4_protocol_ip6_next_header, 680 msdu_end->toeplitz_hash_2_or_4, 681 msdu_end->flow_id_toeplitz, 682 msdu_end->user_rssi, 683 msdu_end->pkt_type, 684 msdu_end->stbc, 685 msdu_end->sgi, 686 msdu_end->rate_mcs, 687 msdu_end->receive_bandwidth, 688 msdu_end->reception_type, 689 msdu_end->mimo_ss_bitmap, 690 msdu_end->ppdu_start_timestamp_31_0, 691 msdu_end->ppdu_start_timestamp_63_32, 692 msdu_end->sw_phy_meta_data, 693 msdu_end->vlan_ctag_ci, 694 msdu_end->vlan_stag_ci, 695 msdu_end->first_mpdu, 696 msdu_end->reserved_30a, 697 msdu_end->mcast_bcast); 698 699 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 700 "rx_msdu_end tlv (6/7)" 701 "ast_index_not_found :%x" 702 "ast_index_timeout :%x" 703 "power_mgmt :%x" 704 "non_qos :%x" 705 "null_data :%x" 706 "mgmt_type :%x" 707 "ctrl_type :%x" 708 "more_data :%x" 709 "eosp :%x" 710 "a_msdu_error :%x" 711 "fragment_flag:%x" 712 "order:%x" 713 "cce_match :%x" 714 "overflow_err :%x" 715 "msdu_length_err :%x" 716 "tcp_udp_chksum_fail :%x" 717 "ip_chksum_fail :%x" 718 "sa_idx_invalid :%x" 719 "da_idx_invalid :%x" 720 "reserved_30b :%x", 721 msdu_end->ast_index_not_found, 722 msdu_end->ast_index_timeout, 723 msdu_end->power_mgmt, 724 msdu_end->non_qos, 725 msdu_end->null_data, 726 msdu_end->mgmt_type, 727 msdu_end->ctrl_type, 728 msdu_end->more_data, 729 msdu_end->eosp, 730 msdu_end->a_msdu_error, 731 msdu_end->fragment_flag, 732 msdu_end->order, 733 msdu_end->cce_match, 734 msdu_end->overflow_err, 735 msdu_end->msdu_length_err, 736 msdu_end->tcp_udp_chksum_fail, 737 msdu_end->ip_chksum_fail, 738 msdu_end->sa_idx_invalid, 739 msdu_end->da_idx_invalid, 740 msdu_end->reserved_30b); 741 742 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 743 "rx_msdu_end tlv (7/7)" 744 "rx_in_tx_decrypt_byp :%x" 745 "encrypt_required :%x" 746 "directed :%x" 747 "buffer_fragment :%x" 748 "mpdu_length_err :%x" 749 "tkip_mic_err :%x" 750 "decrypt_err :%x" 751 "unencrypted_frame_err:%x" 752 "fcs_err :%x" 753 "reserved_31a :%x" 754 "decrypt_status_code :%x" 755 "rx_bitmap_not_updated:%x" 756 "reserved_31b :%x" 757 "msdu_done :%x", 758 msdu_end->rx_in_tx_decrypt_byp, 759 msdu_end->encrypt_required, 760 msdu_end->directed, 761 msdu_end->buffer_fragment, 762 msdu_end->mpdu_length_err, 763 msdu_end->tkip_mic_err, 764 msdu_end->decrypt_err, 765 msdu_end->unencrypted_frame_err, 766 msdu_end->fcs_err, 767 msdu_end->reserved_31a, 768 msdu_end->decrypt_status_code, 769 msdu_end->rx_bitmap_not_updated, 770 msdu_end->reserved_31b, 771 msdu_end->msdu_done); 772 } 773 #endif 774 775 #ifdef NO_RX_PKT_HDR_TLV 776 static inline void hal_rx_dump_pkt_hdr_tlv_kiwi(struct rx_pkt_tlvs *pkt_tlvs, 777 uint8_t dbg_level) 778 { 779 } 780 781 static inline 782 void hal_register_rx_pkt_hdr_tlv_api_kiwi(struct hal_soc *hal_soc) 783 { 784 } 785 786 static uint8_t *hal_rx_desc_get_80211_hdr_be(void *hw_desc_addr) 787 { 788 uint8_t *rx_pkt_hdr; 789 struct rx_mon_pkt_tlvs *rx_desc = 790 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 791 792 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 793 794 return rx_pkt_hdr; 795 } 796 #else 797 static uint8_t *hal_rx_desc_get_80211_hdr_be(void *hw_desc_addr) 798 { 799 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 800 uint8_t *rx_pkt_hdr; 801 802 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 803 804 return rx_pkt_hdr; 805 } 806 807 /** 808 * hal_rx_dump_pkt_hdr_tlv_kiwi() - dump RX pkt header TLV in hex format 809 * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt. 810 * @dbg_level: log level. 811 * 812 * Return: void 813 */ 814 static inline void hal_rx_dump_pkt_hdr_tlv_kiwi(struct rx_pkt_tlvs *pkt_tlvs, 815 uint8_t dbg_level) 816 { 817 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 818 819 hal_verbose_debug("\n---------------\n" 820 "rx_pkt_hdr_tlv\n" 821 "---------------\n" 822 "phy_ppdu_id %lld ", 823 pkt_hdr_tlv->phy_ppdu_id); 824 825 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 826 sizeof(pkt_hdr_tlv->rx_pkt_hdr)); 827 } 828 829 /** 830 * hal_register_rx_pkt_hdr_tlv_api_kiwi: register all rx_pkt_hdr_tlv related api 831 * @hal_soc: HAL soc handler 832 * 833 * Return: none 834 */ 835 static inline 836 void hal_register_rx_pkt_hdr_tlv_api_kiwi(struct hal_soc *hal_soc) 837 { 838 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 839 hal_rx_pkt_tlv_offset_get_generic; 840 } 841 #endif 842 843 /** 844 * hal_rx_dump_mpdu_start_tlv_kiwi(): dump RX mpdu_start TLV in structured 845 * human readable format. 846 * @mpdustart: pointer the rx_attention TLV in pkt. 847 * @dbg_level: log level. 848 * 849 * Return: void 850 */ 851 static inline void hal_rx_dump_mpdu_start_tlv_kiwi(void *mpdustart, 852 uint8_t dbg_level) 853 { 854 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 855 struct rx_mpdu_info *mpdu_info = 856 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 857 858 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 859 "rx_mpdu_start tlv (1/5) - " 860 "rx_reo_queue_desc_addr_31_0 :%x" 861 "rx_reo_queue_desc_addr_39_32 :%x" 862 "receive_queue_number:%x " 863 "pre_delim_err_warning:%x " 864 "first_delim_err:%x " 865 "reserved_2a:%x " 866 "pn_31_0:%x " 867 "pn_63_32:%x " 868 "pn_95_64:%x " 869 "pn_127_96:%x " 870 "epd_en:%x " 871 "all_frames_shall_be_encrypted :%x" 872 "encrypt_type:%x " 873 "wep_key_width_for_variable_key :%x" 874 "bssid_hit:%x " 875 "bssid_number:%x " 876 "tid:%x " 877 "reserved_7a:%x " 878 "peer_meta_data:%x ", 879 mpdu_info->rx_reo_queue_desc_addr_31_0, 880 mpdu_info->rx_reo_queue_desc_addr_39_32, 881 mpdu_info->receive_queue_number, 882 mpdu_info->pre_delim_err_warning, 883 mpdu_info->first_delim_err, 884 mpdu_info->reserved_2a, 885 mpdu_info->pn_31_0, 886 mpdu_info->pn_63_32, 887 mpdu_info->pn_95_64, 888 mpdu_info->pn_127_96, 889 mpdu_info->epd_en, 890 mpdu_info->all_frames_shall_be_encrypted, 891 mpdu_info->encrypt_type, 892 mpdu_info->wep_key_width_for_variable_key, 893 mpdu_info->bssid_hit, 894 mpdu_info->bssid_number, 895 mpdu_info->tid, 896 mpdu_info->reserved_7a, 897 mpdu_info->peer_meta_data); 898 899 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 900 "rx_mpdu_start tlv (2/5) - " 901 "rxpcu_mpdu_filter_in_category :%x" 902 "sw_frame_group_id:%x " 903 "ndp_frame:%x " 904 "phy_err:%x " 905 "phy_err_during_mpdu_header :%x" 906 "protocol_version_err:%x " 907 "ast_based_lookup_valid:%x " 908 "reserved_9a:%x " 909 "phy_ppdu_id:%x " 910 "ast_index:%x " 911 "sw_peer_id:%x " 912 "mpdu_frame_control_valid:%x " 913 "mpdu_duration_valid:%x " 914 "mac_addr_ad1_valid:%x " 915 "mac_addr_ad2_valid:%x " 916 "mac_addr_ad3_valid:%x " 917 "mac_addr_ad4_valid:%x " 918 "mpdu_sequence_control_valid :%x" 919 "mpdu_qos_control_valid:%x " 920 "mpdu_ht_control_valid:%x " 921 "frame_encryption_info_valid :%x", 922 mpdu_info->rxpcu_mpdu_filter_in_category, 923 mpdu_info->sw_frame_group_id, 924 mpdu_info->ndp_frame, 925 mpdu_info->phy_err, 926 mpdu_info->phy_err_during_mpdu_header, 927 mpdu_info->protocol_version_err, 928 mpdu_info->ast_based_lookup_valid, 929 mpdu_info->reserved_9a, 930 mpdu_info->phy_ppdu_id, 931 mpdu_info->ast_index, 932 mpdu_info->sw_peer_id, 933 mpdu_info->mpdu_frame_control_valid, 934 mpdu_info->mpdu_duration_valid, 935 mpdu_info->mac_addr_ad1_valid, 936 mpdu_info->mac_addr_ad2_valid, 937 mpdu_info->mac_addr_ad3_valid, 938 mpdu_info->mac_addr_ad4_valid, 939 mpdu_info->mpdu_sequence_control_valid, 940 mpdu_info->mpdu_qos_control_valid, 941 mpdu_info->mpdu_ht_control_valid, 942 mpdu_info->frame_encryption_info_valid); 943 944 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 945 "rx_mpdu_start tlv (3/5) - " 946 "mpdu_fragment_number:%x " 947 "more_fragment_flag:%x " 948 "reserved_11a:%x " 949 "fr_ds:%x " 950 "to_ds:%x " 951 "encrypted:%x " 952 "mpdu_retry:%x " 953 "mpdu_sequence_number:%x " 954 "key_id_octet:%x " 955 "new_peer_entry:%x " 956 "decrypt_needed:%x " 957 "decap_type:%x " 958 "rx_insert_vlan_c_tag_padding :%x" 959 "rx_insert_vlan_s_tag_padding :%x" 960 "strip_vlan_c_tag_decap:%x " 961 "strip_vlan_s_tag_decap:%x " 962 "pre_delim_count:%x " 963 "ampdu_flag:%x " 964 "bar_frame:%x " 965 "raw_mpdu:%x " 966 "reserved_12:%x " 967 "mpdu_length:%x ", 968 mpdu_info->mpdu_fragment_number, 969 mpdu_info->more_fragment_flag, 970 mpdu_info->reserved_11a, 971 mpdu_info->fr_ds, 972 mpdu_info->to_ds, 973 mpdu_info->encrypted, 974 mpdu_info->mpdu_retry, 975 mpdu_info->mpdu_sequence_number, 976 mpdu_info->key_id_octet, 977 mpdu_info->new_peer_entry, 978 mpdu_info->decrypt_needed, 979 mpdu_info->decap_type, 980 mpdu_info->rx_insert_vlan_c_tag_padding, 981 mpdu_info->rx_insert_vlan_s_tag_padding, 982 mpdu_info->strip_vlan_c_tag_decap, 983 mpdu_info->strip_vlan_s_tag_decap, 984 mpdu_info->pre_delim_count, 985 mpdu_info->ampdu_flag, 986 mpdu_info->bar_frame, 987 mpdu_info->raw_mpdu, 988 mpdu_info->reserved_12, 989 mpdu_info->mpdu_length); 990 991 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 992 "rx_mpdu_start tlv (4/5) - " 993 "mpdu_length:%x " 994 "first_mpdu:%x " 995 "mcast_bcast:%x " 996 "ast_index_not_found:%x " 997 "ast_index_timeout:%x " 998 "power_mgmt:%x " 999 "non_qos:%x " 1000 "null_data:%x " 1001 "mgmt_type:%x " 1002 "ctrl_type:%x " 1003 "more_data:%x " 1004 "eosp:%x " 1005 "fragment_flag:%x " 1006 "order:%x " 1007 "u_apsd_trigger:%x " 1008 "encrypt_required:%x " 1009 "directed:%x " 1010 "amsdu_present:%x " 1011 "reserved_13:%x " 1012 "mpdu_frame_control_field:%x " 1013 "mpdu_duration_field:%x ", 1014 mpdu_info->mpdu_length, 1015 mpdu_info->first_mpdu, 1016 mpdu_info->mcast_bcast, 1017 mpdu_info->ast_index_not_found, 1018 mpdu_info->ast_index_timeout, 1019 mpdu_info->power_mgmt, 1020 mpdu_info->non_qos, 1021 mpdu_info->null_data, 1022 mpdu_info->mgmt_type, 1023 mpdu_info->ctrl_type, 1024 mpdu_info->more_data, 1025 mpdu_info->eosp, 1026 mpdu_info->fragment_flag, 1027 mpdu_info->order, 1028 mpdu_info->u_apsd_trigger, 1029 mpdu_info->encrypt_required, 1030 mpdu_info->directed, 1031 mpdu_info->amsdu_present, 1032 mpdu_info->reserved_13, 1033 mpdu_info->mpdu_frame_control_field, 1034 mpdu_info->mpdu_duration_field); 1035 1036 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 1037 "rx_mpdu_start tlv (5/5) - " 1038 "mac_addr_ad1_31_0:%x " 1039 "mac_addr_ad1_47_32:%x " 1040 "mac_addr_ad2_15_0:%x " 1041 "mac_addr_ad2_47_16:%x " 1042 "mac_addr_ad3_31_0:%x " 1043 "mac_addr_ad3_47_32:%x " 1044 "mpdu_sequence_control_field :%x" 1045 "mac_addr_ad4_31_0:%x " 1046 "mac_addr_ad4_47_32:%x " 1047 "mpdu_qos_control_field:%x " 1048 "mpdu_ht_control_field:%x " 1049 "vdev_id:%x " 1050 "service_code:%x " 1051 "priority_valid:%x " 1052 "reserved_23a:%x ", 1053 mpdu_info->mac_addr_ad1_31_0, 1054 mpdu_info->mac_addr_ad1_47_32, 1055 mpdu_info->mac_addr_ad2_15_0, 1056 mpdu_info->mac_addr_ad2_47_16, 1057 mpdu_info->mac_addr_ad3_31_0, 1058 mpdu_info->mac_addr_ad3_47_32, 1059 mpdu_info->mpdu_sequence_control_field, 1060 mpdu_info->mac_addr_ad4_31_0, 1061 mpdu_info->mac_addr_ad4_47_32, 1062 mpdu_info->mpdu_qos_control_field, 1063 mpdu_info->mpdu_ht_control_field, 1064 mpdu_info->vdev_id, 1065 mpdu_info->service_code, 1066 mpdu_info->priority_valid, 1067 mpdu_info->reserved_23a); 1068 } 1069 1070 /** 1071 * hal_rx_dump_pkt_tlvs_kiwi(): API to print RX Pkt TLVS for kiwi 1072 * @hal_soc_hdl: hal_soc handle 1073 * @buf: pointer the pkt buffer 1074 * @dbg_level: log level 1075 * 1076 * Return: void 1077 */ 1078 static void hal_rx_dump_pkt_tlvs_kiwi(hal_soc_handle_t hal_soc_hdl, 1079 uint8_t *buf, uint8_t dbg_level) 1080 { 1081 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1082 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1083 struct rx_mpdu_start *mpdu_start = 1084 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1085 1086 hal_rx_dump_msdu_end_tlv_kiwi(msdu_end, dbg_level); 1087 hal_rx_dump_mpdu_start_tlv_kiwi(mpdu_start, dbg_level); 1088 hal_rx_dump_pkt_hdr_tlv_kiwi(pkt_tlvs, dbg_level); 1089 } 1090 1091 /** 1092 * hal_rx_get_mpdu_flags_from_tlv() - Populate the local mpdu_flags elements 1093 * from the rx tlvs 1094 * @mpdu_info: buf address to rx_mpdu_info 1095 * 1096 * Return: mpdu_flags. 1097 */ 1098 static inline uint32_t 1099 hal_rx_get_mpdu_flags_from_tlv(struct rx_mpdu_info *mpdu_info) 1100 { 1101 uint32_t mpdu_flags = 0; 1102 1103 if (mpdu_info->fragment_flag) 1104 mpdu_flags |= HAL_MPDU_F_FRAGMENT; 1105 1106 if (mpdu_info->mpdu_retry) 1107 mpdu_flags |= HAL_MPDU_F_RETRY_BIT; 1108 1109 if (mpdu_info->ampdu_flag) 1110 mpdu_flags |= HAL_MPDU_F_AMPDU_FLAG; 1111 1112 if (mpdu_info->raw_mpdu) 1113 mpdu_flags |= HAL_MPDU_F_RAW_AMPDU; 1114 1115 if (mpdu_info->mpdu_qos_control_valid) 1116 mpdu_flags |= HAL_MPDU_F_QOS_CONTROL_VALID; 1117 1118 return mpdu_flags; 1119 } 1120 1121 /** 1122 * hal_rx_tlv_populate_mpdu_desc_info_kiwi() - Populate the local mpdu_desc_info 1123 * elements from the rx tlvs 1124 * @buf: start address of rx tlvs [Validated by caller] 1125 * @mpdu_desc_info_hdl: Buffer to populate the mpdu_dsc_info 1126 * [To be validated by caller] 1127 * 1128 * Return: None 1129 */ 1130 static void 1131 hal_rx_tlv_populate_mpdu_desc_info_kiwi(uint8_t *buf, 1132 void *mpdu_desc_info_hdl) 1133 { 1134 struct hal_rx_mpdu_desc_info *mpdu_desc_info = 1135 (struct hal_rx_mpdu_desc_info *)mpdu_desc_info_hdl; 1136 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1137 struct rx_mpdu_start *mpdu_start = 1138 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1139 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1140 1141 mpdu_desc_info->mpdu_seq = mpdu_info->mpdu_sequence_number; 1142 mpdu_desc_info->mpdu_flags = hal_rx_get_mpdu_flags_from_tlv(mpdu_info); 1143 mpdu_desc_info->peer_meta_data = mpdu_info->peer_meta_data; 1144 mpdu_desc_info->bar_frame = mpdu_info->bar_frame; 1145 } 1146 1147 /** 1148 * hal_reo_status_get_header_kiwi() - Process reo desc info 1149 * @ring_desc: Pointer to reo descriptor 1150 * @b: tlv type info 1151 * @h1: Pointer to hal_reo_status_header where info to be stored 1152 * 1153 * Return: none. 1154 * 1155 */ 1156 static void hal_reo_status_get_header_kiwi(hal_ring_desc_t ring_desc, int b, 1157 void *h1) 1158 { 1159 uint64_t *d = (uint64_t *)ring_desc; 1160 uint64_t val1 = 0; 1161 struct hal_reo_status_header *h = 1162 (struct hal_reo_status_header *)h1; 1163 1164 /* Offsets of descriptor fields defined in HW headers start 1165 * from the field after TLV header 1166 */ 1167 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr)); 1168 1169 switch (b) { 1170 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1171 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1172 STATUS_HEADER_REO_STATUS_NUMBER)]; 1173 break; 1174 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1175 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1176 STATUS_HEADER_REO_STATUS_NUMBER)]; 1177 break; 1178 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1179 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1180 STATUS_HEADER_REO_STATUS_NUMBER)]; 1181 break; 1182 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1183 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1184 STATUS_HEADER_REO_STATUS_NUMBER)]; 1185 break; 1186 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1187 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1188 STATUS_HEADER_REO_STATUS_NUMBER)]; 1189 break; 1190 case HAL_REO_DESC_THRES_STATUS_TLV: 1191 val1 = 1192 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1193 STATUS_HEADER_REO_STATUS_NUMBER)]; 1194 break; 1195 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1196 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1197 STATUS_HEADER_REO_STATUS_NUMBER)]; 1198 break; 1199 default: 1200 qdf_nofl_err("ERROR: Unknown tlv\n"); 1201 break; 1202 } 1203 h->cmd_num = 1204 HAL_GET_FIELD( 1205 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER, 1206 val1); 1207 h->exec_time = 1208 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1209 CMD_EXECUTION_TIME, val1); 1210 h->status = 1211 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1212 REO_CMD_EXECUTION_STATUS, val1); 1213 switch (b) { 1214 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1215 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1216 STATUS_HEADER_TIMESTAMP)]; 1217 break; 1218 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1219 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1220 STATUS_HEADER_TIMESTAMP)]; 1221 break; 1222 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1223 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1224 STATUS_HEADER_TIMESTAMP)]; 1225 break; 1226 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1227 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1228 STATUS_HEADER_TIMESTAMP)]; 1229 break; 1230 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1231 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1232 STATUS_HEADER_TIMESTAMP)]; 1233 break; 1234 case HAL_REO_DESC_THRES_STATUS_TLV: 1235 val1 = 1236 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1237 STATUS_HEADER_TIMESTAMP)]; 1238 break; 1239 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1240 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1241 STATUS_HEADER_TIMESTAMP)]; 1242 break; 1243 default: 1244 qdf_nofl_err("ERROR: Unknown tlv\n"); 1245 break; 1246 } 1247 h->tstamp = 1248 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1); 1249 } 1250 1251 static 1252 void *hal_rx_msdu0_buffer_addr_lsb_kiwi(void *link_desc_va) 1253 { 1254 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1255 } 1256 1257 static 1258 void *hal_rx_msdu_desc_info_ptr_get_kiwi(void *msdu0) 1259 { 1260 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1261 } 1262 1263 static 1264 void *hal_ent_mpdu_desc_info_kiwi(void *ent_ring_desc) 1265 { 1266 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1267 } 1268 1269 static 1270 void *hal_dst_mpdu_desc_info_kiwi(void *dst_ring_desc) 1271 { 1272 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1273 } 1274 1275 /** 1276 * hal_rx_get_tlv_kiwi() - API to get the tlv 1277 * @rx_tlv: TLV data extracted from the rx packet 1278 * 1279 * Return: uint8_t 1280 */ 1281 static uint8_t hal_rx_get_tlv_kiwi(void *rx_tlv) 1282 { 1283 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH); 1284 } 1285 1286 /** 1287 * hal_rx_proc_phyrx_other_receive_info_tlv_kiwi() 1288 * - process other receive info TLV 1289 * @rx_tlv_hdr: pointer to TLV header 1290 * @ppdu_info_handle: pointer to ppdu_info 1291 * 1292 * Return: None 1293 */ 1294 static 1295 void hal_rx_proc_phyrx_other_receive_info_tlv_kiwi(void *rx_tlv_hdr, 1296 void *ppdu_info_handle) 1297 { 1298 uint32_t tlv_tag, tlv_len; 1299 uint32_t temp_len, other_tlv_len, other_tlv_tag; 1300 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 1301 void *other_tlv_hdr = NULL; 1302 void *other_tlv = NULL; 1303 1304 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 1305 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 1306 temp_len = 0; 1307 1308 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 1309 1310 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 1311 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 1312 temp_len += other_tlv_len; 1313 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 1314 1315 switch (other_tlv_tag) { 1316 default: 1317 hal_err_rl("unhandled TLV type: %d, TLV len:%d", 1318 other_tlv_tag, other_tlv_len); 1319 break; 1320 } 1321 } 1322 1323 /** 1324 * hal_reo_config_kiwi(): Set reo config parameters 1325 * @soc: hal soc handle 1326 * @reg_val: value to be set 1327 * @reo_params: reo parameters 1328 * 1329 * Return: void 1330 */ 1331 static 1332 void hal_reo_config_kiwi(struct hal_soc *soc, 1333 uint32_t reg_val, 1334 struct hal_reo_params *reo_params) 1335 { 1336 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1337 } 1338 1339 /** 1340 * hal_rx_msdu_desc_info_get_ptr_kiwi() - Get msdu desc info ptr 1341 * @msdu_details_ptr: Pointer to msdu_details_ptr 1342 * 1343 * Return: Pointer to rx_msdu_desc_info structure. 1344 * 1345 */ 1346 static void *hal_rx_msdu_desc_info_get_ptr_kiwi(void *msdu_details_ptr) 1347 { 1348 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1349 } 1350 1351 /** 1352 * hal_rx_link_desc_msdu0_ptr_kiwi() - Get pointer to rx_msdu details 1353 * @link_desc: Pointer to link desc 1354 * 1355 * Return: Pointer to rx_msdu_details structure 1356 * 1357 */ 1358 static void *hal_rx_link_desc_msdu0_ptr_kiwi(void *link_desc) 1359 { 1360 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1361 } 1362 1363 /** 1364 * hal_get_window_address_kiwi(): Function to get hp/tp address 1365 * @hal_soc: Pointer to hal_soc 1366 * @addr: address offset of register 1367 * 1368 * Return: modified address offset of register 1369 */ 1370 static inline qdf_iomem_t hal_get_window_address_kiwi(struct hal_soc *hal_soc, 1371 qdf_iomem_t addr) 1372 { 1373 return addr; 1374 } 1375 1376 /** 1377 * hal_reo_set_err_dst_remap_kiwi(): Function to set REO error destination 1378 * ring remap register 1379 * @hal_soc: Pointer to hal_soc 1380 * 1381 * Return: none. 1382 */ 1383 static void 1384 hal_reo_set_err_dst_remap_kiwi(void *hal_soc) 1385 { 1386 /* 1387 * Set REO error 2k jump (error code 5) / OOR (error code 7) 1388 * frame routed to REO2SW0 ring. 1389 */ 1390 uint32_t dst_remap_ix0 = 1391 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 0) | 1392 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 1) | 1393 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 2) | 1394 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 3) | 1395 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 4) | 1396 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) | 1397 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) | 1398 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7); 1399 1400 uint32_t dst_remap_ix1 = 1401 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 14) | 1402 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 13) | 1403 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 12) | 1404 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 11) | 1405 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 10) | 1406 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 9) | 1407 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 8); 1408 1409 HAL_REG_WRITE(hal_soc, 1410 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1411 REO_REG_REG_BASE), 1412 dst_remap_ix0); 1413 1414 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x", 1415 HAL_REG_READ( 1416 hal_soc, 1417 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1418 REO_REG_REG_BASE))); 1419 1420 HAL_REG_WRITE(hal_soc, 1421 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1422 REO_REG_REG_BASE), 1423 dst_remap_ix1); 1424 1425 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1 0x%x", 1426 HAL_REG_READ( 1427 hal_soc, 1428 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1429 REO_REG_REG_BASE))); 1430 } 1431 1432 /** 1433 * hal_reo_enable_pn_in_dest_kiwi() - Set the REO register to enable previous PN 1434 * for OOR and 2K-jump frames 1435 * @hal_soc: HAL SoC handle 1436 * 1437 * Return: 1, since the register is set. 1438 */ 1439 static uint8_t hal_reo_enable_pn_in_dest_kiwi(void *hal_soc) 1440 { 1441 HAL_REG_WRITE(hal_soc, HWIO_REO_R0_PN_IN_DEST_ADDR(REO_REG_REG_BASE), 1442 1); 1443 return 1; 1444 } 1445 1446 /** 1447 * hal_rx_flow_setup_fse_kiwi() - Setup a flow search entry in HW FST 1448 * @rx_fst: Pointer to the Rx Flow Search Table 1449 * @table_offset: offset into the table where the flow is to be setup 1450 * @rx_flow: Flow Parameters 1451 * 1452 * Flow table entry fields are updated in host byte order, little endian order. 1453 * 1454 * Return: Success/Failure 1455 */ 1456 static void * 1457 hal_rx_flow_setup_fse_kiwi(uint8_t *rx_fst, uint32_t table_offset, 1458 uint8_t *rx_flow) 1459 { 1460 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1461 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1462 uint8_t *fse; 1463 bool fse_valid; 1464 1465 if (table_offset >= fst->max_entries) { 1466 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1467 "HAL FSE table offset %u exceeds max entries %u", 1468 table_offset, fst->max_entries); 1469 return NULL; 1470 } 1471 1472 fse = (uint8_t *)fst->base_vaddr + 1473 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1474 1475 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1476 1477 if (fse_valid) { 1478 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1479 "HAL FSE %pK already valid", fse); 1480 return NULL; 1481 } 1482 1483 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) = 1484 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1485 (flow->tuple_info.src_ip_127_96)); 1486 1487 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) = 1488 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1489 (flow->tuple_info.src_ip_95_64)); 1490 1491 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) = 1492 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1493 (flow->tuple_info.src_ip_63_32)); 1494 1495 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) = 1496 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1497 (flow->tuple_info.src_ip_31_0)); 1498 1499 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) = 1500 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1501 (flow->tuple_info.dest_ip_127_96)); 1502 1503 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) = 1504 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1505 (flow->tuple_info.dest_ip_95_64)); 1506 1507 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) = 1508 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1509 (flow->tuple_info.dest_ip_63_32)); 1510 1511 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) = 1512 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1513 (flow->tuple_info.dest_ip_31_0)); 1514 1515 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT); 1516 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |= 1517 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1518 (flow->tuple_info.dest_port)); 1519 1520 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT); 1521 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |= 1522 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1523 (flow->tuple_info.src_port)); 1524 1525 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL); 1526 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |= 1527 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1528 flow->tuple_info.l4_protocol); 1529 1530 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER); 1531 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |= 1532 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1533 flow->reo_destination_handler); 1534 1535 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1536 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |= 1537 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1538 1539 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA); 1540 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) = 1541 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1542 (flow->fse_metadata)); 1543 1544 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION); 1545 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |= 1546 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1547 REO_DESTINATION_INDICATION, 1548 flow->reo_destination_indication); 1549 1550 /* Reset all the other fields in FSE */ 1551 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9); 1552 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP); 1553 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT); 1554 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT); 1555 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP); 1556 1557 return fse; 1558 } 1559 1560 /** 1561 * hal_rx_flow_setup_cmem_fse_kiwi() - Setup a flow search entry in HW CMEM FST 1562 * @hal_soc: hal_soc reference 1563 * @cmem_ba: CMEM base address 1564 * @table_offset: offset into the table where the flow is to be setup 1565 * @rx_flow: Flow Parameters 1566 * 1567 * Return: Success/Failure 1568 */ 1569 static uint32_t 1570 hal_rx_flow_setup_cmem_fse_kiwi(struct hal_soc *hal_soc, uint32_t cmem_ba, 1571 uint32_t table_offset, uint8_t *rx_flow) 1572 { 1573 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1574 uint32_t fse_offset; 1575 uint32_t value; 1576 1577 fse_offset = cmem_ba + (table_offset * HAL_RX_FST_ENTRY_SIZE); 1578 1579 /* Reset the Valid bit */ 1580 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1581 VALID), 0); 1582 1583 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1584 (flow->tuple_info.src_ip_127_96)); 1585 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1586 SRC_IP_127_96), value); 1587 1588 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1589 (flow->tuple_info.src_ip_95_64)); 1590 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1591 SRC_IP_95_64), value); 1592 1593 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1594 (flow->tuple_info.src_ip_63_32)); 1595 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1596 SRC_IP_63_32), value); 1597 1598 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1599 (flow->tuple_info.src_ip_31_0)); 1600 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1601 SRC_IP_31_0), value); 1602 1603 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1604 (flow->tuple_info.dest_ip_127_96)); 1605 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1606 DEST_IP_127_96), value); 1607 1608 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1609 (flow->tuple_info.dest_ip_95_64)); 1610 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1611 DEST_IP_95_64), value); 1612 1613 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1614 (flow->tuple_info.dest_ip_63_32)); 1615 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1616 DEST_IP_63_32), value); 1617 1618 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1619 (flow->tuple_info.dest_ip_31_0)); 1620 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1621 DEST_IP_31_0), value); 1622 1623 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1624 (flow->tuple_info.dest_port)); 1625 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1626 (flow->tuple_info.src_port)); 1627 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1628 SRC_PORT), value); 1629 1630 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1631 (flow->fse_metadata)); 1632 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1633 METADATA), value); 1634 1635 /* Reset all the other fields in FSE */ 1636 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1637 MSDU_COUNT), 0); 1638 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1639 MSDU_BYTE_COUNT), 0); 1640 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1641 TIMESTAMP), 0); 1642 1643 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1644 flow->tuple_info.l4_protocol); 1645 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1646 flow->reo_destination_handler); 1647 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1648 REO_DESTINATION_INDICATION, 1649 flow->reo_destination_indication); 1650 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1651 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1652 L4_PROTOCOL), value); 1653 1654 return fse_offset; 1655 } 1656 1657 /** 1658 * hal_rx_flow_get_cmem_fse_ts_kiwi() - Get timestamp field from CMEM FSE 1659 * @hal_soc: hal_soc reference 1660 * @fse_offset: CMEM FSE offset 1661 * 1662 * Return: Timestamp 1663 */ 1664 static uint32_t hal_rx_flow_get_cmem_fse_ts_kiwi(struct hal_soc *hal_soc, 1665 uint32_t fse_offset) 1666 { 1667 return HAL_CMEM_READ(hal_soc, fse_offset + 1668 HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, TIMESTAMP)); 1669 } 1670 1671 /** 1672 * hal_rx_flow_get_cmem_fse_kiwi() - Get FSE from CMEM 1673 * @hal_soc: hal_soc reference 1674 * @fse_offset: CMEM FSE offset 1675 * @fse: reference where FSE will be copied 1676 * @len: length of FSE 1677 * 1678 * Return: If read is successful or not 1679 */ 1680 static void 1681 hal_rx_flow_get_cmem_fse_kiwi(struct hal_soc *hal_soc, uint32_t fse_offset, 1682 uint32_t *fse, qdf_size_t len) 1683 { 1684 int i; 1685 1686 if (len != HAL_RX_FST_ENTRY_SIZE) 1687 return; 1688 1689 for (i = 0; i < NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY; i++) 1690 fse[i] = HAL_CMEM_READ(hal_soc, fse_offset + i * 4); 1691 } 1692 1693 static 1694 void hal_compute_reo_remap_ix2_ix3_kiwi(uint32_t *ring_map, 1695 uint32_t num_rings, uint32_t *remap1, 1696 uint32_t *remap2) 1697 { 1698 1699 switch (num_rings) { 1700 /* should we have all the different possible ring configs */ 1701 default: 1702 case 3: 1703 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1704 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1705 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1706 HAL_REO_REMAP_IX2(ring_map[0], 19) | 1707 HAL_REO_REMAP_IX2(ring_map[1], 20) | 1708 HAL_REO_REMAP_IX2(ring_map[2], 21) | 1709 HAL_REO_REMAP_IX2(ring_map[0], 22) | 1710 HAL_REO_REMAP_IX2(ring_map[1], 23); 1711 1712 *remap2 = HAL_REO_REMAP_IX3(ring_map[2], 24) | 1713 HAL_REO_REMAP_IX3(ring_map[0], 25) | 1714 HAL_REO_REMAP_IX3(ring_map[1], 26) | 1715 HAL_REO_REMAP_IX3(ring_map[2], 27) | 1716 HAL_REO_REMAP_IX3(ring_map[0], 28) | 1717 HAL_REO_REMAP_IX3(ring_map[1], 29) | 1718 HAL_REO_REMAP_IX3(ring_map[2], 30) | 1719 HAL_REO_REMAP_IX3(ring_map[0], 31); 1720 break; 1721 case 4: 1722 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1723 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1724 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1725 HAL_REO_REMAP_IX2(ring_map[3], 19) | 1726 HAL_REO_REMAP_IX2(ring_map[0], 20) | 1727 HAL_REO_REMAP_IX2(ring_map[1], 21) | 1728 HAL_REO_REMAP_IX2(ring_map[2], 22) | 1729 HAL_REO_REMAP_IX2(ring_map[3], 23); 1730 1731 *remap2 = HAL_REO_REMAP_IX3(ring_map[0], 24) | 1732 HAL_REO_REMAP_IX3(ring_map[1], 25) | 1733 HAL_REO_REMAP_IX3(ring_map[2], 26) | 1734 HAL_REO_REMAP_IX3(ring_map[3], 27) | 1735 HAL_REO_REMAP_IX3(ring_map[0], 28) | 1736 HAL_REO_REMAP_IX3(ring_map[1], 29) | 1737 HAL_REO_REMAP_IX3(ring_map[2], 30) | 1738 HAL_REO_REMAP_IX3(ring_map[3], 31); 1739 break; 1740 case 6: 1741 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1742 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1743 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1744 HAL_REO_REMAP_IX2(ring_map[3], 19) | 1745 HAL_REO_REMAP_IX2(ring_map[4], 20) | 1746 HAL_REO_REMAP_IX2(ring_map[5], 21) | 1747 HAL_REO_REMAP_IX2(ring_map[0], 22) | 1748 HAL_REO_REMAP_IX2(ring_map[1], 23); 1749 1750 *remap2 = HAL_REO_REMAP_IX3(ring_map[2], 24) | 1751 HAL_REO_REMAP_IX3(ring_map[3], 25) | 1752 HAL_REO_REMAP_IX3(ring_map[4], 26) | 1753 HAL_REO_REMAP_IX3(ring_map[5], 27) | 1754 HAL_REO_REMAP_IX3(ring_map[0], 28) | 1755 HAL_REO_REMAP_IX3(ring_map[1], 29) | 1756 HAL_REO_REMAP_IX3(ring_map[2], 30) | 1757 HAL_REO_REMAP_IX3(ring_map[3], 31); 1758 break; 1759 case 8: 1760 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1761 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1762 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1763 HAL_REO_REMAP_IX2(ring_map[3], 19) | 1764 HAL_REO_REMAP_IX2(ring_map[4], 20) | 1765 HAL_REO_REMAP_IX2(ring_map[5], 21) | 1766 HAL_REO_REMAP_IX2(ring_map[6], 22) | 1767 HAL_REO_REMAP_IX2(ring_map[7], 23); 1768 1769 *remap2 = HAL_REO_REMAP_IX3(ring_map[0], 24) | 1770 HAL_REO_REMAP_IX3(ring_map[1], 25) | 1771 HAL_REO_REMAP_IX3(ring_map[2], 26) | 1772 HAL_REO_REMAP_IX3(ring_map[3], 27) | 1773 HAL_REO_REMAP_IX3(ring_map[4], 28) | 1774 HAL_REO_REMAP_IX3(ring_map[5], 29) | 1775 HAL_REO_REMAP_IX3(ring_map[6], 30) | 1776 HAL_REO_REMAP_IX3(ring_map[7], 31); 1777 break; 1778 } 1779 } 1780 1781 /* NUM TCL Bank registers in KIWI */ 1782 #define HAL_NUM_TCL_BANKS_KIWI 8 1783 1784 /** 1785 * hal_tx_get_num_tcl_banks_kiwi() - Get number of banks in target 1786 * 1787 * Returns: number of bank 1788 */ 1789 static uint8_t hal_tx_get_num_tcl_banks_kiwi(void) 1790 { 1791 return HAL_NUM_TCL_BANKS_KIWI; 1792 } 1793 1794 /** 1795 * hal_rx_reo_prev_pn_get_kiwi() - Get the previous PN from the REO ring desc. 1796 * @ring_desc: REO ring descriptor [To be validated by caller ] 1797 * @prev_pn: Buffer where the previous PN is to be populated. 1798 * [To be validated by caller] 1799 * 1800 * Return: None 1801 */ 1802 static void hal_rx_reo_prev_pn_get_kiwi(void *ring_desc, 1803 uint64_t *prev_pn) 1804 { 1805 struct reo_destination_ring_with_pn *reo_desc = 1806 (struct reo_destination_ring_with_pn *)ring_desc; 1807 1808 *prev_pn = reo_desc->prev_pn_23_0; 1809 *prev_pn |= ((uint64_t)reo_desc->prev_pn_55_24 << 24); 1810 } 1811 1812 /** 1813 * hal_cmem_write_kiwi() - function for CMEM buffer writing 1814 * @hal_soc_hdl: HAL SOC handle 1815 * @offset: CMEM address 1816 * @value: value to write 1817 * 1818 * Return: None. 1819 */ 1820 static inline void hal_cmem_write_kiwi(hal_soc_handle_t hal_soc_hdl, 1821 uint32_t offset, 1822 uint32_t value) 1823 { 1824 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1825 1826 hal_write32_mb(hal, offset, value); 1827 } 1828 1829 /** 1830 * hal_get_idle_link_bm_id_kiwi() - Get idle link BM id from chid_id 1831 * @chip_id: mlo chip_id 1832 * 1833 * Returns: RBM ID 1834 */ 1835 static uint8_t hal_get_idle_link_bm_id_kiwi(uint8_t chip_id) 1836 { 1837 return WBM_IDLE_DESC_LIST; 1838 } 1839 1840 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1841 /** 1842 * hal_get_first_wow_wakeup_packet_kiwi(): Function to get if the buffer 1843 * is the first one that wakes up host from WoW. 1844 * 1845 * @buf: network buffer 1846 * 1847 * Dummy function for KIWI 1848 * 1849 * Returns: 1 to indicate it is first packet received that wakes up host from 1850 * WoW. Otherwise 0 1851 */ 1852 static inline uint8_t hal_get_first_wow_wakeup_packet_kiwi(uint8_t *buf) 1853 { 1854 return 0; 1855 } 1856 #endif 1857 1858 static uint16_t hal_get_rx_max_ba_window_kiwi(int tid) 1859 { 1860 return HAL_RX_BA_WINDOW_1024; 1861 } 1862 1863 /** 1864 * hal_get_reo_qdesc_size_kiwi()- Get the reo queue descriptor size 1865 * from the give Block-Ack window size 1866 * @ba_window_size: Block-Ack window size 1867 * @tid: TID 1868 * 1869 * Return: reo queue descriptor size 1870 */ 1871 static uint32_t hal_get_reo_qdesc_size_kiwi(uint32_t ba_window_size, int tid) 1872 { 1873 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 1874 * NON_QOS_TID until HW issues are resolved. 1875 */ 1876 if (tid != HAL_NON_QOS_TID) 1877 ba_window_size = hal_get_rx_max_ba_window_kiwi(tid); 1878 1879 /* Return descriptor size corresponding to window size of 2 since 1880 * we set ba_window_size to 2 while setting up REO descriptors as 1881 * a WAR to get 2k jump exception aggregates are received without 1882 * a BA session. 1883 */ 1884 if (ba_window_size <= 1) { 1885 if (tid != HAL_NON_QOS_TID) 1886 return sizeof(struct rx_reo_queue) + 1887 sizeof(struct rx_reo_queue_ext); 1888 else 1889 return sizeof(struct rx_reo_queue); 1890 } 1891 1892 if (ba_window_size <= 105) 1893 return sizeof(struct rx_reo_queue) + 1894 sizeof(struct rx_reo_queue_ext); 1895 1896 if (ba_window_size <= 210) 1897 return sizeof(struct rx_reo_queue) + 1898 (2 * sizeof(struct rx_reo_queue_ext)); 1899 1900 if (ba_window_size <= 256) 1901 return sizeof(struct rx_reo_queue) + 1902 (3 * sizeof(struct rx_reo_queue_ext)); 1903 1904 return sizeof(struct rx_reo_queue) + 1905 (10 * sizeof(struct rx_reo_queue_ext)) + 1906 sizeof(struct rx_reo_queue_1k); 1907 } 1908 1909 #ifdef QCA_GET_TSF_VIA_REG 1910 static inline uint32_t 1911 hal_tsf_read_scratch_reg(struct hal_soc *soc, 1912 enum hal_scratch_reg_enum reg_enum) 1913 { 1914 return hal_read32_mb(soc, PMM_REG_BASE + (reg_enum * 4)); 1915 } 1916 1917 static inline 1918 uint64_t hal_tsf_get_fw_time(struct hal_soc *soc) 1919 { 1920 uint64_t fw_time_low; 1921 uint64_t fw_time_high; 1922 1923 fw_time_low = hal_read32_mb(soc, PCIE_PCIE_MHI_TIME_LOW); 1924 fw_time_high = hal_read32_mb(soc, PCIE_PCIE_MHI_TIME_HIGH); 1925 return (fw_time_high << 32 | fw_time_low); 1926 } 1927 1928 static inline 1929 uint64_t hal_fw_qtime_to_usecs(uint64_t time) 1930 { 1931 /* 1932 * Try to preserve precision by multiplying by 10 first. 1933 * If that would cause a wrap around, divide first instead. 1934 */ 1935 if (time * 10 < time) { 1936 time = qdf_do_div(time, FW_QTIME_CYCLES_PER_10_USEC); 1937 return time * 10; 1938 } 1939 1940 time = time * 10; 1941 time = qdf_do_div(time, FW_QTIME_CYCLES_PER_10_USEC); 1942 1943 return time; 1944 } 1945 1946 /** 1947 * hal_get_tsf_time_kiwi() - Get tsf time from scratch register 1948 * @hal_soc_hdl: HAL soc handle 1949 * @tsf_id: TSF id 1950 * @mac_id: mac_id 1951 * @tsf: pointer to update tsf value 1952 * @tsf_sync_soc_time: pointer to update tsf sync time 1953 * 1954 * Return: None. 1955 */ 1956 static void 1957 hal_get_tsf_time_kiwi(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id, 1958 uint32_t mac_id, uint64_t *tsf, 1959 uint64_t *tsf_sync_soc_time) 1960 { 1961 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 1962 uint64_t global_time_low_offset, global_time_high_offset; 1963 uint64_t tsf_offset_low, tsf_offset_hi; 1964 uint64_t fw_time, global_time, sync_time; 1965 enum hal_scratch_reg_enum tsf_enum_low, tsf_enum_high; 1966 1967 if (hif_force_wake_request(soc->hif_handle)) 1968 return; 1969 1970 hal_get_tsf_enum(tsf_id, mac_id, &tsf_enum_low, &tsf_enum_high); 1971 sync_time = qdf_get_log_timestamp(); 1972 fw_time = hal_tsf_get_fw_time(soc); 1973 1974 global_time_low_offset = 1975 hal_tsf_read_scratch_reg(soc, PMM_QTIMER_GLOBAL_OFFSET_LO_US); 1976 global_time_high_offset = 1977 hal_tsf_read_scratch_reg(soc, PMM_QTIMER_GLOBAL_OFFSET_HI_US); 1978 1979 tsf_offset_low = hal_tsf_read_scratch_reg(soc, tsf_enum_low); 1980 tsf_offset_hi = hal_tsf_read_scratch_reg(soc, tsf_enum_high); 1981 1982 fw_time = hal_fw_qtime_to_usecs(fw_time); 1983 global_time = fw_time + 1984 (global_time_low_offset | 1985 (global_time_high_offset << 32)); 1986 1987 *tsf = global_time + (tsf_offset_low | (tsf_offset_hi << 32)); 1988 *tsf_sync_soc_time = qdf_log_timestamp_to_usecs(sync_time); 1989 1990 hif_force_wake_release(soc->hif_handle); 1991 } 1992 #else 1993 static inline void 1994 hal_get_tsf_time_kiwi(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id, 1995 uint32_t mac_id, uint64_t *tsf, 1996 uint64_t *tsf_sync_soc_time) 1997 { 1998 } 1999 #endif 2000 2001 static QDF_STATUS hal_rx_reo_ent_get_src_link_id_kiwi(hal_rxdma_desc_t rx_desc, 2002 uint8_t *src_link_id) 2003 { 2004 struct reo_entrance_ring *reo_ent_desc = 2005 (struct reo_entrance_ring *)rx_desc; 2006 2007 *src_link_id = reo_ent_desc->src_link_id; 2008 2009 return QDF_STATUS_SUCCESS; 2010 } 2011 2012 static void hal_hw_txrx_ops_attach_kiwi(struct hal_soc *hal_soc) 2013 { 2014 /* init and setup */ 2015 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 2016 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 2017 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 2018 hal_soc->ops->hal_get_window_address = hal_get_window_address_kiwi; 2019 hal_soc->ops->hal_reo_set_err_dst_remap = 2020 hal_reo_set_err_dst_remap_kiwi; 2021 hal_soc->ops->hal_reo_enable_pn_in_dest = 2022 hal_reo_enable_pn_in_dest_kiwi; 2023 /* Overwrite the default BE ops */ 2024 hal_soc->ops->hal_get_rx_max_ba_window = hal_get_rx_max_ba_window_kiwi; 2025 hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_kiwi; 2026 2027 /* tx */ 2028 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_kiwi; 2029 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_kiwi; 2030 hal_soc->ops->hal_tx_comp_get_status = 2031 hal_tx_comp_get_status_generic_be; 2032 hal_soc->ops->hal_tx_init_cmd_credit_ring = 2033 hal_tx_init_cmd_credit_ring_kiwi; 2034 hal_soc->ops->hal_tx_config_rbm_mapping_be = 2035 hal_tx_config_rbm_mapping_be_kiwi; 2036 2037 /* rx */ 2038 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; 2039 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 2040 hal_rx_mon_hw_desc_get_mpdu_status_be; 2041 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_kiwi; 2042 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be; 2043 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 2044 hal_rx_proc_phyrx_other_receive_info_tlv_kiwi; 2045 2046 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_kiwi; 2047 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 2048 hal_rx_dump_mpdu_start_tlv_kiwi; 2049 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_kiwi; 2050 hal_soc->ops->hal_rx_desc_get_80211_hdr = hal_rx_desc_get_80211_hdr_be; 2051 2052 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_kiwi; 2053 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be; 2054 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 2055 hal_rx_tlv_reception_type_get_be; 2056 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 2057 hal_rx_msdu_end_da_idx_get_be; 2058 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 2059 hal_rx_msdu_desc_info_get_ptr_kiwi; 2060 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 2061 hal_rx_link_desc_msdu0_ptr_kiwi; 2062 hal_soc->ops->hal_reo_status_get_header = 2063 hal_reo_status_get_header_kiwi; 2064 hal_soc->ops->hal_rx_status_get_tlv_info = 2065 hal_rx_status_get_tlv_info_wrapper_be; 2066 hal_soc->ops->hal_rx_wbm_err_info_get = 2067 hal_rx_wbm_err_info_get_generic_be; 2068 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 2069 hal_rx_priv_info_set_in_tlv_be; 2070 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 2071 hal_rx_priv_info_get_from_tlv_be; 2072 2073 hal_soc->ops->hal_tx_set_pcp_tid_map = 2074 hal_tx_set_pcp_tid_map_generic_be; 2075 hal_soc->ops->hal_tx_update_pcp_tid_map = 2076 hal_tx_update_pcp_tid_generic_be; 2077 hal_soc->ops->hal_tx_set_tidmap_prty = 2078 hal_tx_update_tidmap_prty_generic_be; 2079 hal_soc->ops->hal_rx_get_rx_fragment_number = 2080 hal_rx_get_rx_fragment_number_be; 2081 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 2082 hal_rx_tlv_da_is_mcbc_get_be; 2083 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 2084 hal_rx_tlv_sa_is_valid_get_be; 2085 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be, 2086 hal_soc->ops->hal_rx_desc_is_first_msdu = 2087 hal_rx_desc_is_first_msdu_be; 2088 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 2089 hal_rx_tlv_l3_hdr_padding_get_be; 2090 hal_soc->ops->hal_rx_encryption_info_valid = 2091 hal_rx_encryption_info_valid_be; 2092 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; 2093 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 2094 hal_rx_tlv_first_msdu_get_be; 2095 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 2096 hal_rx_tlv_da_is_valid_get_be; 2097 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 2098 hal_rx_tlv_last_msdu_get_be; 2099 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 2100 hal_rx_get_mpdu_mac_ad4_valid_be; 2101 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 2102 hal_rx_mpdu_start_sw_peer_id_get_be; 2103 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 2104 hal_rx_mpdu_peer_meta_data_get_be; 2105 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be; 2106 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be; 2107 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 2108 hal_rx_get_mpdu_frame_control_valid_be; 2109 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; 2110 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; 2111 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; 2112 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; 2113 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 2114 hal_rx_get_mpdu_sequence_control_valid_be; 2115 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; 2116 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; 2117 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 2118 hal_rx_hw_desc_get_ppduid_get_be; 2119 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 2120 hal_rx_msdu0_buffer_addr_lsb_kiwi; 2121 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 2122 hal_rx_msdu_desc_info_ptr_get_kiwi; 2123 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_kiwi; 2124 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_kiwi; 2125 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; 2126 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; 2127 hal_soc->ops->hal_rx_get_mac_addr2_valid = 2128 hal_rx_get_mac_addr2_valid_be; 2129 hal_soc->ops->hal_rx_get_filter_category = 2130 hal_rx_get_filter_category_be; 2131 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be; 2132 hal_soc->ops->hal_reo_config = hal_reo_config_kiwi; 2133 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; 2134 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 2135 hal_rx_msdu_flow_idx_invalid_be; 2136 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 2137 hal_rx_msdu_flow_idx_timeout_be; 2138 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 2139 hal_rx_msdu_fse_metadata_get_be; 2140 hal_soc->ops->hal_rx_msdu_cce_match_get = 2141 hal_rx_msdu_cce_match_get_be; 2142 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 2143 hal_rx_msdu_cce_metadata_get_be; 2144 hal_soc->ops->hal_rx_msdu_get_flow_params = 2145 hal_rx_msdu_get_flow_params_be; 2146 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 2147 hal_rx_tlv_get_tcp_chksum_be; 2148 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be; 2149 #if defined(QCA_WIFI_KIWI) && defined(WLAN_CFR_ENABLE) && \ 2150 defined(WLAN_ENH_CFR_ENABLE) 2151 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_kiwi; 2152 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_kiwi; 2153 #else 2154 hal_soc->ops->hal_rx_get_bb_info = NULL; 2155 hal_soc->ops->hal_rx_get_rtt_info = NULL; 2156 #endif 2157 /* rx - msdu end fast path info fields */ 2158 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 2159 hal_rx_msdu_packet_metadata_get_generic_be; 2160 hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum = 2161 hal_rx_get_fisa_cumulative_l4_checksum_be; 2162 hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length = 2163 hal_rx_get_fisa_cumulative_ip_length_be; 2164 hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_be; 2165 hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation = 2166 hal_rx_get_flow_agg_continuation_be; 2167 hal_soc->ops->hal_rx_get_fisa_flow_agg_count = 2168 hal_rx_get_flow_agg_count_be; 2169 hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_be; 2170 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 2171 hal_rx_mpdu_start_tlv_tag_valid_be; 2172 hal_soc->ops->hal_rx_reo_prev_pn_get = hal_rx_reo_prev_pn_get_kiwi; 2173 2174 /* rx - TLV struct offsets */ 2175 hal_register_rx_pkt_hdr_tlv_api_kiwi(hal_soc); 2176 hal_soc->ops->hal_rx_msdu_end_offset_get = 2177 hal_rx_msdu_end_offset_get_generic; 2178 hal_soc->ops->hal_rx_mpdu_start_offset_get = 2179 hal_rx_mpdu_start_offset_get_generic; 2180 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_kiwi; 2181 hal_soc->ops->hal_rx_flow_get_tuple_info = 2182 hal_rx_flow_get_tuple_info_be; 2183 hal_soc->ops->hal_rx_flow_delete_entry = 2184 hal_rx_flow_delete_entry_be; 2185 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be; 2186 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 2187 hal_compute_reo_remap_ix2_ix3_kiwi; 2188 hal_soc->ops->hal_rx_flow_setup_cmem_fse = 2189 hal_rx_flow_setup_cmem_fse_kiwi; 2190 hal_soc->ops->hal_rx_flow_get_cmem_fse_ts = 2191 hal_rx_flow_get_cmem_fse_ts_kiwi; 2192 hal_soc->ops->hal_rx_flow_get_cmem_fse = hal_rx_flow_get_cmem_fse_kiwi; 2193 hal_soc->ops->hal_cmem_write = hal_cmem_write_kiwi; 2194 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 2195 hal_rx_msdu_get_reo_destination_indication_be; 2196 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_kiwi; 2197 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; 2198 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 2199 hal_rx_msdu_is_wlan_mcast_generic_be; 2200 hal_soc->ops->hal_rx_tlv_bw_get = 2201 hal_rx_tlv_bw_get_be; 2202 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 2203 hal_rx_tlv_get_is_decrypted_be; 2204 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be; 2205 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be; 2206 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 2207 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 2208 hal_soc->ops->hal_rx_tlv_mpdu_len_err_get = 2209 hal_rx_tlv_mpdu_len_err_get_be; 2210 hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get = 2211 hal_rx_tlv_mpdu_fcs_err_get_be; 2212 2213 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be; 2214 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 2215 hal_rx_tlv_decrypt_err_get_be; 2216 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; 2217 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; 2218 hal_soc->ops->hal_rx_tlv_decap_format_get = 2219 hal_rx_tlv_decap_format_get_be; 2220 hal_soc->ops->hal_rx_tlv_get_offload_info = 2221 hal_rx_tlv_get_offload_info_be; 2222 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 2223 hal_rx_attn_phy_ppdu_id_get_be; 2224 hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_tlv_msdu_done_get_be; 2225 hal_soc->ops->hal_rx_tlv_msdu_len_get = 2226 hal_rx_msdu_start_msdu_len_get_be; 2227 hal_soc->ops->hal_rx_get_frame_ctrl_field = 2228 hal_rx_get_frame_ctrl_field_be; 2229 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; 2230 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; 2231 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; 2232 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 2233 hal_rx_mpdu_info_ampdu_flag_get_be; 2234 hal_soc->ops->hal_rx_tlv_msdu_len_set = 2235 hal_rx_msdu_start_msdu_len_set_be; 2236 hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info = 2237 hal_rx_tlv_populate_mpdu_desc_info_kiwi; 2238 hal_soc->ops->hal_get_idle_link_bm_id = hal_get_idle_link_bm_id_kiwi; 2239 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 2240 hal_soc->ops->hal_get_first_wow_wakeup_packet = 2241 hal_get_first_wow_wakeup_packet_kiwi; 2242 #endif 2243 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 2244 2245 hal_soc->ops->hal_rx_tlv_l3_type_get = hal_rx_tlv_l3_type_get_be; 2246 hal_soc->ops->hal_tx_vdev_mismatch_routing_set = 2247 hal_tx_vdev_mismatch_routing_set_generic_be; 2248 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = 2249 hal_tx_mcast_mlo_reinject_routing_set_generic_be; 2250 hal_soc->ops->hal_get_ba_aging_timeout = 2251 hal_get_ba_aging_timeout_be_generic; 2252 hal_soc->ops->hal_setup_link_idle_list = 2253 hal_setup_link_idle_list_generic_be; 2254 hal_soc->ops->hal_cookie_conversion_reg_cfg_be = 2255 hal_cookie_conversion_reg_cfg_generic_be; 2256 hal_soc->ops->hal_set_ba_aging_timeout = 2257 hal_set_ba_aging_timeout_be_generic; 2258 hal_soc->ops->hal_tx_populate_bank_register = 2259 hal_tx_populate_bank_register_be; 2260 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = 2261 hal_tx_vdev_mcast_ctrl_set_be; 2262 hal_soc->ops->hal_get_tsf_time = hal_get_tsf_time_kiwi; 2263 hal_soc->ops->hal_rx_reo_ent_get_src_link_id = 2264 hal_rx_reo_ent_get_src_link_id_kiwi; 2265 #ifdef FEATURE_DIRECT_LINK 2266 hal_soc->ops->hal_srng_set_msi_config = hal_srng_set_msi_config; 2267 #endif 2268 }; 2269 2270 struct hal_hw_srng_config hw_srng_table_kiwi[] = { 2271 /* TODO: max_rings can populated by querying HW capabilities */ 2272 { /* REO_DST */ 2273 .start_ring_id = HAL_SRNG_REO2SW1, 2274 .max_rings = 8, 2275 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2276 .lmac_ring = FALSE, 2277 .ring_dir = HAL_SRNG_DST_RING, 2278 .nf_irq_support = true, 2279 .reg_start = { 2280 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 2281 REO_REG_REG_BASE), 2282 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 2283 REO_REG_REG_BASE) 2284 }, 2285 .reg_size = { 2286 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 2287 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 2288 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 2289 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 2290 }, 2291 .max_size = 2292 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 2293 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 2294 }, 2295 { /* REO_EXCEPTION */ 2296 /* Designating REO2SW0 ring as exception ring. */ 2297 .start_ring_id = HAL_SRNG_REO2SW0, 2298 .max_rings = 1, 2299 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2300 .lmac_ring = FALSE, 2301 .ring_dir = HAL_SRNG_DST_RING, 2302 .reg_start = { 2303 HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR( 2304 REO_REG_REG_BASE), 2305 HWIO_REO_R2_REO2SW0_RING_HP_ADDR( 2306 REO_REG_REG_BASE) 2307 }, 2308 /* Single ring - provide ring size if multiple rings of this 2309 * type are supported 2310 */ 2311 .reg_size = {}, 2312 .max_size = 2313 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >> 2314 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT, 2315 }, 2316 { /* REO_REINJECT */ 2317 .start_ring_id = HAL_SRNG_SW2REO, 2318 .max_rings = 1, 2319 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2320 .lmac_ring = FALSE, 2321 .ring_dir = HAL_SRNG_SRC_RING, 2322 .reg_start = { 2323 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 2324 REO_REG_REG_BASE), 2325 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 2326 REO_REG_REG_BASE) 2327 }, 2328 /* Single ring - provide ring size if multiple rings of this 2329 * type are supported 2330 */ 2331 .reg_size = {}, 2332 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 2333 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 2334 }, 2335 { /* REO_CMD */ 2336 .start_ring_id = HAL_SRNG_REO_CMD, 2337 .max_rings = 1, 2338 .entry_size = (sizeof(struct tlv_32_hdr) + 2339 sizeof(struct reo_get_queue_stats)) >> 2, 2340 .lmac_ring = FALSE, 2341 .ring_dir = HAL_SRNG_SRC_RING, 2342 .reg_start = { 2343 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 2344 REO_REG_REG_BASE), 2345 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 2346 REO_REG_REG_BASE), 2347 }, 2348 /* Single ring - provide ring size if multiple rings of this 2349 * type are supported 2350 */ 2351 .reg_size = {}, 2352 .max_size = 2353 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 2354 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 2355 }, 2356 { /* REO_STATUS */ 2357 .start_ring_id = HAL_SRNG_REO_STATUS, 2358 .max_rings = 1, 2359 .entry_size = (sizeof(struct tlv_32_hdr) + 2360 sizeof(struct reo_get_queue_stats_status)) >> 2, 2361 .lmac_ring = FALSE, 2362 .ring_dir = HAL_SRNG_DST_RING, 2363 .reg_start = { 2364 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2365 REO_REG_REG_BASE), 2366 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2367 REO_REG_REG_BASE), 2368 }, 2369 /* Single ring - provide ring size if multiple rings of this 2370 * type are supported 2371 */ 2372 .reg_size = {}, 2373 .max_size = 2374 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2375 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2376 }, 2377 { /* TCL_DATA */ 2378 .start_ring_id = HAL_SRNG_SW2TCL1, 2379 .max_rings = 5, 2380 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 2381 .lmac_ring = FALSE, 2382 .ring_dir = HAL_SRNG_SRC_RING, 2383 .reg_start = { 2384 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2385 MAC_TCL_REG_REG_BASE), 2386 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2387 MAC_TCL_REG_REG_BASE), 2388 }, 2389 .reg_size = { 2390 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2391 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2392 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2393 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2394 }, 2395 .max_size = 2396 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2397 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2398 }, 2399 { /* TCL_CMD */ 2400 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2401 #ifndef WLAN_DP_DISABLE_TCL_CMD_CRED_SRNG 2402 .max_rings = 1, 2403 #else 2404 .max_rings = 0, 2405 #endif 2406 .entry_size = sizeof(struct tcl_gse_cmd) >> 2, 2407 .lmac_ring = FALSE, 2408 .ring_dir = HAL_SRNG_SRC_RING, 2409 .reg_start = { 2410 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2411 MAC_TCL_REG_REG_BASE), 2412 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2413 MAC_TCL_REG_REG_BASE), 2414 }, 2415 /* Single ring - provide ring size if multiple rings of this 2416 * type are supported 2417 */ 2418 .reg_size = {}, 2419 .max_size = 2420 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2421 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2422 }, 2423 { /* TCL_STATUS */ 2424 .start_ring_id = HAL_SRNG_TCL_STATUS, 2425 #ifndef WLAN_DP_DISABLE_TCL_CMD_CRED_SRNG 2426 .max_rings = 1, 2427 #else 2428 .max_rings = 0, 2429 #endif 2430 /* confirm that TLV header is needed */ 2431 .entry_size = sizeof(struct tcl_status_ring) >> 2, 2432 .lmac_ring = FALSE, 2433 .ring_dir = HAL_SRNG_DST_RING, 2434 .reg_start = { 2435 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2436 MAC_TCL_REG_REG_BASE), 2437 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2438 MAC_TCL_REG_REG_BASE), 2439 }, 2440 /* Single ring - provide ring size if multiple rings of this 2441 * type are supported 2442 */ 2443 .reg_size = {}, 2444 .max_size = 2445 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2446 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2447 }, 2448 { /* CE_SRC */ 2449 .start_ring_id = HAL_SRNG_CE_0_SRC, 2450 .max_rings = 12, 2451 .entry_size = sizeof(struct ce_src_desc) >> 2, 2452 .lmac_ring = FALSE, 2453 .ring_dir = HAL_SRNG_SRC_RING, 2454 .reg_start = { 2455 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, 2456 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, 2457 }, 2458 .reg_size = { 2459 SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 2460 SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 2461 SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 2462 SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 2463 }, 2464 .max_size = 2465 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >> 2466 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT, 2467 }, 2468 { /* CE_DST */ 2469 .start_ring_id = HAL_SRNG_CE_0_DST, 2470 .max_rings = 12, 2471 .entry_size = 8 >> 2, 2472 /*TODO: entry_size above should actually be 2473 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2474 * of struct ce_dst_desc in HW header files 2475 */ 2476 .lmac_ring = FALSE, 2477 .ring_dir = HAL_SRNG_SRC_RING, 2478 .reg_start = { 2479 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, 2480 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, 2481 }, 2482 .reg_size = { 2483 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2484 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2485 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2486 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2487 }, 2488 .max_size = 2489 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2490 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2491 }, 2492 { /* CE_DST_STATUS */ 2493 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2494 .max_rings = 12, 2495 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2496 .lmac_ring = FALSE, 2497 .ring_dir = HAL_SRNG_DST_RING, 2498 .reg_start = { 2499 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, 2500 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, 2501 }, 2502 .reg_size = { 2503 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2504 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2505 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2506 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2507 }, 2508 .max_size = 2509 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2510 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2511 }, 2512 { /* WBM_IDLE_LINK */ 2513 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2514 .max_rings = 1, 2515 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2516 .lmac_ring = FALSE, 2517 .ring_dir = HAL_SRNG_SRC_RING, 2518 .reg_start = { 2519 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2520 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE), 2521 }, 2522 /* Single ring - provide ring size if multiple rings of this 2523 * type are supported 2524 */ 2525 .reg_size = {}, 2526 .max_size = 2527 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2528 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2529 }, 2530 { /* SW2WBM_RELEASE */ 2531 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2532 .max_rings = 1, 2533 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2534 .lmac_ring = FALSE, 2535 .ring_dir = HAL_SRNG_SRC_RING, 2536 .reg_start = { 2537 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2538 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2539 }, 2540 /* Single ring - provide ring size if multiple rings of this 2541 * type are supported 2542 */ 2543 .reg_size = {}, 2544 .max_size = 2545 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2546 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2547 }, 2548 { /* WBM2SW_RELEASE */ 2549 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2550 .max_rings = 8, 2551 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2552 .lmac_ring = FALSE, 2553 .ring_dir = HAL_SRNG_DST_RING, 2554 .nf_irq_support = true, 2555 .reg_start = { 2556 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2557 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2558 }, 2559 .reg_size = { 2560 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE) - 2561 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2562 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE) - 2563 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2564 }, 2565 .max_size = 2566 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2567 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2568 }, 2569 { /* RXDMA_BUF */ 2570 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2571 #if defined(IPA_OFFLOAD) && defined(FEATURE_DIRECT_LINK) 2572 .max_rings = 4, 2573 #elif defined(IPA_OFFLOAD) || defined(FEATURE_DIRECT_LINK) 2574 .max_rings = 3, 2575 #else 2576 .max_rings = 2, 2577 #endif 2578 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2579 .lmac_ring = TRUE, 2580 .ring_dir = HAL_SRNG_SRC_RING, 2581 /* reg_start is not set because LMAC rings are not accessed 2582 * from host 2583 */ 2584 .reg_start = {}, 2585 .reg_size = {}, 2586 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2587 }, 2588 { /* RXDMA_DST */ 2589 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2590 .max_rings = 1, 2591 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2592 .lmac_ring = TRUE, 2593 .ring_dir = HAL_SRNG_DST_RING, 2594 /* reg_start is not set because LMAC rings are not accessed 2595 * from host 2596 */ 2597 .reg_start = {}, 2598 .reg_size = {}, 2599 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2600 }, 2601 { /* RXDMA_MONITOR_BUF */ 2602 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2603 .max_rings = 1, 2604 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2605 .lmac_ring = TRUE, 2606 .ring_dir = HAL_SRNG_SRC_RING, 2607 /* reg_start is not set because LMAC rings are not accessed 2608 * from host 2609 */ 2610 .reg_start = {}, 2611 .reg_size = {}, 2612 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2613 }, 2614 { /* RXDMA_MONITOR_STATUS */ 2615 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2616 .max_rings = 1, 2617 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2618 .lmac_ring = TRUE, 2619 .ring_dir = HAL_SRNG_SRC_RING, 2620 /* reg_start is not set because LMAC rings are not accessed 2621 * from host 2622 */ 2623 .reg_start = {}, 2624 .reg_size = {}, 2625 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2626 }, 2627 { /* RXDMA_MONITOR_DST */ 2628 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2629 .max_rings = 1, 2630 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2631 .lmac_ring = TRUE, 2632 .ring_dir = HAL_SRNG_DST_RING, 2633 /* reg_start is not set because LMAC rings are not accessed 2634 * from host 2635 */ 2636 .reg_start = {}, 2637 .reg_size = {}, 2638 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2639 }, 2640 { /* RXDMA_MONITOR_DESC */ 2641 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2642 .max_rings = 1, 2643 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2644 .lmac_ring = TRUE, 2645 .ring_dir = HAL_SRNG_SRC_RING, 2646 /* reg_start is not set because LMAC rings are not accessed 2647 * from host 2648 */ 2649 .reg_start = {}, 2650 .reg_size = {}, 2651 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2652 }, 2653 { /* DIR_BUF_RX_DMA_SRC */ 2654 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2655 /* 2656 * one ring is for spectral scan 2657 * the other is for cfr 2658 */ 2659 .max_rings = 2, 2660 .entry_size = 2, 2661 .lmac_ring = TRUE, 2662 .ring_dir = HAL_SRNG_SRC_RING, 2663 /* reg_start is not set because LMAC rings are not accessed 2664 * from host 2665 */ 2666 .reg_start = {}, 2667 .reg_size = {}, 2668 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2669 }, 2670 #ifdef WLAN_FEATURE_CIF_CFR 2671 { /* WIFI_POS_SRC */ 2672 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2673 .max_rings = 1, 2674 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2675 .lmac_ring = TRUE, 2676 .ring_dir = HAL_SRNG_SRC_RING, 2677 /* reg_start is not set because LMAC rings are not accessed 2678 * from host 2679 */ 2680 .reg_start = {}, 2681 .reg_size = {}, 2682 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2683 }, 2684 #endif 2685 { /* REO2PPE */ 0}, 2686 { /* PPE2TCL */ 0}, 2687 { /* PPE_RELEASE */ 0}, 2688 { /* TX_MONITOR_BUF */ 0}, 2689 { /* TX_MONITOR_DST */ 0}, 2690 { /* SW2RXDMA_NEW */ 0}, 2691 }; 2692 2693 /** 2694 * hal_srng_hw_reg_offset_init_kiwi() - Initialize the HW srng reg offset 2695 * applicable only for KIWI 2696 * @hal_soc: HAL Soc handle 2697 * 2698 * Return: None 2699 */ 2700 static inline void hal_srng_hw_reg_offset_init_kiwi(struct hal_soc *hal_soc) 2701 { 2702 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 2703 2704 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB), 2705 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB), 2706 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA), 2707 hw_reg_offset[DST_PRODUCER_INT2_SETUP] = 2708 REG_OFFSET(DST, PRODUCER_INT2_SETUP); 2709 } 2710 2711 void hal_kiwi_attach(struct hal_soc *hal_soc) 2712 { 2713 hal_soc->hw_srng_table = hw_srng_table_kiwi; 2714 2715 hal_srng_hw_reg_offset_init_generic(hal_soc); 2716 hal_srng_hw_reg_offset_init_kiwi(hal_soc); 2717 hal_hw_txrx_default_ops_attach_be(hal_soc); 2718 hal_hw_txrx_ops_attach_kiwi(hal_soc); 2719 } 2720