1 /* 2 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "qdf_types.h" 21 #include "qdf_util.h" 22 #include "qdf_types.h" 23 #include "qdf_lock.h" 24 #include "qdf_mem.h" 25 #include "qdf_nbuf.h" 26 #include "hal_hw_headers.h" 27 #include "hal_internal.h" 28 #include "hal_api.h" 29 #include "target_type.h" 30 #include "wcss_version.h" 31 #include "qdf_module.h" 32 #include "hal_flow.h" 33 #include "rx_flow_search_entry.h" 34 #include "hal_rx_flow_info.h" 35 #include "hal_be_api.h" 36 #include "reo_destination_ring_with_pn.h" 37 #include "rx_reo_queue_1k.h" 38 39 #include <hal_be_rx.h> 40 41 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 42 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 43 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 44 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 45 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 46 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 47 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 48 PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 49 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 50 PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 51 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 52 PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 53 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 54 PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 59 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 60 PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 61 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 62 PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 63 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 64 PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 65 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 66 PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 67 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 68 PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 69 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 70 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 71 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 72 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 73 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 74 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 75 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 76 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 77 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 78 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 79 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 80 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 81 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 82 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 83 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 84 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 85 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 86 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 87 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 88 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 89 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 90 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 91 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 92 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 94 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 95 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 96 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 97 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 98 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 99 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 100 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 101 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 102 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 103 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 104 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 105 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 106 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 107 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 108 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 109 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 110 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 112 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 113 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 114 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 115 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 116 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 117 118 #include "hal_kiwi_tx.h" 119 #include "hal_kiwi_rx.h" 120 121 #include "hal_be_rx_tlv.h" 122 123 #include <hal_generic_api.h> 124 #include <hal_be_generic_api.h> 125 #include "hal_be_api_mon.h" 126 127 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 128 129 #ifdef QCA_GET_TSF_VIA_REG 130 #define PCIE_PCIE_MHI_TIME_LOW 0xA28 131 #define PCIE_PCIE_MHI_TIME_HIGH 0xA2C 132 133 #define PMM_REG_BASE 0xB500FC 134 135 #define FW_QTIME_CYCLES_PER_10_USEC 192 136 137 /* enum to indicate which scratch registers hold which value*/ 138 /* Obtain from pcie_reg_scratch.h? */ 139 enum hal_scratch_reg_enum { 140 PMM_QTIMER_GLOBAL_OFFSET_LO_US, 141 PMM_QTIMER_GLOBAL_OFFSET_HI_US, 142 PMM_MAC0_TSF1_OFFSET_LO_US, 143 PMM_MAC0_TSF1_OFFSET_HI_US, 144 PMM_MAC0_TSF2_OFFSET_LO_US, 145 PMM_MAC0_TSF2_OFFSET_HI_US, 146 PMM_MAC1_TSF1_OFFSET_LO_US, 147 PMM_MAC1_TSF1_OFFSET_HI_US, 148 PMM_MAC1_TSF2_OFFSET_LO_US, 149 PMM_MAC1_TSF2_OFFSET_HI_US, 150 PMM_MLO_OFFSET_LO_US, 151 PMM_MLO_OFFSET_HI_US, 152 PMM_TQM_CLOCK_OFFSET_LO_US, 153 PMM_TQM_CLOCK_OFFSET_HI_US, 154 PMM_Q6_CRASH_REASON, 155 PMM_PMM_REG_MAX 156 }; 157 #endif 158 159 static uint32_t hal_get_link_desc_size_kiwi(void) 160 { 161 return LINK_DESC_SIZE; 162 } 163 164 /** 165 * hal_rx_dump_msdu_end_tlv_kiwi: dump RX msdu_end TLV in structured 166 * human readable format. 167 * @ msdu_end: pointer the msdu_end TLV in pkt. 168 * @ dbg_level: log level. 169 * 170 * Return: void 171 */ 172 #ifdef QCA_WIFI_KIWI_V2 173 static void hal_rx_dump_msdu_end_tlv_kiwi(void *msduend, 174 uint8_t dbg_level) 175 { 176 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 177 178 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 179 "rx_msdu_end tlv (1/5)- " 180 "rxpcu_mpdu_filter_in_category :%x " 181 "sw_frame_group_id :%x " 182 "reserved_0 :%x " 183 "phy_ppdu_id :%x " 184 "ip_hdr_chksum :%x " 185 "reported_mpdu_length :%x " 186 "reserved_1a :%x " 187 "reserved_2a :%x " 188 "cce_super_rule :%x " 189 "cce_classify_not_done_truncate :%x " 190 "cce_classify_not_done_cce_dis :%x " 191 "cumulative_l3_checksum :%x " 192 "rule_indication_31_0 :%x " 193 "ipv6_options_crc :%x " 194 "da_offset :%x " 195 "sa_offset :%x " 196 "da_offset_valid :%x " 197 "sa_offset_valid :%x " 198 "reserved_5a :%x " 199 "l3_type :%x", 200 msdu_end->rxpcu_mpdu_filter_in_category, 201 msdu_end->sw_frame_group_id, 202 msdu_end->reserved_0, 203 msdu_end->phy_ppdu_id, 204 msdu_end->ip_hdr_chksum, 205 msdu_end->reported_mpdu_length, 206 msdu_end->reserved_1a, 207 msdu_end->reserved_2a, 208 msdu_end->cce_super_rule, 209 msdu_end->cce_classify_not_done_truncate, 210 msdu_end->cce_classify_not_done_cce_dis, 211 msdu_end->cumulative_l3_checksum, 212 msdu_end->rule_indication_31_0, 213 msdu_end->ipv6_options_crc, 214 msdu_end->da_offset, 215 msdu_end->sa_offset, 216 msdu_end->da_offset_valid, 217 msdu_end->sa_offset_valid, 218 msdu_end->reserved_5a, 219 msdu_end->l3_type); 220 221 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 222 "rx_msdu_end tlv (2/5)- " 223 "rule_indication_63_32 :%x " 224 "tcp_seq_number :%x " 225 "tcp_ack_number :%x " 226 "tcp_flag :%x " 227 "lro_eligible :%x " 228 "reserved_9a :%x " 229 "window_size :%x " 230 "sa_sw_peer_id :%x " 231 "sa_idx_timeout :%x " 232 "da_idx_timeout :%x " 233 "to_ds :%x " 234 "tid :%x " 235 "sa_is_valid :%x " 236 "da_is_valid :%x " 237 "da_is_mcbc :%x " 238 "l3_header_padding :%x " 239 "first_msdu :%x " 240 "last_msdu :%x " 241 "fr_ds :%x " 242 "ip_chksum_fail_copy :%x " 243 "sa_idx :%x " 244 "da_idx_or_sw_peer_id :%x", 245 msdu_end->rule_indication_63_32, 246 msdu_end->tcp_seq_number, 247 msdu_end->tcp_ack_number, 248 msdu_end->tcp_flag, 249 msdu_end->lro_eligible, 250 msdu_end->reserved_9a, 251 msdu_end->window_size, 252 msdu_end->sa_sw_peer_id, 253 msdu_end->sa_idx_timeout, 254 msdu_end->da_idx_timeout, 255 msdu_end->to_ds, 256 msdu_end->tid, 257 msdu_end->sa_is_valid, 258 msdu_end->da_is_valid, 259 msdu_end->da_is_mcbc, 260 msdu_end->l3_header_padding, 261 msdu_end->first_msdu, 262 msdu_end->last_msdu, 263 msdu_end->fr_ds, 264 msdu_end->ip_chksum_fail_copy, 265 msdu_end->sa_idx, 266 msdu_end->da_idx_or_sw_peer_id); 267 268 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 269 "rx_msdu_end tlv (3/5)- " 270 "msdu_drop :%x " 271 "reo_destination_indication :%x " 272 "flow_idx :%x " 273 "use_ppe :%x " 274 "__reserved_g_0003 :%x " 275 "vlan_ctag_stripped :%x " 276 "vlan_stag_stripped :%x " 277 "fragment_flag :%x " 278 "fse_metadata :%x " 279 "cce_metadata :%x " 280 "tcp_udp_chksum :%x " 281 "aggregation_count :%x " 282 "flow_aggregation_continuation :%x " 283 "fisa_timeout :%x " 284 "tcp_udp_chksum_fail_copy :%x " 285 "msdu_limit_error :%x " 286 "flow_idx_timeout :%x " 287 "flow_idx_invalid :%x " 288 "cce_match :%x " 289 "amsdu_parser_error :%x " 290 "cumulative_ip_length :%x " 291 "key_id_octet :%x " 292 "reserved_16a :%x " 293 "reserved_17a :%x " 294 "service_code :%x " 295 "priority_valid :%x " 296 "intra_bss :%x " 297 "dest_chip_id :%x " 298 "multicast_echo :%x " 299 "wds_learning_event :%x " 300 "wds_roaming_event :%x " 301 "wds_keep_alive_event :%x " 302 "reserved_17b :%x", 303 msdu_end->msdu_drop, 304 msdu_end->reo_destination_indication, 305 msdu_end->flow_idx, 306 msdu_end->use_ppe, 307 msdu_end->__reserved_g_0003, 308 msdu_end->vlan_ctag_stripped, 309 msdu_end->vlan_stag_stripped, 310 msdu_end->fragment_flag, 311 msdu_end->fse_metadata, 312 msdu_end->cce_metadata, 313 msdu_end->tcp_udp_chksum, 314 msdu_end->aggregation_count, 315 msdu_end->flow_aggregation_continuation, 316 msdu_end->fisa_timeout, 317 msdu_end->tcp_udp_chksum_fail_copy, 318 msdu_end->msdu_limit_error, 319 msdu_end->flow_idx_timeout, 320 msdu_end->flow_idx_invalid, 321 msdu_end->cce_match, 322 msdu_end->amsdu_parser_error, 323 msdu_end->cumulative_ip_length, 324 msdu_end->key_id_octet, 325 msdu_end->reserved_16a, 326 msdu_end->reserved_17a, 327 msdu_end->service_code, 328 msdu_end->priority_valid, 329 msdu_end->intra_bss, 330 msdu_end->dest_chip_id, 331 msdu_end->multicast_echo, 332 msdu_end->wds_learning_event, 333 msdu_end->wds_roaming_event, 334 msdu_end->wds_keep_alive_event, 335 msdu_end->reserved_17b); 336 337 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 338 "rx_msdu_end tlv (4/5)- " 339 "msdu_length :%x " 340 "stbc :%x " 341 "ipsec_esp :%x " 342 "l3_offset :%x " 343 "ipsec_ah :%x " 344 "l4_offset :%x " 345 "msdu_number :%x " 346 "decap_format :%x " 347 "ipv4_proto :%x " 348 "ipv6_proto :%x " 349 "tcp_proto :%x " 350 "udp_proto :%x " 351 "ip_frag :%x " 352 "tcp_only_ack :%x " 353 "da_is_bcast_mcast :%x " 354 "toeplitz_hash_sel :%x " 355 "ip_fixed_header_valid :%x " 356 "ip_extn_header_valid :%x " 357 "tcp_udp_header_valid :%x " 358 "mesh_control_present :%x " 359 "ldpc :%x " 360 "ip4_protocol_ip6_next_header :%x " 361 "vlan_ctag_ci :%x " 362 "vlan_stag_ci :%x " 363 "peer_meta_data :%x " 364 "user_rssi :%x " 365 "pkt_type :%x " 366 "sgi :%x " 367 "rate_mcs :%x " 368 "receive_bandwidth :%x " 369 "reception_type :%x " 370 "mimo_ss_bitmap :%x " 371 "msdu_done_copy :%x " 372 "flow_id_toeplitz :%x", 373 msdu_end->msdu_length, 374 msdu_end->stbc, 375 msdu_end->ipsec_esp, 376 msdu_end->l3_offset, 377 msdu_end->ipsec_ah, 378 msdu_end->l4_offset, 379 msdu_end->msdu_number, 380 msdu_end->decap_format, 381 msdu_end->ipv4_proto, 382 msdu_end->ipv6_proto, 383 msdu_end->tcp_proto, 384 msdu_end->udp_proto, 385 msdu_end->ip_frag, 386 msdu_end->tcp_only_ack, 387 msdu_end->da_is_bcast_mcast, 388 msdu_end->toeplitz_hash_sel, 389 msdu_end->ip_fixed_header_valid, 390 msdu_end->ip_extn_header_valid, 391 msdu_end->tcp_udp_header_valid, 392 msdu_end->mesh_control_present, 393 msdu_end->ldpc, 394 msdu_end->ip4_protocol_ip6_next_header, 395 msdu_end->vlan_ctag_ci, 396 msdu_end->vlan_stag_ci, 397 msdu_end->peer_meta_data, 398 msdu_end->user_rssi, 399 msdu_end->pkt_type, 400 msdu_end->sgi, 401 msdu_end->rate_mcs, 402 msdu_end->receive_bandwidth, 403 msdu_end->reception_type, 404 msdu_end->mimo_ss_bitmap, 405 msdu_end->msdu_done_copy, 406 msdu_end->flow_id_toeplitz); 407 408 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 409 "rx_msdu_end tlv (5/5)- " 410 "ppdu_start_timestamp_63_32 :%x " 411 "sw_phy_meta_data :%x " 412 "ppdu_start_timestamp_31_0 :%x " 413 "toeplitz_hash_2_or_4 :%x " 414 "reserved_28a :%x " 415 "sa_15_0 :%x " 416 "sa_47_16 :%x " 417 "first_mpdu :%x " 418 "reserved_30a :%x " 419 "mcast_bcast :%x " 420 "ast_index_not_found :%x " 421 "ast_index_timeout :%x " 422 "power_mgmt :%x " 423 "non_qos :%x " 424 "null_data :%x " 425 "mgmt_type :%x " 426 "ctrl_type :%x " 427 "more_data :%x " 428 "eosp :%x " 429 "a_msdu_error :%x " 430 "reserved_30b :%x " 431 "order :%x " 432 "wifi_parser_error :%x " 433 "overflow_err :%x " 434 "msdu_length_err :%x " 435 "tcp_udp_chksum_fail :%x " 436 "ip_chksum_fail :%x " 437 "sa_idx_invalid :%x " 438 "da_idx_invalid :%x " 439 "amsdu_addr_mismatch :%x " 440 "rx_in_tx_decrypt_byp :%x " 441 "encrypt_required :%x " 442 "directed :%x " 443 "buffer_fragment :%x " 444 "mpdu_length_err :%x " 445 "tkip_mic_err :%x " 446 "decrypt_err :%x " 447 "unencrypted_frame_err :%x " 448 "fcs_err :%x " 449 "reserved_31a :%x " 450 "decrypt_status_code :%x " 451 "rx_bitmap_not_updated :%x " 452 "reserved_31b :%x " 453 "msdu_done :%x", 454 msdu_end->ppdu_start_timestamp_63_32, 455 msdu_end->sw_phy_meta_data, 456 msdu_end->ppdu_start_timestamp_31_0, 457 msdu_end->toeplitz_hash_2_or_4, 458 msdu_end->reserved_28a, 459 msdu_end->sa_15_0, 460 msdu_end->sa_47_16, 461 msdu_end->first_mpdu, 462 msdu_end->reserved_30a, 463 msdu_end->mcast_bcast, 464 msdu_end->ast_index_not_found, 465 msdu_end->ast_index_timeout, 466 msdu_end->power_mgmt, 467 msdu_end->non_qos, 468 msdu_end->null_data, 469 msdu_end->mgmt_type, 470 msdu_end->ctrl_type, 471 msdu_end->more_data, 472 msdu_end->eosp, 473 msdu_end->a_msdu_error, 474 msdu_end->reserved_30b, 475 msdu_end->order, 476 msdu_end->wifi_parser_error, 477 msdu_end->overflow_err, 478 msdu_end->msdu_length_err, 479 msdu_end->tcp_udp_chksum_fail, 480 msdu_end->ip_chksum_fail, 481 msdu_end->sa_idx_invalid, 482 msdu_end->da_idx_invalid, 483 msdu_end->amsdu_addr_mismatch, 484 msdu_end->rx_in_tx_decrypt_byp, 485 msdu_end->encrypt_required, 486 msdu_end->directed, 487 msdu_end->buffer_fragment, 488 msdu_end->mpdu_length_err, 489 msdu_end->tkip_mic_err, 490 msdu_end->decrypt_err, 491 msdu_end->unencrypted_frame_err, 492 msdu_end->fcs_err, 493 msdu_end->reserved_31a, 494 msdu_end->decrypt_status_code, 495 msdu_end->rx_bitmap_not_updated, 496 msdu_end->reserved_31b, 497 msdu_end->msdu_done); 498 } 499 #else 500 static void hal_rx_dump_msdu_end_tlv_kiwi(void *msduend, 501 uint8_t dbg_level) 502 { 503 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 504 505 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 506 "rx_msdu_end tlv (1/7)- " 507 "rxpcu_mpdu_filter_in_category :%x" 508 "sw_frame_group_id :%x" 509 "reserved_0 :%x" 510 "phy_ppdu_id :%x" 511 "ip_hdr_chksum:%x" 512 "reported_mpdu_length :%x" 513 "reserved_1a :%x" 514 "key_id_octet :%x" 515 "cce_super_rule :%x" 516 "cce_classify_not_done_truncate :%x" 517 "cce_classify_not_done_cce_dis:%x" 518 "cumulative_l3_checksum :%x" 519 "rule_indication_31_0 :%x" 520 "rule_indication_63_32:%x" 521 "da_offset :%x" 522 "sa_offset :%x" 523 "da_offset_valid :%x" 524 "sa_offset_valid :%x" 525 "reserved_5a :%x" 526 "l3_type :%x", 527 msdu_end->rxpcu_mpdu_filter_in_category, 528 msdu_end->sw_frame_group_id, 529 msdu_end->reserved_0, 530 msdu_end->phy_ppdu_id, 531 msdu_end->ip_hdr_chksum, 532 msdu_end->reported_mpdu_length, 533 msdu_end->reserved_1a, 534 msdu_end->key_id_octet, 535 msdu_end->cce_super_rule, 536 msdu_end->cce_classify_not_done_truncate, 537 msdu_end->cce_classify_not_done_cce_dis, 538 msdu_end->cumulative_l3_checksum, 539 msdu_end->rule_indication_31_0, 540 msdu_end->rule_indication_63_32, 541 msdu_end->da_offset, 542 msdu_end->sa_offset, 543 msdu_end->da_offset_valid, 544 msdu_end->sa_offset_valid, 545 msdu_end->reserved_5a, 546 msdu_end->l3_type); 547 548 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 549 "rx_msdu_end tlv (2/7)- " 550 "ipv6_options_crc :%x" 551 "tcp_seq_number :%x" 552 "tcp_ack_number :%x" 553 "tcp_flag :%x" 554 "lro_eligible :%x" 555 "reserved_9a :%x" 556 "window_size :%x" 557 "tcp_udp_chksum :%x" 558 "sa_idx_timeout :%x" 559 "da_idx_timeout :%x" 560 "msdu_limit_error :%x" 561 "flow_idx_timeout :%x" 562 "flow_idx_invalid :%x" 563 "wifi_parser_error :%x" 564 "amsdu_parser_error :%x" 565 "sa_is_valid :%x" 566 "da_is_valid :%x" 567 "da_is_mcbc :%x" 568 "l3_header_padding :%x" 569 "first_msdu :%x" 570 "last_msdu :%x", 571 msdu_end->ipv6_options_crc, 572 msdu_end->tcp_seq_number, 573 msdu_end->tcp_ack_number, 574 msdu_end->tcp_flag, 575 msdu_end->lro_eligible, 576 msdu_end->reserved_9a, 577 msdu_end->window_size, 578 msdu_end->tcp_udp_chksum, 579 msdu_end->sa_idx_timeout, 580 msdu_end->da_idx_timeout, 581 msdu_end->msdu_limit_error, 582 msdu_end->flow_idx_timeout, 583 msdu_end->flow_idx_invalid, 584 msdu_end->wifi_parser_error, 585 msdu_end->amsdu_parser_error, 586 msdu_end->sa_is_valid, 587 msdu_end->da_is_valid, 588 msdu_end->da_is_mcbc, 589 msdu_end->l3_header_padding, 590 msdu_end->first_msdu, 591 msdu_end->last_msdu); 592 593 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 594 "rx_msdu_end tlv (3/7)" 595 "tcp_udp_chksum_fail_copy :%x" 596 "ip_chksum_fail_copy :%x" 597 "sa_idx :%x" 598 "da_idx_or_sw_peer_id :%x" 599 "msdu_drop :%x" 600 "reo_destination_indication :%x" 601 "flow_idx :%x" 602 "reserved_12a :%x" 603 "fse_metadata :%x" 604 "cce_metadata :%x" 605 "sa_sw_peer_id:%x" 606 "aggregation_count :%x" 607 "flow_aggregation_continuation:%x" 608 "fisa_timeout :%x" 609 "reserved_15a :%x" 610 "cumulative_l4_checksum :%x" 611 "cumulative_ip_length :%x" 612 "service_code :%x" 613 "priority_valid :%x", 614 msdu_end->tcp_udp_chksum_fail_copy, 615 msdu_end->ip_chksum_fail_copy, 616 msdu_end->sa_idx, 617 msdu_end->da_idx_or_sw_peer_id, 618 msdu_end->msdu_drop, 619 msdu_end->reo_destination_indication, 620 msdu_end->flow_idx, 621 msdu_end->reserved_12a, 622 msdu_end->fse_metadata, 623 msdu_end->cce_metadata, 624 msdu_end->sa_sw_peer_id, 625 msdu_end->aggregation_count, 626 msdu_end->flow_aggregation_continuation, 627 msdu_end->fisa_timeout, 628 msdu_end->reserved_15a, 629 msdu_end->cumulative_l4_checksum, 630 msdu_end->cumulative_ip_length, 631 msdu_end->service_code, 632 msdu_end->priority_valid); 633 634 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 635 "rx_msdu_end tlv (4/7)" 636 "reserved_17a :%x" 637 "msdu_length :%x" 638 "ipsec_esp :%x" 639 "l3_offset :%x" 640 "ipsec_ah :%x" 641 "l4_offset :%x" 642 "msdu_number :%x" 643 "decap_format :%x" 644 "ipv4_proto :%x" 645 "ipv6_proto :%x" 646 "tcp_proto :%x" 647 "udp_proto :%x" 648 "ip_frag :%x" 649 "tcp_only_ack :%x" 650 "da_is_bcast_mcast :%x" 651 "toeplitz_hash_sel :%x" 652 "ip_fixed_header_valid:%x" 653 "ip_extn_header_valid :%x" 654 "tcp_udp_header_valid :%x", 655 msdu_end->reserved_17a, 656 msdu_end->msdu_length, 657 msdu_end->ipsec_esp, 658 msdu_end->l3_offset, 659 msdu_end->ipsec_ah, 660 msdu_end->l4_offset, 661 msdu_end->msdu_number, 662 msdu_end->decap_format, 663 msdu_end->ipv4_proto, 664 msdu_end->ipv6_proto, 665 msdu_end->tcp_proto, 666 msdu_end->udp_proto, 667 msdu_end->ip_frag, 668 msdu_end->tcp_only_ack, 669 msdu_end->da_is_bcast_mcast, 670 msdu_end->toeplitz_hash_sel, 671 msdu_end->ip_fixed_header_valid, 672 msdu_end->ip_extn_header_valid, 673 msdu_end->tcp_udp_header_valid); 674 675 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 676 "rx_msdu_end tlv (5/7)" 677 "mesh_control_present :%x" 678 "ldpc :%x" 679 "ip4_protocol_ip6_next_header :%x" 680 "toeplitz_hash_2_or_4 :%x" 681 "flow_id_toeplitz :%x" 682 "user_rssi :%x" 683 "pkt_type :%x" 684 "stbc :%x" 685 "sgi :%x" 686 "rate_mcs :%x" 687 "receive_bandwidth :%x" 688 "reception_type :%x" 689 "mimo_ss_bitmap :%x" 690 "ppdu_start_timestamp_31_0 :%x" 691 "ppdu_start_timestamp_63_32 :%x" 692 "sw_phy_meta_data :%x" 693 "vlan_ctag_ci :%x" 694 "vlan_stag_ci :%x" 695 "first_mpdu :%x" 696 "reserved_30a :%x" 697 "mcast_bcast :%x", 698 msdu_end->mesh_control_present, 699 msdu_end->ldpc, 700 msdu_end->ip4_protocol_ip6_next_header, 701 msdu_end->toeplitz_hash_2_or_4, 702 msdu_end->flow_id_toeplitz, 703 msdu_end->user_rssi, 704 msdu_end->pkt_type, 705 msdu_end->stbc, 706 msdu_end->sgi, 707 msdu_end->rate_mcs, 708 msdu_end->receive_bandwidth, 709 msdu_end->reception_type, 710 msdu_end->mimo_ss_bitmap, 711 msdu_end->ppdu_start_timestamp_31_0, 712 msdu_end->ppdu_start_timestamp_63_32, 713 msdu_end->sw_phy_meta_data, 714 msdu_end->vlan_ctag_ci, 715 msdu_end->vlan_stag_ci, 716 msdu_end->first_mpdu, 717 msdu_end->reserved_30a, 718 msdu_end->mcast_bcast); 719 720 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 721 "rx_msdu_end tlv (6/7)" 722 "ast_index_not_found :%x" 723 "ast_index_timeout :%x" 724 "power_mgmt :%x" 725 "non_qos :%x" 726 "null_data :%x" 727 "mgmt_type :%x" 728 "ctrl_type :%x" 729 "more_data :%x" 730 "eosp :%x" 731 "a_msdu_error :%x" 732 "fragment_flag:%x" 733 "order:%x" 734 "cce_match :%x" 735 "overflow_err :%x" 736 "msdu_length_err :%x" 737 "tcp_udp_chksum_fail :%x" 738 "ip_chksum_fail :%x" 739 "sa_idx_invalid :%x" 740 "da_idx_invalid :%x" 741 "reserved_30b :%x", 742 msdu_end->ast_index_not_found, 743 msdu_end->ast_index_timeout, 744 msdu_end->power_mgmt, 745 msdu_end->non_qos, 746 msdu_end->null_data, 747 msdu_end->mgmt_type, 748 msdu_end->ctrl_type, 749 msdu_end->more_data, 750 msdu_end->eosp, 751 msdu_end->a_msdu_error, 752 msdu_end->fragment_flag, 753 msdu_end->order, 754 msdu_end->cce_match, 755 msdu_end->overflow_err, 756 msdu_end->msdu_length_err, 757 msdu_end->tcp_udp_chksum_fail, 758 msdu_end->ip_chksum_fail, 759 msdu_end->sa_idx_invalid, 760 msdu_end->da_idx_invalid, 761 msdu_end->reserved_30b); 762 763 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 764 "rx_msdu_end tlv (7/7)" 765 "rx_in_tx_decrypt_byp :%x" 766 "encrypt_required :%x" 767 "directed :%x" 768 "buffer_fragment :%x" 769 "mpdu_length_err :%x" 770 "tkip_mic_err :%x" 771 "decrypt_err :%x" 772 "unencrypted_frame_err:%x" 773 "fcs_err :%x" 774 "reserved_31a :%x" 775 "decrypt_status_code :%x" 776 "rx_bitmap_not_updated:%x" 777 "reserved_31b :%x" 778 "msdu_done :%x", 779 msdu_end->rx_in_tx_decrypt_byp, 780 msdu_end->encrypt_required, 781 msdu_end->directed, 782 msdu_end->buffer_fragment, 783 msdu_end->mpdu_length_err, 784 msdu_end->tkip_mic_err, 785 msdu_end->decrypt_err, 786 msdu_end->unencrypted_frame_err, 787 msdu_end->fcs_err, 788 msdu_end->reserved_31a, 789 msdu_end->decrypt_status_code, 790 msdu_end->rx_bitmap_not_updated, 791 msdu_end->reserved_31b, 792 msdu_end->msdu_done); 793 } 794 #endif 795 796 #ifdef NO_RX_PKT_HDR_TLV 797 static inline void hal_rx_dump_pkt_hdr_tlv_kiwi(struct rx_pkt_tlvs *pkt_tlvs, 798 uint8_t dbg_level) 799 { 800 } 801 802 static inline 803 void hal_register_rx_pkt_hdr_tlv_api_kiwi(struct hal_soc *hal_soc) 804 { 805 } 806 807 static uint8_t *hal_rx_desc_get_80211_hdr_be(void *hw_desc_addr) 808 { 809 uint8_t *rx_pkt_hdr; 810 struct rx_mon_pkt_tlvs *rx_desc = 811 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 812 813 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 814 815 return rx_pkt_hdr; 816 } 817 #else 818 static uint8_t *hal_rx_desc_get_80211_hdr_be(void *hw_desc_addr) 819 { 820 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 821 uint8_t *rx_pkt_hdr; 822 823 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 824 825 return rx_pkt_hdr; 826 } 827 828 /** 829 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 830 * @pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 831 * @dbg_level: log level. 832 * 833 * Return: void 834 */ 835 static inline void hal_rx_dump_pkt_hdr_tlv_kiwi(struct rx_pkt_tlvs *pkt_tlvs, 836 uint8_t dbg_level) 837 { 838 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 839 840 hal_verbose_debug("\n---------------\n" 841 "rx_pkt_hdr_tlv\n" 842 "---------------\n" 843 "phy_ppdu_id %lld ", 844 pkt_hdr_tlv->phy_ppdu_id); 845 846 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 847 sizeof(pkt_hdr_tlv->rx_pkt_hdr)); 848 } 849 850 /** 851 * hal_register_rx_pkt_hdr_tlv_api_kiwi: register all rx_pkt_hdr_tlv related api 852 * @hal_soc: HAL soc handler 853 * 854 * Return: none 855 */ 856 static inline 857 void hal_register_rx_pkt_hdr_tlv_api_kiwi(struct hal_soc *hal_soc) 858 { 859 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 860 hal_rx_pkt_tlv_offset_get_generic; 861 } 862 #endif 863 864 /** 865 * hal_rx_dump_mpdu_start_tlv_generic_be: dump RX mpdu_start TLV in structured 866 * human readable format. 867 * @mpdu_start: pointer the rx_attention TLV in pkt. 868 * @dbg_level: log level. 869 * 870 * Return: void 871 */ 872 static inline void hal_rx_dump_mpdu_start_tlv_kiwi(void *mpdustart, 873 uint8_t dbg_level) 874 { 875 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 876 struct rx_mpdu_info *mpdu_info = 877 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 878 879 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 880 "rx_mpdu_start tlv (1/5) - " 881 "rx_reo_queue_desc_addr_31_0 :%x" 882 "rx_reo_queue_desc_addr_39_32 :%x" 883 "receive_queue_number:%x " 884 "pre_delim_err_warning:%x " 885 "first_delim_err:%x " 886 "reserved_2a:%x " 887 "pn_31_0:%x " 888 "pn_63_32:%x " 889 "pn_95_64:%x " 890 "pn_127_96:%x " 891 "epd_en:%x " 892 "all_frames_shall_be_encrypted :%x" 893 "encrypt_type:%x " 894 "wep_key_width_for_variable_key :%x" 895 "bssid_hit:%x " 896 "bssid_number:%x " 897 "tid:%x " 898 "reserved_7a:%x " 899 "peer_meta_data:%x ", 900 mpdu_info->rx_reo_queue_desc_addr_31_0, 901 mpdu_info->rx_reo_queue_desc_addr_39_32, 902 mpdu_info->receive_queue_number, 903 mpdu_info->pre_delim_err_warning, 904 mpdu_info->first_delim_err, 905 mpdu_info->reserved_2a, 906 mpdu_info->pn_31_0, 907 mpdu_info->pn_63_32, 908 mpdu_info->pn_95_64, 909 mpdu_info->pn_127_96, 910 mpdu_info->epd_en, 911 mpdu_info->all_frames_shall_be_encrypted, 912 mpdu_info->encrypt_type, 913 mpdu_info->wep_key_width_for_variable_key, 914 mpdu_info->bssid_hit, 915 mpdu_info->bssid_number, 916 mpdu_info->tid, 917 mpdu_info->reserved_7a, 918 mpdu_info->peer_meta_data); 919 920 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 921 "rx_mpdu_start tlv (2/5) - " 922 "rxpcu_mpdu_filter_in_category :%x" 923 "sw_frame_group_id:%x " 924 "ndp_frame:%x " 925 "phy_err:%x " 926 "phy_err_during_mpdu_header :%x" 927 "protocol_version_err:%x " 928 "ast_based_lookup_valid:%x " 929 "reserved_9a:%x " 930 "phy_ppdu_id:%x " 931 "ast_index:%x " 932 "sw_peer_id:%x " 933 "mpdu_frame_control_valid:%x " 934 "mpdu_duration_valid:%x " 935 "mac_addr_ad1_valid:%x " 936 "mac_addr_ad2_valid:%x " 937 "mac_addr_ad3_valid:%x " 938 "mac_addr_ad4_valid:%x " 939 "mpdu_sequence_control_valid :%x" 940 "mpdu_qos_control_valid:%x " 941 "mpdu_ht_control_valid:%x " 942 "frame_encryption_info_valid :%x", 943 mpdu_info->rxpcu_mpdu_filter_in_category, 944 mpdu_info->sw_frame_group_id, 945 mpdu_info->ndp_frame, 946 mpdu_info->phy_err, 947 mpdu_info->phy_err_during_mpdu_header, 948 mpdu_info->protocol_version_err, 949 mpdu_info->ast_based_lookup_valid, 950 mpdu_info->reserved_9a, 951 mpdu_info->phy_ppdu_id, 952 mpdu_info->ast_index, 953 mpdu_info->sw_peer_id, 954 mpdu_info->mpdu_frame_control_valid, 955 mpdu_info->mpdu_duration_valid, 956 mpdu_info->mac_addr_ad1_valid, 957 mpdu_info->mac_addr_ad2_valid, 958 mpdu_info->mac_addr_ad3_valid, 959 mpdu_info->mac_addr_ad4_valid, 960 mpdu_info->mpdu_sequence_control_valid, 961 mpdu_info->mpdu_qos_control_valid, 962 mpdu_info->mpdu_ht_control_valid, 963 mpdu_info->frame_encryption_info_valid); 964 965 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 966 "rx_mpdu_start tlv (3/5) - " 967 "mpdu_fragment_number:%x " 968 "more_fragment_flag:%x " 969 "reserved_11a:%x " 970 "fr_ds:%x " 971 "to_ds:%x " 972 "encrypted:%x " 973 "mpdu_retry:%x " 974 "mpdu_sequence_number:%x " 975 "key_id_octet:%x " 976 "new_peer_entry:%x " 977 "decrypt_needed:%x " 978 "decap_type:%x " 979 "rx_insert_vlan_c_tag_padding :%x" 980 "rx_insert_vlan_s_tag_padding :%x" 981 "strip_vlan_c_tag_decap:%x " 982 "strip_vlan_s_tag_decap:%x " 983 "pre_delim_count:%x " 984 "ampdu_flag:%x " 985 "bar_frame:%x " 986 "raw_mpdu:%x " 987 "reserved_12:%x " 988 "mpdu_length:%x ", 989 mpdu_info->mpdu_fragment_number, 990 mpdu_info->more_fragment_flag, 991 mpdu_info->reserved_11a, 992 mpdu_info->fr_ds, 993 mpdu_info->to_ds, 994 mpdu_info->encrypted, 995 mpdu_info->mpdu_retry, 996 mpdu_info->mpdu_sequence_number, 997 mpdu_info->key_id_octet, 998 mpdu_info->new_peer_entry, 999 mpdu_info->decrypt_needed, 1000 mpdu_info->decap_type, 1001 mpdu_info->rx_insert_vlan_c_tag_padding, 1002 mpdu_info->rx_insert_vlan_s_tag_padding, 1003 mpdu_info->strip_vlan_c_tag_decap, 1004 mpdu_info->strip_vlan_s_tag_decap, 1005 mpdu_info->pre_delim_count, 1006 mpdu_info->ampdu_flag, 1007 mpdu_info->bar_frame, 1008 mpdu_info->raw_mpdu, 1009 mpdu_info->reserved_12, 1010 mpdu_info->mpdu_length); 1011 1012 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 1013 "rx_mpdu_start tlv (4/5) - " 1014 "mpdu_length:%x " 1015 "first_mpdu:%x " 1016 "mcast_bcast:%x " 1017 "ast_index_not_found:%x " 1018 "ast_index_timeout:%x " 1019 "power_mgmt:%x " 1020 "non_qos:%x " 1021 "null_data:%x " 1022 "mgmt_type:%x " 1023 "ctrl_type:%x " 1024 "more_data:%x " 1025 "eosp:%x " 1026 "fragment_flag:%x " 1027 "order:%x " 1028 "u_apsd_trigger:%x " 1029 "encrypt_required:%x " 1030 "directed:%x " 1031 "amsdu_present:%x " 1032 "reserved_13:%x " 1033 "mpdu_frame_control_field:%x " 1034 "mpdu_duration_field:%x ", 1035 mpdu_info->mpdu_length, 1036 mpdu_info->first_mpdu, 1037 mpdu_info->mcast_bcast, 1038 mpdu_info->ast_index_not_found, 1039 mpdu_info->ast_index_timeout, 1040 mpdu_info->power_mgmt, 1041 mpdu_info->non_qos, 1042 mpdu_info->null_data, 1043 mpdu_info->mgmt_type, 1044 mpdu_info->ctrl_type, 1045 mpdu_info->more_data, 1046 mpdu_info->eosp, 1047 mpdu_info->fragment_flag, 1048 mpdu_info->order, 1049 mpdu_info->u_apsd_trigger, 1050 mpdu_info->encrypt_required, 1051 mpdu_info->directed, 1052 mpdu_info->amsdu_present, 1053 mpdu_info->reserved_13, 1054 mpdu_info->mpdu_frame_control_field, 1055 mpdu_info->mpdu_duration_field); 1056 1057 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 1058 "rx_mpdu_start tlv (5/5) - " 1059 "mac_addr_ad1_31_0:%x " 1060 "mac_addr_ad1_47_32:%x " 1061 "mac_addr_ad2_15_0:%x " 1062 "mac_addr_ad2_47_16:%x " 1063 "mac_addr_ad3_31_0:%x " 1064 "mac_addr_ad3_47_32:%x " 1065 "mpdu_sequence_control_field :%x" 1066 "mac_addr_ad4_31_0:%x " 1067 "mac_addr_ad4_47_32:%x " 1068 "mpdu_qos_control_field:%x " 1069 "mpdu_ht_control_field:%x " 1070 "vdev_id:%x " 1071 "service_code:%x " 1072 "priority_valid:%x " 1073 "reserved_23a:%x ", 1074 mpdu_info->mac_addr_ad1_31_0, 1075 mpdu_info->mac_addr_ad1_47_32, 1076 mpdu_info->mac_addr_ad2_15_0, 1077 mpdu_info->mac_addr_ad2_47_16, 1078 mpdu_info->mac_addr_ad3_31_0, 1079 mpdu_info->mac_addr_ad3_47_32, 1080 mpdu_info->mpdu_sequence_control_field, 1081 mpdu_info->mac_addr_ad4_31_0, 1082 mpdu_info->mac_addr_ad4_47_32, 1083 mpdu_info->mpdu_qos_control_field, 1084 mpdu_info->mpdu_ht_control_field, 1085 mpdu_info->vdev_id, 1086 mpdu_info->service_code, 1087 mpdu_info->priority_valid, 1088 mpdu_info->reserved_23a); 1089 } 1090 1091 /** 1092 * hal_rx_dump_pkt_tlvs_kiwi(): API to print RX Pkt TLVS for kiwi 1093 * @hal_soc_hdl: hal_soc handle 1094 * @buf: pointer the pkt buffer 1095 * @dbg_level: log level 1096 * 1097 * Return: void 1098 */ 1099 static void hal_rx_dump_pkt_tlvs_kiwi(hal_soc_handle_t hal_soc_hdl, 1100 uint8_t *buf, uint8_t dbg_level) 1101 { 1102 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1103 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1104 struct rx_mpdu_start *mpdu_start = 1105 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1106 1107 hal_rx_dump_msdu_end_tlv_kiwi(msdu_end, dbg_level); 1108 hal_rx_dump_mpdu_start_tlv_kiwi(mpdu_start, dbg_level); 1109 hal_rx_dump_pkt_hdr_tlv_kiwi(pkt_tlvs, dbg_level); 1110 } 1111 1112 /** 1113 * hal_rx_get_mpdu_flags_from_tlv() - Populate the local mpdu_flags elements 1114 * from the rx tlvs 1115 * @mpdu_info: buf address to rx_mpdu_info 1116 * 1117 * Return: mpdu_flags. 1118 */ 1119 static inline uint32_t 1120 hal_rx_get_mpdu_flags_from_tlv(struct rx_mpdu_info *mpdu_info) 1121 { 1122 uint32_t mpdu_flags = 0; 1123 1124 if (mpdu_info->fragment_flag) 1125 mpdu_flags |= HAL_MPDU_F_FRAGMENT; 1126 1127 if (mpdu_info->mpdu_retry) 1128 mpdu_flags |= HAL_MPDU_F_RETRY_BIT; 1129 1130 if (mpdu_info->ampdu_flag) 1131 mpdu_flags |= HAL_MPDU_F_AMPDU_FLAG; 1132 1133 if (mpdu_info->raw_mpdu) 1134 mpdu_flags |= HAL_MPDU_F_RAW_AMPDU; 1135 1136 if (mpdu_info->mpdu_qos_control_valid) 1137 mpdu_flags |= HAL_MPDU_F_QOS_CONTROL_VALID; 1138 1139 return mpdu_flags; 1140 } 1141 1142 /** 1143 * hal_rx_tlv_populate_mpdu_desc_info_kiwi() - Populate the local mpdu_desc_info 1144 * elements from the rx tlvs 1145 * @buf: start address of rx tlvs [Validated by caller] 1146 * @mpdu_desc_info_hdl: Buffer to populate the mpdu_dsc_info 1147 * [To be validated by caller] 1148 * 1149 * Return: None 1150 */ 1151 static void 1152 hal_rx_tlv_populate_mpdu_desc_info_kiwi(uint8_t *buf, 1153 void *mpdu_desc_info_hdl) 1154 { 1155 struct hal_rx_mpdu_desc_info *mpdu_desc_info = 1156 (struct hal_rx_mpdu_desc_info *)mpdu_desc_info_hdl; 1157 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1158 struct rx_mpdu_start *mpdu_start = 1159 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1160 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1161 1162 mpdu_desc_info->mpdu_seq = mpdu_info->mpdu_sequence_number; 1163 mpdu_desc_info->mpdu_flags = hal_rx_get_mpdu_flags_from_tlv(mpdu_info); 1164 mpdu_desc_info->peer_meta_data = mpdu_info->peer_meta_data; 1165 mpdu_desc_info->bar_frame = mpdu_info->bar_frame; 1166 } 1167 1168 /** 1169 * hal_reo_status_get_header_kiwi - Process reo desc info 1170 * @d - Pointer to reo descriptior 1171 * @b - tlv type info 1172 * @h1 - Pointer to hal_reo_status_header where info to be stored 1173 * 1174 * Return - none. 1175 * 1176 */ 1177 static void hal_reo_status_get_header_kiwi(hal_ring_desc_t ring_desc, int b, 1178 void *h1) 1179 { 1180 uint64_t *d = (uint64_t *)ring_desc; 1181 uint64_t val1 = 0; 1182 struct hal_reo_status_header *h = 1183 (struct hal_reo_status_header *)h1; 1184 1185 /* Offsets of descriptor fields defined in HW headers start 1186 * from the field after TLV header 1187 */ 1188 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr)); 1189 1190 switch (b) { 1191 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1192 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1193 STATUS_HEADER_REO_STATUS_NUMBER)]; 1194 break; 1195 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1196 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1197 STATUS_HEADER_REO_STATUS_NUMBER)]; 1198 break; 1199 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1200 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1201 STATUS_HEADER_REO_STATUS_NUMBER)]; 1202 break; 1203 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1204 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1205 STATUS_HEADER_REO_STATUS_NUMBER)]; 1206 break; 1207 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1208 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1209 STATUS_HEADER_REO_STATUS_NUMBER)]; 1210 break; 1211 case HAL_REO_DESC_THRES_STATUS_TLV: 1212 val1 = 1213 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1214 STATUS_HEADER_REO_STATUS_NUMBER)]; 1215 break; 1216 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1217 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1218 STATUS_HEADER_REO_STATUS_NUMBER)]; 1219 break; 1220 default: 1221 qdf_nofl_err("ERROR: Unknown tlv\n"); 1222 break; 1223 } 1224 h->cmd_num = 1225 HAL_GET_FIELD( 1226 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER, 1227 val1); 1228 h->exec_time = 1229 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1230 CMD_EXECUTION_TIME, val1); 1231 h->status = 1232 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1233 REO_CMD_EXECUTION_STATUS, val1); 1234 switch (b) { 1235 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1236 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1237 STATUS_HEADER_TIMESTAMP)]; 1238 break; 1239 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1240 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1241 STATUS_HEADER_TIMESTAMP)]; 1242 break; 1243 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1244 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1245 STATUS_HEADER_TIMESTAMP)]; 1246 break; 1247 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1248 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1249 STATUS_HEADER_TIMESTAMP)]; 1250 break; 1251 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1252 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1253 STATUS_HEADER_TIMESTAMP)]; 1254 break; 1255 case HAL_REO_DESC_THRES_STATUS_TLV: 1256 val1 = 1257 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1258 STATUS_HEADER_TIMESTAMP)]; 1259 break; 1260 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1261 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1262 STATUS_HEADER_TIMESTAMP)]; 1263 break; 1264 default: 1265 qdf_nofl_err("ERROR: Unknown tlv\n"); 1266 break; 1267 } 1268 h->tstamp = 1269 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1); 1270 } 1271 1272 static 1273 void *hal_rx_msdu0_buffer_addr_lsb_kiwi(void *link_desc_va) 1274 { 1275 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1276 } 1277 1278 static 1279 void *hal_rx_msdu_desc_info_ptr_get_kiwi(void *msdu0) 1280 { 1281 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1282 } 1283 1284 static 1285 void *hal_ent_mpdu_desc_info_kiwi(void *ent_ring_desc) 1286 { 1287 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1288 } 1289 1290 static 1291 void *hal_dst_mpdu_desc_info_kiwi(void *dst_ring_desc) 1292 { 1293 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1294 } 1295 1296 /* 1297 * hal_rx_get_tlv_kiwi(): API to get the tlv 1298 * 1299 * @rx_tlv: TLV data extracted from the rx packet 1300 * Return: uint8_t 1301 */ 1302 static uint8_t hal_rx_get_tlv_kiwi(void *rx_tlv) 1303 { 1304 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH); 1305 } 1306 1307 /** 1308 * hal_rx_proc_phyrx_other_receive_info_tlv_kiwi() 1309 * - process other receive info TLV 1310 * @rx_tlv_hdr: pointer to TLV header 1311 * @ppdu_info: pointer to ppdu_info 1312 * 1313 * Return: None 1314 */ 1315 static 1316 void hal_rx_proc_phyrx_other_receive_info_tlv_kiwi(void *rx_tlv_hdr, 1317 void *ppdu_info_handle) 1318 { 1319 uint32_t tlv_tag, tlv_len; 1320 uint32_t temp_len, other_tlv_len, other_tlv_tag; 1321 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 1322 void *other_tlv_hdr = NULL; 1323 void *other_tlv = NULL; 1324 1325 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 1326 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 1327 temp_len = 0; 1328 1329 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 1330 1331 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 1332 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 1333 temp_len += other_tlv_len; 1334 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 1335 1336 switch (other_tlv_tag) { 1337 default: 1338 hal_err_rl("unhandled TLV type: %d, TLV len:%d", 1339 other_tlv_tag, other_tlv_len); 1340 break; 1341 } 1342 } 1343 1344 /** 1345 * hal_reo_config_kiwi(): Set reo config parameters 1346 * @soc: hal soc handle 1347 * @reg_val: value to be set 1348 * @reo_params: reo parameters 1349 * 1350 * Return: void 1351 */ 1352 static 1353 void hal_reo_config_kiwi(struct hal_soc *soc, 1354 uint32_t reg_val, 1355 struct hal_reo_params *reo_params) 1356 { 1357 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1358 } 1359 1360 /** 1361 * hal_rx_msdu_desc_info_get_ptr_kiwi() - Get msdu desc info ptr 1362 * @msdu_details_ptr - Pointer to msdu_details_ptr 1363 * 1364 * Return - Pointer to rx_msdu_desc_info structure. 1365 * 1366 */ 1367 static void *hal_rx_msdu_desc_info_get_ptr_kiwi(void *msdu_details_ptr) 1368 { 1369 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1370 } 1371 1372 /** 1373 * hal_rx_link_desc_msdu0_ptr_kiwi - Get pointer to rx_msdu details 1374 * @link_desc - Pointer to link desc 1375 * 1376 * Return - Pointer to rx_msdu_details structure 1377 * 1378 */ 1379 static void *hal_rx_link_desc_msdu0_ptr_kiwi(void *link_desc) 1380 { 1381 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1382 } 1383 1384 /** 1385 * hal_get_window_address_kiwi(): Function to get hp/tp address 1386 * @hal_soc: Pointer to hal_soc 1387 * @addr: address offset of register 1388 * 1389 * Return: modified address offset of register 1390 */ 1391 static inline qdf_iomem_t hal_get_window_address_kiwi(struct hal_soc *hal_soc, 1392 qdf_iomem_t addr) 1393 { 1394 return addr; 1395 } 1396 1397 /** 1398 * hal_reo_set_err_dst_remap_kiwi(): Function to set REO error destination 1399 * ring remap register 1400 * @hal_soc: Pointer to hal_soc 1401 * 1402 * Return: none. 1403 */ 1404 static void 1405 hal_reo_set_err_dst_remap_kiwi(void *hal_soc) 1406 { 1407 /* 1408 * Set REO error 2k jump (error code 5) / OOR (error code 7) 1409 * frame routed to REO2SW0 ring. 1410 */ 1411 uint32_t dst_remap_ix0 = 1412 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 0) | 1413 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 1) | 1414 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 2) | 1415 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 3) | 1416 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 4) | 1417 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) | 1418 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) | 1419 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7); 1420 1421 uint32_t dst_remap_ix1 = 1422 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 14) | 1423 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 13) | 1424 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 12) | 1425 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 11) | 1426 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 10) | 1427 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 9) | 1428 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 8); 1429 1430 HAL_REG_WRITE(hal_soc, 1431 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1432 REO_REG_REG_BASE), 1433 dst_remap_ix0); 1434 1435 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x", 1436 HAL_REG_READ( 1437 hal_soc, 1438 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1439 REO_REG_REG_BASE))); 1440 1441 HAL_REG_WRITE(hal_soc, 1442 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1443 REO_REG_REG_BASE), 1444 dst_remap_ix1); 1445 1446 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1 0x%x", 1447 HAL_REG_READ( 1448 hal_soc, 1449 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1450 REO_REG_REG_BASE))); 1451 } 1452 1453 /** 1454 * hal_reo_enable_pn_in_dest_kiwi() - Set the REO register to enable previous PN 1455 * for OOR and 2K-jump frames 1456 * @hal_soc: HAL SoC handle 1457 * 1458 * Return: 1, since the register is set. 1459 */ 1460 static uint8_t hal_reo_enable_pn_in_dest_kiwi(void *hal_soc) 1461 { 1462 HAL_REG_WRITE(hal_soc, HWIO_REO_R0_PN_IN_DEST_ADDR(REO_REG_REG_BASE), 1463 1); 1464 return 1; 1465 } 1466 1467 /** 1468 * hal_rx_flow_setup_fse_kiwi() - Setup a flow search entry in HW FST 1469 * @fst: Pointer to the Rx Flow Search Table 1470 * @table_offset: offset into the table where the flow is to be setup 1471 * @flow: Flow Parameters 1472 * 1473 * Flow table entry fields are updated in host byte order, little endian order. 1474 * 1475 * Return: Success/Failure 1476 */ 1477 static void * 1478 hal_rx_flow_setup_fse_kiwi(uint8_t *rx_fst, uint32_t table_offset, 1479 uint8_t *rx_flow) 1480 { 1481 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1482 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1483 uint8_t *fse; 1484 bool fse_valid; 1485 1486 if (table_offset >= fst->max_entries) { 1487 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1488 "HAL FSE table offset %u exceeds max entries %u", 1489 table_offset, fst->max_entries); 1490 return NULL; 1491 } 1492 1493 fse = (uint8_t *)fst->base_vaddr + 1494 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1495 1496 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1497 1498 if (fse_valid) { 1499 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1500 "HAL FSE %pK already valid", fse); 1501 return NULL; 1502 } 1503 1504 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) = 1505 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1506 (flow->tuple_info.src_ip_127_96)); 1507 1508 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) = 1509 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1510 (flow->tuple_info.src_ip_95_64)); 1511 1512 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) = 1513 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1514 (flow->tuple_info.src_ip_63_32)); 1515 1516 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) = 1517 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1518 (flow->tuple_info.src_ip_31_0)); 1519 1520 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) = 1521 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1522 (flow->tuple_info.dest_ip_127_96)); 1523 1524 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) = 1525 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1526 (flow->tuple_info.dest_ip_95_64)); 1527 1528 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) = 1529 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1530 (flow->tuple_info.dest_ip_63_32)); 1531 1532 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) = 1533 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1534 (flow->tuple_info.dest_ip_31_0)); 1535 1536 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT); 1537 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |= 1538 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1539 (flow->tuple_info.dest_port)); 1540 1541 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT); 1542 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |= 1543 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1544 (flow->tuple_info.src_port)); 1545 1546 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL); 1547 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |= 1548 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1549 flow->tuple_info.l4_protocol); 1550 1551 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER); 1552 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |= 1553 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1554 flow->reo_destination_handler); 1555 1556 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1557 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |= 1558 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1559 1560 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA); 1561 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) = 1562 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1563 (flow->fse_metadata)); 1564 1565 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION); 1566 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |= 1567 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1568 REO_DESTINATION_INDICATION, 1569 flow->reo_destination_indication); 1570 1571 /* Reset all the other fields in FSE */ 1572 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9); 1573 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP); 1574 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT); 1575 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT); 1576 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP); 1577 1578 return fse; 1579 } 1580 1581 /* 1582 * hal_rx_flow_setup_cmem_fse_kiwi() - Setup a flow search entry in HW CMEM FST 1583 * @hal_soc: hal_soc reference 1584 * @cmem_ba: CMEM base address 1585 * @table_offset: offset into the table where the flow is to be setup 1586 * @flow: Flow Parameters 1587 * 1588 * Return: Success/Failure 1589 */ 1590 static uint32_t 1591 hal_rx_flow_setup_cmem_fse_kiwi(struct hal_soc *hal_soc, uint32_t cmem_ba, 1592 uint32_t table_offset, uint8_t *rx_flow) 1593 { 1594 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1595 uint32_t fse_offset; 1596 uint32_t value; 1597 1598 fse_offset = cmem_ba + (table_offset * HAL_RX_FST_ENTRY_SIZE); 1599 1600 /* Reset the Valid bit */ 1601 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1602 VALID), 0); 1603 1604 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1605 (flow->tuple_info.src_ip_127_96)); 1606 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1607 SRC_IP_127_96), value); 1608 1609 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1610 (flow->tuple_info.src_ip_95_64)); 1611 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1612 SRC_IP_95_64), value); 1613 1614 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1615 (flow->tuple_info.src_ip_63_32)); 1616 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1617 SRC_IP_63_32), value); 1618 1619 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1620 (flow->tuple_info.src_ip_31_0)); 1621 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1622 SRC_IP_31_0), value); 1623 1624 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1625 (flow->tuple_info.dest_ip_127_96)); 1626 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1627 DEST_IP_127_96), value); 1628 1629 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1630 (flow->tuple_info.dest_ip_95_64)); 1631 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1632 DEST_IP_95_64), value); 1633 1634 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1635 (flow->tuple_info.dest_ip_63_32)); 1636 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1637 DEST_IP_63_32), value); 1638 1639 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1640 (flow->tuple_info.dest_ip_31_0)); 1641 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1642 DEST_IP_31_0), value); 1643 1644 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1645 (flow->tuple_info.dest_port)); 1646 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1647 (flow->tuple_info.src_port)); 1648 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1649 SRC_PORT), value); 1650 1651 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1652 (flow->fse_metadata)); 1653 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1654 METADATA), value); 1655 1656 /* Reset all the other fields in FSE */ 1657 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1658 MSDU_COUNT), 0); 1659 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1660 MSDU_BYTE_COUNT), 0); 1661 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1662 TIMESTAMP), 0); 1663 1664 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1665 flow->tuple_info.l4_protocol); 1666 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1667 flow->reo_destination_handler); 1668 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1669 REO_DESTINATION_INDICATION, 1670 flow->reo_destination_indication); 1671 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1672 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1673 L4_PROTOCOL), value); 1674 1675 return fse_offset; 1676 } 1677 1678 /** 1679 * hal_rx_flow_get_cmem_fse_ts_kiwi() - Get timestamp field from CMEM FSE 1680 * @hal_soc: hal_soc reference 1681 * @fse_offset: CMEM FSE offset 1682 * 1683 * Return: Timestamp 1684 */ 1685 static uint32_t hal_rx_flow_get_cmem_fse_ts_kiwi(struct hal_soc *hal_soc, 1686 uint32_t fse_offset) 1687 { 1688 return HAL_CMEM_READ(hal_soc, fse_offset + 1689 HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, TIMESTAMP)); 1690 } 1691 1692 /** 1693 * hal_rx_flow_get_cmem_fse_kiwi() - Get FSE from CMEM 1694 * @hal_soc: hal_soc reference 1695 * @fse_offset: CMEM FSE offset 1696 * @fse: referece where FSE will be copied 1697 * @len: length of FSE 1698 * 1699 * Return: If read is succesfull or not 1700 */ 1701 static void 1702 hal_rx_flow_get_cmem_fse_kiwi(struct hal_soc *hal_soc, uint32_t fse_offset, 1703 uint32_t *fse, qdf_size_t len) 1704 { 1705 int i; 1706 1707 if (len != HAL_RX_FST_ENTRY_SIZE) 1708 return; 1709 1710 for (i = 0; i < NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY; i++) 1711 fse[i] = HAL_CMEM_READ(hal_soc, fse_offset + i * 4); 1712 } 1713 1714 static 1715 void hal_compute_reo_remap_ix2_ix3_kiwi(uint32_t *ring_map, 1716 uint32_t num_rings, uint32_t *remap1, 1717 uint32_t *remap2) 1718 { 1719 1720 switch (num_rings) { 1721 /* should we have all the different possible ring configs */ 1722 default: 1723 case 3: 1724 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1725 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1726 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1727 HAL_REO_REMAP_IX2(ring_map[0], 19) | 1728 HAL_REO_REMAP_IX2(ring_map[1], 20) | 1729 HAL_REO_REMAP_IX2(ring_map[2], 21) | 1730 HAL_REO_REMAP_IX2(ring_map[0], 22) | 1731 HAL_REO_REMAP_IX2(ring_map[1], 23); 1732 1733 *remap2 = HAL_REO_REMAP_IX3(ring_map[2], 24) | 1734 HAL_REO_REMAP_IX3(ring_map[0], 25) | 1735 HAL_REO_REMAP_IX3(ring_map[1], 26) | 1736 HAL_REO_REMAP_IX3(ring_map[2], 27) | 1737 HAL_REO_REMAP_IX3(ring_map[0], 28) | 1738 HAL_REO_REMAP_IX3(ring_map[1], 29) | 1739 HAL_REO_REMAP_IX3(ring_map[2], 30) | 1740 HAL_REO_REMAP_IX3(ring_map[0], 31); 1741 break; 1742 case 4: 1743 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1744 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1745 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1746 HAL_REO_REMAP_IX2(ring_map[3], 19) | 1747 HAL_REO_REMAP_IX2(ring_map[0], 20) | 1748 HAL_REO_REMAP_IX2(ring_map[1], 21) | 1749 HAL_REO_REMAP_IX2(ring_map[2], 22) | 1750 HAL_REO_REMAP_IX2(ring_map[3], 23); 1751 1752 *remap2 = HAL_REO_REMAP_IX3(ring_map[0], 24) | 1753 HAL_REO_REMAP_IX3(ring_map[1], 25) | 1754 HAL_REO_REMAP_IX3(ring_map[2], 26) | 1755 HAL_REO_REMAP_IX3(ring_map[3], 27) | 1756 HAL_REO_REMAP_IX3(ring_map[0], 28) | 1757 HAL_REO_REMAP_IX3(ring_map[1], 29) | 1758 HAL_REO_REMAP_IX3(ring_map[2], 30) | 1759 HAL_REO_REMAP_IX3(ring_map[3], 31); 1760 break; 1761 case 6: 1762 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1763 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1764 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1765 HAL_REO_REMAP_IX2(ring_map[3], 19) | 1766 HAL_REO_REMAP_IX2(ring_map[4], 20) | 1767 HAL_REO_REMAP_IX2(ring_map[5], 21) | 1768 HAL_REO_REMAP_IX2(ring_map[0], 22) | 1769 HAL_REO_REMAP_IX2(ring_map[1], 23); 1770 1771 *remap2 = HAL_REO_REMAP_IX3(ring_map[2], 24) | 1772 HAL_REO_REMAP_IX3(ring_map[3], 25) | 1773 HAL_REO_REMAP_IX3(ring_map[4], 26) | 1774 HAL_REO_REMAP_IX3(ring_map[5], 27) | 1775 HAL_REO_REMAP_IX3(ring_map[0], 28) | 1776 HAL_REO_REMAP_IX3(ring_map[1], 29) | 1777 HAL_REO_REMAP_IX3(ring_map[2], 30) | 1778 HAL_REO_REMAP_IX3(ring_map[3], 31); 1779 break; 1780 case 8: 1781 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1782 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1783 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1784 HAL_REO_REMAP_IX2(ring_map[3], 19) | 1785 HAL_REO_REMAP_IX2(ring_map[4], 20) | 1786 HAL_REO_REMAP_IX2(ring_map[5], 21) | 1787 HAL_REO_REMAP_IX2(ring_map[6], 22) | 1788 HAL_REO_REMAP_IX2(ring_map[7], 23); 1789 1790 *remap2 = HAL_REO_REMAP_IX3(ring_map[0], 24) | 1791 HAL_REO_REMAP_IX3(ring_map[1], 25) | 1792 HAL_REO_REMAP_IX3(ring_map[2], 26) | 1793 HAL_REO_REMAP_IX3(ring_map[3], 27) | 1794 HAL_REO_REMAP_IX3(ring_map[4], 28) | 1795 HAL_REO_REMAP_IX3(ring_map[5], 29) | 1796 HAL_REO_REMAP_IX3(ring_map[6], 30) | 1797 HAL_REO_REMAP_IX3(ring_map[7], 31); 1798 break; 1799 } 1800 } 1801 1802 /* NUM TCL Bank registers in KIWI */ 1803 #define HAL_NUM_TCL_BANKS_KIWI 8 1804 1805 /** 1806 * hal_tx_get_num_tcl_banks_kiwi() - Get number of banks in target 1807 * 1808 * Returns: number of bank 1809 */ 1810 static uint8_t hal_tx_get_num_tcl_banks_kiwi(void) 1811 { 1812 return HAL_NUM_TCL_BANKS_KIWI; 1813 } 1814 1815 /** 1816 * hal_rx_reo_prev_pn_get_kiwi() - Get the previous PN from the REO ring desc. 1817 * @ring_desc: REO ring descriptor [To be validated by caller ] 1818 * @prev_pn: Buffer where the previous PN is to be populated. 1819 * [To be validated by caller] 1820 * 1821 * Return: None 1822 */ 1823 static void hal_rx_reo_prev_pn_get_kiwi(void *ring_desc, 1824 uint64_t *prev_pn) 1825 { 1826 struct reo_destination_ring_with_pn *reo_desc = 1827 (struct reo_destination_ring_with_pn *)ring_desc; 1828 1829 *prev_pn = reo_desc->prev_pn_23_0; 1830 *prev_pn |= ((uint64_t)reo_desc->prev_pn_55_24 << 24); 1831 } 1832 1833 /** 1834 * hal_cmem_write_kiwi() - function for CMEM buffer writing 1835 * @hal_soc_hdl: HAL SOC handle 1836 * @offset: CMEM address 1837 * @value: value to write 1838 * 1839 * Return: None. 1840 */ 1841 static inline void hal_cmem_write_kiwi(hal_soc_handle_t hal_soc_hdl, 1842 uint32_t offset, 1843 uint32_t value) 1844 { 1845 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1846 1847 hal_write32_mb(hal, offset, value); 1848 } 1849 1850 /** 1851 * hal_get_idle_link_bm_id_kiwi() - Get idle link BM id from chid_id 1852 * @chip_id: mlo chip_id 1853 * 1854 * Returns: RBM ID 1855 */ 1856 static uint8_t hal_get_idle_link_bm_id_kiwi(uint8_t chip_id) 1857 { 1858 return WBM_IDLE_DESC_LIST; 1859 } 1860 1861 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1862 /** 1863 * hal_get_first_wow_wakeup_packet_kiwi(): Function to get if the buffer 1864 * is the first one that wakes up host from WoW. 1865 * 1866 * @buf: network buffer 1867 * 1868 * Dummy function for KIWI 1869 * 1870 * Returns: 1 to indicate it is first packet received that wakes up host from 1871 * WoW. Otherwise 0 1872 */ 1873 static inline uint8_t hal_get_first_wow_wakeup_packet_kiwi(uint8_t *buf) 1874 { 1875 return 0; 1876 } 1877 #endif 1878 1879 static uint16_t hal_get_rx_max_ba_window_kiwi(int tid) 1880 { 1881 return HAL_RX_BA_WINDOW_1024; 1882 } 1883 1884 /** 1885 * hal_get_reo_qdesc_size_kiwi()- Get the reo queue descriptor size 1886 * from the give Block-Ack window size 1887 * Return: reo queue descriptor size 1888 */ 1889 static uint32_t hal_get_reo_qdesc_size_kiwi(uint32_t ba_window_size, int tid) 1890 { 1891 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 1892 * NON_QOS_TID until HW issues are resolved. 1893 */ 1894 if (tid != HAL_NON_QOS_TID) 1895 ba_window_size = hal_get_rx_max_ba_window_kiwi(tid); 1896 1897 /* Return descriptor size corresponding to window size of 2 since 1898 * we set ba_window_size to 2 while setting up REO descriptors as 1899 * a WAR to get 2k jump exception aggregates are received without 1900 * a BA session. 1901 */ 1902 if (ba_window_size <= 1) { 1903 if (tid != HAL_NON_QOS_TID) 1904 return sizeof(struct rx_reo_queue) + 1905 sizeof(struct rx_reo_queue_ext); 1906 else 1907 return sizeof(struct rx_reo_queue); 1908 } 1909 1910 if (ba_window_size <= 105) 1911 return sizeof(struct rx_reo_queue) + 1912 sizeof(struct rx_reo_queue_ext); 1913 1914 if (ba_window_size <= 210) 1915 return sizeof(struct rx_reo_queue) + 1916 (2 * sizeof(struct rx_reo_queue_ext)); 1917 1918 if (ba_window_size <= 256) 1919 return sizeof(struct rx_reo_queue) + 1920 (3 * sizeof(struct rx_reo_queue_ext)); 1921 1922 return sizeof(struct rx_reo_queue) + 1923 (10 * sizeof(struct rx_reo_queue_ext)) + 1924 sizeof(struct rx_reo_queue_1k); 1925 } 1926 1927 #ifdef QCA_GET_TSF_VIA_REG 1928 static inline void 1929 hal_get_tsf_enum(uint32_t tsf_id, uint32_t mac_id, 1930 enum hal_scratch_reg_enum *tsf_enum_low, 1931 enum hal_scratch_reg_enum *tsf_enum_hi) 1932 { 1933 if (mac_id == 0) { 1934 if (tsf_id == 0) { 1935 *tsf_enum_low = PMM_MAC0_TSF1_OFFSET_LO_US; 1936 *tsf_enum_hi = PMM_MAC0_TSF1_OFFSET_HI_US; 1937 } else if (tsf_id == 1) { 1938 *tsf_enum_low = PMM_MAC0_TSF2_OFFSET_LO_US; 1939 *tsf_enum_hi = PMM_MAC0_TSF2_OFFSET_HI_US; 1940 } 1941 } else if (mac_id == 1) { 1942 if (tsf_id == 0) { 1943 *tsf_enum_low = PMM_MAC1_TSF1_OFFSET_LO_US; 1944 *tsf_enum_hi = PMM_MAC1_TSF1_OFFSET_HI_US; 1945 } else if (tsf_id == 1) { 1946 *tsf_enum_low = PMM_MAC1_TSF2_OFFSET_LO_US; 1947 *tsf_enum_hi = PMM_MAC1_TSF2_OFFSET_HI_US; 1948 } 1949 } 1950 } 1951 1952 static inline uint32_t 1953 hal_tsf_read_scratch_reg(struct hal_soc *soc, 1954 enum hal_scratch_reg_enum reg_enum) 1955 { 1956 return hal_read32_mb(soc, PMM_REG_BASE + (reg_enum * 4)); 1957 } 1958 1959 static inline 1960 uint64_t hal_tsf_get_fw_time(struct hal_soc *soc) 1961 { 1962 uint64_t fw_time_low; 1963 uint64_t fw_time_high; 1964 1965 fw_time_low = hal_read32_mb(soc, PCIE_PCIE_MHI_TIME_LOW); 1966 fw_time_high = hal_read32_mb(soc, PCIE_PCIE_MHI_TIME_HIGH); 1967 return (fw_time_high << 32 | fw_time_low); 1968 } 1969 1970 static inline 1971 uint64_t hal_fw_qtime_to_usecs(uint64_t time) 1972 { 1973 /* 1974 * Try to preserve precision by multiplying by 10 first. 1975 * If that would cause a wrap around, divide first instead. 1976 */ 1977 if (time * 10 < time) { 1978 time = qdf_do_div(time, FW_QTIME_CYCLES_PER_10_USEC); 1979 return time * 10; 1980 } 1981 1982 time = time * 10; 1983 time = qdf_do_div(time, FW_QTIME_CYCLES_PER_10_USEC); 1984 1985 return time; 1986 } 1987 1988 /** 1989 * hal_get_tsf_time_kiwi() - Get tsf time from scatch register 1990 * @hal_soc_hdl: HAL soc handle 1991 * @mac_id: mac_id 1992 * @tsf: pointer to update tsf value 1993 * @tsf_sync_soc_time: pointer to update tsf sync time 1994 * 1995 * Return: None. 1996 */ 1997 static void 1998 hal_get_tsf_time_kiwi(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id, 1999 uint32_t mac_id, uint64_t *tsf, 2000 uint64_t *tsf_sync_soc_time) 2001 { 2002 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 2003 uint64_t global_time_low_offset, global_time_high_offset; 2004 uint64_t tsf_offset_low, tsf_offset_hi; 2005 uint64_t fw_time, global_time, sync_time; 2006 enum hal_scratch_reg_enum tsf_enum_low, tsf_enum_high; 2007 2008 if (hif_force_wake_request(soc->hif_handle)) 2009 return; 2010 2011 hal_get_tsf_enum(tsf_id, mac_id, &tsf_enum_low, &tsf_enum_high); 2012 sync_time = qdf_get_log_timestamp(); 2013 fw_time = hal_tsf_get_fw_time(soc); 2014 2015 global_time_low_offset = 2016 hal_tsf_read_scratch_reg(soc, PMM_QTIMER_GLOBAL_OFFSET_LO_US); 2017 global_time_high_offset = 2018 hal_tsf_read_scratch_reg(soc, PMM_QTIMER_GLOBAL_OFFSET_HI_US); 2019 2020 tsf_offset_low = hal_tsf_read_scratch_reg(soc, tsf_enum_low); 2021 tsf_offset_hi = hal_tsf_read_scratch_reg(soc, tsf_enum_high); 2022 2023 fw_time = hal_fw_qtime_to_usecs(fw_time); 2024 global_time = fw_time + 2025 (global_time_low_offset | 2026 (global_time_high_offset << 32)); 2027 2028 *tsf = global_time + (tsf_offset_low | (tsf_offset_hi << 32)); 2029 *tsf_sync_soc_time = qdf_log_timestamp_to_usecs(sync_time); 2030 2031 hif_force_wake_release(soc->hif_handle); 2032 } 2033 #else 2034 static inline void 2035 hal_get_tsf_time_kiwi(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id, 2036 uint32_t mac_id, uint64_t *tsf, 2037 uint64_t *tsf_sync_soc_time) 2038 { 2039 } 2040 #endif 2041 2042 static void hal_hw_txrx_ops_attach_kiwi(struct hal_soc *hal_soc) 2043 { 2044 /* init and setup */ 2045 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 2046 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 2047 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 2048 hal_soc->ops->hal_get_window_address = hal_get_window_address_kiwi; 2049 hal_soc->ops->hal_reo_set_err_dst_remap = 2050 hal_reo_set_err_dst_remap_kiwi; 2051 hal_soc->ops->hal_reo_enable_pn_in_dest = 2052 hal_reo_enable_pn_in_dest_kiwi; 2053 /* Overwrite the default BE ops */ 2054 hal_soc->ops->hal_get_rx_max_ba_window = hal_get_rx_max_ba_window_kiwi; 2055 hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_kiwi; 2056 2057 /* tx */ 2058 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_kiwi; 2059 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_kiwi; 2060 hal_soc->ops->hal_tx_comp_get_status = 2061 hal_tx_comp_get_status_generic_be; 2062 hal_soc->ops->hal_tx_init_cmd_credit_ring = 2063 hal_tx_init_cmd_credit_ring_kiwi; 2064 hal_soc->ops->hal_tx_config_rbm_mapping_be = 2065 hal_tx_config_rbm_mapping_be_kiwi; 2066 2067 /* rx */ 2068 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; 2069 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 2070 hal_rx_mon_hw_desc_get_mpdu_status_be; 2071 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_kiwi; 2072 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be; 2073 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 2074 hal_rx_proc_phyrx_other_receive_info_tlv_kiwi; 2075 2076 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_kiwi; 2077 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 2078 hal_rx_dump_mpdu_start_tlv_kiwi; 2079 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_kiwi; 2080 hal_soc->ops->hal_rx_desc_get_80211_hdr = hal_rx_desc_get_80211_hdr_be; 2081 2082 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_kiwi; 2083 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be; 2084 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 2085 hal_rx_tlv_reception_type_get_be; 2086 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 2087 hal_rx_msdu_end_da_idx_get_be; 2088 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 2089 hal_rx_msdu_desc_info_get_ptr_kiwi; 2090 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 2091 hal_rx_link_desc_msdu0_ptr_kiwi; 2092 hal_soc->ops->hal_reo_status_get_header = 2093 hal_reo_status_get_header_kiwi; 2094 hal_soc->ops->hal_rx_status_get_tlv_info = 2095 hal_rx_status_get_tlv_info_wrapper_be; 2096 hal_soc->ops->hal_rx_wbm_err_info_get = 2097 hal_rx_wbm_err_info_get_generic_be; 2098 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 2099 hal_rx_priv_info_set_in_tlv_be; 2100 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 2101 hal_rx_priv_info_get_from_tlv_be; 2102 2103 hal_soc->ops->hal_tx_set_pcp_tid_map = 2104 hal_tx_set_pcp_tid_map_generic_be; 2105 hal_soc->ops->hal_tx_update_pcp_tid_map = 2106 hal_tx_update_pcp_tid_generic_be; 2107 hal_soc->ops->hal_tx_set_tidmap_prty = 2108 hal_tx_update_tidmap_prty_generic_be; 2109 hal_soc->ops->hal_rx_get_rx_fragment_number = 2110 hal_rx_get_rx_fragment_number_be; 2111 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 2112 hal_rx_tlv_da_is_mcbc_get_be; 2113 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 2114 hal_rx_tlv_sa_is_valid_get_be; 2115 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be, 2116 hal_soc->ops->hal_rx_desc_is_first_msdu = 2117 hal_rx_desc_is_first_msdu_be; 2118 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 2119 hal_rx_tlv_l3_hdr_padding_get_be; 2120 hal_soc->ops->hal_rx_encryption_info_valid = 2121 hal_rx_encryption_info_valid_be; 2122 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; 2123 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 2124 hal_rx_tlv_first_msdu_get_be; 2125 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 2126 hal_rx_tlv_da_is_valid_get_be; 2127 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 2128 hal_rx_tlv_last_msdu_get_be; 2129 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 2130 hal_rx_get_mpdu_mac_ad4_valid_be; 2131 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 2132 hal_rx_mpdu_start_sw_peer_id_get_be; 2133 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 2134 hal_rx_mpdu_peer_meta_data_get_be; 2135 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be; 2136 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be; 2137 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 2138 hal_rx_get_mpdu_frame_control_valid_be; 2139 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; 2140 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; 2141 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; 2142 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; 2143 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 2144 hal_rx_get_mpdu_sequence_control_valid_be; 2145 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; 2146 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; 2147 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 2148 hal_rx_hw_desc_get_ppduid_get_be; 2149 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 2150 hal_rx_msdu0_buffer_addr_lsb_kiwi; 2151 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 2152 hal_rx_msdu_desc_info_ptr_get_kiwi; 2153 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_kiwi; 2154 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_kiwi; 2155 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; 2156 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; 2157 hal_soc->ops->hal_rx_get_mac_addr2_valid = 2158 hal_rx_get_mac_addr2_valid_be; 2159 hal_soc->ops->hal_rx_get_filter_category = 2160 hal_rx_get_filter_category_be; 2161 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be; 2162 hal_soc->ops->hal_reo_config = hal_reo_config_kiwi; 2163 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; 2164 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 2165 hal_rx_msdu_flow_idx_invalid_be; 2166 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 2167 hal_rx_msdu_flow_idx_timeout_be; 2168 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 2169 hal_rx_msdu_fse_metadata_get_be; 2170 hal_soc->ops->hal_rx_msdu_cce_match_get = 2171 hal_rx_msdu_cce_match_get_be; 2172 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 2173 hal_rx_msdu_cce_metadata_get_be; 2174 hal_soc->ops->hal_rx_msdu_get_flow_params = 2175 hal_rx_msdu_get_flow_params_be; 2176 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 2177 hal_rx_tlv_get_tcp_chksum_be; 2178 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be; 2179 #if defined(QCA_WIFI_KIWI) && defined(WLAN_CFR_ENABLE) && \ 2180 defined(WLAN_ENH_CFR_ENABLE) 2181 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_kiwi; 2182 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_kiwi; 2183 #else 2184 hal_soc->ops->hal_rx_get_bb_info = NULL; 2185 hal_soc->ops->hal_rx_get_rtt_info = NULL; 2186 #endif 2187 /* rx - msdu end fast path info fields */ 2188 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 2189 hal_rx_msdu_packet_metadata_get_generic_be; 2190 hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum = 2191 hal_rx_get_fisa_cumulative_l4_checksum_be; 2192 hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length = 2193 hal_rx_get_fisa_cumulative_ip_length_be; 2194 hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_be; 2195 hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation = 2196 hal_rx_get_flow_agg_continuation_be; 2197 hal_soc->ops->hal_rx_get_fisa_flow_agg_count = 2198 hal_rx_get_flow_agg_count_be; 2199 hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_be; 2200 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 2201 hal_rx_mpdu_start_tlv_tag_valid_be; 2202 hal_soc->ops->hal_rx_reo_prev_pn_get = hal_rx_reo_prev_pn_get_kiwi; 2203 2204 /* rx - TLV struct offsets */ 2205 hal_register_rx_pkt_hdr_tlv_api_kiwi(hal_soc); 2206 hal_soc->ops->hal_rx_msdu_end_offset_get = 2207 hal_rx_msdu_end_offset_get_generic; 2208 hal_soc->ops->hal_rx_mpdu_start_offset_get = 2209 hal_rx_mpdu_start_offset_get_generic; 2210 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_kiwi; 2211 hal_soc->ops->hal_rx_flow_get_tuple_info = 2212 hal_rx_flow_get_tuple_info_be; 2213 hal_soc->ops->hal_rx_flow_delete_entry = 2214 hal_rx_flow_delete_entry_be; 2215 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be; 2216 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 2217 hal_compute_reo_remap_ix2_ix3_kiwi; 2218 hal_soc->ops->hal_rx_flow_setup_cmem_fse = 2219 hal_rx_flow_setup_cmem_fse_kiwi; 2220 hal_soc->ops->hal_rx_flow_get_cmem_fse_ts = 2221 hal_rx_flow_get_cmem_fse_ts_kiwi; 2222 hal_soc->ops->hal_rx_flow_get_cmem_fse = hal_rx_flow_get_cmem_fse_kiwi; 2223 hal_soc->ops->hal_cmem_write = hal_cmem_write_kiwi; 2224 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 2225 hal_rx_msdu_get_reo_destination_indication_be; 2226 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_kiwi; 2227 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; 2228 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 2229 hal_rx_msdu_is_wlan_mcast_generic_be; 2230 hal_soc->ops->hal_rx_tlv_bw_get = 2231 hal_rx_tlv_bw_get_be; 2232 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 2233 hal_rx_tlv_get_is_decrypted_be; 2234 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be; 2235 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be; 2236 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 2237 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 2238 hal_soc->ops->hal_rx_tlv_mpdu_len_err_get = 2239 hal_rx_tlv_mpdu_len_err_get_be; 2240 hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get = 2241 hal_rx_tlv_mpdu_fcs_err_get_be; 2242 2243 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be; 2244 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 2245 hal_rx_tlv_decrypt_err_get_be; 2246 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; 2247 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; 2248 hal_soc->ops->hal_rx_tlv_decap_format_get = 2249 hal_rx_tlv_decap_format_get_be; 2250 hal_soc->ops->hal_rx_tlv_get_offload_info = 2251 hal_rx_tlv_get_offload_info_be; 2252 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 2253 hal_rx_attn_phy_ppdu_id_get_be; 2254 hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_tlv_msdu_done_get_be; 2255 hal_soc->ops->hal_rx_tlv_msdu_len_get = 2256 hal_rx_msdu_start_msdu_len_get_be; 2257 hal_soc->ops->hal_rx_get_frame_ctrl_field = 2258 hal_rx_get_frame_ctrl_field_be; 2259 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; 2260 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; 2261 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; 2262 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 2263 hal_rx_mpdu_info_ampdu_flag_get_be; 2264 hal_soc->ops->hal_rx_tlv_msdu_len_set = 2265 hal_rx_msdu_start_msdu_len_set_be; 2266 hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info = 2267 hal_rx_tlv_populate_mpdu_desc_info_kiwi; 2268 hal_soc->ops->hal_get_idle_link_bm_id = hal_get_idle_link_bm_id_kiwi; 2269 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 2270 hal_soc->ops->hal_get_first_wow_wakeup_packet = 2271 hal_get_first_wow_wakeup_packet_kiwi; 2272 #endif 2273 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 2274 2275 hal_soc->ops->hal_rx_tlv_l3_type_get = hal_rx_tlv_l3_type_get_be; 2276 hal_soc->ops->hal_tx_vdev_mismatch_routing_set = 2277 hal_tx_vdev_mismatch_routing_set_generic_be; 2278 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = 2279 hal_tx_mcast_mlo_reinject_routing_set_generic_be; 2280 hal_soc->ops->hal_get_ba_aging_timeout = 2281 hal_get_ba_aging_timeout_be_generic; 2282 hal_soc->ops->hal_setup_link_idle_list = 2283 hal_setup_link_idle_list_generic_be; 2284 hal_soc->ops->hal_cookie_conversion_reg_cfg_be = 2285 hal_cookie_conversion_reg_cfg_generic_be; 2286 hal_soc->ops->hal_set_ba_aging_timeout = 2287 hal_set_ba_aging_timeout_be_generic; 2288 hal_soc->ops->hal_tx_populate_bank_register = 2289 hal_tx_populate_bank_register_be; 2290 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = 2291 hal_tx_vdev_mcast_ctrl_set_be; 2292 hal_soc->ops->hal_get_tsf_time = hal_get_tsf_time_kiwi; 2293 }; 2294 2295 struct hal_hw_srng_config hw_srng_table_kiwi[] = { 2296 /* TODO: max_rings can populated by querying HW capabilities */ 2297 { /* REO_DST */ 2298 .start_ring_id = HAL_SRNG_REO2SW1, 2299 .max_rings = 8, 2300 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2301 .lmac_ring = FALSE, 2302 .ring_dir = HAL_SRNG_DST_RING, 2303 .nf_irq_support = true, 2304 .reg_start = { 2305 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 2306 REO_REG_REG_BASE), 2307 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 2308 REO_REG_REG_BASE) 2309 }, 2310 .reg_size = { 2311 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 2312 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 2313 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 2314 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 2315 }, 2316 .max_size = 2317 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 2318 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 2319 }, 2320 { /* REO_EXCEPTION */ 2321 /* Designating REO2SW0 ring as exception ring. */ 2322 .start_ring_id = HAL_SRNG_REO2SW0, 2323 .max_rings = 1, 2324 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2325 .lmac_ring = FALSE, 2326 .ring_dir = HAL_SRNG_DST_RING, 2327 .reg_start = { 2328 HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR( 2329 REO_REG_REG_BASE), 2330 HWIO_REO_R2_REO2SW0_RING_HP_ADDR( 2331 REO_REG_REG_BASE) 2332 }, 2333 /* Single ring - provide ring size if multiple rings of this 2334 * type are supported 2335 */ 2336 .reg_size = {}, 2337 .max_size = 2338 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >> 2339 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT, 2340 }, 2341 { /* REO_REINJECT */ 2342 .start_ring_id = HAL_SRNG_SW2REO, 2343 .max_rings = 1, 2344 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2345 .lmac_ring = FALSE, 2346 .ring_dir = HAL_SRNG_SRC_RING, 2347 .reg_start = { 2348 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 2349 REO_REG_REG_BASE), 2350 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 2351 REO_REG_REG_BASE) 2352 }, 2353 /* Single ring - provide ring size if multiple rings of this 2354 * type are supported 2355 */ 2356 .reg_size = {}, 2357 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 2358 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 2359 }, 2360 { /* REO_CMD */ 2361 .start_ring_id = HAL_SRNG_REO_CMD, 2362 .max_rings = 1, 2363 .entry_size = (sizeof(struct tlv_32_hdr) + 2364 sizeof(struct reo_get_queue_stats)) >> 2, 2365 .lmac_ring = FALSE, 2366 .ring_dir = HAL_SRNG_SRC_RING, 2367 .reg_start = { 2368 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 2369 REO_REG_REG_BASE), 2370 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 2371 REO_REG_REG_BASE), 2372 }, 2373 /* Single ring - provide ring size if multiple rings of this 2374 * type are supported 2375 */ 2376 .reg_size = {}, 2377 .max_size = 2378 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 2379 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 2380 }, 2381 { /* REO_STATUS */ 2382 .start_ring_id = HAL_SRNG_REO_STATUS, 2383 .max_rings = 1, 2384 .entry_size = (sizeof(struct tlv_32_hdr) + 2385 sizeof(struct reo_get_queue_stats_status)) >> 2, 2386 .lmac_ring = FALSE, 2387 .ring_dir = HAL_SRNG_DST_RING, 2388 .reg_start = { 2389 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2390 REO_REG_REG_BASE), 2391 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2392 REO_REG_REG_BASE), 2393 }, 2394 /* Single ring - provide ring size if multiple rings of this 2395 * type are supported 2396 */ 2397 .reg_size = {}, 2398 .max_size = 2399 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2400 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2401 }, 2402 { /* TCL_DATA */ 2403 .start_ring_id = HAL_SRNG_SW2TCL1, 2404 .max_rings = 5, 2405 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 2406 .lmac_ring = FALSE, 2407 .ring_dir = HAL_SRNG_SRC_RING, 2408 .reg_start = { 2409 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2410 MAC_TCL_REG_REG_BASE), 2411 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2412 MAC_TCL_REG_REG_BASE), 2413 }, 2414 .reg_size = { 2415 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2416 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2417 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2418 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2419 }, 2420 .max_size = 2421 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2422 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2423 }, 2424 { /* TCL_CMD */ 2425 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2426 #ifndef WLAN_DP_DISABLE_TCL_CMD_CRED_SRNG 2427 .max_rings = 1, 2428 #else 2429 .max_rings = 0, 2430 #endif 2431 .entry_size = sizeof(struct tcl_gse_cmd) >> 2, 2432 .lmac_ring = FALSE, 2433 .ring_dir = HAL_SRNG_SRC_RING, 2434 .reg_start = { 2435 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2436 MAC_TCL_REG_REG_BASE), 2437 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2438 MAC_TCL_REG_REG_BASE), 2439 }, 2440 /* Single ring - provide ring size if multiple rings of this 2441 * type are supported 2442 */ 2443 .reg_size = {}, 2444 .max_size = 2445 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2446 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2447 }, 2448 { /* TCL_STATUS */ 2449 .start_ring_id = HAL_SRNG_TCL_STATUS, 2450 #ifndef WLAN_DP_DISABLE_TCL_CMD_CRED_SRNG 2451 .max_rings = 1, 2452 #else 2453 .max_rings = 0, 2454 #endif 2455 /* confirm that TLV header is needed */ 2456 .entry_size = sizeof(struct tcl_status_ring) >> 2, 2457 .lmac_ring = FALSE, 2458 .ring_dir = HAL_SRNG_DST_RING, 2459 .reg_start = { 2460 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2461 MAC_TCL_REG_REG_BASE), 2462 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2463 MAC_TCL_REG_REG_BASE), 2464 }, 2465 /* Single ring - provide ring size if multiple rings of this 2466 * type are supported 2467 */ 2468 .reg_size = {}, 2469 .max_size = 2470 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2471 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2472 }, 2473 { /* CE_SRC */ 2474 .start_ring_id = HAL_SRNG_CE_0_SRC, 2475 .max_rings = 12, 2476 .entry_size = sizeof(struct ce_src_desc) >> 2, 2477 .lmac_ring = FALSE, 2478 .ring_dir = HAL_SRNG_SRC_RING, 2479 .reg_start = { 2480 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, 2481 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, 2482 }, 2483 .reg_size = { 2484 SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 2485 SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 2486 SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 2487 SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 2488 }, 2489 .max_size = 2490 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >> 2491 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT, 2492 }, 2493 { /* CE_DST */ 2494 .start_ring_id = HAL_SRNG_CE_0_DST, 2495 .max_rings = 12, 2496 .entry_size = 8 >> 2, 2497 /*TODO: entry_size above should actually be 2498 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2499 * of struct ce_dst_desc in HW header files 2500 */ 2501 .lmac_ring = FALSE, 2502 .ring_dir = HAL_SRNG_SRC_RING, 2503 .reg_start = { 2504 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, 2505 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, 2506 }, 2507 .reg_size = { 2508 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2509 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2510 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2511 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2512 }, 2513 .max_size = 2514 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2515 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2516 }, 2517 { /* CE_DST_STATUS */ 2518 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2519 .max_rings = 12, 2520 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2521 .lmac_ring = FALSE, 2522 .ring_dir = HAL_SRNG_DST_RING, 2523 .reg_start = { 2524 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, 2525 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, 2526 }, 2527 .reg_size = { 2528 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2529 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2530 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2531 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2532 }, 2533 .max_size = 2534 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2535 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2536 }, 2537 { /* WBM_IDLE_LINK */ 2538 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2539 .max_rings = 1, 2540 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2541 .lmac_ring = FALSE, 2542 .ring_dir = HAL_SRNG_SRC_RING, 2543 .reg_start = { 2544 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2545 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE), 2546 }, 2547 /* Single ring - provide ring size if multiple rings of this 2548 * type are supported 2549 */ 2550 .reg_size = {}, 2551 .max_size = 2552 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2553 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2554 }, 2555 { /* SW2WBM_RELEASE */ 2556 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2557 .max_rings = 1, 2558 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2559 .lmac_ring = FALSE, 2560 .ring_dir = HAL_SRNG_SRC_RING, 2561 .reg_start = { 2562 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2563 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2564 }, 2565 /* Single ring - provide ring size if multiple rings of this 2566 * type are supported 2567 */ 2568 .reg_size = {}, 2569 .max_size = 2570 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2571 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2572 }, 2573 { /* WBM2SW_RELEASE */ 2574 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2575 .max_rings = 8, 2576 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2577 .lmac_ring = FALSE, 2578 .ring_dir = HAL_SRNG_DST_RING, 2579 .nf_irq_support = true, 2580 .reg_start = { 2581 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2582 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2583 }, 2584 .reg_size = { 2585 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE) - 2586 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2587 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE) - 2588 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2589 }, 2590 .max_size = 2591 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2592 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2593 }, 2594 { /* RXDMA_BUF */ 2595 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2596 #ifdef IPA_OFFLOAD 2597 .max_rings = 3, 2598 #else 2599 .max_rings = 2, 2600 #endif 2601 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2602 .lmac_ring = TRUE, 2603 .ring_dir = HAL_SRNG_SRC_RING, 2604 /* reg_start is not set because LMAC rings are not accessed 2605 * from host 2606 */ 2607 .reg_start = {}, 2608 .reg_size = {}, 2609 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2610 }, 2611 { /* RXDMA_DST */ 2612 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2613 .max_rings = 1, 2614 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2615 .lmac_ring = TRUE, 2616 .ring_dir = HAL_SRNG_DST_RING, 2617 /* reg_start is not set because LMAC rings are not accessed 2618 * from host 2619 */ 2620 .reg_start = {}, 2621 .reg_size = {}, 2622 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2623 }, 2624 { /* RXDMA_MONITOR_BUF */ 2625 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2626 .max_rings = 1, 2627 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2628 .lmac_ring = TRUE, 2629 .ring_dir = HAL_SRNG_SRC_RING, 2630 /* reg_start is not set because LMAC rings are not accessed 2631 * from host 2632 */ 2633 .reg_start = {}, 2634 .reg_size = {}, 2635 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2636 }, 2637 { /* RXDMA_MONITOR_STATUS */ 2638 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2639 .max_rings = 1, 2640 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2641 .lmac_ring = TRUE, 2642 .ring_dir = HAL_SRNG_SRC_RING, 2643 /* reg_start is not set because LMAC rings are not accessed 2644 * from host 2645 */ 2646 .reg_start = {}, 2647 .reg_size = {}, 2648 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2649 }, 2650 { /* RXDMA_MONITOR_DST */ 2651 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2652 .max_rings = 1, 2653 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2654 .lmac_ring = TRUE, 2655 .ring_dir = HAL_SRNG_DST_RING, 2656 /* reg_start is not set because LMAC rings are not accessed 2657 * from host 2658 */ 2659 .reg_start = {}, 2660 .reg_size = {}, 2661 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2662 }, 2663 { /* RXDMA_MONITOR_DESC */ 2664 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2665 .max_rings = 1, 2666 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2667 .lmac_ring = TRUE, 2668 .ring_dir = HAL_SRNG_SRC_RING, 2669 /* reg_start is not set because LMAC rings are not accessed 2670 * from host 2671 */ 2672 .reg_start = {}, 2673 .reg_size = {}, 2674 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2675 }, 2676 { /* DIR_BUF_RX_DMA_SRC */ 2677 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2678 /* 2679 * one ring is for spectral scan 2680 * the other is for cfr 2681 */ 2682 .max_rings = 2, 2683 .entry_size = 2, 2684 .lmac_ring = TRUE, 2685 .ring_dir = HAL_SRNG_SRC_RING, 2686 /* reg_start is not set because LMAC rings are not accessed 2687 * from host 2688 */ 2689 .reg_start = {}, 2690 .reg_size = {}, 2691 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2692 }, 2693 #ifdef WLAN_FEATURE_CIF_CFR 2694 { /* WIFI_POS_SRC */ 2695 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2696 .max_rings = 1, 2697 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2698 .lmac_ring = TRUE, 2699 .ring_dir = HAL_SRNG_SRC_RING, 2700 /* reg_start is not set because LMAC rings are not accessed 2701 * from host 2702 */ 2703 .reg_start = {}, 2704 .reg_size = {}, 2705 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2706 }, 2707 #endif 2708 { /* REO2PPE */ 0}, 2709 { /* PPE2TCL */ 0}, 2710 { /* PPE_RELEASE */ 0}, 2711 { /* TX_MONITOR_BUF */ 0}, 2712 { /* TX_MONITOR_DST */ 0}, 2713 { /* SW2RXDMA_NEW */ 0}, 2714 }; 2715 2716 /** 2717 * hal_srng_hw_reg_offset_init_kiwi() - Initialize the HW srng reg offset 2718 * applicable only for KIWI 2719 * @hal_soc: HAL Soc handle 2720 * 2721 * Return: None 2722 */ 2723 static inline void hal_srng_hw_reg_offset_init_kiwi(struct hal_soc *hal_soc) 2724 { 2725 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 2726 2727 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB), 2728 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB), 2729 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA), 2730 hw_reg_offset[DST_PRODUCER_INT2_SETUP] = 2731 REG_OFFSET(DST, PRODUCER_INT2_SETUP); 2732 } 2733 2734 /** 2735 * hal_kiwi_attach() - Attach kiwi target specific hal_soc ops, 2736 * offset and srng table 2737 */ 2738 void hal_kiwi_attach(struct hal_soc *hal_soc) 2739 { 2740 hal_soc->hw_srng_table = hw_srng_table_kiwi; 2741 2742 hal_srng_hw_reg_offset_init_generic(hal_soc); 2743 hal_srng_hw_reg_offset_init_kiwi(hal_soc); 2744 hal_hw_txrx_default_ops_attach_be(hal_soc); 2745 hal_hw_txrx_ops_attach_kiwi(hal_soc); 2746 } 2747