1 /* 2 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "qdf_types.h" 21 #include "qdf_util.h" 22 #include "qdf_types.h" 23 #include "qdf_lock.h" 24 #include "qdf_mem.h" 25 #include "qdf_nbuf.h" 26 #include "hal_hw_headers.h" 27 #include "hal_internal.h" 28 #include "hal_api.h" 29 #include "target_type.h" 30 #include "wcss_version.h" 31 #include "qdf_module.h" 32 #include "hal_flow.h" 33 #include "rx_flow_search_entry.h" 34 #include "hal_rx_flow_info.h" 35 #include "hal_be_api.h" 36 #include "reo_destination_ring_with_pn.h" 37 #include "rx_reo_queue_1k.h" 38 39 #include <hal_be_rx.h> 40 41 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 42 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 43 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 44 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 45 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 46 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 47 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 48 PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 49 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 50 PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 51 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 52 PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 53 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 54 PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 59 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 60 PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 61 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 62 PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 63 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 64 PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 65 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 66 PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 67 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 68 PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 69 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 70 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 71 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 72 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 73 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 74 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 75 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 76 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 77 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 78 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 79 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 80 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 81 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 82 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 83 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 84 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 85 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 86 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 87 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 88 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 89 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 90 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 91 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 92 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 94 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 95 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 96 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 97 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 98 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 99 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 100 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 101 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 102 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 103 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 104 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 105 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 106 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 107 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 108 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 109 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 110 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 112 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 113 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 114 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 115 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 116 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 117 118 #include "hal_kiwi_tx.h" 119 #include "hal_kiwi_rx.h" 120 121 #include "hal_be_rx_tlv.h" 122 123 #include <hal_generic_api.h> 124 #include "hal_be_api_mon.h" 125 #include <hal_be_generic_api.h> 126 127 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 128 129 /* For Berryllium sw2rxdma ring size increased to 20 bits */ 130 #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF 131 132 #ifdef QCA_GET_TSF_VIA_REG 133 #define PCIE_PCIE_MHI_TIME_LOW 0xA28 134 #define PCIE_PCIE_MHI_TIME_HIGH 0xA2C 135 136 #define PMM_REG_BASE 0xB500FC 137 138 #define FW_QTIME_CYCLES_PER_10_USEC 192 139 #endif 140 141 struct wbm2sw_completion_ring_tx gwbm2sw_tx_comp_symbol __attribute__((used)); 142 struct wbm2sw_completion_ring_rx gwbm2sw_rx_comp_symbol __attribute__((used)); 143 144 static uint32_t hal_get_link_desc_size_kiwi(void) 145 { 146 return LINK_DESC_SIZE; 147 } 148 149 /** 150 * hal_rx_dump_msdu_end_tlv_kiwi() - dump RX msdu_end TLV in structured 151 * human readable format. 152 * @msduend: pointer the msdu_end TLV in pkt. 153 * @dbg_level: log level. 154 * 155 * Return: void 156 */ 157 #ifdef QCA_WIFI_KIWI_V2 158 static void hal_rx_dump_msdu_end_tlv_kiwi(void *msduend, 159 uint8_t dbg_level) 160 { 161 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 162 163 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 164 "rx_msdu_end tlv (1/5)- " 165 "rxpcu_mpdu_filter_in_category :%x " 166 "sw_frame_group_id :%x " 167 "reserved_0 :%x " 168 "phy_ppdu_id :%x " 169 "ip_hdr_chksum :%x " 170 "reported_mpdu_length :%x " 171 "reserved_1a :%x " 172 "reserved_2a :%x " 173 "cce_super_rule :%x " 174 "cce_classify_not_done_truncate :%x " 175 "cce_classify_not_done_cce_dis :%x " 176 "cumulative_l3_checksum :%x " 177 "rule_indication_31_0 :%x " 178 "ipv6_options_crc :%x " 179 "da_offset :%x " 180 "sa_offset :%x " 181 "da_offset_valid :%x " 182 "sa_offset_valid :%x " 183 "reserved_5a :%x " 184 "l3_type :%x", 185 msdu_end->rxpcu_mpdu_filter_in_category, 186 msdu_end->sw_frame_group_id, 187 msdu_end->reserved_0, 188 msdu_end->phy_ppdu_id, 189 msdu_end->ip_hdr_chksum, 190 msdu_end->reported_mpdu_length, 191 msdu_end->reserved_1a, 192 msdu_end->reserved_2a, 193 msdu_end->cce_super_rule, 194 msdu_end->cce_classify_not_done_truncate, 195 msdu_end->cce_classify_not_done_cce_dis, 196 msdu_end->cumulative_l3_checksum, 197 msdu_end->rule_indication_31_0, 198 msdu_end->ipv6_options_crc, 199 msdu_end->da_offset, 200 msdu_end->sa_offset, 201 msdu_end->da_offset_valid, 202 msdu_end->sa_offset_valid, 203 msdu_end->reserved_5a, 204 msdu_end->l3_type); 205 206 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 207 "rx_msdu_end tlv (2/5)- " 208 "rule_indication_63_32 :%x " 209 "tcp_seq_number :%x " 210 "tcp_ack_number :%x " 211 "tcp_flag :%x " 212 "lro_eligible :%x " 213 "reserved_9a :%x " 214 "window_size :%x " 215 "sa_sw_peer_id :%x " 216 "sa_idx_timeout :%x " 217 "da_idx_timeout :%x " 218 "to_ds :%x " 219 "tid :%x " 220 "sa_is_valid :%x " 221 "da_is_valid :%x " 222 "da_is_mcbc :%x " 223 "l3_header_padding :%x " 224 "first_msdu :%x " 225 "last_msdu :%x " 226 "fr_ds :%x " 227 "ip_chksum_fail_copy :%x " 228 "sa_idx :%x " 229 "da_idx_or_sw_peer_id :%x", 230 msdu_end->rule_indication_63_32, 231 msdu_end->tcp_seq_number, 232 msdu_end->tcp_ack_number, 233 msdu_end->tcp_flag, 234 msdu_end->lro_eligible, 235 msdu_end->reserved_9a, 236 msdu_end->window_size, 237 msdu_end->sa_sw_peer_id, 238 msdu_end->sa_idx_timeout, 239 msdu_end->da_idx_timeout, 240 msdu_end->to_ds, 241 msdu_end->tid, 242 msdu_end->sa_is_valid, 243 msdu_end->da_is_valid, 244 msdu_end->da_is_mcbc, 245 msdu_end->l3_header_padding, 246 msdu_end->first_msdu, 247 msdu_end->last_msdu, 248 msdu_end->fr_ds, 249 msdu_end->ip_chksum_fail_copy, 250 msdu_end->sa_idx, 251 msdu_end->da_idx_or_sw_peer_id); 252 253 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 254 "rx_msdu_end tlv (3/5)- " 255 "msdu_drop :%x " 256 "reo_destination_indication :%x " 257 "flow_idx :%x " 258 "use_ppe :%x " 259 "__reserved_g_0003 :%x " 260 "vlan_ctag_stripped :%x " 261 "vlan_stag_stripped :%x " 262 "fragment_flag :%x " 263 "fse_metadata :%x " 264 "cce_metadata :%x " 265 "tcp_udp_chksum :%x " 266 "aggregation_count :%x " 267 "flow_aggregation_continuation :%x " 268 "fisa_timeout :%x " 269 "tcp_udp_chksum_fail_copy :%x " 270 "msdu_limit_error :%x " 271 "flow_idx_timeout :%x " 272 "flow_idx_invalid :%x " 273 "cce_match :%x " 274 "amsdu_parser_error :%x " 275 "cumulative_ip_length :%x " 276 "key_id_octet :%x " 277 "reserved_16a :%x " 278 "reserved_17a :%x " 279 "service_code :%x " 280 "priority_valid :%x " 281 "intra_bss :%x " 282 "dest_chip_id :%x " 283 "multicast_echo :%x " 284 "wds_learning_event :%x " 285 "wds_roaming_event :%x " 286 "wds_keep_alive_event :%x " 287 "reserved_17b :%x", 288 msdu_end->msdu_drop, 289 msdu_end->reo_destination_indication, 290 msdu_end->flow_idx, 291 msdu_end->use_ppe, 292 msdu_end->__reserved_g_0003, 293 msdu_end->vlan_ctag_stripped, 294 msdu_end->vlan_stag_stripped, 295 msdu_end->fragment_flag, 296 msdu_end->fse_metadata, 297 msdu_end->cce_metadata, 298 msdu_end->tcp_udp_chksum, 299 msdu_end->aggregation_count, 300 msdu_end->flow_aggregation_continuation, 301 msdu_end->fisa_timeout, 302 msdu_end->tcp_udp_chksum_fail_copy, 303 msdu_end->msdu_limit_error, 304 msdu_end->flow_idx_timeout, 305 msdu_end->flow_idx_invalid, 306 msdu_end->cce_match, 307 msdu_end->amsdu_parser_error, 308 msdu_end->cumulative_ip_length, 309 msdu_end->key_id_octet, 310 msdu_end->reserved_16a, 311 msdu_end->reserved_17a, 312 msdu_end->service_code, 313 msdu_end->priority_valid, 314 msdu_end->intra_bss, 315 msdu_end->dest_chip_id, 316 msdu_end->multicast_echo, 317 msdu_end->wds_learning_event, 318 msdu_end->wds_roaming_event, 319 msdu_end->wds_keep_alive_event, 320 msdu_end->reserved_17b); 321 322 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 323 "rx_msdu_end tlv (4/5)- " 324 "msdu_length :%x " 325 "stbc :%x " 326 "ipsec_esp :%x " 327 "l3_offset :%x " 328 "ipsec_ah :%x " 329 "l4_offset :%x " 330 "msdu_number :%x " 331 "decap_format :%x " 332 "ipv4_proto :%x " 333 "ipv6_proto :%x " 334 "tcp_proto :%x " 335 "udp_proto :%x " 336 "ip_frag :%x " 337 "tcp_only_ack :%x " 338 "da_is_bcast_mcast :%x " 339 "toeplitz_hash_sel :%x " 340 "ip_fixed_header_valid :%x " 341 "ip_extn_header_valid :%x " 342 "tcp_udp_header_valid :%x " 343 "mesh_control_present :%x " 344 "ldpc :%x " 345 "ip4_protocol_ip6_next_header :%x " 346 "vlan_ctag_ci :%x " 347 "vlan_stag_ci :%x " 348 "peer_meta_data :%x " 349 "user_rssi :%x " 350 "pkt_type :%x " 351 "sgi :%x " 352 "rate_mcs :%x " 353 "receive_bandwidth :%x " 354 "reception_type :%x " 355 "mimo_ss_bitmap :%x " 356 "msdu_done_copy :%x " 357 "flow_id_toeplitz :%x", 358 msdu_end->msdu_length, 359 msdu_end->stbc, 360 msdu_end->ipsec_esp, 361 msdu_end->l3_offset, 362 msdu_end->ipsec_ah, 363 msdu_end->l4_offset, 364 msdu_end->msdu_number, 365 msdu_end->decap_format, 366 msdu_end->ipv4_proto, 367 msdu_end->ipv6_proto, 368 msdu_end->tcp_proto, 369 msdu_end->udp_proto, 370 msdu_end->ip_frag, 371 msdu_end->tcp_only_ack, 372 msdu_end->da_is_bcast_mcast, 373 msdu_end->toeplitz_hash_sel, 374 msdu_end->ip_fixed_header_valid, 375 msdu_end->ip_extn_header_valid, 376 msdu_end->tcp_udp_header_valid, 377 msdu_end->mesh_control_present, 378 msdu_end->ldpc, 379 msdu_end->ip4_protocol_ip6_next_header, 380 msdu_end->vlan_ctag_ci, 381 msdu_end->vlan_stag_ci, 382 msdu_end->peer_meta_data, 383 msdu_end->user_rssi, 384 msdu_end->pkt_type, 385 msdu_end->sgi, 386 msdu_end->rate_mcs, 387 msdu_end->receive_bandwidth, 388 msdu_end->reception_type, 389 msdu_end->mimo_ss_bitmap, 390 msdu_end->msdu_done_copy, 391 msdu_end->flow_id_toeplitz); 392 393 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 394 "rx_msdu_end tlv (5/5)- " 395 "ppdu_start_timestamp_63_32 :%x " 396 "sw_phy_meta_data :%x " 397 "ppdu_start_timestamp_31_0 :%x " 398 "toeplitz_hash_2_or_4 :%x " 399 "reserved_28a :%x " 400 "sa_15_0 :%x " 401 "sa_47_16 :%x " 402 "first_mpdu :%x " 403 "reserved_30a :%x " 404 "mcast_bcast :%x " 405 "ast_index_not_found :%x " 406 "ast_index_timeout :%x " 407 "power_mgmt :%x " 408 "non_qos :%x " 409 "null_data :%x " 410 "mgmt_type :%x " 411 "ctrl_type :%x " 412 "more_data :%x " 413 "eosp :%x " 414 "a_msdu_error :%x " 415 "reserved_30b :%x " 416 "order :%x " 417 "wifi_parser_error :%x " 418 "overflow_err :%x " 419 "msdu_length_err :%x " 420 "tcp_udp_chksum_fail :%x " 421 "ip_chksum_fail :%x " 422 "sa_idx_invalid :%x " 423 "da_idx_invalid :%x " 424 "amsdu_addr_mismatch :%x " 425 "rx_in_tx_decrypt_byp :%x " 426 "encrypt_required :%x " 427 "directed :%x " 428 "buffer_fragment :%x " 429 "mpdu_length_err :%x " 430 "tkip_mic_err :%x " 431 "decrypt_err :%x " 432 "unencrypted_frame_err :%x " 433 "fcs_err :%x " 434 "reserved_31a :%x " 435 "decrypt_status_code :%x " 436 "rx_bitmap_not_updated :%x " 437 "reserved_31b :%x " 438 "msdu_done :%x", 439 msdu_end->ppdu_start_timestamp_63_32, 440 msdu_end->sw_phy_meta_data, 441 msdu_end->ppdu_start_timestamp_31_0, 442 msdu_end->toeplitz_hash_2_or_4, 443 msdu_end->reserved_28a, 444 msdu_end->sa_15_0, 445 msdu_end->sa_47_16, 446 msdu_end->first_mpdu, 447 msdu_end->reserved_30a, 448 msdu_end->mcast_bcast, 449 msdu_end->ast_index_not_found, 450 msdu_end->ast_index_timeout, 451 msdu_end->power_mgmt, 452 msdu_end->non_qos, 453 msdu_end->null_data, 454 msdu_end->mgmt_type, 455 msdu_end->ctrl_type, 456 msdu_end->more_data, 457 msdu_end->eosp, 458 msdu_end->a_msdu_error, 459 msdu_end->reserved_30b, 460 msdu_end->order, 461 msdu_end->wifi_parser_error, 462 msdu_end->overflow_err, 463 msdu_end->msdu_length_err, 464 msdu_end->tcp_udp_chksum_fail, 465 msdu_end->ip_chksum_fail, 466 msdu_end->sa_idx_invalid, 467 msdu_end->da_idx_invalid, 468 msdu_end->amsdu_addr_mismatch, 469 msdu_end->rx_in_tx_decrypt_byp, 470 msdu_end->encrypt_required, 471 msdu_end->directed, 472 msdu_end->buffer_fragment, 473 msdu_end->mpdu_length_err, 474 msdu_end->tkip_mic_err, 475 msdu_end->decrypt_err, 476 msdu_end->unencrypted_frame_err, 477 msdu_end->fcs_err, 478 msdu_end->reserved_31a, 479 msdu_end->decrypt_status_code, 480 msdu_end->rx_bitmap_not_updated, 481 msdu_end->reserved_31b, 482 msdu_end->msdu_done); 483 } 484 #else 485 static void hal_rx_dump_msdu_end_tlv_kiwi(void *msduend, 486 uint8_t dbg_level) 487 { 488 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 489 490 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 491 "rx_msdu_end tlv (1/7)- " 492 "rxpcu_mpdu_filter_in_category :%x" 493 "sw_frame_group_id :%x" 494 "reserved_0 :%x" 495 "phy_ppdu_id :%x" 496 "ip_hdr_chksum:%x" 497 "reported_mpdu_length :%x" 498 "reserved_1a :%x" 499 "key_id_octet :%x" 500 "cce_super_rule :%x" 501 "cce_classify_not_done_truncate :%x" 502 "cce_classify_not_done_cce_dis:%x" 503 "cumulative_l3_checksum :%x" 504 "rule_indication_31_0 :%x" 505 "rule_indication_63_32:%x" 506 "da_offset :%x" 507 "sa_offset :%x" 508 "da_offset_valid :%x" 509 "sa_offset_valid :%x" 510 "reserved_5a :%x" 511 "l3_type :%x", 512 msdu_end->rxpcu_mpdu_filter_in_category, 513 msdu_end->sw_frame_group_id, 514 msdu_end->reserved_0, 515 msdu_end->phy_ppdu_id, 516 msdu_end->ip_hdr_chksum, 517 msdu_end->reported_mpdu_length, 518 msdu_end->reserved_1a, 519 msdu_end->key_id_octet, 520 msdu_end->cce_super_rule, 521 msdu_end->cce_classify_not_done_truncate, 522 msdu_end->cce_classify_not_done_cce_dis, 523 msdu_end->cumulative_l3_checksum, 524 msdu_end->rule_indication_31_0, 525 msdu_end->rule_indication_63_32, 526 msdu_end->da_offset, 527 msdu_end->sa_offset, 528 msdu_end->da_offset_valid, 529 msdu_end->sa_offset_valid, 530 msdu_end->reserved_5a, 531 msdu_end->l3_type); 532 533 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 534 "rx_msdu_end tlv (2/7)- " 535 "ipv6_options_crc :%x" 536 "tcp_seq_number :%x" 537 "tcp_ack_number :%x" 538 "tcp_flag :%x" 539 "lro_eligible :%x" 540 "reserved_9a :%x" 541 "window_size :%x" 542 "tcp_udp_chksum :%x" 543 "sa_idx_timeout :%x" 544 "da_idx_timeout :%x" 545 "msdu_limit_error :%x" 546 "flow_idx_timeout :%x" 547 "flow_idx_invalid :%x" 548 "wifi_parser_error :%x" 549 "amsdu_parser_error :%x" 550 "sa_is_valid :%x" 551 "da_is_valid :%x" 552 "da_is_mcbc :%x" 553 "l3_header_padding :%x" 554 "first_msdu :%x" 555 "last_msdu :%x", 556 msdu_end->ipv6_options_crc, 557 msdu_end->tcp_seq_number, 558 msdu_end->tcp_ack_number, 559 msdu_end->tcp_flag, 560 msdu_end->lro_eligible, 561 msdu_end->reserved_9a, 562 msdu_end->window_size, 563 msdu_end->tcp_udp_chksum, 564 msdu_end->sa_idx_timeout, 565 msdu_end->da_idx_timeout, 566 msdu_end->msdu_limit_error, 567 msdu_end->flow_idx_timeout, 568 msdu_end->flow_idx_invalid, 569 msdu_end->wifi_parser_error, 570 msdu_end->amsdu_parser_error, 571 msdu_end->sa_is_valid, 572 msdu_end->da_is_valid, 573 msdu_end->da_is_mcbc, 574 msdu_end->l3_header_padding, 575 msdu_end->first_msdu, 576 msdu_end->last_msdu); 577 578 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 579 "rx_msdu_end tlv (3/7)" 580 "tcp_udp_chksum_fail_copy :%x" 581 "ip_chksum_fail_copy :%x" 582 "sa_idx :%x" 583 "da_idx_or_sw_peer_id :%x" 584 "msdu_drop :%x" 585 "reo_destination_indication :%x" 586 "flow_idx :%x" 587 "reserved_12a :%x" 588 "fse_metadata :%x" 589 "cce_metadata :%x" 590 "sa_sw_peer_id:%x" 591 "aggregation_count :%x" 592 "flow_aggregation_continuation:%x" 593 "fisa_timeout :%x" 594 "reserved_15a :%x" 595 "cumulative_l4_checksum :%x" 596 "cumulative_ip_length :%x" 597 "service_code :%x" 598 "priority_valid :%x", 599 msdu_end->tcp_udp_chksum_fail_copy, 600 msdu_end->ip_chksum_fail_copy, 601 msdu_end->sa_idx, 602 msdu_end->da_idx_or_sw_peer_id, 603 msdu_end->msdu_drop, 604 msdu_end->reo_destination_indication, 605 msdu_end->flow_idx, 606 msdu_end->reserved_12a, 607 msdu_end->fse_metadata, 608 msdu_end->cce_metadata, 609 msdu_end->sa_sw_peer_id, 610 msdu_end->aggregation_count, 611 msdu_end->flow_aggregation_continuation, 612 msdu_end->fisa_timeout, 613 msdu_end->reserved_15a, 614 msdu_end->cumulative_l4_checksum, 615 msdu_end->cumulative_ip_length, 616 msdu_end->service_code, 617 msdu_end->priority_valid); 618 619 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 620 "rx_msdu_end tlv (4/7)" 621 "reserved_17a :%x" 622 "msdu_length :%x" 623 "ipsec_esp :%x" 624 "l3_offset :%x" 625 "ipsec_ah :%x" 626 "l4_offset :%x" 627 "msdu_number :%x" 628 "decap_format :%x" 629 "ipv4_proto :%x" 630 "ipv6_proto :%x" 631 "tcp_proto :%x" 632 "udp_proto :%x" 633 "ip_frag :%x" 634 "tcp_only_ack :%x" 635 "da_is_bcast_mcast :%x" 636 "toeplitz_hash_sel :%x" 637 "ip_fixed_header_valid:%x" 638 "ip_extn_header_valid :%x" 639 "tcp_udp_header_valid :%x", 640 msdu_end->reserved_17a, 641 msdu_end->msdu_length, 642 msdu_end->ipsec_esp, 643 msdu_end->l3_offset, 644 msdu_end->ipsec_ah, 645 msdu_end->l4_offset, 646 msdu_end->msdu_number, 647 msdu_end->decap_format, 648 msdu_end->ipv4_proto, 649 msdu_end->ipv6_proto, 650 msdu_end->tcp_proto, 651 msdu_end->udp_proto, 652 msdu_end->ip_frag, 653 msdu_end->tcp_only_ack, 654 msdu_end->da_is_bcast_mcast, 655 msdu_end->toeplitz_hash_sel, 656 msdu_end->ip_fixed_header_valid, 657 msdu_end->ip_extn_header_valid, 658 msdu_end->tcp_udp_header_valid); 659 660 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 661 "rx_msdu_end tlv (5/7)" 662 "mesh_control_present :%x" 663 "ldpc :%x" 664 "ip4_protocol_ip6_next_header :%x" 665 "toeplitz_hash_2_or_4 :%x" 666 "flow_id_toeplitz :%x" 667 "user_rssi :%x" 668 "pkt_type :%x" 669 "stbc :%x" 670 "sgi :%x" 671 "rate_mcs :%x" 672 "receive_bandwidth :%x" 673 "reception_type :%x" 674 "mimo_ss_bitmap :%x" 675 "ppdu_start_timestamp_31_0 :%x" 676 "ppdu_start_timestamp_63_32 :%x" 677 "sw_phy_meta_data :%x" 678 "vlan_ctag_ci :%x" 679 "vlan_stag_ci :%x" 680 "first_mpdu :%x" 681 "reserved_30a :%x" 682 "mcast_bcast :%x", 683 msdu_end->mesh_control_present, 684 msdu_end->ldpc, 685 msdu_end->ip4_protocol_ip6_next_header, 686 msdu_end->toeplitz_hash_2_or_4, 687 msdu_end->flow_id_toeplitz, 688 msdu_end->user_rssi, 689 msdu_end->pkt_type, 690 msdu_end->stbc, 691 msdu_end->sgi, 692 msdu_end->rate_mcs, 693 msdu_end->receive_bandwidth, 694 msdu_end->reception_type, 695 msdu_end->mimo_ss_bitmap, 696 msdu_end->ppdu_start_timestamp_31_0, 697 msdu_end->ppdu_start_timestamp_63_32, 698 msdu_end->sw_phy_meta_data, 699 msdu_end->vlan_ctag_ci, 700 msdu_end->vlan_stag_ci, 701 msdu_end->first_mpdu, 702 msdu_end->reserved_30a, 703 msdu_end->mcast_bcast); 704 705 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 706 "rx_msdu_end tlv (6/7)" 707 "ast_index_not_found :%x" 708 "ast_index_timeout :%x" 709 "power_mgmt :%x" 710 "non_qos :%x" 711 "null_data :%x" 712 "mgmt_type :%x" 713 "ctrl_type :%x" 714 "more_data :%x" 715 "eosp :%x" 716 "a_msdu_error :%x" 717 "fragment_flag:%x" 718 "order:%x" 719 "cce_match :%x" 720 "overflow_err :%x" 721 "msdu_length_err :%x" 722 "tcp_udp_chksum_fail :%x" 723 "ip_chksum_fail :%x" 724 "sa_idx_invalid :%x" 725 "da_idx_invalid :%x" 726 "reserved_30b :%x", 727 msdu_end->ast_index_not_found, 728 msdu_end->ast_index_timeout, 729 msdu_end->power_mgmt, 730 msdu_end->non_qos, 731 msdu_end->null_data, 732 msdu_end->mgmt_type, 733 msdu_end->ctrl_type, 734 msdu_end->more_data, 735 msdu_end->eosp, 736 msdu_end->a_msdu_error, 737 msdu_end->fragment_flag, 738 msdu_end->order, 739 msdu_end->cce_match, 740 msdu_end->overflow_err, 741 msdu_end->msdu_length_err, 742 msdu_end->tcp_udp_chksum_fail, 743 msdu_end->ip_chksum_fail, 744 msdu_end->sa_idx_invalid, 745 msdu_end->da_idx_invalid, 746 msdu_end->reserved_30b); 747 748 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 749 "rx_msdu_end tlv (7/7)" 750 "rx_in_tx_decrypt_byp :%x" 751 "encrypt_required :%x" 752 "directed :%x" 753 "buffer_fragment :%x" 754 "mpdu_length_err :%x" 755 "tkip_mic_err :%x" 756 "decrypt_err :%x" 757 "unencrypted_frame_err:%x" 758 "fcs_err :%x" 759 "reserved_31a :%x" 760 "decrypt_status_code :%x" 761 "rx_bitmap_not_updated:%x" 762 "reserved_31b :%x" 763 "msdu_done :%x", 764 msdu_end->rx_in_tx_decrypt_byp, 765 msdu_end->encrypt_required, 766 msdu_end->directed, 767 msdu_end->buffer_fragment, 768 msdu_end->mpdu_length_err, 769 msdu_end->tkip_mic_err, 770 msdu_end->decrypt_err, 771 msdu_end->unencrypted_frame_err, 772 msdu_end->fcs_err, 773 msdu_end->reserved_31a, 774 msdu_end->decrypt_status_code, 775 msdu_end->rx_bitmap_not_updated, 776 msdu_end->reserved_31b, 777 msdu_end->msdu_done); 778 } 779 #endif 780 781 #ifdef NO_RX_PKT_HDR_TLV 782 static inline void hal_rx_dump_pkt_hdr_tlv_kiwi(struct rx_pkt_tlvs *pkt_tlvs, 783 uint8_t dbg_level) 784 { 785 } 786 787 static inline 788 void hal_register_rx_pkt_hdr_tlv_api_kiwi(struct hal_soc *hal_soc) 789 { 790 } 791 792 static uint8_t *hal_rx_desc_get_80211_hdr_be(void *hw_desc_addr) 793 { 794 uint8_t *rx_pkt_hdr; 795 struct rx_mon_pkt_tlvs *rx_desc = 796 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 797 798 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 799 800 return rx_pkt_hdr; 801 } 802 #else 803 static uint8_t *hal_rx_desc_get_80211_hdr_be(void *hw_desc_addr) 804 { 805 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 806 uint8_t *rx_pkt_hdr; 807 808 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 809 810 return rx_pkt_hdr; 811 } 812 813 /** 814 * hal_rx_dump_pkt_hdr_tlv_kiwi() - dump RX pkt header TLV in hex format 815 * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt. 816 * @dbg_level: log level. 817 * 818 * Return: void 819 */ 820 static inline void hal_rx_dump_pkt_hdr_tlv_kiwi(struct rx_pkt_tlvs *pkt_tlvs, 821 uint8_t dbg_level) 822 { 823 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 824 825 hal_verbose_debug("\n---------------\n" 826 "rx_pkt_hdr_tlv\n" 827 "---------------\n" 828 "phy_ppdu_id %lld ", 829 pkt_hdr_tlv->phy_ppdu_id); 830 831 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 832 sizeof(pkt_hdr_tlv->rx_pkt_hdr)); 833 } 834 835 /** 836 * hal_register_rx_pkt_hdr_tlv_api_kiwi: register all rx_pkt_hdr_tlv related api 837 * @hal_soc: HAL soc handler 838 * 839 * Return: none 840 */ 841 static inline 842 void hal_register_rx_pkt_hdr_tlv_api_kiwi(struct hal_soc *hal_soc) 843 { 844 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 845 hal_rx_pkt_tlv_offset_get_generic; 846 } 847 #endif 848 849 /** 850 * hal_rx_dump_mpdu_start_tlv_kiwi(): dump RX mpdu_start TLV in structured 851 * human readable format. 852 * @mpdustart: pointer the rx_attention TLV in pkt. 853 * @dbg_level: log level. 854 * 855 * Return: void 856 */ 857 static inline void hal_rx_dump_mpdu_start_tlv_kiwi(void *mpdustart, 858 uint8_t dbg_level) 859 { 860 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 861 struct rx_mpdu_info *mpdu_info = 862 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 863 864 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 865 "rx_mpdu_start tlv (1/5) - " 866 "rx_reo_queue_desc_addr_31_0 :%x" 867 "rx_reo_queue_desc_addr_39_32 :%x" 868 "receive_queue_number:%x " 869 "pre_delim_err_warning:%x " 870 "first_delim_err:%x " 871 "reserved_2a:%x " 872 "pn_31_0:%x " 873 "pn_63_32:%x " 874 "pn_95_64:%x " 875 "pn_127_96:%x " 876 "epd_en:%x " 877 "all_frames_shall_be_encrypted :%x" 878 "encrypt_type:%x " 879 "wep_key_width_for_variable_key :%x" 880 "bssid_hit:%x " 881 "bssid_number:%x " 882 "tid:%x " 883 "reserved_7a:%x " 884 "peer_meta_data:%x ", 885 mpdu_info->rx_reo_queue_desc_addr_31_0, 886 mpdu_info->rx_reo_queue_desc_addr_39_32, 887 mpdu_info->receive_queue_number, 888 mpdu_info->pre_delim_err_warning, 889 mpdu_info->first_delim_err, 890 mpdu_info->reserved_2a, 891 mpdu_info->pn_31_0, 892 mpdu_info->pn_63_32, 893 mpdu_info->pn_95_64, 894 mpdu_info->pn_127_96, 895 mpdu_info->epd_en, 896 mpdu_info->all_frames_shall_be_encrypted, 897 mpdu_info->encrypt_type, 898 mpdu_info->wep_key_width_for_variable_key, 899 mpdu_info->bssid_hit, 900 mpdu_info->bssid_number, 901 mpdu_info->tid, 902 mpdu_info->reserved_7a, 903 mpdu_info->peer_meta_data); 904 905 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 906 "rx_mpdu_start tlv (2/5) - " 907 "rxpcu_mpdu_filter_in_category :%x" 908 "sw_frame_group_id:%x " 909 "ndp_frame:%x " 910 "phy_err:%x " 911 "phy_err_during_mpdu_header :%x" 912 "protocol_version_err:%x " 913 "ast_based_lookup_valid:%x " 914 "reserved_9a:%x " 915 "phy_ppdu_id:%x " 916 "ast_index:%x " 917 "sw_peer_id:%x " 918 "mpdu_frame_control_valid:%x " 919 "mpdu_duration_valid:%x " 920 "mac_addr_ad1_valid:%x " 921 "mac_addr_ad2_valid:%x " 922 "mac_addr_ad3_valid:%x " 923 "mac_addr_ad4_valid:%x " 924 "mpdu_sequence_control_valid :%x" 925 "mpdu_qos_control_valid:%x " 926 "mpdu_ht_control_valid:%x " 927 "frame_encryption_info_valid :%x", 928 mpdu_info->rxpcu_mpdu_filter_in_category, 929 mpdu_info->sw_frame_group_id, 930 mpdu_info->ndp_frame, 931 mpdu_info->phy_err, 932 mpdu_info->phy_err_during_mpdu_header, 933 mpdu_info->protocol_version_err, 934 mpdu_info->ast_based_lookup_valid, 935 mpdu_info->reserved_9a, 936 mpdu_info->phy_ppdu_id, 937 mpdu_info->ast_index, 938 mpdu_info->sw_peer_id, 939 mpdu_info->mpdu_frame_control_valid, 940 mpdu_info->mpdu_duration_valid, 941 mpdu_info->mac_addr_ad1_valid, 942 mpdu_info->mac_addr_ad2_valid, 943 mpdu_info->mac_addr_ad3_valid, 944 mpdu_info->mac_addr_ad4_valid, 945 mpdu_info->mpdu_sequence_control_valid, 946 mpdu_info->mpdu_qos_control_valid, 947 mpdu_info->mpdu_ht_control_valid, 948 mpdu_info->frame_encryption_info_valid); 949 950 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 951 "rx_mpdu_start tlv (3/5) - " 952 "mpdu_fragment_number:%x " 953 "more_fragment_flag:%x " 954 "reserved_11a:%x " 955 "fr_ds:%x " 956 "to_ds:%x " 957 "encrypted:%x " 958 "mpdu_retry:%x " 959 "mpdu_sequence_number:%x " 960 "key_id_octet:%x " 961 "new_peer_entry:%x " 962 "decrypt_needed:%x " 963 "decap_type:%x " 964 "rx_insert_vlan_c_tag_padding :%x" 965 "rx_insert_vlan_s_tag_padding :%x" 966 "strip_vlan_c_tag_decap:%x " 967 "strip_vlan_s_tag_decap:%x " 968 "pre_delim_count:%x " 969 "ampdu_flag:%x " 970 "bar_frame:%x " 971 "raw_mpdu:%x " 972 "reserved_12:%x " 973 "mpdu_length:%x ", 974 mpdu_info->mpdu_fragment_number, 975 mpdu_info->more_fragment_flag, 976 mpdu_info->reserved_11a, 977 mpdu_info->fr_ds, 978 mpdu_info->to_ds, 979 mpdu_info->encrypted, 980 mpdu_info->mpdu_retry, 981 mpdu_info->mpdu_sequence_number, 982 mpdu_info->key_id_octet, 983 mpdu_info->new_peer_entry, 984 mpdu_info->decrypt_needed, 985 mpdu_info->decap_type, 986 mpdu_info->rx_insert_vlan_c_tag_padding, 987 mpdu_info->rx_insert_vlan_s_tag_padding, 988 mpdu_info->strip_vlan_c_tag_decap, 989 mpdu_info->strip_vlan_s_tag_decap, 990 mpdu_info->pre_delim_count, 991 mpdu_info->ampdu_flag, 992 mpdu_info->bar_frame, 993 mpdu_info->raw_mpdu, 994 mpdu_info->reserved_12, 995 mpdu_info->mpdu_length); 996 997 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 998 "rx_mpdu_start tlv (4/5) - " 999 "mpdu_length:%x " 1000 "first_mpdu:%x " 1001 "mcast_bcast:%x " 1002 "ast_index_not_found:%x " 1003 "ast_index_timeout:%x " 1004 "power_mgmt:%x " 1005 "non_qos:%x " 1006 "null_data:%x " 1007 "mgmt_type:%x " 1008 "ctrl_type:%x " 1009 "more_data:%x " 1010 "eosp:%x " 1011 "fragment_flag:%x " 1012 "order:%x " 1013 "u_apsd_trigger:%x " 1014 "encrypt_required:%x " 1015 "directed:%x " 1016 "amsdu_present:%x " 1017 "reserved_13:%x " 1018 "mpdu_frame_control_field:%x " 1019 "mpdu_duration_field:%x ", 1020 mpdu_info->mpdu_length, 1021 mpdu_info->first_mpdu, 1022 mpdu_info->mcast_bcast, 1023 mpdu_info->ast_index_not_found, 1024 mpdu_info->ast_index_timeout, 1025 mpdu_info->power_mgmt, 1026 mpdu_info->non_qos, 1027 mpdu_info->null_data, 1028 mpdu_info->mgmt_type, 1029 mpdu_info->ctrl_type, 1030 mpdu_info->more_data, 1031 mpdu_info->eosp, 1032 mpdu_info->fragment_flag, 1033 mpdu_info->order, 1034 mpdu_info->u_apsd_trigger, 1035 mpdu_info->encrypt_required, 1036 mpdu_info->directed, 1037 mpdu_info->amsdu_present, 1038 mpdu_info->reserved_13, 1039 mpdu_info->mpdu_frame_control_field, 1040 mpdu_info->mpdu_duration_field); 1041 1042 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 1043 "rx_mpdu_start tlv (5/5) - " 1044 "mac_addr_ad1_31_0:%x " 1045 "mac_addr_ad1_47_32:%x " 1046 "mac_addr_ad2_15_0:%x " 1047 "mac_addr_ad2_47_16:%x " 1048 "mac_addr_ad3_31_0:%x " 1049 "mac_addr_ad3_47_32:%x " 1050 "mpdu_sequence_control_field :%x" 1051 "mac_addr_ad4_31_0:%x " 1052 "mac_addr_ad4_47_32:%x " 1053 "mpdu_qos_control_field:%x " 1054 "mpdu_ht_control_field:%x " 1055 "vdev_id:%x " 1056 "service_code:%x " 1057 "priority_valid:%x " 1058 "reserved_23a:%x ", 1059 mpdu_info->mac_addr_ad1_31_0, 1060 mpdu_info->mac_addr_ad1_47_32, 1061 mpdu_info->mac_addr_ad2_15_0, 1062 mpdu_info->mac_addr_ad2_47_16, 1063 mpdu_info->mac_addr_ad3_31_0, 1064 mpdu_info->mac_addr_ad3_47_32, 1065 mpdu_info->mpdu_sequence_control_field, 1066 mpdu_info->mac_addr_ad4_31_0, 1067 mpdu_info->mac_addr_ad4_47_32, 1068 mpdu_info->mpdu_qos_control_field, 1069 mpdu_info->mpdu_ht_control_field, 1070 mpdu_info->vdev_id, 1071 mpdu_info->service_code, 1072 mpdu_info->priority_valid, 1073 mpdu_info->reserved_23a); 1074 } 1075 1076 /** 1077 * hal_rx_dump_pkt_tlvs_kiwi(): API to print RX Pkt TLVS for kiwi 1078 * @hal_soc_hdl: hal_soc handle 1079 * @buf: pointer the pkt buffer 1080 * @dbg_level: log level 1081 * 1082 * Return: void 1083 */ 1084 static void hal_rx_dump_pkt_tlvs_kiwi(hal_soc_handle_t hal_soc_hdl, 1085 uint8_t *buf, uint8_t dbg_level) 1086 { 1087 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1088 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1089 struct rx_mpdu_start *mpdu_start = 1090 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1091 1092 hal_rx_dump_msdu_end_tlv_kiwi(msdu_end, dbg_level); 1093 hal_rx_dump_mpdu_start_tlv_kiwi(mpdu_start, dbg_level); 1094 hal_rx_dump_pkt_hdr_tlv_kiwi(pkt_tlvs, dbg_level); 1095 } 1096 1097 /** 1098 * hal_rx_get_mpdu_flags_from_tlv() - Populate the local mpdu_flags elements 1099 * from the rx tlvs 1100 * @mpdu_info: buf address to rx_mpdu_info 1101 * 1102 * Return: mpdu_flags. 1103 */ 1104 static inline uint32_t 1105 hal_rx_get_mpdu_flags_from_tlv(struct rx_mpdu_info *mpdu_info) 1106 { 1107 uint32_t mpdu_flags = 0; 1108 1109 if (mpdu_info->fragment_flag) 1110 mpdu_flags |= HAL_MPDU_F_FRAGMENT; 1111 1112 if (mpdu_info->mpdu_retry) 1113 mpdu_flags |= HAL_MPDU_F_RETRY_BIT; 1114 1115 if (mpdu_info->ampdu_flag) 1116 mpdu_flags |= HAL_MPDU_F_AMPDU_FLAG; 1117 1118 if (mpdu_info->raw_mpdu) 1119 mpdu_flags |= HAL_MPDU_F_RAW_AMPDU; 1120 1121 if (mpdu_info->mpdu_qos_control_valid) 1122 mpdu_flags |= HAL_MPDU_F_QOS_CONTROL_VALID; 1123 1124 return mpdu_flags; 1125 } 1126 1127 /** 1128 * hal_rx_tlv_populate_mpdu_desc_info_kiwi() - Populate the local mpdu_desc_info 1129 * elements from the rx tlvs 1130 * @buf: start address of rx tlvs [Validated by caller] 1131 * @mpdu_desc_info_hdl: Buffer to populate the mpdu_dsc_info 1132 * [To be validated by caller] 1133 * 1134 * Return: None 1135 */ 1136 static void 1137 hal_rx_tlv_populate_mpdu_desc_info_kiwi(uint8_t *buf, 1138 void *mpdu_desc_info_hdl) 1139 { 1140 struct hal_rx_mpdu_desc_info *mpdu_desc_info = 1141 (struct hal_rx_mpdu_desc_info *)mpdu_desc_info_hdl; 1142 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1143 struct rx_mpdu_start *mpdu_start = 1144 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1145 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1146 1147 mpdu_desc_info->mpdu_seq = mpdu_info->mpdu_sequence_number; 1148 mpdu_desc_info->mpdu_flags = hal_rx_get_mpdu_flags_from_tlv(mpdu_info); 1149 mpdu_desc_info->peer_meta_data = mpdu_info->peer_meta_data; 1150 mpdu_desc_info->bar_frame = mpdu_info->bar_frame; 1151 } 1152 1153 /** 1154 * hal_reo_status_get_header_kiwi() - Process reo desc info 1155 * @ring_desc: Pointer to reo descriptor 1156 * @b: tlv type info 1157 * @h1: Pointer to hal_reo_status_header where info to be stored 1158 * 1159 * Return: none. 1160 * 1161 */ 1162 static void hal_reo_status_get_header_kiwi(hal_ring_desc_t ring_desc, int b, 1163 void *h1) 1164 { 1165 uint64_t *d = (uint64_t *)ring_desc; 1166 uint64_t val1 = 0; 1167 struct hal_reo_status_header *h = 1168 (struct hal_reo_status_header *)h1; 1169 1170 /* Offsets of descriptor fields defined in HW headers start 1171 * from the field after TLV header 1172 */ 1173 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr)); 1174 1175 switch (b) { 1176 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1177 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1178 STATUS_HEADER_REO_STATUS_NUMBER)]; 1179 break; 1180 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1181 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1182 STATUS_HEADER_REO_STATUS_NUMBER)]; 1183 break; 1184 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1185 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1186 STATUS_HEADER_REO_STATUS_NUMBER)]; 1187 break; 1188 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1189 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1190 STATUS_HEADER_REO_STATUS_NUMBER)]; 1191 break; 1192 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1193 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1194 STATUS_HEADER_REO_STATUS_NUMBER)]; 1195 break; 1196 case HAL_REO_DESC_THRES_STATUS_TLV: 1197 val1 = 1198 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1199 STATUS_HEADER_REO_STATUS_NUMBER)]; 1200 break; 1201 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1202 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1203 STATUS_HEADER_REO_STATUS_NUMBER)]; 1204 break; 1205 default: 1206 qdf_nofl_err("ERROR: Unknown tlv\n"); 1207 break; 1208 } 1209 h->cmd_num = 1210 HAL_GET_FIELD( 1211 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER, 1212 val1); 1213 h->exec_time = 1214 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1215 CMD_EXECUTION_TIME, val1); 1216 h->status = 1217 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1218 REO_CMD_EXECUTION_STATUS, val1); 1219 switch (b) { 1220 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1221 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1222 STATUS_HEADER_TIMESTAMP)]; 1223 break; 1224 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1225 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1226 STATUS_HEADER_TIMESTAMP)]; 1227 break; 1228 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1229 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1230 STATUS_HEADER_TIMESTAMP)]; 1231 break; 1232 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1233 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1234 STATUS_HEADER_TIMESTAMP)]; 1235 break; 1236 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1237 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1238 STATUS_HEADER_TIMESTAMP)]; 1239 break; 1240 case HAL_REO_DESC_THRES_STATUS_TLV: 1241 val1 = 1242 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1243 STATUS_HEADER_TIMESTAMP)]; 1244 break; 1245 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1246 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1247 STATUS_HEADER_TIMESTAMP)]; 1248 break; 1249 default: 1250 qdf_nofl_err("ERROR: Unknown tlv\n"); 1251 break; 1252 } 1253 h->tstamp = 1254 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1); 1255 } 1256 1257 static 1258 void *hal_rx_msdu0_buffer_addr_lsb_kiwi(void *link_desc_va) 1259 { 1260 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1261 } 1262 1263 static 1264 void *hal_rx_msdu_desc_info_ptr_get_kiwi(void *msdu0) 1265 { 1266 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1267 } 1268 1269 static 1270 void *hal_ent_mpdu_desc_info_kiwi(void *ent_ring_desc) 1271 { 1272 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1273 } 1274 1275 static 1276 void *hal_dst_mpdu_desc_info_kiwi(void *dst_ring_desc) 1277 { 1278 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1279 } 1280 1281 /** 1282 * hal_rx_get_tlv_kiwi() - API to get the tlv 1283 * @rx_tlv: TLV data extracted from the rx packet 1284 * 1285 * Return: uint8_t 1286 */ 1287 static uint8_t hal_rx_get_tlv_kiwi(void *rx_tlv) 1288 { 1289 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH); 1290 } 1291 1292 /** 1293 * hal_rx_proc_phyrx_other_receive_info_tlv_kiwi() 1294 * - process other receive info TLV 1295 * @rx_tlv_hdr: pointer to TLV header 1296 * @ppdu_info_handle: pointer to ppdu_info 1297 * 1298 * Return: None 1299 */ 1300 static 1301 void hal_rx_proc_phyrx_other_receive_info_tlv_kiwi(void *rx_tlv_hdr, 1302 void *ppdu_info_handle) 1303 { 1304 uint32_t tlv_tag, tlv_len; 1305 uint32_t temp_len, other_tlv_len, other_tlv_tag; 1306 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 1307 void *other_tlv_hdr = NULL; 1308 void *other_tlv = NULL; 1309 1310 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 1311 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 1312 temp_len = 0; 1313 1314 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 1315 1316 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 1317 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 1318 temp_len += other_tlv_len; 1319 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 1320 1321 switch (other_tlv_tag) { 1322 default: 1323 hal_err_rl("unhandled TLV type: %d, TLV len:%d", 1324 other_tlv_tag, other_tlv_len); 1325 break; 1326 } 1327 } 1328 1329 /** 1330 * hal_reo_config_kiwi(): Set reo config parameters 1331 * @soc: hal soc handle 1332 * @reg_val: value to be set 1333 * @reo_params: reo parameters 1334 * 1335 * Return: void 1336 */ 1337 static 1338 void hal_reo_config_kiwi(struct hal_soc *soc, 1339 uint32_t reg_val, 1340 struct hal_reo_params *reo_params) 1341 { 1342 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1343 } 1344 1345 /** 1346 * hal_rx_msdu_desc_info_get_ptr_kiwi() - Get msdu desc info ptr 1347 * @msdu_details_ptr: Pointer to msdu_details_ptr 1348 * 1349 * Return: Pointer to rx_msdu_desc_info structure. 1350 * 1351 */ 1352 static void *hal_rx_msdu_desc_info_get_ptr_kiwi(void *msdu_details_ptr) 1353 { 1354 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1355 } 1356 1357 /** 1358 * hal_rx_link_desc_msdu0_ptr_kiwi() - Get pointer to rx_msdu details 1359 * @link_desc: Pointer to link desc 1360 * 1361 * Return: Pointer to rx_msdu_details structure 1362 * 1363 */ 1364 static void *hal_rx_link_desc_msdu0_ptr_kiwi(void *link_desc) 1365 { 1366 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1367 } 1368 1369 /** 1370 * hal_get_window_address_kiwi(): Function to get hp/tp address 1371 * @hal_soc: Pointer to hal_soc 1372 * @addr: address offset of register 1373 * 1374 * Return: modified address offset of register 1375 */ 1376 static inline qdf_iomem_t hal_get_window_address_kiwi(struct hal_soc *hal_soc, 1377 qdf_iomem_t addr) 1378 { 1379 return addr; 1380 } 1381 1382 /** 1383 * hal_reo_set_err_dst_remap_kiwi(): Function to set REO error destination 1384 * ring remap register 1385 * @hal_soc: Pointer to hal_soc 1386 * 1387 * Return: none. 1388 */ 1389 static void 1390 hal_reo_set_err_dst_remap_kiwi(void *hal_soc) 1391 { 1392 /* 1393 * Set REO error 2k jump (error code 5) / OOR (error code 7) 1394 * frame routed to REO2SW0 ring. 1395 */ 1396 uint32_t dst_remap_ix0 = 1397 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 0) | 1398 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 1) | 1399 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 2) | 1400 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 3) | 1401 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 4) | 1402 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) | 1403 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) | 1404 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7); 1405 1406 uint32_t dst_remap_ix1 = 1407 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 14) | 1408 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 13) | 1409 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 12) | 1410 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 11) | 1411 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 10) | 1412 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 9) | 1413 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 8); 1414 1415 HAL_REG_WRITE(hal_soc, 1416 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1417 REO_REG_REG_BASE), 1418 dst_remap_ix0); 1419 1420 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x", 1421 HAL_REG_READ( 1422 hal_soc, 1423 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1424 REO_REG_REG_BASE))); 1425 1426 HAL_REG_WRITE(hal_soc, 1427 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1428 REO_REG_REG_BASE), 1429 dst_remap_ix1); 1430 1431 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1 0x%x", 1432 HAL_REG_READ( 1433 hal_soc, 1434 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1435 REO_REG_REG_BASE))); 1436 } 1437 1438 /** 1439 * hal_reo_enable_pn_in_dest_kiwi() - Set the REO register to enable previous PN 1440 * for OOR and 2K-jump frames 1441 * @hal_soc: HAL SoC handle 1442 * 1443 * Return: 1, since the register is set. 1444 */ 1445 static uint8_t hal_reo_enable_pn_in_dest_kiwi(void *hal_soc) 1446 { 1447 HAL_REG_WRITE(hal_soc, HWIO_REO_R0_PN_IN_DEST_ADDR(REO_REG_REG_BASE), 1448 1); 1449 return 1; 1450 } 1451 1452 /** 1453 * hal_rx_flow_setup_fse_kiwi() - Setup a flow search entry in HW FST 1454 * @rx_fst: Pointer to the Rx Flow Search Table 1455 * @table_offset: offset into the table where the flow is to be setup 1456 * @rx_flow: Flow Parameters 1457 * 1458 * Flow table entry fields are updated in host byte order, little endian order. 1459 * 1460 * Return: Success/Failure 1461 */ 1462 static void * 1463 hal_rx_flow_setup_fse_kiwi(uint8_t *rx_fst, uint32_t table_offset, 1464 uint8_t *rx_flow) 1465 { 1466 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1467 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1468 uint8_t *fse; 1469 bool fse_valid; 1470 1471 if (table_offset >= fst->max_entries) { 1472 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1473 "HAL FSE table offset %u exceeds max entries %u", 1474 table_offset, fst->max_entries); 1475 return NULL; 1476 } 1477 1478 fse = (uint8_t *)fst->base_vaddr + 1479 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1480 1481 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1482 1483 if (fse_valid) { 1484 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1485 "HAL FSE %pK already valid", fse); 1486 return NULL; 1487 } 1488 1489 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) = 1490 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1491 (flow->tuple_info.src_ip_127_96)); 1492 1493 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) = 1494 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1495 (flow->tuple_info.src_ip_95_64)); 1496 1497 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) = 1498 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1499 (flow->tuple_info.src_ip_63_32)); 1500 1501 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) = 1502 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1503 (flow->tuple_info.src_ip_31_0)); 1504 1505 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) = 1506 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1507 (flow->tuple_info.dest_ip_127_96)); 1508 1509 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) = 1510 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1511 (flow->tuple_info.dest_ip_95_64)); 1512 1513 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) = 1514 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1515 (flow->tuple_info.dest_ip_63_32)); 1516 1517 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) = 1518 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1519 (flow->tuple_info.dest_ip_31_0)); 1520 1521 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT); 1522 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |= 1523 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1524 (flow->tuple_info.dest_port)); 1525 1526 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT); 1527 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |= 1528 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1529 (flow->tuple_info.src_port)); 1530 1531 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL); 1532 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |= 1533 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1534 flow->tuple_info.l4_protocol); 1535 1536 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER); 1537 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |= 1538 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1539 flow->reo_destination_handler); 1540 1541 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1542 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |= 1543 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1544 1545 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA); 1546 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) = 1547 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1548 (flow->fse_metadata)); 1549 1550 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION); 1551 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |= 1552 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1553 REO_DESTINATION_INDICATION, 1554 flow->reo_destination_indication); 1555 1556 /* Reset all the other fields in FSE */ 1557 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9); 1558 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP); 1559 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT); 1560 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT); 1561 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP); 1562 1563 return fse; 1564 } 1565 1566 /** 1567 * hal_rx_flow_setup_cmem_fse_kiwi() - Setup a flow search entry in HW CMEM FST 1568 * @hal_soc: hal_soc reference 1569 * @cmem_ba: CMEM base address 1570 * @table_offset: offset into the table where the flow is to be setup 1571 * @rx_flow: Flow Parameters 1572 * 1573 * Return: Success/Failure 1574 */ 1575 static uint32_t 1576 hal_rx_flow_setup_cmem_fse_kiwi(struct hal_soc *hal_soc, uint32_t cmem_ba, 1577 uint32_t table_offset, uint8_t *rx_flow) 1578 { 1579 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1580 uint32_t fse_offset; 1581 uint32_t value; 1582 1583 fse_offset = cmem_ba + (table_offset * HAL_RX_FST_ENTRY_SIZE); 1584 1585 /* Reset the Valid bit */ 1586 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1587 VALID), 0); 1588 1589 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1590 (flow->tuple_info.src_ip_127_96)); 1591 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1592 SRC_IP_127_96), value); 1593 1594 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1595 (flow->tuple_info.src_ip_95_64)); 1596 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1597 SRC_IP_95_64), value); 1598 1599 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1600 (flow->tuple_info.src_ip_63_32)); 1601 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1602 SRC_IP_63_32), value); 1603 1604 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1605 (flow->tuple_info.src_ip_31_0)); 1606 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1607 SRC_IP_31_0), value); 1608 1609 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1610 (flow->tuple_info.dest_ip_127_96)); 1611 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1612 DEST_IP_127_96), value); 1613 1614 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1615 (flow->tuple_info.dest_ip_95_64)); 1616 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1617 DEST_IP_95_64), value); 1618 1619 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1620 (flow->tuple_info.dest_ip_63_32)); 1621 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1622 DEST_IP_63_32), value); 1623 1624 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1625 (flow->tuple_info.dest_ip_31_0)); 1626 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1627 DEST_IP_31_0), value); 1628 1629 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1630 (flow->tuple_info.dest_port)); 1631 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1632 (flow->tuple_info.src_port)); 1633 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1634 SRC_PORT), value); 1635 1636 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1637 (flow->fse_metadata)); 1638 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1639 METADATA), value); 1640 1641 /* Reset all the other fields in FSE */ 1642 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1643 MSDU_COUNT), 0); 1644 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1645 MSDU_BYTE_COUNT), 0); 1646 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1647 TIMESTAMP), 0); 1648 1649 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1650 flow->tuple_info.l4_protocol); 1651 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1652 flow->reo_destination_handler); 1653 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1654 REO_DESTINATION_INDICATION, 1655 flow->reo_destination_indication); 1656 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1657 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1658 L4_PROTOCOL), value); 1659 1660 return fse_offset; 1661 } 1662 1663 /** 1664 * hal_rx_flow_get_cmem_fse_ts_kiwi() - Get timestamp field from CMEM FSE 1665 * @hal_soc: hal_soc reference 1666 * @fse_offset: CMEM FSE offset 1667 * 1668 * Return: Timestamp 1669 */ 1670 static uint32_t hal_rx_flow_get_cmem_fse_ts_kiwi(struct hal_soc *hal_soc, 1671 uint32_t fse_offset) 1672 { 1673 return HAL_CMEM_READ(hal_soc, fse_offset + 1674 HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, TIMESTAMP)); 1675 } 1676 1677 /** 1678 * hal_rx_flow_get_cmem_fse_kiwi() - Get FSE from CMEM 1679 * @hal_soc: hal_soc reference 1680 * @fse_offset: CMEM FSE offset 1681 * @fse: reference where FSE will be copied 1682 * @len: length of FSE 1683 * 1684 * Return: If read is successful or not 1685 */ 1686 static void 1687 hal_rx_flow_get_cmem_fse_kiwi(struct hal_soc *hal_soc, uint32_t fse_offset, 1688 uint32_t *fse, qdf_size_t len) 1689 { 1690 int i; 1691 1692 if (len != HAL_RX_FST_ENTRY_SIZE) 1693 return; 1694 1695 for (i = 0; i < NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY; i++) 1696 fse[i] = HAL_CMEM_READ(hal_soc, fse_offset + i * 4); 1697 } 1698 1699 static 1700 void hal_compute_reo_remap_ix2_ix3_kiwi(uint32_t *ring_map, 1701 uint32_t num_rings, uint32_t *remap1, 1702 uint32_t *remap2) 1703 { 1704 1705 switch (num_rings) { 1706 /* should we have all the different possible ring configs */ 1707 default: 1708 case 3: 1709 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1710 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1711 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1712 HAL_REO_REMAP_IX2(ring_map[0], 19) | 1713 HAL_REO_REMAP_IX2(ring_map[1], 20) | 1714 HAL_REO_REMAP_IX2(ring_map[2], 21) | 1715 HAL_REO_REMAP_IX2(ring_map[0], 22) | 1716 HAL_REO_REMAP_IX2(ring_map[1], 23); 1717 1718 *remap2 = HAL_REO_REMAP_IX3(ring_map[2], 24) | 1719 HAL_REO_REMAP_IX3(ring_map[0], 25) | 1720 HAL_REO_REMAP_IX3(ring_map[1], 26) | 1721 HAL_REO_REMAP_IX3(ring_map[2], 27) | 1722 HAL_REO_REMAP_IX3(ring_map[0], 28) | 1723 HAL_REO_REMAP_IX3(ring_map[1], 29) | 1724 HAL_REO_REMAP_IX3(ring_map[2], 30) | 1725 HAL_REO_REMAP_IX3(ring_map[0], 31); 1726 break; 1727 case 4: 1728 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1729 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1730 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1731 HAL_REO_REMAP_IX2(ring_map[3], 19) | 1732 HAL_REO_REMAP_IX2(ring_map[0], 20) | 1733 HAL_REO_REMAP_IX2(ring_map[1], 21) | 1734 HAL_REO_REMAP_IX2(ring_map[2], 22) | 1735 HAL_REO_REMAP_IX2(ring_map[3], 23); 1736 1737 *remap2 = HAL_REO_REMAP_IX3(ring_map[0], 24) | 1738 HAL_REO_REMAP_IX3(ring_map[1], 25) | 1739 HAL_REO_REMAP_IX3(ring_map[2], 26) | 1740 HAL_REO_REMAP_IX3(ring_map[3], 27) | 1741 HAL_REO_REMAP_IX3(ring_map[0], 28) | 1742 HAL_REO_REMAP_IX3(ring_map[1], 29) | 1743 HAL_REO_REMAP_IX3(ring_map[2], 30) | 1744 HAL_REO_REMAP_IX3(ring_map[3], 31); 1745 break; 1746 case 6: 1747 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1748 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1749 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1750 HAL_REO_REMAP_IX2(ring_map[3], 19) | 1751 HAL_REO_REMAP_IX2(ring_map[4], 20) | 1752 HAL_REO_REMAP_IX2(ring_map[5], 21) | 1753 HAL_REO_REMAP_IX2(ring_map[0], 22) | 1754 HAL_REO_REMAP_IX2(ring_map[1], 23); 1755 1756 *remap2 = HAL_REO_REMAP_IX3(ring_map[2], 24) | 1757 HAL_REO_REMAP_IX3(ring_map[3], 25) | 1758 HAL_REO_REMAP_IX3(ring_map[4], 26) | 1759 HAL_REO_REMAP_IX3(ring_map[5], 27) | 1760 HAL_REO_REMAP_IX3(ring_map[0], 28) | 1761 HAL_REO_REMAP_IX3(ring_map[1], 29) | 1762 HAL_REO_REMAP_IX3(ring_map[2], 30) | 1763 HAL_REO_REMAP_IX3(ring_map[3], 31); 1764 break; 1765 case 8: 1766 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1767 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1768 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1769 HAL_REO_REMAP_IX2(ring_map[3], 19) | 1770 HAL_REO_REMAP_IX2(ring_map[4], 20) | 1771 HAL_REO_REMAP_IX2(ring_map[5], 21) | 1772 HAL_REO_REMAP_IX2(ring_map[6], 22) | 1773 HAL_REO_REMAP_IX2(ring_map[7], 23); 1774 1775 *remap2 = HAL_REO_REMAP_IX3(ring_map[0], 24) | 1776 HAL_REO_REMAP_IX3(ring_map[1], 25) | 1777 HAL_REO_REMAP_IX3(ring_map[2], 26) | 1778 HAL_REO_REMAP_IX3(ring_map[3], 27) | 1779 HAL_REO_REMAP_IX3(ring_map[4], 28) | 1780 HAL_REO_REMAP_IX3(ring_map[5], 29) | 1781 HAL_REO_REMAP_IX3(ring_map[6], 30) | 1782 HAL_REO_REMAP_IX3(ring_map[7], 31); 1783 break; 1784 } 1785 } 1786 1787 /* NUM TCL Bank registers in KIWI */ 1788 #define HAL_NUM_TCL_BANKS_KIWI 8 1789 1790 /** 1791 * hal_tx_get_num_tcl_banks_kiwi() - Get number of banks in target 1792 * 1793 * Returns: number of bank 1794 */ 1795 static uint8_t hal_tx_get_num_tcl_banks_kiwi(void) 1796 { 1797 return HAL_NUM_TCL_BANKS_KIWI; 1798 } 1799 1800 /** 1801 * hal_rx_reo_prev_pn_get_kiwi() - Get the previous PN from the REO ring desc. 1802 * @ring_desc: REO ring descriptor [To be validated by caller ] 1803 * @prev_pn: Buffer where the previous PN is to be populated. 1804 * [To be validated by caller] 1805 * 1806 * Return: None 1807 */ 1808 static void hal_rx_reo_prev_pn_get_kiwi(void *ring_desc, 1809 uint64_t *prev_pn) 1810 { 1811 struct reo_destination_ring_with_pn *reo_desc = 1812 (struct reo_destination_ring_with_pn *)ring_desc; 1813 1814 *prev_pn = reo_desc->prev_pn_23_0; 1815 *prev_pn |= ((uint64_t)reo_desc->prev_pn_55_24 << 24); 1816 } 1817 1818 /** 1819 * hal_cmem_write_kiwi() - function for CMEM buffer writing 1820 * @hal_soc_hdl: HAL SOC handle 1821 * @offset: CMEM address 1822 * @value: value to write 1823 * 1824 * Return: None. 1825 */ 1826 static inline void hal_cmem_write_kiwi(hal_soc_handle_t hal_soc_hdl, 1827 uint32_t offset, 1828 uint32_t value) 1829 { 1830 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1831 1832 hal_write32_mb(hal, offset, value); 1833 } 1834 1835 /** 1836 * hal_get_idle_link_bm_id_kiwi() - Get idle link BM id from chid_id 1837 * @chip_id: mlo chip_id 1838 * 1839 * Returns: RBM ID 1840 */ 1841 static uint8_t hal_get_idle_link_bm_id_kiwi(uint8_t chip_id) 1842 { 1843 return WBM_IDLE_DESC_LIST; 1844 } 1845 1846 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1847 /** 1848 * hal_get_first_wow_wakeup_packet_kiwi(): Function to get if the buffer 1849 * is the first one that wakes up host from WoW. 1850 * 1851 * @buf: network buffer 1852 * 1853 * Dummy function for KIWI 1854 * 1855 * Returns: 1 to indicate it is first packet received that wakes up host from 1856 * WoW. Otherwise 0 1857 */ 1858 static inline uint8_t hal_get_first_wow_wakeup_packet_kiwi(uint8_t *buf) 1859 { 1860 return 0; 1861 } 1862 #endif 1863 1864 static uint16_t hal_get_rx_max_ba_window_kiwi(int tid) 1865 { 1866 return HAL_RX_BA_WINDOW_1024; 1867 } 1868 1869 /** 1870 * hal_get_reo_qdesc_size_kiwi()- Get the reo queue descriptor size 1871 * from the give Block-Ack window size 1872 * @ba_window_size: Block-Ack window size 1873 * @tid: TID 1874 * 1875 * Return: reo queue descriptor size 1876 */ 1877 static uint32_t hal_get_reo_qdesc_size_kiwi(uint32_t ba_window_size, int tid) 1878 { 1879 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 1880 * NON_QOS_TID until HW issues are resolved. 1881 */ 1882 if (tid != HAL_NON_QOS_TID) 1883 ba_window_size = hal_get_rx_max_ba_window_kiwi(tid); 1884 1885 /* Return descriptor size corresponding to window size of 2 since 1886 * we set ba_window_size to 2 while setting up REO descriptors as 1887 * a WAR to get 2k jump exception aggregates are received without 1888 * a BA session. 1889 */ 1890 if (ba_window_size <= 1) { 1891 if (tid != HAL_NON_QOS_TID) 1892 return sizeof(struct rx_reo_queue) + 1893 sizeof(struct rx_reo_queue_ext); 1894 else 1895 return sizeof(struct rx_reo_queue); 1896 } 1897 1898 if (ba_window_size <= 105) 1899 return sizeof(struct rx_reo_queue) + 1900 sizeof(struct rx_reo_queue_ext); 1901 1902 if (ba_window_size <= 210) 1903 return sizeof(struct rx_reo_queue) + 1904 (2 * sizeof(struct rx_reo_queue_ext)); 1905 1906 if (ba_window_size <= 256) 1907 return sizeof(struct rx_reo_queue) + 1908 (3 * sizeof(struct rx_reo_queue_ext)); 1909 1910 return sizeof(struct rx_reo_queue) + 1911 (10 * sizeof(struct rx_reo_queue_ext)) + 1912 sizeof(struct rx_reo_queue_1k); 1913 } 1914 1915 #ifdef QCA_GET_TSF_VIA_REG 1916 static inline uint32_t 1917 hal_tsf_read_scratch_reg(struct hal_soc *soc, 1918 enum hal_scratch_reg_enum reg_enum) 1919 { 1920 return hal_read32_mb(soc, PMM_REG_BASE + (reg_enum * 4)); 1921 } 1922 1923 static inline 1924 uint64_t hal_tsf_get_fw_time(struct hal_soc *soc) 1925 { 1926 uint64_t fw_time_low; 1927 uint64_t fw_time_high; 1928 1929 fw_time_low = hal_read32_mb(soc, PCIE_PCIE_MHI_TIME_LOW); 1930 fw_time_high = hal_read32_mb(soc, PCIE_PCIE_MHI_TIME_HIGH); 1931 return (fw_time_high << 32 | fw_time_low); 1932 } 1933 1934 static inline 1935 uint64_t hal_fw_qtime_to_usecs(uint64_t time) 1936 { 1937 /* 1938 * Try to preserve precision by multiplying by 10 first. 1939 * If that would cause a wrap around, divide first instead. 1940 */ 1941 if (time * 10 < time) { 1942 time = qdf_do_div(time, FW_QTIME_CYCLES_PER_10_USEC); 1943 return time * 10; 1944 } 1945 1946 time = time * 10; 1947 time = qdf_do_div(time, FW_QTIME_CYCLES_PER_10_USEC); 1948 1949 return time; 1950 } 1951 1952 /** 1953 * hal_get_tsf_time_kiwi() - Get tsf time from scratch register 1954 * @hal_soc_hdl: HAL soc handle 1955 * @tsf_id: TSF id 1956 * @mac_id: mac_id 1957 * @tsf: pointer to update tsf value 1958 * @tsf_sync_soc_time: pointer to update tsf sync time 1959 * 1960 * Return: None. 1961 */ 1962 static void 1963 hal_get_tsf_time_kiwi(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id, 1964 uint32_t mac_id, uint64_t *tsf, 1965 uint64_t *tsf_sync_soc_time) 1966 { 1967 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 1968 uint64_t global_time_low_offset, global_time_high_offset; 1969 uint64_t tsf_offset_low, tsf_offset_hi; 1970 uint64_t fw_time, global_time, sync_time; 1971 enum hal_scratch_reg_enum tsf_enum_low, tsf_enum_high; 1972 1973 if (hif_force_wake_request(soc->hif_handle)) 1974 return; 1975 1976 hal_get_tsf_enum(tsf_id, mac_id, &tsf_enum_low, &tsf_enum_high); 1977 sync_time = qdf_get_log_timestamp(); 1978 fw_time = hal_tsf_get_fw_time(soc); 1979 1980 global_time_low_offset = 1981 hal_tsf_read_scratch_reg(soc, PMM_QTIMER_GLOBAL_OFFSET_LO_US); 1982 global_time_high_offset = 1983 hal_tsf_read_scratch_reg(soc, PMM_QTIMER_GLOBAL_OFFSET_HI_US); 1984 1985 tsf_offset_low = hal_tsf_read_scratch_reg(soc, tsf_enum_low); 1986 tsf_offset_hi = hal_tsf_read_scratch_reg(soc, tsf_enum_high); 1987 1988 fw_time = hal_fw_qtime_to_usecs(fw_time); 1989 global_time = fw_time + 1990 (global_time_low_offset | 1991 (global_time_high_offset << 32)); 1992 1993 *tsf = global_time + (tsf_offset_low | (tsf_offset_hi << 32)); 1994 *tsf_sync_soc_time = qdf_log_timestamp_to_usecs(sync_time); 1995 1996 hif_force_wake_release(soc->hif_handle); 1997 } 1998 #else 1999 static inline void 2000 hal_get_tsf_time_kiwi(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id, 2001 uint32_t mac_id, uint64_t *tsf, 2002 uint64_t *tsf_sync_soc_time) 2003 { 2004 } 2005 #endif 2006 2007 static QDF_STATUS hal_rx_reo_ent_get_src_link_id_kiwi(hal_rxdma_desc_t rx_desc, 2008 uint8_t *src_link_id) 2009 { 2010 struct reo_entrance_ring *reo_ent_desc = 2011 (struct reo_entrance_ring *)rx_desc; 2012 2013 *src_link_id = reo_ent_desc->src_link_id; 2014 2015 return QDF_STATUS_SUCCESS; 2016 } 2017 2018 /** 2019 * hal_rx_en_mcast_fp_data_filter_kiwi() - Is mcast filter pass enabled 2020 * 2021 * Return: false for BE MCC 2022 */ 2023 static inline 2024 bool hal_rx_en_mcast_fp_data_filter_kiwi(void) 2025 { 2026 return false; 2027 } 2028 2029 #ifdef QCA_WIFI_KIWI_V2 2030 /** 2031 * hal_srng_dst_hw_init_misc_1_kiwi() - Function to initialize MISC_1 register 2032 * of destination ring HW 2033 * @srng: SRNG ring pointer 2034 * 2035 * Return: None 2036 */ 2037 static inline 2038 void hal_srng_dst_hw_init_misc_1_kiwi(struct hal_srng *srng) 2039 { 2040 uint32_t reg_val = 0; 2041 2042 /* number threshold for pointer update */ 2043 if (srng->pointer_num_threshold) 2044 reg_val |= SRNG_SM(SRNG_DST_HW_FLD(MISC_1, 2045 NUM_THRESHOLD_TO_UPDATE), 2046 srng->pointer_num_threshold); 2047 /* timer threshold for pointer update */ 2048 if (srng->pointer_timer_threshold) 2049 reg_val |= SRNG_SM(SRNG_DST_HW_FLD(MISC_1, 2050 TIME_THRESHOLD_TO_UPDATE), 2051 srng->pointer_timer_threshold); 2052 2053 if (reg_val) 2054 SRNG_DST_REG_WRITE(srng, MISC_1, reg_val); 2055 } 2056 2057 /** 2058 * hal_srng_hw_reg_offset_init_misc_1_kiwi() - Initialize the HW srng register 2059 * offset of MISC_1 2060 * @hal_soc: HAL Soc handle 2061 * 2062 * Return: None 2063 */ 2064 static inline 2065 void hal_srng_hw_reg_offset_init_misc_1_kiwi(struct hal_soc *hal_soc) 2066 { 2067 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 2068 2069 hw_reg_offset[DST_MISC_1] = REG_OFFSET(DST, MISC_1); 2070 } 2071 #else 2072 static inline 2073 void hal_srng_dst_hw_init_misc_1_kiwi(struct hal_srng *srng) 2074 { 2075 } 2076 2077 static inline 2078 void hal_srng_hw_reg_offset_init_misc_1_kiwi(struct hal_soc *hal_soc) 2079 { 2080 } 2081 #endif 2082 2083 /** 2084 * hal_srng_dst_hw_init_kiwi() - Function to initialize SRNG 2085 * destination ring HW 2086 * @hal_soc: HAL SOC handle 2087 * @srng: SRNG ring pointer 2088 * @idle_check: Check if ring is idle 2089 * @idx: Ring index 2090 * 2091 * Return: None 2092 */ 2093 static inline 2094 void hal_srng_dst_hw_init_kiwi(struct hal_soc *hal_soc, 2095 struct hal_srng *srng, 2096 bool idle_check, 2097 uint32_t idx) 2098 { 2099 hal_srng_dst_hw_init_misc_1_kiwi(srng); 2100 2101 hal_srng_dst_hw_init_generic(hal_soc, srng, idle_check, idx); 2102 } 2103 2104 static void hal_hw_txrx_ops_attach_kiwi(struct hal_soc *hal_soc) 2105 { 2106 /* init and setup */ 2107 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_kiwi; 2108 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 2109 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 2110 hal_soc->ops->hal_get_window_address = hal_get_window_address_kiwi; 2111 hal_soc->ops->hal_reo_set_err_dst_remap = 2112 hal_reo_set_err_dst_remap_kiwi; 2113 hal_soc->ops->hal_reo_enable_pn_in_dest = 2114 hal_reo_enable_pn_in_dest_kiwi; 2115 /* Overwrite the default BE ops */ 2116 hal_soc->ops->hal_get_rx_max_ba_window = hal_get_rx_max_ba_window_kiwi; 2117 hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_kiwi; 2118 2119 /* tx */ 2120 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_kiwi; 2121 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_kiwi; 2122 hal_soc->ops->hal_tx_comp_get_status = 2123 hal_tx_comp_get_status_generic_be; 2124 hal_soc->ops->hal_tx_init_cmd_credit_ring = 2125 hal_tx_init_cmd_credit_ring_kiwi; 2126 hal_soc->ops->hal_tx_config_rbm_mapping_be = 2127 hal_tx_config_rbm_mapping_be_kiwi; 2128 2129 /* rx */ 2130 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; 2131 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 2132 hal_rx_mon_hw_desc_get_mpdu_status_be; 2133 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_kiwi; 2134 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be; 2135 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 2136 hal_rx_proc_phyrx_other_receive_info_tlv_kiwi; 2137 2138 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_kiwi; 2139 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 2140 hal_rx_dump_mpdu_start_tlv_kiwi; 2141 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_kiwi; 2142 hal_soc->ops->hal_rx_desc_get_80211_hdr = hal_rx_desc_get_80211_hdr_be; 2143 2144 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_kiwi; 2145 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be; 2146 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 2147 hal_rx_tlv_reception_type_get_be; 2148 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 2149 hal_rx_msdu_end_da_idx_get_be; 2150 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 2151 hal_rx_msdu_desc_info_get_ptr_kiwi; 2152 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 2153 hal_rx_link_desc_msdu0_ptr_kiwi; 2154 hal_soc->ops->hal_reo_status_get_header = 2155 hal_reo_status_get_header_kiwi; 2156 hal_soc->ops->hal_rx_status_get_tlv_info = 2157 hal_rx_status_get_tlv_info_wrapper_be; 2158 hal_soc->ops->hal_rx_wbm_err_info_get = 2159 hal_rx_wbm_err_info_get_generic_be; 2160 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 2161 hal_rx_priv_info_set_in_tlv_be; 2162 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 2163 hal_rx_priv_info_get_from_tlv_be; 2164 2165 hal_soc->ops->hal_tx_set_pcp_tid_map = 2166 hal_tx_set_pcp_tid_map_generic_be; 2167 hal_soc->ops->hal_tx_update_pcp_tid_map = 2168 hal_tx_update_pcp_tid_generic_be; 2169 hal_soc->ops->hal_tx_set_tidmap_prty = 2170 hal_tx_update_tidmap_prty_generic_be; 2171 hal_soc->ops->hal_rx_get_rx_fragment_number = 2172 hal_rx_get_rx_fragment_number_be; 2173 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 2174 hal_rx_tlv_da_is_mcbc_get_be; 2175 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 2176 hal_rx_tlv_sa_is_valid_get_be; 2177 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be, 2178 hal_soc->ops->hal_rx_desc_is_first_msdu = 2179 hal_rx_desc_is_first_msdu_be; 2180 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 2181 hal_rx_tlv_l3_hdr_padding_get_be; 2182 hal_soc->ops->hal_rx_encryption_info_valid = 2183 hal_rx_encryption_info_valid_be; 2184 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; 2185 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 2186 hal_rx_tlv_first_msdu_get_be; 2187 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 2188 hal_rx_tlv_da_is_valid_get_be; 2189 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 2190 hal_rx_tlv_last_msdu_get_be; 2191 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 2192 hal_rx_get_mpdu_mac_ad4_valid_be; 2193 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 2194 hal_rx_mpdu_start_sw_peer_id_get_be; 2195 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 2196 hal_rx_mpdu_peer_meta_data_get_be; 2197 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be; 2198 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be; 2199 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 2200 hal_rx_get_mpdu_frame_control_valid_be; 2201 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; 2202 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; 2203 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; 2204 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; 2205 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 2206 hal_rx_get_mpdu_sequence_control_valid_be; 2207 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; 2208 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; 2209 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 2210 hal_rx_hw_desc_get_ppduid_get_be; 2211 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 2212 hal_rx_msdu0_buffer_addr_lsb_kiwi; 2213 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 2214 hal_rx_msdu_desc_info_ptr_get_kiwi; 2215 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_kiwi; 2216 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_kiwi; 2217 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; 2218 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; 2219 hal_soc->ops->hal_rx_get_mac_addr2_valid = 2220 hal_rx_get_mac_addr2_valid_be; 2221 hal_soc->ops->hal_rx_get_filter_category = 2222 hal_rx_get_filter_category_be; 2223 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be; 2224 hal_soc->ops->hal_reo_config = hal_reo_config_kiwi; 2225 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; 2226 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 2227 hal_rx_msdu_flow_idx_invalid_be; 2228 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 2229 hal_rx_msdu_flow_idx_timeout_be; 2230 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 2231 hal_rx_msdu_fse_metadata_get_be; 2232 hal_soc->ops->hal_rx_msdu_cce_match_get = 2233 hal_rx_msdu_cce_match_get_be; 2234 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 2235 hal_rx_msdu_cce_metadata_get_be; 2236 hal_soc->ops->hal_rx_msdu_get_flow_params = 2237 hal_rx_msdu_get_flow_params_be; 2238 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 2239 hal_rx_tlv_get_tcp_chksum_be; 2240 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be; 2241 #if defined(QCA_WIFI_KIWI) && defined(WLAN_CFR_ENABLE) && \ 2242 defined(WLAN_ENH_CFR_ENABLE) 2243 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_kiwi; 2244 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_kiwi; 2245 #else 2246 hal_soc->ops->hal_rx_get_bb_info = NULL; 2247 hal_soc->ops->hal_rx_get_rtt_info = NULL; 2248 #endif 2249 /* rx - msdu end fast path info fields */ 2250 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 2251 hal_rx_msdu_packet_metadata_get_generic_be; 2252 hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum = 2253 hal_rx_get_fisa_cumulative_l4_checksum_be; 2254 hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length = 2255 hal_rx_get_fisa_cumulative_ip_length_be; 2256 hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_be; 2257 hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation = 2258 hal_rx_get_flow_agg_continuation_be; 2259 hal_soc->ops->hal_rx_get_fisa_flow_agg_count = 2260 hal_rx_get_flow_agg_count_be; 2261 hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_be; 2262 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 2263 hal_rx_mpdu_start_tlv_tag_valid_be; 2264 hal_soc->ops->hal_rx_reo_prev_pn_get = hal_rx_reo_prev_pn_get_kiwi; 2265 2266 /* rx - TLV struct offsets */ 2267 hal_register_rx_pkt_hdr_tlv_api_kiwi(hal_soc); 2268 hal_soc->ops->hal_rx_msdu_end_offset_get = 2269 hal_rx_msdu_end_offset_get_generic; 2270 hal_soc->ops->hal_rx_mpdu_start_offset_get = 2271 hal_rx_mpdu_start_offset_get_generic; 2272 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_kiwi; 2273 hal_soc->ops->hal_rx_flow_get_tuple_info = 2274 hal_rx_flow_get_tuple_info_be; 2275 hal_soc->ops->hal_rx_flow_delete_entry = 2276 hal_rx_flow_delete_entry_be; 2277 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be; 2278 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 2279 hal_compute_reo_remap_ix2_ix3_kiwi; 2280 hal_soc->ops->hal_rx_flow_setup_cmem_fse = 2281 hal_rx_flow_setup_cmem_fse_kiwi; 2282 hal_soc->ops->hal_rx_flow_get_cmem_fse_ts = 2283 hal_rx_flow_get_cmem_fse_ts_kiwi; 2284 hal_soc->ops->hal_rx_flow_get_cmem_fse = hal_rx_flow_get_cmem_fse_kiwi; 2285 hal_soc->ops->hal_cmem_write = hal_cmem_write_kiwi; 2286 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 2287 hal_rx_msdu_get_reo_destination_indication_be; 2288 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_kiwi; 2289 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; 2290 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 2291 hal_rx_msdu_is_wlan_mcast_generic_be; 2292 hal_soc->ops->hal_rx_tlv_bw_get = 2293 hal_rx_tlv_bw_get_be; 2294 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 2295 hal_rx_tlv_get_is_decrypted_be; 2296 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be; 2297 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be; 2298 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 2299 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 2300 hal_soc->ops->hal_rx_tlv_mpdu_len_err_get = 2301 hal_rx_tlv_mpdu_len_err_get_be; 2302 hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get = 2303 hal_rx_tlv_mpdu_fcs_err_get_be; 2304 2305 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be; 2306 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 2307 hal_rx_tlv_decrypt_err_get_be; 2308 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; 2309 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; 2310 hal_soc->ops->hal_rx_tlv_decap_format_get = 2311 hal_rx_tlv_decap_format_get_be; 2312 hal_soc->ops->hal_rx_tlv_get_offload_info = 2313 hal_rx_tlv_get_offload_info_be; 2314 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 2315 hal_rx_attn_phy_ppdu_id_get_be; 2316 hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_tlv_msdu_done_get_be; 2317 hal_soc->ops->hal_rx_tlv_msdu_len_get = 2318 hal_rx_msdu_start_msdu_len_get_be; 2319 hal_soc->ops->hal_rx_get_frame_ctrl_field = 2320 hal_rx_get_frame_ctrl_field_be; 2321 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; 2322 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; 2323 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; 2324 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 2325 hal_rx_mpdu_info_ampdu_flag_get_be; 2326 hal_soc->ops->hal_rx_tlv_msdu_len_set = 2327 hal_rx_msdu_start_msdu_len_set_be; 2328 hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info = 2329 hal_rx_tlv_populate_mpdu_desc_info_kiwi; 2330 hal_soc->ops->hal_get_idle_link_bm_id = hal_get_idle_link_bm_id_kiwi; 2331 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 2332 hal_soc->ops->hal_get_first_wow_wakeup_packet = 2333 hal_get_first_wow_wakeup_packet_kiwi; 2334 #endif 2335 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 2336 2337 hal_soc->ops->hal_rx_tlv_l3_type_get = hal_rx_tlv_l3_type_get_be; 2338 hal_soc->ops->hal_tx_vdev_mismatch_routing_set = 2339 hal_tx_vdev_mismatch_routing_set_generic_be; 2340 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = 2341 hal_tx_mcast_mlo_reinject_routing_set_generic_be; 2342 hal_soc->ops->hal_get_ba_aging_timeout = 2343 hal_get_ba_aging_timeout_be_generic; 2344 hal_soc->ops->hal_setup_link_idle_list = 2345 hal_setup_link_idle_list_generic_be; 2346 hal_soc->ops->hal_cookie_conversion_reg_cfg_be = 2347 hal_cookie_conversion_reg_cfg_generic_be; 2348 hal_soc->ops->hal_set_ba_aging_timeout = 2349 hal_set_ba_aging_timeout_be_generic; 2350 hal_soc->ops->hal_tx_populate_bank_register = 2351 hal_tx_populate_bank_register_be; 2352 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = 2353 hal_tx_vdev_mcast_ctrl_set_be; 2354 hal_soc->ops->hal_get_tsf_time = hal_get_tsf_time_kiwi; 2355 hal_soc->ops->hal_rx_reo_ent_get_src_link_id = 2356 hal_rx_reo_ent_get_src_link_id_kiwi; 2357 #ifdef FEATURE_DIRECT_LINK 2358 hal_soc->ops->hal_srng_set_msi_config = hal_srng_set_msi_config; 2359 #endif 2360 hal_soc->ops->hal_rx_en_mcast_fp_data_filter = 2361 hal_rx_en_mcast_fp_data_filter_kiwi; 2362 #ifdef WLAN_PKT_CAPTURE_TX_2_0 2363 hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv = 2364 hal_txmon_is_mon_buf_addr_tlv_generic_be; 2365 hal_soc->ops->hal_txmon_populate_packet_info = 2366 hal_txmon_populate_packet_info_generic_be; 2367 hal_soc->ops->hal_txmon_status_parse_tlv = 2368 hal_txmon_status_parse_tlv_generic_be; 2369 hal_soc->ops->hal_txmon_status_get_num_users = 2370 hal_txmon_status_get_num_users_generic_be; 2371 #endif /* WLAN_PKT_CAPTURE_TX_2_0 */ 2372 }; 2373 2374 struct hal_hw_srng_config hw_srng_table_kiwi[] = { 2375 /* TODO: max_rings can populated by querying HW capabilities */ 2376 { /* REO_DST */ 2377 .start_ring_id = HAL_SRNG_REO2SW1, 2378 .max_rings = 8, 2379 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2380 .lmac_ring = FALSE, 2381 .ring_dir = HAL_SRNG_DST_RING, 2382 .nf_irq_support = true, 2383 .reg_start = { 2384 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 2385 REO_REG_REG_BASE), 2386 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 2387 REO_REG_REG_BASE) 2388 }, 2389 .reg_size = { 2390 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 2391 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 2392 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 2393 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 2394 }, 2395 .max_size = 2396 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 2397 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 2398 }, 2399 { /* REO_EXCEPTION */ 2400 /* Designating REO2SW0 ring as exception ring. */ 2401 .start_ring_id = HAL_SRNG_REO2SW0, 2402 .max_rings = 1, 2403 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2404 .lmac_ring = FALSE, 2405 .ring_dir = HAL_SRNG_DST_RING, 2406 .reg_start = { 2407 HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR( 2408 REO_REG_REG_BASE), 2409 HWIO_REO_R2_REO2SW0_RING_HP_ADDR( 2410 REO_REG_REG_BASE) 2411 }, 2412 /* Single ring - provide ring size if multiple rings of this 2413 * type are supported 2414 */ 2415 .reg_size = {}, 2416 .max_size = 2417 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >> 2418 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT, 2419 }, 2420 { /* REO_REINJECT */ 2421 .start_ring_id = HAL_SRNG_SW2REO, 2422 .max_rings = 1, 2423 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2424 .lmac_ring = FALSE, 2425 .ring_dir = HAL_SRNG_SRC_RING, 2426 .reg_start = { 2427 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 2428 REO_REG_REG_BASE), 2429 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 2430 REO_REG_REG_BASE) 2431 }, 2432 /* Single ring - provide ring size if multiple rings of this 2433 * type are supported 2434 */ 2435 .reg_size = {}, 2436 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 2437 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 2438 }, 2439 { /* REO_CMD */ 2440 .start_ring_id = HAL_SRNG_REO_CMD, 2441 .max_rings = 1, 2442 .entry_size = (sizeof(struct tlv_32_hdr) + 2443 sizeof(struct reo_get_queue_stats)) >> 2, 2444 .lmac_ring = FALSE, 2445 .ring_dir = HAL_SRNG_SRC_RING, 2446 .reg_start = { 2447 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 2448 REO_REG_REG_BASE), 2449 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 2450 REO_REG_REG_BASE), 2451 }, 2452 /* Single ring - provide ring size if multiple rings of this 2453 * type are supported 2454 */ 2455 .reg_size = {}, 2456 .max_size = 2457 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 2458 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 2459 }, 2460 { /* REO_STATUS */ 2461 .start_ring_id = HAL_SRNG_REO_STATUS, 2462 .max_rings = 1, 2463 .entry_size = (sizeof(struct tlv_32_hdr) + 2464 sizeof(struct reo_get_queue_stats_status)) >> 2, 2465 .lmac_ring = FALSE, 2466 .ring_dir = HAL_SRNG_DST_RING, 2467 .reg_start = { 2468 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2469 REO_REG_REG_BASE), 2470 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2471 REO_REG_REG_BASE), 2472 }, 2473 /* Single ring - provide ring size if multiple rings of this 2474 * type are supported 2475 */ 2476 .reg_size = {}, 2477 .max_size = 2478 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2479 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2480 }, 2481 { /* TCL_DATA */ 2482 .start_ring_id = HAL_SRNG_SW2TCL1, 2483 .max_rings = 5, 2484 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 2485 .lmac_ring = FALSE, 2486 .ring_dir = HAL_SRNG_SRC_RING, 2487 .reg_start = { 2488 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2489 MAC_TCL_REG_REG_BASE), 2490 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2491 MAC_TCL_REG_REG_BASE), 2492 }, 2493 .reg_size = { 2494 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2495 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2496 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2497 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2498 }, 2499 .max_size = 2500 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2501 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2502 }, 2503 { /* TCL_CMD */ 2504 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2505 #ifndef WLAN_DP_DISABLE_TCL_CMD_CRED_SRNG 2506 .max_rings = 1, 2507 #else 2508 .max_rings = 0, 2509 #endif 2510 .entry_size = sizeof(struct tcl_gse_cmd) >> 2, 2511 .lmac_ring = FALSE, 2512 .ring_dir = HAL_SRNG_SRC_RING, 2513 .reg_start = { 2514 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2515 MAC_TCL_REG_REG_BASE), 2516 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2517 MAC_TCL_REG_REG_BASE), 2518 }, 2519 /* Single ring - provide ring size if multiple rings of this 2520 * type are supported 2521 */ 2522 .reg_size = {}, 2523 .max_size = 2524 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2525 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2526 }, 2527 { /* TCL_STATUS */ 2528 .start_ring_id = HAL_SRNG_TCL_STATUS, 2529 #ifndef WLAN_DP_DISABLE_TCL_CMD_CRED_SRNG 2530 .max_rings = 1, 2531 #else 2532 .max_rings = 0, 2533 #endif 2534 /* confirm that TLV header is needed */ 2535 .entry_size = sizeof(struct tcl_status_ring) >> 2, 2536 .lmac_ring = FALSE, 2537 .ring_dir = HAL_SRNG_DST_RING, 2538 .reg_start = { 2539 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2540 MAC_TCL_REG_REG_BASE), 2541 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2542 MAC_TCL_REG_REG_BASE), 2543 }, 2544 /* Single ring - provide ring size if multiple rings of this 2545 * type are supported 2546 */ 2547 .reg_size = {}, 2548 .max_size = 2549 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2550 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2551 }, 2552 { /* CE_SRC */ 2553 .start_ring_id = HAL_SRNG_CE_0_SRC, 2554 .max_rings = 12, 2555 .entry_size = sizeof(struct ce_src_desc) >> 2, 2556 .lmac_ring = FALSE, 2557 .ring_dir = HAL_SRNG_SRC_RING, 2558 .reg_start = { 2559 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, 2560 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, 2561 }, 2562 .reg_size = { 2563 SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 2564 SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 2565 SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 2566 SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 2567 }, 2568 .max_size = 2569 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >> 2570 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT, 2571 }, 2572 { /* CE_DST */ 2573 .start_ring_id = HAL_SRNG_CE_0_DST, 2574 .max_rings = 12, 2575 .entry_size = 8 >> 2, 2576 /*TODO: entry_size above should actually be 2577 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2578 * of struct ce_dst_desc in HW header files 2579 */ 2580 .lmac_ring = FALSE, 2581 .ring_dir = HAL_SRNG_SRC_RING, 2582 .reg_start = { 2583 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, 2584 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, 2585 }, 2586 .reg_size = { 2587 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2588 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2589 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2590 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2591 }, 2592 .max_size = 2593 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2594 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2595 }, 2596 { /* CE_DST_STATUS */ 2597 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2598 .max_rings = 12, 2599 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2600 .lmac_ring = FALSE, 2601 .ring_dir = HAL_SRNG_DST_RING, 2602 .reg_start = { 2603 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, 2604 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, 2605 }, 2606 .reg_size = { 2607 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2608 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2609 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2610 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2611 }, 2612 .max_size = 2613 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2614 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2615 }, 2616 { /* WBM_IDLE_LINK */ 2617 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2618 .max_rings = 1, 2619 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2620 .lmac_ring = FALSE, 2621 .ring_dir = HAL_SRNG_SRC_RING, 2622 .reg_start = { 2623 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2624 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE), 2625 }, 2626 /* Single ring - provide ring size if multiple rings of this 2627 * type are supported 2628 */ 2629 .reg_size = {}, 2630 .max_size = 2631 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2632 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2633 }, 2634 { /* SW2WBM_RELEASE */ 2635 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2636 .max_rings = 1, 2637 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2638 .lmac_ring = FALSE, 2639 .ring_dir = HAL_SRNG_SRC_RING, 2640 .reg_start = { 2641 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2642 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2643 }, 2644 /* Single ring - provide ring size if multiple rings of this 2645 * type are supported 2646 */ 2647 .reg_size = {}, 2648 .max_size = 2649 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2650 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2651 }, 2652 { /* WBM2SW_RELEASE */ 2653 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2654 .max_rings = 8, 2655 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2656 .lmac_ring = FALSE, 2657 .ring_dir = HAL_SRNG_DST_RING, 2658 .nf_irq_support = true, 2659 .reg_start = { 2660 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2661 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2662 }, 2663 .reg_size = { 2664 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE) - 2665 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2666 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE) - 2667 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2668 }, 2669 .max_size = 2670 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2671 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2672 }, 2673 { /* RXDMA_BUF */ 2674 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2675 #if defined(IPA_OFFLOAD) && defined(FEATURE_DIRECT_LINK) 2676 .max_rings = 4, 2677 #elif defined(IPA_OFFLOAD) || defined(FEATURE_DIRECT_LINK) 2678 .max_rings = 3, 2679 #else 2680 .max_rings = 2, 2681 #endif 2682 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2683 .lmac_ring = TRUE, 2684 .ring_dir = HAL_SRNG_SRC_RING, 2685 /* reg_start is not set because LMAC rings are not accessed 2686 * from host 2687 */ 2688 .reg_start = {}, 2689 .reg_size = {}, 2690 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2691 }, 2692 { /* RXDMA_DST */ 2693 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2694 .max_rings = 1, 2695 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2696 .lmac_ring = TRUE, 2697 .ring_dir = HAL_SRNG_DST_RING, 2698 /* reg_start is not set because LMAC rings are not accessed 2699 * from host 2700 */ 2701 .reg_start = {}, 2702 .reg_size = {}, 2703 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2704 }, 2705 { /* RXDMA_MONITOR_BUF */ 2706 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2707 .max_rings = 1, 2708 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2709 .lmac_ring = TRUE, 2710 .ring_dir = HAL_SRNG_SRC_RING, 2711 /* reg_start is not set because LMAC rings are not accessed 2712 * from host 2713 */ 2714 .reg_start = {}, 2715 .reg_size = {}, 2716 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2717 }, 2718 { /* RXDMA_MONITOR_STATUS */ 2719 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2720 .max_rings = 1, 2721 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2722 .lmac_ring = TRUE, 2723 .ring_dir = HAL_SRNG_SRC_RING, 2724 /* reg_start is not set because LMAC rings are not accessed 2725 * from host 2726 */ 2727 .reg_start = {}, 2728 .reg_size = {}, 2729 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2730 }, 2731 { /* RXDMA_MONITOR_DST */ 2732 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2733 .max_rings = 1, 2734 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2735 .lmac_ring = TRUE, 2736 .ring_dir = HAL_SRNG_DST_RING, 2737 /* reg_start is not set because LMAC rings are not accessed 2738 * from host 2739 */ 2740 .reg_start = {}, 2741 .reg_size = {}, 2742 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2743 }, 2744 { /* RXDMA_MONITOR_DESC */ 2745 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2746 .max_rings = 1, 2747 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2748 .lmac_ring = TRUE, 2749 .ring_dir = HAL_SRNG_SRC_RING, 2750 /* reg_start is not set because LMAC rings are not accessed 2751 * from host 2752 */ 2753 .reg_start = {}, 2754 .reg_size = {}, 2755 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2756 }, 2757 { /* DIR_BUF_RX_DMA_SRC */ 2758 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2759 /* 2760 * one ring is for spectral scan 2761 * the other is for cfr 2762 */ 2763 .max_rings = 2, 2764 .entry_size = 2, 2765 .lmac_ring = TRUE, 2766 .ring_dir = HAL_SRNG_SRC_RING, 2767 /* reg_start is not set because LMAC rings are not accessed 2768 * from host 2769 */ 2770 .reg_start = {}, 2771 .reg_size = {}, 2772 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2773 }, 2774 #ifdef WLAN_FEATURE_CIF_CFR 2775 { /* WIFI_POS_SRC */ 2776 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2777 .max_rings = 1, 2778 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2779 .lmac_ring = TRUE, 2780 .ring_dir = HAL_SRNG_SRC_RING, 2781 /* reg_start is not set because LMAC rings are not accessed 2782 * from host 2783 */ 2784 .reg_start = {}, 2785 .reg_size = {}, 2786 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2787 }, 2788 #endif 2789 { /* REO2PPE */ 0}, 2790 { /* PPE2TCL */ 0}, 2791 { /* PPE_RELEASE */ 0}, 2792 #ifdef WLAN_PKT_CAPTURE_TX_2_0 2793 { /* TX_MONITOR_BUF */ 2794 .start_ring_id = HAL_SRNG_SW2TXMON_BUF0, 2795 .max_rings = 1, 2796 .entry_size = sizeof(struct mon_ingress_ring) >> 2, 2797 .lmac_ring = TRUE, 2798 .ring_dir = HAL_SRNG_SRC_RING, 2799 /* reg_start is not set because LMAC rings are not accessed 2800 * from host 2801 */ 2802 .reg_start = {}, 2803 .reg_size = {}, 2804 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2805 }, 2806 { /* TX_MONITOR_DST */ 2807 .start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0, 2808 .max_rings = 2, 2809 .entry_size = sizeof(struct mon_destination_ring) >> 2, 2810 .lmac_ring = TRUE, 2811 .ring_dir = HAL_SRNG_DST_RING, 2812 /* reg_start is not set because LMAC rings are not accessed 2813 * from host 2814 */ 2815 .reg_start = {}, 2816 .reg_size = {}, 2817 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, 2818 }, 2819 #else 2820 {0}, 2821 {0}, 2822 #endif 2823 { /* SW2RXDMA_NEW */ 0}, 2824 }; 2825 2826 /** 2827 * hal_srng_hw_reg_offset_init_kiwi() - Initialize the HW srng reg offset 2828 * applicable only for KIWI 2829 * @hal_soc: HAL Soc handle 2830 * 2831 * Return: None 2832 */ 2833 static inline void hal_srng_hw_reg_offset_init_kiwi(struct hal_soc *hal_soc) 2834 { 2835 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 2836 2837 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB), 2838 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB), 2839 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA), 2840 hw_reg_offset[DST_PRODUCER_INT2_SETUP] = 2841 REG_OFFSET(DST, PRODUCER_INT2_SETUP); 2842 hal_srng_hw_reg_offset_init_misc_1_kiwi(hal_soc); 2843 } 2844 2845 void hal_kiwi_attach(struct hal_soc *hal_soc) 2846 { 2847 hal_soc->hw_srng_table = hw_srng_table_kiwi; 2848 2849 hal_srng_hw_reg_offset_init_generic(hal_soc); 2850 hal_srng_hw_reg_offset_init_kiwi(hal_soc); 2851 hal_hw_txrx_default_ops_attach_be(hal_soc); 2852 hal_hw_txrx_ops_attach_kiwi(hal_soc); 2853 } 2854