1 /* 2 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "qdf_types.h" 21 #include "qdf_util.h" 22 #include "qdf_types.h" 23 #include "qdf_lock.h" 24 #include "qdf_mem.h" 25 #include "qdf_nbuf.h" 26 #include "hal_hw_headers.h" 27 #include "hal_internal.h" 28 #include "hal_api.h" 29 #include "target_type.h" 30 #include "wcss_version.h" 31 #include "qdf_module.h" 32 #include "hal_flow.h" 33 #include "rx_flow_search_entry.h" 34 #include "hal_rx_flow_info.h" 35 #include "hal_be_api.h" 36 #include "reo_destination_ring_with_pn.h" 37 #include "rx_reo_queue_1k.h" 38 39 #include <hal_be_rx.h> 40 41 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 42 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 43 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 44 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 45 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 46 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 47 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 48 PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 49 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 50 PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 51 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 52 PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 53 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 54 PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 59 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 60 PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 61 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 62 PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 63 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 64 PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 65 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 66 PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 67 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 68 PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 69 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 70 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 71 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 72 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 73 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 74 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 75 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 76 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 77 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 78 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 79 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 80 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 81 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 82 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 83 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 84 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 85 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 86 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 87 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 88 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 89 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 90 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 91 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 92 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 94 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 95 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 96 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 97 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 98 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 99 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 100 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 101 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 102 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 103 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 104 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 105 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 106 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 107 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 108 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 109 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 110 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 112 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 113 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 114 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 115 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 116 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 117 118 #include "hal_kiwi_tx.h" 119 #include "hal_kiwi_rx.h" 120 121 #include "hal_be_rx_tlv.h" 122 123 #include <hal_generic_api.h> 124 #include <hal_be_generic_api.h> 125 #include "hal_be_api_mon.h" 126 127 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 128 129 static uint32_t hal_get_link_desc_size_kiwi(void) 130 { 131 return LINK_DESC_SIZE; 132 } 133 134 /** 135 * hal_rx_dump_msdu_end_tlv_kiwi: dump RX msdu_end TLV in structured 136 * human readable format. 137 * @ msdu_end: pointer the msdu_end TLV in pkt. 138 * @ dbg_level: log level. 139 * 140 * Return: void 141 */ 142 #ifdef QCA_WIFI_KIWI_V2 143 static void hal_rx_dump_msdu_end_tlv_kiwi(void *msduend, 144 uint8_t dbg_level) 145 { 146 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 147 148 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 149 "rx_msdu_end tlv (1/5)- " 150 "rxpcu_mpdu_filter_in_category :%x " 151 "sw_frame_group_id :%x " 152 "reserved_0 :%x " 153 "phy_ppdu_id :%x " 154 "ip_hdr_chksum :%x " 155 "reported_mpdu_length :%x " 156 "reserved_1a :%x " 157 "reserved_2a :%x " 158 "cce_super_rule :%x " 159 "cce_classify_not_done_truncate :%x " 160 "cce_classify_not_done_cce_dis :%x " 161 "cumulative_l3_checksum :%x " 162 "rule_indication_31_0 :%x " 163 "ipv6_options_crc :%x " 164 "da_offset :%x " 165 "sa_offset :%x " 166 "da_offset_valid :%x " 167 "sa_offset_valid :%x " 168 "reserved_5a :%x " 169 "l3_type :%x", 170 msdu_end->rxpcu_mpdu_filter_in_category, 171 msdu_end->sw_frame_group_id, 172 msdu_end->reserved_0, 173 msdu_end->phy_ppdu_id, 174 msdu_end->ip_hdr_chksum, 175 msdu_end->reported_mpdu_length, 176 msdu_end->reserved_1a, 177 msdu_end->reserved_2a, 178 msdu_end->cce_super_rule, 179 msdu_end->cce_classify_not_done_truncate, 180 msdu_end->cce_classify_not_done_cce_dis, 181 msdu_end->cumulative_l3_checksum, 182 msdu_end->rule_indication_31_0, 183 msdu_end->ipv6_options_crc, 184 msdu_end->da_offset, 185 msdu_end->sa_offset, 186 msdu_end->da_offset_valid, 187 msdu_end->sa_offset_valid, 188 msdu_end->reserved_5a, 189 msdu_end->l3_type); 190 191 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 192 "rx_msdu_end tlv (2/5)- " 193 "rule_indication_63_32 :%x " 194 "tcp_seq_number :%x " 195 "tcp_ack_number :%x " 196 "tcp_flag :%x " 197 "lro_eligible :%x " 198 "reserved_9a :%x " 199 "window_size :%x " 200 "sa_sw_peer_id :%x " 201 "sa_idx_timeout :%x " 202 "da_idx_timeout :%x " 203 "to_ds :%x " 204 "tid :%x " 205 "sa_is_valid :%x " 206 "da_is_valid :%x " 207 "da_is_mcbc :%x " 208 "l3_header_padding :%x " 209 "first_msdu :%x " 210 "last_msdu :%x " 211 "fr_ds :%x " 212 "ip_chksum_fail_copy :%x " 213 "sa_idx :%x " 214 "da_idx_or_sw_peer_id :%x", 215 msdu_end->rule_indication_63_32, 216 msdu_end->tcp_seq_number, 217 msdu_end->tcp_ack_number, 218 msdu_end->tcp_flag, 219 msdu_end->lro_eligible, 220 msdu_end->reserved_9a, 221 msdu_end->window_size, 222 msdu_end->sa_sw_peer_id, 223 msdu_end->sa_idx_timeout, 224 msdu_end->da_idx_timeout, 225 msdu_end->to_ds, 226 msdu_end->tid, 227 msdu_end->sa_is_valid, 228 msdu_end->da_is_valid, 229 msdu_end->da_is_mcbc, 230 msdu_end->l3_header_padding, 231 msdu_end->first_msdu, 232 msdu_end->last_msdu, 233 msdu_end->fr_ds, 234 msdu_end->ip_chksum_fail_copy, 235 msdu_end->sa_idx, 236 msdu_end->da_idx_or_sw_peer_id); 237 238 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 239 "rx_msdu_end tlv (3/5)- " 240 "msdu_drop :%x " 241 "reo_destination_indication :%x " 242 "flow_idx :%x " 243 "use_ppe :%x " 244 "__reserved_g_0003 :%x " 245 "vlan_ctag_stripped :%x " 246 "vlan_stag_stripped :%x " 247 "fragment_flag :%x " 248 "fse_metadata :%x " 249 "cce_metadata :%x " 250 "tcp_udp_chksum :%x " 251 "aggregation_count :%x " 252 "flow_aggregation_continuation :%x " 253 "fisa_timeout :%x " 254 "tcp_udp_chksum_fail_copy :%x " 255 "msdu_limit_error :%x " 256 "flow_idx_timeout :%x " 257 "flow_idx_invalid :%x " 258 "cce_match :%x " 259 "amsdu_parser_error :%x " 260 "cumulative_ip_length :%x " 261 "key_id_octet :%x " 262 "reserved_16a :%x " 263 "reserved_17a :%x " 264 "service_code :%x " 265 "priority_valid :%x " 266 "intra_bss :%x " 267 "dest_chip_id :%x " 268 "multicast_echo :%x " 269 "wds_learning_event :%x " 270 "wds_roaming_event :%x " 271 "wds_keep_alive_event :%x " 272 "reserved_17b :%x", 273 msdu_end->msdu_drop, 274 msdu_end->reo_destination_indication, 275 msdu_end->flow_idx, 276 msdu_end->use_ppe, 277 msdu_end->__reserved_g_0003, 278 msdu_end->vlan_ctag_stripped, 279 msdu_end->vlan_stag_stripped, 280 msdu_end->fragment_flag, 281 msdu_end->fse_metadata, 282 msdu_end->cce_metadata, 283 msdu_end->tcp_udp_chksum, 284 msdu_end->aggregation_count, 285 msdu_end->flow_aggregation_continuation, 286 msdu_end->fisa_timeout, 287 msdu_end->tcp_udp_chksum_fail_copy, 288 msdu_end->msdu_limit_error, 289 msdu_end->flow_idx_timeout, 290 msdu_end->flow_idx_invalid, 291 msdu_end->cce_match, 292 msdu_end->amsdu_parser_error, 293 msdu_end->cumulative_ip_length, 294 msdu_end->key_id_octet, 295 msdu_end->reserved_16a, 296 msdu_end->reserved_17a, 297 msdu_end->service_code, 298 msdu_end->priority_valid, 299 msdu_end->intra_bss, 300 msdu_end->dest_chip_id, 301 msdu_end->multicast_echo, 302 msdu_end->wds_learning_event, 303 msdu_end->wds_roaming_event, 304 msdu_end->wds_keep_alive_event, 305 msdu_end->reserved_17b); 306 307 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 308 "rx_msdu_end tlv (4/5)- " 309 "msdu_length :%x " 310 "stbc :%x " 311 "ipsec_esp :%x " 312 "l3_offset :%x " 313 "ipsec_ah :%x " 314 "l4_offset :%x " 315 "msdu_number :%x " 316 "decap_format :%x " 317 "ipv4_proto :%x " 318 "ipv6_proto :%x " 319 "tcp_proto :%x " 320 "udp_proto :%x " 321 "ip_frag :%x " 322 "tcp_only_ack :%x " 323 "da_is_bcast_mcast :%x " 324 "toeplitz_hash_sel :%x " 325 "ip_fixed_header_valid :%x " 326 "ip_extn_header_valid :%x " 327 "tcp_udp_header_valid :%x " 328 "mesh_control_present :%x " 329 "ldpc :%x " 330 "ip4_protocol_ip6_next_header :%x " 331 "vlan_ctag_ci :%x " 332 "vlan_stag_ci :%x " 333 "peer_meta_data :%x " 334 "user_rssi :%x " 335 "pkt_type :%x " 336 "sgi :%x " 337 "rate_mcs :%x " 338 "receive_bandwidth :%x " 339 "reception_type :%x " 340 "mimo_ss_bitmap :%x " 341 "msdu_done_copy :%x " 342 "flow_id_toeplitz :%x", 343 msdu_end->msdu_length, 344 msdu_end->stbc, 345 msdu_end->ipsec_esp, 346 msdu_end->l3_offset, 347 msdu_end->ipsec_ah, 348 msdu_end->l4_offset, 349 msdu_end->msdu_number, 350 msdu_end->decap_format, 351 msdu_end->ipv4_proto, 352 msdu_end->ipv6_proto, 353 msdu_end->tcp_proto, 354 msdu_end->udp_proto, 355 msdu_end->ip_frag, 356 msdu_end->tcp_only_ack, 357 msdu_end->da_is_bcast_mcast, 358 msdu_end->toeplitz_hash_sel, 359 msdu_end->ip_fixed_header_valid, 360 msdu_end->ip_extn_header_valid, 361 msdu_end->tcp_udp_header_valid, 362 msdu_end->mesh_control_present, 363 msdu_end->ldpc, 364 msdu_end->ip4_protocol_ip6_next_header, 365 msdu_end->vlan_ctag_ci, 366 msdu_end->vlan_stag_ci, 367 msdu_end->peer_meta_data, 368 msdu_end->user_rssi, 369 msdu_end->pkt_type, 370 msdu_end->sgi, 371 msdu_end->rate_mcs, 372 msdu_end->receive_bandwidth, 373 msdu_end->reception_type, 374 msdu_end->mimo_ss_bitmap, 375 msdu_end->msdu_done_copy, 376 msdu_end->flow_id_toeplitz); 377 378 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 379 "rx_msdu_end tlv (5/5)- " 380 "ppdu_start_timestamp_63_32 :%x " 381 "sw_phy_meta_data :%x " 382 "ppdu_start_timestamp_31_0 :%x " 383 "toeplitz_hash_2_or_4 :%x " 384 "reserved_28a :%x " 385 "sa_15_0 :%x " 386 "sa_47_16 :%x " 387 "first_mpdu :%x " 388 "reserved_30a :%x " 389 "mcast_bcast :%x " 390 "ast_index_not_found :%x " 391 "ast_index_timeout :%x " 392 "power_mgmt :%x " 393 "non_qos :%x " 394 "null_data :%x " 395 "mgmt_type :%x " 396 "ctrl_type :%x " 397 "more_data :%x " 398 "eosp :%x " 399 "a_msdu_error :%x " 400 "reserved_30b :%x " 401 "order :%x " 402 "wifi_parser_error :%x " 403 "overflow_err :%x " 404 "msdu_length_err :%x " 405 "tcp_udp_chksum_fail :%x " 406 "ip_chksum_fail :%x " 407 "sa_idx_invalid :%x " 408 "da_idx_invalid :%x " 409 "amsdu_addr_mismatch :%x " 410 "rx_in_tx_decrypt_byp :%x " 411 "encrypt_required :%x " 412 "directed :%x " 413 "buffer_fragment :%x " 414 "mpdu_length_err :%x " 415 "tkip_mic_err :%x " 416 "decrypt_err :%x " 417 "unencrypted_frame_err :%x " 418 "fcs_err :%x " 419 "reserved_31a :%x " 420 "decrypt_status_code :%x " 421 "rx_bitmap_not_updated :%x " 422 "reserved_31b :%x " 423 "msdu_done :%x", 424 msdu_end->ppdu_start_timestamp_63_32, 425 msdu_end->sw_phy_meta_data, 426 msdu_end->ppdu_start_timestamp_31_0, 427 msdu_end->toeplitz_hash_2_or_4, 428 msdu_end->reserved_28a, 429 msdu_end->sa_15_0, 430 msdu_end->sa_47_16, 431 msdu_end->first_mpdu, 432 msdu_end->reserved_30a, 433 msdu_end->mcast_bcast, 434 msdu_end->ast_index_not_found, 435 msdu_end->ast_index_timeout, 436 msdu_end->power_mgmt, 437 msdu_end->non_qos, 438 msdu_end->null_data, 439 msdu_end->mgmt_type, 440 msdu_end->ctrl_type, 441 msdu_end->more_data, 442 msdu_end->eosp, 443 msdu_end->a_msdu_error, 444 msdu_end->reserved_30b, 445 msdu_end->order, 446 msdu_end->wifi_parser_error, 447 msdu_end->overflow_err, 448 msdu_end->msdu_length_err, 449 msdu_end->tcp_udp_chksum_fail, 450 msdu_end->ip_chksum_fail, 451 msdu_end->sa_idx_invalid, 452 msdu_end->da_idx_invalid, 453 msdu_end->amsdu_addr_mismatch, 454 msdu_end->rx_in_tx_decrypt_byp, 455 msdu_end->encrypt_required, 456 msdu_end->directed, 457 msdu_end->buffer_fragment, 458 msdu_end->mpdu_length_err, 459 msdu_end->tkip_mic_err, 460 msdu_end->decrypt_err, 461 msdu_end->unencrypted_frame_err, 462 msdu_end->fcs_err, 463 msdu_end->reserved_31a, 464 msdu_end->decrypt_status_code, 465 msdu_end->rx_bitmap_not_updated, 466 msdu_end->reserved_31b, 467 msdu_end->msdu_done); 468 } 469 #else 470 static void hal_rx_dump_msdu_end_tlv_kiwi(void *msduend, 471 uint8_t dbg_level) 472 { 473 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; 474 475 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 476 "rx_msdu_end tlv (1/7)- " 477 "rxpcu_mpdu_filter_in_category :%x" 478 "sw_frame_group_id :%x" 479 "reserved_0 :%x" 480 "phy_ppdu_id :%x" 481 "ip_hdr_chksum:%x" 482 "reported_mpdu_length :%x" 483 "reserved_1a :%x" 484 "key_id_octet :%x" 485 "cce_super_rule :%x" 486 "cce_classify_not_done_truncate :%x" 487 "cce_classify_not_done_cce_dis:%x" 488 "cumulative_l3_checksum :%x" 489 "rule_indication_31_0 :%x" 490 "rule_indication_63_32:%x" 491 "da_offset :%x" 492 "sa_offset :%x" 493 "da_offset_valid :%x" 494 "sa_offset_valid :%x" 495 "reserved_5a :%x" 496 "l3_type :%x", 497 msdu_end->rxpcu_mpdu_filter_in_category, 498 msdu_end->sw_frame_group_id, 499 msdu_end->reserved_0, 500 msdu_end->phy_ppdu_id, 501 msdu_end->ip_hdr_chksum, 502 msdu_end->reported_mpdu_length, 503 msdu_end->reserved_1a, 504 msdu_end->key_id_octet, 505 msdu_end->cce_super_rule, 506 msdu_end->cce_classify_not_done_truncate, 507 msdu_end->cce_classify_not_done_cce_dis, 508 msdu_end->cumulative_l3_checksum, 509 msdu_end->rule_indication_31_0, 510 msdu_end->rule_indication_63_32, 511 msdu_end->da_offset, 512 msdu_end->sa_offset, 513 msdu_end->da_offset_valid, 514 msdu_end->sa_offset_valid, 515 msdu_end->reserved_5a, 516 msdu_end->l3_type); 517 518 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 519 "rx_msdu_end tlv (2/7)- " 520 "ipv6_options_crc :%x" 521 "tcp_seq_number :%x" 522 "tcp_ack_number :%x" 523 "tcp_flag :%x" 524 "lro_eligible :%x" 525 "reserved_9a :%x" 526 "window_size :%x" 527 "tcp_udp_chksum :%x" 528 "sa_idx_timeout :%x" 529 "da_idx_timeout :%x" 530 "msdu_limit_error :%x" 531 "flow_idx_timeout :%x" 532 "flow_idx_invalid :%x" 533 "wifi_parser_error :%x" 534 "amsdu_parser_error :%x" 535 "sa_is_valid :%x" 536 "da_is_valid :%x" 537 "da_is_mcbc :%x" 538 "l3_header_padding :%x" 539 "first_msdu :%x" 540 "last_msdu :%x", 541 msdu_end->ipv6_options_crc, 542 msdu_end->tcp_seq_number, 543 msdu_end->tcp_ack_number, 544 msdu_end->tcp_flag, 545 msdu_end->lro_eligible, 546 msdu_end->reserved_9a, 547 msdu_end->window_size, 548 msdu_end->tcp_udp_chksum, 549 msdu_end->sa_idx_timeout, 550 msdu_end->da_idx_timeout, 551 msdu_end->msdu_limit_error, 552 msdu_end->flow_idx_timeout, 553 msdu_end->flow_idx_invalid, 554 msdu_end->wifi_parser_error, 555 msdu_end->amsdu_parser_error, 556 msdu_end->sa_is_valid, 557 msdu_end->da_is_valid, 558 msdu_end->da_is_mcbc, 559 msdu_end->l3_header_padding, 560 msdu_end->first_msdu, 561 msdu_end->last_msdu); 562 563 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 564 "rx_msdu_end tlv (3/7)" 565 "tcp_udp_chksum_fail_copy :%x" 566 "ip_chksum_fail_copy :%x" 567 "sa_idx :%x" 568 "da_idx_or_sw_peer_id :%x" 569 "msdu_drop :%x" 570 "reo_destination_indication :%x" 571 "flow_idx :%x" 572 "reserved_12a :%x" 573 "fse_metadata :%x" 574 "cce_metadata :%x" 575 "sa_sw_peer_id:%x" 576 "aggregation_count :%x" 577 "flow_aggregation_continuation:%x" 578 "fisa_timeout :%x" 579 "reserved_15a :%x" 580 "cumulative_l4_checksum :%x" 581 "cumulative_ip_length :%x" 582 "service_code :%x" 583 "priority_valid :%x", 584 msdu_end->tcp_udp_chksum_fail_copy, 585 msdu_end->ip_chksum_fail_copy, 586 msdu_end->sa_idx, 587 msdu_end->da_idx_or_sw_peer_id, 588 msdu_end->msdu_drop, 589 msdu_end->reo_destination_indication, 590 msdu_end->flow_idx, 591 msdu_end->reserved_12a, 592 msdu_end->fse_metadata, 593 msdu_end->cce_metadata, 594 msdu_end->sa_sw_peer_id, 595 msdu_end->aggregation_count, 596 msdu_end->flow_aggregation_continuation, 597 msdu_end->fisa_timeout, 598 msdu_end->reserved_15a, 599 msdu_end->cumulative_l4_checksum, 600 msdu_end->cumulative_ip_length, 601 msdu_end->service_code, 602 msdu_end->priority_valid); 603 604 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 605 "rx_msdu_end tlv (4/7)" 606 "reserved_17a :%x" 607 "msdu_length :%x" 608 "ipsec_esp :%x" 609 "l3_offset :%x" 610 "ipsec_ah :%x" 611 "l4_offset :%x" 612 "msdu_number :%x" 613 "decap_format :%x" 614 "ipv4_proto :%x" 615 "ipv6_proto :%x" 616 "tcp_proto :%x" 617 "udp_proto :%x" 618 "ip_frag :%x" 619 "tcp_only_ack :%x" 620 "da_is_bcast_mcast :%x" 621 "toeplitz_hash_sel :%x" 622 "ip_fixed_header_valid:%x" 623 "ip_extn_header_valid :%x" 624 "tcp_udp_header_valid :%x", 625 msdu_end->reserved_17a, 626 msdu_end->msdu_length, 627 msdu_end->ipsec_esp, 628 msdu_end->l3_offset, 629 msdu_end->ipsec_ah, 630 msdu_end->l4_offset, 631 msdu_end->msdu_number, 632 msdu_end->decap_format, 633 msdu_end->ipv4_proto, 634 msdu_end->ipv6_proto, 635 msdu_end->tcp_proto, 636 msdu_end->udp_proto, 637 msdu_end->ip_frag, 638 msdu_end->tcp_only_ack, 639 msdu_end->da_is_bcast_mcast, 640 msdu_end->toeplitz_hash_sel, 641 msdu_end->ip_fixed_header_valid, 642 msdu_end->ip_extn_header_valid, 643 msdu_end->tcp_udp_header_valid); 644 645 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 646 "rx_msdu_end tlv (5/7)" 647 "mesh_control_present :%x" 648 "ldpc :%x" 649 "ip4_protocol_ip6_next_header :%x" 650 "toeplitz_hash_2_or_4 :%x" 651 "flow_id_toeplitz :%x" 652 "user_rssi :%x" 653 "pkt_type :%x" 654 "stbc :%x" 655 "sgi :%x" 656 "rate_mcs :%x" 657 "receive_bandwidth :%x" 658 "reception_type :%x" 659 "mimo_ss_bitmap :%x" 660 "ppdu_start_timestamp_31_0 :%x" 661 "ppdu_start_timestamp_63_32 :%x" 662 "sw_phy_meta_data :%x" 663 "vlan_ctag_ci :%x" 664 "vlan_stag_ci :%x" 665 "first_mpdu :%x" 666 "reserved_30a :%x" 667 "mcast_bcast :%x", 668 msdu_end->mesh_control_present, 669 msdu_end->ldpc, 670 msdu_end->ip4_protocol_ip6_next_header, 671 msdu_end->toeplitz_hash_2_or_4, 672 msdu_end->flow_id_toeplitz, 673 msdu_end->user_rssi, 674 msdu_end->pkt_type, 675 msdu_end->stbc, 676 msdu_end->sgi, 677 msdu_end->rate_mcs, 678 msdu_end->receive_bandwidth, 679 msdu_end->reception_type, 680 msdu_end->mimo_ss_bitmap, 681 msdu_end->ppdu_start_timestamp_31_0, 682 msdu_end->ppdu_start_timestamp_63_32, 683 msdu_end->sw_phy_meta_data, 684 msdu_end->vlan_ctag_ci, 685 msdu_end->vlan_stag_ci, 686 msdu_end->first_mpdu, 687 msdu_end->reserved_30a, 688 msdu_end->mcast_bcast); 689 690 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 691 "rx_msdu_end tlv (6/7)" 692 "ast_index_not_found :%x" 693 "ast_index_timeout :%x" 694 "power_mgmt :%x" 695 "non_qos :%x" 696 "null_data :%x" 697 "mgmt_type :%x" 698 "ctrl_type :%x" 699 "more_data :%x" 700 "eosp :%x" 701 "a_msdu_error :%x" 702 "fragment_flag:%x" 703 "order:%x" 704 "cce_match :%x" 705 "overflow_err :%x" 706 "msdu_length_err :%x" 707 "tcp_udp_chksum_fail :%x" 708 "ip_chksum_fail :%x" 709 "sa_idx_invalid :%x" 710 "da_idx_invalid :%x" 711 "reserved_30b :%x", 712 msdu_end->ast_index_not_found, 713 msdu_end->ast_index_timeout, 714 msdu_end->power_mgmt, 715 msdu_end->non_qos, 716 msdu_end->null_data, 717 msdu_end->mgmt_type, 718 msdu_end->ctrl_type, 719 msdu_end->more_data, 720 msdu_end->eosp, 721 msdu_end->a_msdu_error, 722 msdu_end->fragment_flag, 723 msdu_end->order, 724 msdu_end->cce_match, 725 msdu_end->overflow_err, 726 msdu_end->msdu_length_err, 727 msdu_end->tcp_udp_chksum_fail, 728 msdu_end->ip_chksum_fail, 729 msdu_end->sa_idx_invalid, 730 msdu_end->da_idx_invalid, 731 msdu_end->reserved_30b); 732 733 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 734 "rx_msdu_end tlv (7/7)" 735 "rx_in_tx_decrypt_byp :%x" 736 "encrypt_required :%x" 737 "directed :%x" 738 "buffer_fragment :%x" 739 "mpdu_length_err :%x" 740 "tkip_mic_err :%x" 741 "decrypt_err :%x" 742 "unencrypted_frame_err:%x" 743 "fcs_err :%x" 744 "reserved_31a :%x" 745 "decrypt_status_code :%x" 746 "rx_bitmap_not_updated:%x" 747 "reserved_31b :%x" 748 "msdu_done :%x", 749 msdu_end->rx_in_tx_decrypt_byp, 750 msdu_end->encrypt_required, 751 msdu_end->directed, 752 msdu_end->buffer_fragment, 753 msdu_end->mpdu_length_err, 754 msdu_end->tkip_mic_err, 755 msdu_end->decrypt_err, 756 msdu_end->unencrypted_frame_err, 757 msdu_end->fcs_err, 758 msdu_end->reserved_31a, 759 msdu_end->decrypt_status_code, 760 msdu_end->rx_bitmap_not_updated, 761 msdu_end->reserved_31b, 762 msdu_end->msdu_done); 763 } 764 #endif 765 766 #ifdef NO_RX_PKT_HDR_TLV 767 static inline void hal_rx_dump_pkt_hdr_tlv_kiwi(struct rx_pkt_tlvs *pkt_tlvs, 768 uint8_t dbg_level) 769 { 770 } 771 772 static inline 773 void hal_register_rx_pkt_hdr_tlv_api_kiwi(struct hal_soc *hal_soc) 774 { 775 } 776 777 static uint8_t *hal_rx_desc_get_80211_hdr_be(void *hw_desc_addr) 778 { 779 uint8_t *rx_pkt_hdr; 780 struct rx_mon_pkt_tlvs *rx_desc = 781 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 782 783 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 784 785 return rx_pkt_hdr; 786 } 787 #else 788 static uint8_t *hal_rx_desc_get_80211_hdr_be(void *hw_desc_addr) 789 { 790 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 791 uint8_t *rx_pkt_hdr; 792 793 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 794 795 return rx_pkt_hdr; 796 } 797 798 /** 799 * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format 800 * @pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt. 801 * @dbg_level: log level. 802 * 803 * Return: void 804 */ 805 static inline void hal_rx_dump_pkt_hdr_tlv_kiwi(struct rx_pkt_tlvs *pkt_tlvs, 806 uint8_t dbg_level) 807 { 808 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; 809 810 hal_verbose_debug("\n---------------\n" 811 "rx_pkt_hdr_tlv\n" 812 "---------------\n" 813 "phy_ppdu_id %lld ", 814 pkt_hdr_tlv->phy_ppdu_id); 815 816 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 817 sizeof(pkt_hdr_tlv->rx_pkt_hdr)); 818 } 819 820 /** 821 * hal_register_rx_pkt_hdr_tlv_api_kiwi: register all rx_pkt_hdr_tlv related api 822 * @hal_soc: HAL soc handler 823 * 824 * Return: none 825 */ 826 static inline 827 void hal_register_rx_pkt_hdr_tlv_api_kiwi(struct hal_soc *hal_soc) 828 { 829 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 830 hal_rx_pkt_tlv_offset_get_generic; 831 } 832 #endif 833 834 /** 835 * hal_rx_dump_mpdu_start_tlv_generic_be: dump RX mpdu_start TLV in structured 836 * human readable format. 837 * @mpdu_start: pointer the rx_attention TLV in pkt. 838 * @dbg_level: log level. 839 * 840 * Return: void 841 */ 842 static inline void hal_rx_dump_mpdu_start_tlv_kiwi(void *mpdustart, 843 uint8_t dbg_level) 844 { 845 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; 846 struct rx_mpdu_info *mpdu_info = 847 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; 848 849 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 850 "rx_mpdu_start tlv (1/5) - " 851 "rx_reo_queue_desc_addr_31_0 :%x" 852 "rx_reo_queue_desc_addr_39_32 :%x" 853 "receive_queue_number:%x " 854 "pre_delim_err_warning:%x " 855 "first_delim_err:%x " 856 "reserved_2a:%x " 857 "pn_31_0:%x " 858 "pn_63_32:%x " 859 "pn_95_64:%x " 860 "pn_127_96:%x " 861 "epd_en:%x " 862 "all_frames_shall_be_encrypted :%x" 863 "encrypt_type:%x " 864 "wep_key_width_for_variable_key :%x" 865 "bssid_hit:%x " 866 "bssid_number:%x " 867 "tid:%x " 868 "reserved_7a:%x " 869 "peer_meta_data:%x ", 870 mpdu_info->rx_reo_queue_desc_addr_31_0, 871 mpdu_info->rx_reo_queue_desc_addr_39_32, 872 mpdu_info->receive_queue_number, 873 mpdu_info->pre_delim_err_warning, 874 mpdu_info->first_delim_err, 875 mpdu_info->reserved_2a, 876 mpdu_info->pn_31_0, 877 mpdu_info->pn_63_32, 878 mpdu_info->pn_95_64, 879 mpdu_info->pn_127_96, 880 mpdu_info->epd_en, 881 mpdu_info->all_frames_shall_be_encrypted, 882 mpdu_info->encrypt_type, 883 mpdu_info->wep_key_width_for_variable_key, 884 mpdu_info->bssid_hit, 885 mpdu_info->bssid_number, 886 mpdu_info->tid, 887 mpdu_info->reserved_7a, 888 mpdu_info->peer_meta_data); 889 890 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 891 "rx_mpdu_start tlv (2/5) - " 892 "rxpcu_mpdu_filter_in_category :%x" 893 "sw_frame_group_id:%x " 894 "ndp_frame:%x " 895 "phy_err:%x " 896 "phy_err_during_mpdu_header :%x" 897 "protocol_version_err:%x " 898 "ast_based_lookup_valid:%x " 899 "reserved_9a:%x " 900 "phy_ppdu_id:%x " 901 "ast_index:%x " 902 "sw_peer_id:%x " 903 "mpdu_frame_control_valid:%x " 904 "mpdu_duration_valid:%x " 905 "mac_addr_ad1_valid:%x " 906 "mac_addr_ad2_valid:%x " 907 "mac_addr_ad3_valid:%x " 908 "mac_addr_ad4_valid:%x " 909 "mpdu_sequence_control_valid :%x" 910 "mpdu_qos_control_valid:%x " 911 "mpdu_ht_control_valid:%x " 912 "frame_encryption_info_valid :%x", 913 mpdu_info->rxpcu_mpdu_filter_in_category, 914 mpdu_info->sw_frame_group_id, 915 mpdu_info->ndp_frame, 916 mpdu_info->phy_err, 917 mpdu_info->phy_err_during_mpdu_header, 918 mpdu_info->protocol_version_err, 919 mpdu_info->ast_based_lookup_valid, 920 mpdu_info->reserved_9a, 921 mpdu_info->phy_ppdu_id, 922 mpdu_info->ast_index, 923 mpdu_info->sw_peer_id, 924 mpdu_info->mpdu_frame_control_valid, 925 mpdu_info->mpdu_duration_valid, 926 mpdu_info->mac_addr_ad1_valid, 927 mpdu_info->mac_addr_ad2_valid, 928 mpdu_info->mac_addr_ad3_valid, 929 mpdu_info->mac_addr_ad4_valid, 930 mpdu_info->mpdu_sequence_control_valid, 931 mpdu_info->mpdu_qos_control_valid, 932 mpdu_info->mpdu_ht_control_valid, 933 mpdu_info->frame_encryption_info_valid); 934 935 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 936 "rx_mpdu_start tlv (3/5) - " 937 "mpdu_fragment_number:%x " 938 "more_fragment_flag:%x " 939 "reserved_11a:%x " 940 "fr_ds:%x " 941 "to_ds:%x " 942 "encrypted:%x " 943 "mpdu_retry:%x " 944 "mpdu_sequence_number:%x " 945 "key_id_octet:%x " 946 "new_peer_entry:%x " 947 "decrypt_needed:%x " 948 "decap_type:%x " 949 "rx_insert_vlan_c_tag_padding :%x" 950 "rx_insert_vlan_s_tag_padding :%x" 951 "strip_vlan_c_tag_decap:%x " 952 "strip_vlan_s_tag_decap:%x " 953 "pre_delim_count:%x " 954 "ampdu_flag:%x " 955 "bar_frame:%x " 956 "raw_mpdu:%x " 957 "reserved_12:%x " 958 "mpdu_length:%x ", 959 mpdu_info->mpdu_fragment_number, 960 mpdu_info->more_fragment_flag, 961 mpdu_info->reserved_11a, 962 mpdu_info->fr_ds, 963 mpdu_info->to_ds, 964 mpdu_info->encrypted, 965 mpdu_info->mpdu_retry, 966 mpdu_info->mpdu_sequence_number, 967 mpdu_info->key_id_octet, 968 mpdu_info->new_peer_entry, 969 mpdu_info->decrypt_needed, 970 mpdu_info->decap_type, 971 mpdu_info->rx_insert_vlan_c_tag_padding, 972 mpdu_info->rx_insert_vlan_s_tag_padding, 973 mpdu_info->strip_vlan_c_tag_decap, 974 mpdu_info->strip_vlan_s_tag_decap, 975 mpdu_info->pre_delim_count, 976 mpdu_info->ampdu_flag, 977 mpdu_info->bar_frame, 978 mpdu_info->raw_mpdu, 979 mpdu_info->reserved_12, 980 mpdu_info->mpdu_length); 981 982 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 983 "rx_mpdu_start tlv (4/5) - " 984 "mpdu_length:%x " 985 "first_mpdu:%x " 986 "mcast_bcast:%x " 987 "ast_index_not_found:%x " 988 "ast_index_timeout:%x " 989 "power_mgmt:%x " 990 "non_qos:%x " 991 "null_data:%x " 992 "mgmt_type:%x " 993 "ctrl_type:%x " 994 "more_data:%x " 995 "eosp:%x " 996 "fragment_flag:%x " 997 "order:%x " 998 "u_apsd_trigger:%x " 999 "encrypt_required:%x " 1000 "directed:%x " 1001 "amsdu_present:%x " 1002 "reserved_13:%x " 1003 "mpdu_frame_control_field:%x " 1004 "mpdu_duration_field:%x ", 1005 mpdu_info->mpdu_length, 1006 mpdu_info->first_mpdu, 1007 mpdu_info->mcast_bcast, 1008 mpdu_info->ast_index_not_found, 1009 mpdu_info->ast_index_timeout, 1010 mpdu_info->power_mgmt, 1011 mpdu_info->non_qos, 1012 mpdu_info->null_data, 1013 mpdu_info->mgmt_type, 1014 mpdu_info->ctrl_type, 1015 mpdu_info->more_data, 1016 mpdu_info->eosp, 1017 mpdu_info->fragment_flag, 1018 mpdu_info->order, 1019 mpdu_info->u_apsd_trigger, 1020 mpdu_info->encrypt_required, 1021 mpdu_info->directed, 1022 mpdu_info->amsdu_present, 1023 mpdu_info->reserved_13, 1024 mpdu_info->mpdu_frame_control_field, 1025 mpdu_info->mpdu_duration_field); 1026 1027 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL, 1028 "rx_mpdu_start tlv (5/5) - " 1029 "mac_addr_ad1_31_0:%x " 1030 "mac_addr_ad1_47_32:%x " 1031 "mac_addr_ad2_15_0:%x " 1032 "mac_addr_ad2_47_16:%x " 1033 "mac_addr_ad3_31_0:%x " 1034 "mac_addr_ad3_47_32:%x " 1035 "mpdu_sequence_control_field :%x" 1036 "mac_addr_ad4_31_0:%x " 1037 "mac_addr_ad4_47_32:%x " 1038 "mpdu_qos_control_field:%x " 1039 "mpdu_ht_control_field:%x " 1040 "vdev_id:%x " 1041 "service_code:%x " 1042 "priority_valid:%x " 1043 "reserved_23a:%x ", 1044 mpdu_info->mac_addr_ad1_31_0, 1045 mpdu_info->mac_addr_ad1_47_32, 1046 mpdu_info->mac_addr_ad2_15_0, 1047 mpdu_info->mac_addr_ad2_47_16, 1048 mpdu_info->mac_addr_ad3_31_0, 1049 mpdu_info->mac_addr_ad3_47_32, 1050 mpdu_info->mpdu_sequence_control_field, 1051 mpdu_info->mac_addr_ad4_31_0, 1052 mpdu_info->mac_addr_ad4_47_32, 1053 mpdu_info->mpdu_qos_control_field, 1054 mpdu_info->mpdu_ht_control_field, 1055 mpdu_info->vdev_id, 1056 mpdu_info->service_code, 1057 mpdu_info->priority_valid, 1058 mpdu_info->reserved_23a); 1059 } 1060 1061 /** 1062 * hal_rx_dump_pkt_tlvs_kiwi(): API to print RX Pkt TLVS for kiwi 1063 * @hal_soc_hdl: hal_soc handle 1064 * @buf: pointer the pkt buffer 1065 * @dbg_level: log level 1066 * 1067 * Return: void 1068 */ 1069 static void hal_rx_dump_pkt_tlvs_kiwi(hal_soc_handle_t hal_soc_hdl, 1070 uint8_t *buf, uint8_t dbg_level) 1071 { 1072 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1073 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1074 struct rx_mpdu_start *mpdu_start = 1075 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1076 1077 hal_rx_dump_msdu_end_tlv_kiwi(msdu_end, dbg_level); 1078 hal_rx_dump_mpdu_start_tlv_kiwi(mpdu_start, dbg_level); 1079 hal_rx_dump_pkt_hdr_tlv_kiwi(pkt_tlvs, dbg_level); 1080 } 1081 1082 /** 1083 * hal_rx_tlv_populate_mpdu_desc_info_kiwi() - Populate the local mpdu_desc_info 1084 * elements from the rx tlvs 1085 * @buf: start address of rx tlvs [Validated by caller] 1086 * @mpdu_desc_info_hdl: Buffer to populate the mpdu_dsc_info 1087 * [To be validated by caller] 1088 * 1089 * Return: None 1090 */ 1091 static void 1092 hal_rx_tlv_populate_mpdu_desc_info_kiwi(uint8_t *buf, 1093 void *mpdu_desc_info_hdl) 1094 { 1095 struct hal_rx_mpdu_desc_info *mpdu_desc_info = 1096 (struct hal_rx_mpdu_desc_info *)mpdu_desc_info_hdl; 1097 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1098 struct rx_mpdu_start *mpdu_start = 1099 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1100 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1101 1102 mpdu_desc_info->mpdu_seq = mpdu_info->mpdu_sequence_number; 1103 mpdu_desc_info->mpdu_flags = hal_rx_get_mpdu_flags((uint32_t *) 1104 mpdu_info); 1105 mpdu_desc_info->peer_meta_data = mpdu_info->peer_meta_data; 1106 mpdu_desc_info->bar_frame = mpdu_info->bar_frame; 1107 } 1108 1109 /** 1110 * hal_reo_status_get_header_kiwi - Process reo desc info 1111 * @d - Pointer to reo descriptior 1112 * @b - tlv type info 1113 * @h1 - Pointer to hal_reo_status_header where info to be stored 1114 * 1115 * Return - none. 1116 * 1117 */ 1118 static void hal_reo_status_get_header_kiwi(hal_ring_desc_t ring_desc, int b, 1119 void *h1) 1120 { 1121 uint64_t *d = (uint64_t *)ring_desc; 1122 uint64_t val1 = 0; 1123 struct hal_reo_status_header *h = 1124 (struct hal_reo_status_header *)h1; 1125 1126 /* Offsets of descriptor fields defined in HW headers start 1127 * from the field after TLV header 1128 */ 1129 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr)); 1130 1131 switch (b) { 1132 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1133 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1134 STATUS_HEADER_REO_STATUS_NUMBER)]; 1135 break; 1136 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1137 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1138 STATUS_HEADER_REO_STATUS_NUMBER)]; 1139 break; 1140 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1141 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1142 STATUS_HEADER_REO_STATUS_NUMBER)]; 1143 break; 1144 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1145 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1146 STATUS_HEADER_REO_STATUS_NUMBER)]; 1147 break; 1148 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1149 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1150 STATUS_HEADER_REO_STATUS_NUMBER)]; 1151 break; 1152 case HAL_REO_DESC_THRES_STATUS_TLV: 1153 val1 = 1154 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1155 STATUS_HEADER_REO_STATUS_NUMBER)]; 1156 break; 1157 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1158 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1159 STATUS_HEADER_REO_STATUS_NUMBER)]; 1160 break; 1161 default: 1162 qdf_nofl_err("ERROR: Unknown tlv\n"); 1163 break; 1164 } 1165 h->cmd_num = 1166 HAL_GET_FIELD( 1167 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER, 1168 val1); 1169 h->exec_time = 1170 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1171 CMD_EXECUTION_TIME, val1); 1172 h->status = 1173 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, 1174 REO_CMD_EXECUTION_STATUS, val1); 1175 switch (b) { 1176 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1177 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, 1178 STATUS_HEADER_TIMESTAMP)]; 1179 break; 1180 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1181 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS, 1182 STATUS_HEADER_TIMESTAMP)]; 1183 break; 1184 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1185 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS, 1186 STATUS_HEADER_TIMESTAMP)]; 1187 break; 1188 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1189 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS, 1190 STATUS_HEADER_TIMESTAMP)]; 1191 break; 1192 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1193 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS, 1194 STATUS_HEADER_TIMESTAMP)]; 1195 break; 1196 case HAL_REO_DESC_THRES_STATUS_TLV: 1197 val1 = 1198 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS, 1199 STATUS_HEADER_TIMESTAMP)]; 1200 break; 1201 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1202 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS, 1203 STATUS_HEADER_TIMESTAMP)]; 1204 break; 1205 default: 1206 qdf_nofl_err("ERROR: Unknown tlv\n"); 1207 break; 1208 } 1209 h->tstamp = 1210 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1); 1211 } 1212 1213 static 1214 void *hal_rx_msdu0_buffer_addr_lsb_kiwi(void *link_desc_va) 1215 { 1216 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1217 } 1218 1219 static 1220 void *hal_rx_msdu_desc_info_ptr_get_kiwi(void *msdu0) 1221 { 1222 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1223 } 1224 1225 static 1226 void *hal_ent_mpdu_desc_info_kiwi(void *ent_ring_desc) 1227 { 1228 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1229 } 1230 1231 static 1232 void *hal_dst_mpdu_desc_info_kiwi(void *dst_ring_desc) 1233 { 1234 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1235 } 1236 1237 /* 1238 * hal_rx_get_tlv_kiwi(): API to get the tlv 1239 * 1240 * @rx_tlv: TLV data extracted from the rx packet 1241 * Return: uint8_t 1242 */ 1243 static uint8_t hal_rx_get_tlv_kiwi(void *rx_tlv) 1244 { 1245 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH); 1246 } 1247 1248 /** 1249 * hal_rx_proc_phyrx_other_receive_info_tlv_kiwi() 1250 * - process other receive info TLV 1251 * @rx_tlv_hdr: pointer to TLV header 1252 * @ppdu_info: pointer to ppdu_info 1253 * 1254 * Return: None 1255 */ 1256 static 1257 void hal_rx_proc_phyrx_other_receive_info_tlv_kiwi(void *rx_tlv_hdr, 1258 void *ppdu_info_handle) 1259 { 1260 uint32_t tlv_tag, tlv_len; 1261 uint32_t temp_len, other_tlv_len, other_tlv_tag; 1262 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 1263 void *other_tlv_hdr = NULL; 1264 void *other_tlv = NULL; 1265 1266 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 1267 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 1268 temp_len = 0; 1269 1270 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; 1271 1272 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); 1273 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); 1274 temp_len += other_tlv_len; 1275 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; 1276 1277 switch (other_tlv_tag) { 1278 default: 1279 hal_err_rl("unhandled TLV type: %d, TLV len:%d", 1280 other_tlv_tag, other_tlv_len); 1281 break; 1282 } 1283 } 1284 1285 /** 1286 * hal_reo_config_kiwi(): Set reo config parameters 1287 * @soc: hal soc handle 1288 * @reg_val: value to be set 1289 * @reo_params: reo parameters 1290 * 1291 * Return: void 1292 */ 1293 static 1294 void hal_reo_config_kiwi(struct hal_soc *soc, 1295 uint32_t reg_val, 1296 struct hal_reo_params *reo_params) 1297 { 1298 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1299 } 1300 1301 /** 1302 * hal_rx_msdu_desc_info_get_ptr_kiwi() - Get msdu desc info ptr 1303 * @msdu_details_ptr - Pointer to msdu_details_ptr 1304 * 1305 * Return - Pointer to rx_msdu_desc_info structure. 1306 * 1307 */ 1308 static void *hal_rx_msdu_desc_info_get_ptr_kiwi(void *msdu_details_ptr) 1309 { 1310 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1311 } 1312 1313 /** 1314 * hal_rx_link_desc_msdu0_ptr_kiwi - Get pointer to rx_msdu details 1315 * @link_desc - Pointer to link desc 1316 * 1317 * Return - Pointer to rx_msdu_details structure 1318 * 1319 */ 1320 static void *hal_rx_link_desc_msdu0_ptr_kiwi(void *link_desc) 1321 { 1322 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1323 } 1324 1325 /** 1326 * hal_get_window_address_kiwi(): Function to get hp/tp address 1327 * @hal_soc: Pointer to hal_soc 1328 * @addr: address offset of register 1329 * 1330 * Return: modified address offset of register 1331 */ 1332 static inline qdf_iomem_t hal_get_window_address_kiwi(struct hal_soc *hal_soc, 1333 qdf_iomem_t addr) 1334 { 1335 return addr; 1336 } 1337 1338 /** 1339 * hal_reo_set_err_dst_remap_kiwi(): Function to set REO error destination 1340 * ring remap register 1341 * @hal_soc: Pointer to hal_soc 1342 * 1343 * Return: none. 1344 */ 1345 static void 1346 hal_reo_set_err_dst_remap_kiwi(void *hal_soc) 1347 { 1348 /* 1349 * Set REO error 2k jump (error code 5) / OOR (error code 7) 1350 * frame routed to REO2SW0 ring. 1351 */ 1352 uint32_t dst_remap_ix0 = 1353 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 0) | 1354 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 1) | 1355 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 2) | 1356 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 3) | 1357 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 4) | 1358 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) | 1359 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) | 1360 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7); 1361 1362 uint32_t dst_remap_ix1 = 1363 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 14) | 1364 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 13) | 1365 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 12) | 1366 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 11) | 1367 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 10) | 1368 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 9) | 1369 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 8); 1370 1371 HAL_REG_WRITE(hal_soc, 1372 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1373 REO_REG_REG_BASE), 1374 dst_remap_ix0); 1375 1376 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x", 1377 HAL_REG_READ( 1378 hal_soc, 1379 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR( 1380 REO_REG_REG_BASE))); 1381 1382 HAL_REG_WRITE(hal_soc, 1383 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1384 REO_REG_REG_BASE), 1385 dst_remap_ix1); 1386 1387 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1 0x%x", 1388 HAL_REG_READ( 1389 hal_soc, 1390 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR( 1391 REO_REG_REG_BASE))); 1392 } 1393 1394 /** 1395 * hal_reo_enable_pn_in_dest_kiwi() - Set the REO register to enable previous PN 1396 * for OOR and 2K-jump frames 1397 * @hal_soc: HAL SoC handle 1398 * 1399 * Return: 1, since the register is set. 1400 */ 1401 static uint8_t hal_reo_enable_pn_in_dest_kiwi(void *hal_soc) 1402 { 1403 HAL_REG_WRITE(hal_soc, HWIO_REO_R0_PN_IN_DEST_ADDR(REO_REG_REG_BASE), 1404 1); 1405 return 1; 1406 } 1407 1408 /** 1409 * hal_rx_flow_setup_fse_kiwi() - Setup a flow search entry in HW FST 1410 * @fst: Pointer to the Rx Flow Search Table 1411 * @table_offset: offset into the table where the flow is to be setup 1412 * @flow: Flow Parameters 1413 * 1414 * Flow table entry fields are updated in host byte order, little endian order. 1415 * 1416 * Return: Success/Failure 1417 */ 1418 static void * 1419 hal_rx_flow_setup_fse_kiwi(uint8_t *rx_fst, uint32_t table_offset, 1420 uint8_t *rx_flow) 1421 { 1422 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1423 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1424 uint8_t *fse; 1425 bool fse_valid; 1426 1427 if (table_offset >= fst->max_entries) { 1428 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1429 "HAL FSE table offset %u exceeds max entries %u", 1430 table_offset, fst->max_entries); 1431 return NULL; 1432 } 1433 1434 fse = (uint8_t *)fst->base_vaddr + 1435 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1436 1437 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1438 1439 if (fse_valid) { 1440 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1441 "HAL FSE %pK already valid", fse); 1442 return NULL; 1443 } 1444 1445 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) = 1446 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1447 (flow->tuple_info.src_ip_127_96)); 1448 1449 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) = 1450 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1451 (flow->tuple_info.src_ip_95_64)); 1452 1453 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) = 1454 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1455 (flow->tuple_info.src_ip_63_32)); 1456 1457 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) = 1458 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1459 (flow->tuple_info.src_ip_31_0)); 1460 1461 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) = 1462 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1463 (flow->tuple_info.dest_ip_127_96)); 1464 1465 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) = 1466 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1467 (flow->tuple_info.dest_ip_95_64)); 1468 1469 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) = 1470 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1471 (flow->tuple_info.dest_ip_63_32)); 1472 1473 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) = 1474 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1475 (flow->tuple_info.dest_ip_31_0)); 1476 1477 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT); 1478 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |= 1479 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1480 (flow->tuple_info.dest_port)); 1481 1482 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT); 1483 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |= 1484 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1485 (flow->tuple_info.src_port)); 1486 1487 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL); 1488 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |= 1489 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1490 flow->tuple_info.l4_protocol); 1491 1492 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER); 1493 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |= 1494 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1495 flow->reo_destination_handler); 1496 1497 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 1498 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |= 1499 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1500 1501 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA); 1502 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) = 1503 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1504 (flow->fse_metadata)); 1505 1506 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION); 1507 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |= 1508 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1509 REO_DESTINATION_INDICATION, 1510 flow->reo_destination_indication); 1511 1512 /* Reset all the other fields in FSE */ 1513 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9); 1514 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP); 1515 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT); 1516 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT); 1517 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP); 1518 1519 return fse; 1520 } 1521 1522 /* 1523 * hal_rx_flow_setup_cmem_fse_kiwi() - Setup a flow search entry in HW CMEM FST 1524 * @hal_soc: hal_soc reference 1525 * @cmem_ba: CMEM base address 1526 * @table_offset: offset into the table where the flow is to be setup 1527 * @flow: Flow Parameters 1528 * 1529 * Return: Success/Failure 1530 */ 1531 static uint32_t 1532 hal_rx_flow_setup_cmem_fse_kiwi(struct hal_soc *hal_soc, uint32_t cmem_ba, 1533 uint32_t table_offset, uint8_t *rx_flow) 1534 { 1535 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1536 uint32_t fse_offset; 1537 uint32_t value; 1538 1539 fse_offset = cmem_ba + (table_offset * HAL_RX_FST_ENTRY_SIZE); 1540 1541 /* Reset the Valid bit */ 1542 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1543 VALID), 0); 1544 1545 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96, 1546 (flow->tuple_info.src_ip_127_96)); 1547 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1548 SRC_IP_127_96), value); 1549 1550 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64, 1551 (flow->tuple_info.src_ip_95_64)); 1552 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1553 SRC_IP_95_64), value); 1554 1555 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32, 1556 (flow->tuple_info.src_ip_63_32)); 1557 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1558 SRC_IP_63_32), value); 1559 1560 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0, 1561 (flow->tuple_info.src_ip_31_0)); 1562 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1563 SRC_IP_31_0), value); 1564 1565 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96, 1566 (flow->tuple_info.dest_ip_127_96)); 1567 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1568 DEST_IP_127_96), value); 1569 1570 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64, 1571 (flow->tuple_info.dest_ip_95_64)); 1572 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1573 DEST_IP_95_64), value); 1574 1575 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32, 1576 (flow->tuple_info.dest_ip_63_32)); 1577 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1578 DEST_IP_63_32), value); 1579 1580 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0, 1581 (flow->tuple_info.dest_ip_31_0)); 1582 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1583 DEST_IP_31_0), value); 1584 1585 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT, 1586 (flow->tuple_info.dest_port)); 1587 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT, 1588 (flow->tuple_info.src_port)); 1589 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1590 SRC_PORT), value); 1591 1592 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA, 1593 (flow->fse_metadata)); 1594 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1595 METADATA), value); 1596 1597 /* Reset all the other fields in FSE */ 1598 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1599 MSDU_COUNT), 0); 1600 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1601 MSDU_BYTE_COUNT), 0); 1602 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1603 TIMESTAMP), 0); 1604 1605 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL, 1606 flow->tuple_info.l4_protocol); 1607 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER, 1608 flow->reo_destination_handler); 1609 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, 1610 REO_DESTINATION_INDICATION, 1611 flow->reo_destination_indication); 1612 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1); 1613 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, 1614 L4_PROTOCOL), value); 1615 1616 return fse_offset; 1617 } 1618 1619 /** 1620 * hal_rx_flow_get_cmem_fse_ts_kiwi() - Get timestamp field from CMEM FSE 1621 * @hal_soc: hal_soc reference 1622 * @fse_offset: CMEM FSE offset 1623 * 1624 * Return: Timestamp 1625 */ 1626 static uint32_t hal_rx_flow_get_cmem_fse_ts_kiwi(struct hal_soc *hal_soc, 1627 uint32_t fse_offset) 1628 { 1629 return HAL_CMEM_READ(hal_soc, fse_offset + 1630 HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, TIMESTAMP)); 1631 } 1632 1633 /** 1634 * hal_rx_flow_get_cmem_fse_kiwi() - Get FSE from CMEM 1635 * @hal_soc: hal_soc reference 1636 * @fse_offset: CMEM FSE offset 1637 * @fse: referece where FSE will be copied 1638 * @len: length of FSE 1639 * 1640 * Return: If read is succesfull or not 1641 */ 1642 static void 1643 hal_rx_flow_get_cmem_fse_kiwi(struct hal_soc *hal_soc, uint32_t fse_offset, 1644 uint32_t *fse, qdf_size_t len) 1645 { 1646 int i; 1647 1648 if (len != HAL_RX_FST_ENTRY_SIZE) 1649 return; 1650 1651 for (i = 0; i < NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY; i++) 1652 fse[i] = HAL_CMEM_READ(hal_soc, fse_offset + i * 4); 1653 } 1654 1655 static 1656 void hal_compute_reo_remap_ix2_ix3_kiwi(uint32_t *ring_map, 1657 uint32_t num_rings, uint32_t *remap1, 1658 uint32_t *remap2) 1659 { 1660 1661 switch (num_rings) { 1662 /* should we have all the different possible ring configs */ 1663 default: 1664 case 3: 1665 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1666 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1667 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1668 HAL_REO_REMAP_IX2(ring_map[0], 19) | 1669 HAL_REO_REMAP_IX2(ring_map[1], 20) | 1670 HAL_REO_REMAP_IX2(ring_map[2], 21) | 1671 HAL_REO_REMAP_IX2(ring_map[0], 22) | 1672 HAL_REO_REMAP_IX2(ring_map[1], 23); 1673 1674 *remap2 = HAL_REO_REMAP_IX3(ring_map[2], 24) | 1675 HAL_REO_REMAP_IX3(ring_map[0], 25) | 1676 HAL_REO_REMAP_IX3(ring_map[1], 26) | 1677 HAL_REO_REMAP_IX3(ring_map[2], 27) | 1678 HAL_REO_REMAP_IX3(ring_map[0], 28) | 1679 HAL_REO_REMAP_IX3(ring_map[1], 29) | 1680 HAL_REO_REMAP_IX3(ring_map[2], 30) | 1681 HAL_REO_REMAP_IX3(ring_map[0], 31); 1682 break; 1683 case 4: 1684 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1685 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1686 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1687 HAL_REO_REMAP_IX2(ring_map[3], 19) | 1688 HAL_REO_REMAP_IX2(ring_map[0], 20) | 1689 HAL_REO_REMAP_IX2(ring_map[1], 21) | 1690 HAL_REO_REMAP_IX2(ring_map[2], 22) | 1691 HAL_REO_REMAP_IX2(ring_map[3], 23); 1692 1693 *remap2 = HAL_REO_REMAP_IX3(ring_map[0], 24) | 1694 HAL_REO_REMAP_IX3(ring_map[1], 25) | 1695 HAL_REO_REMAP_IX3(ring_map[2], 26) | 1696 HAL_REO_REMAP_IX3(ring_map[3], 27) | 1697 HAL_REO_REMAP_IX3(ring_map[0], 28) | 1698 HAL_REO_REMAP_IX3(ring_map[1], 29) | 1699 HAL_REO_REMAP_IX3(ring_map[2], 30) | 1700 HAL_REO_REMAP_IX3(ring_map[3], 31); 1701 break; 1702 case 6: 1703 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1704 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1705 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1706 HAL_REO_REMAP_IX2(ring_map[3], 19) | 1707 HAL_REO_REMAP_IX2(ring_map[4], 20) | 1708 HAL_REO_REMAP_IX2(ring_map[5], 21) | 1709 HAL_REO_REMAP_IX2(ring_map[0], 22) | 1710 HAL_REO_REMAP_IX2(ring_map[1], 23); 1711 1712 *remap2 = HAL_REO_REMAP_IX3(ring_map[2], 24) | 1713 HAL_REO_REMAP_IX3(ring_map[3], 25) | 1714 HAL_REO_REMAP_IX3(ring_map[4], 26) | 1715 HAL_REO_REMAP_IX3(ring_map[5], 27) | 1716 HAL_REO_REMAP_IX3(ring_map[0], 28) | 1717 HAL_REO_REMAP_IX3(ring_map[1], 29) | 1718 HAL_REO_REMAP_IX3(ring_map[2], 30) | 1719 HAL_REO_REMAP_IX3(ring_map[3], 31); 1720 break; 1721 case 8: 1722 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) | 1723 HAL_REO_REMAP_IX2(ring_map[1], 17) | 1724 HAL_REO_REMAP_IX2(ring_map[2], 18) | 1725 HAL_REO_REMAP_IX2(ring_map[3], 19) | 1726 HAL_REO_REMAP_IX2(ring_map[4], 20) | 1727 HAL_REO_REMAP_IX2(ring_map[5], 21) | 1728 HAL_REO_REMAP_IX2(ring_map[6], 22) | 1729 HAL_REO_REMAP_IX2(ring_map[7], 23); 1730 1731 *remap2 = HAL_REO_REMAP_IX3(ring_map[0], 24) | 1732 HAL_REO_REMAP_IX3(ring_map[1], 25) | 1733 HAL_REO_REMAP_IX3(ring_map[2], 26) | 1734 HAL_REO_REMAP_IX3(ring_map[3], 27) | 1735 HAL_REO_REMAP_IX3(ring_map[4], 28) | 1736 HAL_REO_REMAP_IX3(ring_map[5], 29) | 1737 HAL_REO_REMAP_IX3(ring_map[6], 30) | 1738 HAL_REO_REMAP_IX3(ring_map[7], 31); 1739 break; 1740 } 1741 } 1742 1743 /* NUM TCL Bank registers in KIWI */ 1744 #define HAL_NUM_TCL_BANKS_KIWI 8 1745 1746 /** 1747 * hal_tx_get_num_tcl_banks_kiwi() - Get number of banks in target 1748 * 1749 * Returns: number of bank 1750 */ 1751 static uint8_t hal_tx_get_num_tcl_banks_kiwi(void) 1752 { 1753 return HAL_NUM_TCL_BANKS_KIWI; 1754 } 1755 1756 /** 1757 * hal_rx_reo_prev_pn_get_kiwi() - Get the previous PN from the REO ring desc. 1758 * @ring_desc: REO ring descriptor [To be validated by caller ] 1759 * @prev_pn: Buffer where the previous PN is to be populated. 1760 * [To be validated by caller] 1761 * 1762 * Return: None 1763 */ 1764 static void hal_rx_reo_prev_pn_get_kiwi(void *ring_desc, 1765 uint64_t *prev_pn) 1766 { 1767 struct reo_destination_ring_with_pn *reo_desc = 1768 (struct reo_destination_ring_with_pn *)ring_desc; 1769 1770 *prev_pn = reo_desc->prev_pn_23_0; 1771 *prev_pn |= ((uint64_t)reo_desc->prev_pn_55_24 << 24); 1772 } 1773 1774 /** 1775 * hal_cmem_write_kiwi() - function for CMEM buffer writing 1776 * @hal_soc_hdl: HAL SOC handle 1777 * @offset: CMEM address 1778 * @value: value to write 1779 * 1780 * Return: None. 1781 */ 1782 static inline void hal_cmem_write_kiwi(hal_soc_handle_t hal_soc_hdl, 1783 uint32_t offset, 1784 uint32_t value) 1785 { 1786 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1787 1788 hal_write32_mb(hal, offset, value); 1789 } 1790 1791 /** 1792 * hal_get_idle_link_bm_id_kiwi() - Get idle link BM id from chid_id 1793 * @chip_id: mlo chip_id 1794 * 1795 * Returns: RBM ID 1796 */ 1797 static uint8_t hal_get_idle_link_bm_id_kiwi(uint8_t chip_id) 1798 { 1799 return WBM_IDLE_DESC_LIST; 1800 } 1801 1802 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 1803 /** 1804 * hal_get_first_wow_wakeup_packet_kiwi(): Function to get if the buffer 1805 * is the first one that wakes up host from WoW. 1806 * 1807 * @buf: network buffer 1808 * 1809 * Dummy function for KIWI 1810 * 1811 * Returns: 1 to indicate it is first packet received that wakes up host from 1812 * WoW. Otherwise 0 1813 */ 1814 static inline uint8_t hal_get_first_wow_wakeup_packet_kiwi(uint8_t *buf) 1815 { 1816 return 0; 1817 } 1818 #endif 1819 1820 static uint16_t hal_get_rx_max_ba_window_kiwi(int tid) 1821 { 1822 return HAL_RX_BA_WINDOW_1024; 1823 } 1824 1825 /** 1826 * hal_get_reo_qdesc_size_kiwi()- Get the reo queue descriptor size 1827 * from the give Block-Ack window size 1828 * Return: reo queue descriptor size 1829 */ 1830 static uint32_t hal_get_reo_qdesc_size_kiwi(uint32_t ba_window_size, int tid) 1831 { 1832 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 1833 * NON_QOS_TID until HW issues are resolved. 1834 */ 1835 if (tid != HAL_NON_QOS_TID) 1836 ba_window_size = hal_get_rx_max_ba_window_kiwi(tid); 1837 1838 /* Return descriptor size corresponding to window size of 2 since 1839 * we set ba_window_size to 2 while setting up REO descriptors as 1840 * a WAR to get 2k jump exception aggregates are received without 1841 * a BA session. 1842 */ 1843 if (ba_window_size <= 1) { 1844 if (tid != HAL_NON_QOS_TID) 1845 return sizeof(struct rx_reo_queue) + 1846 sizeof(struct rx_reo_queue_ext); 1847 else 1848 return sizeof(struct rx_reo_queue); 1849 } 1850 1851 if (ba_window_size <= 105) 1852 return sizeof(struct rx_reo_queue) + 1853 sizeof(struct rx_reo_queue_ext); 1854 1855 if (ba_window_size <= 210) 1856 return sizeof(struct rx_reo_queue) + 1857 (2 * sizeof(struct rx_reo_queue_ext)); 1858 1859 if (ba_window_size <= 256) 1860 return sizeof(struct rx_reo_queue) + 1861 (3 * sizeof(struct rx_reo_queue_ext)); 1862 1863 return sizeof(struct rx_reo_queue) + 1864 (10 * sizeof(struct rx_reo_queue_ext)) + 1865 sizeof(struct rx_reo_queue_1k); 1866 } 1867 1868 static void hal_hw_txrx_ops_attach_kiwi(struct hal_soc *hal_soc) 1869 { 1870 /* init and setup */ 1871 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1872 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1873 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1874 hal_soc->ops->hal_get_window_address = hal_get_window_address_kiwi; 1875 hal_soc->ops->hal_reo_set_err_dst_remap = 1876 hal_reo_set_err_dst_remap_kiwi; 1877 hal_soc->ops->hal_reo_enable_pn_in_dest = 1878 hal_reo_enable_pn_in_dest_kiwi; 1879 /* Overwrite the default BE ops */ 1880 hal_soc->ops->hal_get_rx_max_ba_window = hal_get_rx_max_ba_window_kiwi; 1881 hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_kiwi; 1882 1883 /* tx */ 1884 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_kiwi; 1885 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_kiwi; 1886 hal_soc->ops->hal_tx_comp_get_status = 1887 hal_tx_comp_get_status_generic_be; 1888 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1889 hal_tx_init_cmd_credit_ring_kiwi; 1890 hal_soc->ops->hal_tx_config_rbm_mapping_be = 1891 hal_tx_config_rbm_mapping_be_kiwi; 1892 1893 /* rx */ 1894 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; 1895 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1896 hal_rx_mon_hw_desc_get_mpdu_status_be; 1897 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_kiwi; 1898 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be; 1899 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1900 hal_rx_proc_phyrx_other_receive_info_tlv_kiwi; 1901 1902 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_kiwi; 1903 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1904 hal_rx_dump_mpdu_start_tlv_kiwi; 1905 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_kiwi; 1906 hal_soc->ops->hal_rx_desc_get_80211_hdr = hal_rx_desc_get_80211_hdr_be; 1907 1908 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_kiwi; 1909 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be; 1910 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1911 hal_rx_tlv_reception_type_get_be; 1912 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1913 hal_rx_msdu_end_da_idx_get_be; 1914 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1915 hal_rx_msdu_desc_info_get_ptr_kiwi; 1916 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1917 hal_rx_link_desc_msdu0_ptr_kiwi; 1918 hal_soc->ops->hal_reo_status_get_header = 1919 hal_reo_status_get_header_kiwi; 1920 hal_soc->ops->hal_rx_status_get_tlv_info = 1921 hal_rx_status_get_tlv_info_wrapper_be; 1922 hal_soc->ops->hal_rx_wbm_err_info_get = 1923 hal_rx_wbm_err_info_get_generic_be; 1924 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1925 hal_rx_priv_info_set_in_tlv_be; 1926 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1927 hal_rx_priv_info_get_from_tlv_be; 1928 1929 hal_soc->ops->hal_tx_set_pcp_tid_map = 1930 hal_tx_set_pcp_tid_map_generic_be; 1931 hal_soc->ops->hal_tx_update_pcp_tid_map = 1932 hal_tx_update_pcp_tid_generic_be; 1933 hal_soc->ops->hal_tx_set_tidmap_prty = 1934 hal_tx_update_tidmap_prty_generic_be; 1935 hal_soc->ops->hal_rx_get_rx_fragment_number = 1936 hal_rx_get_rx_fragment_number_be; 1937 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1938 hal_rx_tlv_da_is_mcbc_get_be; 1939 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1940 hal_rx_tlv_sa_is_valid_get_be; 1941 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be, 1942 hal_soc->ops->hal_rx_desc_is_first_msdu = 1943 hal_rx_desc_is_first_msdu_be; 1944 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1945 hal_rx_tlv_l3_hdr_padding_get_be; 1946 hal_soc->ops->hal_rx_encryption_info_valid = 1947 hal_rx_encryption_info_valid_be; 1948 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; 1949 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1950 hal_rx_tlv_first_msdu_get_be; 1951 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1952 hal_rx_tlv_da_is_valid_get_be; 1953 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1954 hal_rx_tlv_last_msdu_get_be; 1955 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1956 hal_rx_get_mpdu_mac_ad4_valid_be; 1957 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1958 hal_rx_mpdu_start_sw_peer_id_get_be; 1959 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1960 hal_rx_mpdu_peer_meta_data_get_be; 1961 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be; 1962 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be; 1963 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1964 hal_rx_get_mpdu_frame_control_valid_be; 1965 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be; 1966 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be; 1967 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be; 1968 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; 1969 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1970 hal_rx_get_mpdu_sequence_control_valid_be; 1971 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be; 1972 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; 1973 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1974 hal_rx_hw_desc_get_ppduid_get_be; 1975 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1976 hal_rx_msdu0_buffer_addr_lsb_kiwi; 1977 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1978 hal_rx_msdu_desc_info_ptr_get_kiwi; 1979 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_kiwi; 1980 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_kiwi; 1981 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; 1982 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; 1983 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1984 hal_rx_get_mac_addr2_valid_be; 1985 hal_soc->ops->hal_rx_get_filter_category = 1986 hal_rx_get_filter_category_be; 1987 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be; 1988 hal_soc->ops->hal_reo_config = hal_reo_config_kiwi; 1989 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; 1990 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1991 hal_rx_msdu_flow_idx_invalid_be; 1992 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1993 hal_rx_msdu_flow_idx_timeout_be; 1994 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1995 hal_rx_msdu_fse_metadata_get_be; 1996 hal_soc->ops->hal_rx_msdu_cce_match_get = 1997 hal_rx_msdu_cce_match_get_be; 1998 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1999 hal_rx_msdu_cce_metadata_get_be; 2000 hal_soc->ops->hal_rx_msdu_get_flow_params = 2001 hal_rx_msdu_get_flow_params_be; 2002 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 2003 hal_rx_tlv_get_tcp_chksum_be; 2004 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be; 2005 #if defined(QCA_WIFI_KIWI) && defined(WLAN_CFR_ENABLE) && \ 2006 defined(WLAN_ENH_CFR_ENABLE) 2007 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_kiwi; 2008 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_kiwi; 2009 #else 2010 hal_soc->ops->hal_rx_get_bb_info = NULL; 2011 hal_soc->ops->hal_rx_get_rtt_info = NULL; 2012 #endif 2013 /* rx - msdu end fast path info fields */ 2014 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 2015 hal_rx_msdu_packet_metadata_get_generic_be; 2016 hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum = 2017 hal_rx_get_fisa_cumulative_l4_checksum_be; 2018 hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length = 2019 hal_rx_get_fisa_cumulative_ip_length_be; 2020 hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_be; 2021 hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation = 2022 hal_rx_get_flow_agg_continuation_be; 2023 hal_soc->ops->hal_rx_get_fisa_flow_agg_count = 2024 hal_rx_get_flow_agg_count_be; 2025 hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_be; 2026 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 2027 hal_rx_mpdu_start_tlv_tag_valid_be; 2028 hal_soc->ops->hal_rx_reo_prev_pn_get = hal_rx_reo_prev_pn_get_kiwi; 2029 2030 /* rx - TLV struct offsets */ 2031 hal_register_rx_pkt_hdr_tlv_api_kiwi(hal_soc); 2032 hal_soc->ops->hal_rx_msdu_end_offset_get = 2033 hal_rx_msdu_end_offset_get_generic; 2034 hal_soc->ops->hal_rx_mpdu_start_offset_get = 2035 hal_rx_mpdu_start_offset_get_generic; 2036 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_kiwi; 2037 hal_soc->ops->hal_rx_flow_get_tuple_info = 2038 hal_rx_flow_get_tuple_info_be; 2039 hal_soc->ops->hal_rx_flow_delete_entry = 2040 hal_rx_flow_delete_entry_be; 2041 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be; 2042 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 2043 hal_compute_reo_remap_ix2_ix3_kiwi; 2044 hal_soc->ops->hal_rx_flow_setup_cmem_fse = 2045 hal_rx_flow_setup_cmem_fse_kiwi; 2046 hal_soc->ops->hal_rx_flow_get_cmem_fse_ts = 2047 hal_rx_flow_get_cmem_fse_ts_kiwi; 2048 hal_soc->ops->hal_rx_flow_get_cmem_fse = hal_rx_flow_get_cmem_fse_kiwi; 2049 hal_soc->ops->hal_cmem_write = hal_cmem_write_kiwi; 2050 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = 2051 hal_rx_msdu_get_reo_destination_indication_be; 2052 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_kiwi; 2053 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; 2054 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 2055 hal_rx_msdu_is_wlan_mcast_generic_be; 2056 hal_soc->ops->hal_rx_tlv_bw_get = 2057 hal_rx_tlv_bw_get_be; 2058 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 2059 hal_rx_tlv_get_is_decrypted_be; 2060 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be; 2061 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be; 2062 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 2063 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; 2064 hal_soc->ops->hal_rx_tlv_mpdu_len_err_get = 2065 hal_rx_tlv_mpdu_len_err_get_be; 2066 hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get = 2067 hal_rx_tlv_mpdu_fcs_err_get_be; 2068 2069 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be; 2070 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 2071 hal_rx_tlv_decrypt_err_get_be; 2072 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; 2073 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; 2074 hal_soc->ops->hal_rx_tlv_decap_format_get = 2075 hal_rx_tlv_decap_format_get_be; 2076 hal_soc->ops->hal_rx_tlv_get_offload_info = 2077 hal_rx_tlv_get_offload_info_be; 2078 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 2079 hal_rx_attn_phy_ppdu_id_get_be; 2080 hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_tlv_msdu_done_get_be; 2081 hal_soc->ops->hal_rx_tlv_msdu_len_get = 2082 hal_rx_msdu_start_msdu_len_get_be; 2083 hal_soc->ops->hal_rx_get_frame_ctrl_field = 2084 hal_rx_get_frame_ctrl_field_be; 2085 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be; 2086 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be; 2087 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; 2088 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 2089 hal_rx_mpdu_info_ampdu_flag_get_be; 2090 hal_soc->ops->hal_rx_tlv_msdu_len_set = 2091 hal_rx_msdu_start_msdu_len_set_be; 2092 hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info = 2093 hal_rx_tlv_populate_mpdu_desc_info_kiwi; 2094 hal_soc->ops->hal_rx_tlv_get_pn_num = 2095 hal_rx_tlv_get_pn_num_be; 2096 hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr = 2097 hal_get_reo_ent_desc_qdesc_addr_be; 2098 hal_soc->ops->hal_rx_get_qdesc_addr = 2099 hal_rx_get_qdesc_addr_be; 2100 hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind = 2101 hal_set_reo_ent_desc_reo_dest_ind_be; 2102 hal_soc->ops->hal_get_idle_link_bm_id = hal_get_idle_link_bm_id_kiwi; 2103 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET 2104 hal_soc->ops->hal_get_first_wow_wakeup_packet = 2105 hal_get_first_wow_wakeup_packet_kiwi; 2106 #endif 2107 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 2108 2109 hal_soc->ops->hal_rx_tlv_l3_type_get = hal_rx_tlv_l3_type_get_be; 2110 hal_soc->ops->hal_tx_vdev_mismatch_routing_set = 2111 hal_tx_vdev_mismatch_routing_set_generic_be; 2112 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = 2113 hal_tx_mcast_mlo_reinject_routing_set_generic_be; 2114 hal_soc->ops->hal_get_ba_aging_timeout = 2115 hal_get_ba_aging_timeout_be_generic; 2116 hal_soc->ops->hal_setup_link_idle_list = 2117 hal_setup_link_idle_list_generic_be; 2118 hal_soc->ops->hal_cookie_conversion_reg_cfg_be = 2119 hal_cookie_conversion_reg_cfg_generic_be; 2120 hal_soc->ops->hal_set_ba_aging_timeout = 2121 hal_set_ba_aging_timeout_be_generic; 2122 hal_soc->ops->hal_tx_populate_bank_register = 2123 hal_tx_populate_bank_register_be; 2124 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = 2125 hal_tx_vdev_mcast_ctrl_set_be; 2126 }; 2127 2128 struct hal_hw_srng_config hw_srng_table_kiwi[] = { 2129 /* TODO: max_rings can populated by querying HW capabilities */ 2130 { /* REO_DST */ 2131 .start_ring_id = HAL_SRNG_REO2SW1, 2132 .max_rings = 8, 2133 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2134 .lmac_ring = FALSE, 2135 .ring_dir = HAL_SRNG_DST_RING, 2136 .nf_irq_support = true, 2137 .reg_start = { 2138 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 2139 REO_REG_REG_BASE), 2140 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 2141 REO_REG_REG_BASE) 2142 }, 2143 .reg_size = { 2144 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 2145 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 2146 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 2147 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 2148 }, 2149 .max_size = 2150 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 2151 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 2152 }, 2153 { /* REO_EXCEPTION */ 2154 /* Designating REO2SW0 ring as exception ring. */ 2155 .start_ring_id = HAL_SRNG_REO2SW0, 2156 .max_rings = 1, 2157 .entry_size = sizeof(struct reo_destination_ring) >> 2, 2158 .lmac_ring = FALSE, 2159 .ring_dir = HAL_SRNG_DST_RING, 2160 .reg_start = { 2161 HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR( 2162 REO_REG_REG_BASE), 2163 HWIO_REO_R2_REO2SW0_RING_HP_ADDR( 2164 REO_REG_REG_BASE) 2165 }, 2166 /* Single ring - provide ring size if multiple rings of this 2167 * type are supported 2168 */ 2169 .reg_size = {}, 2170 .max_size = 2171 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >> 2172 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT, 2173 }, 2174 { /* REO_REINJECT */ 2175 .start_ring_id = HAL_SRNG_SW2REO, 2176 .max_rings = 1, 2177 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2178 .lmac_ring = FALSE, 2179 .ring_dir = HAL_SRNG_SRC_RING, 2180 .reg_start = { 2181 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 2182 REO_REG_REG_BASE), 2183 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 2184 REO_REG_REG_BASE) 2185 }, 2186 /* Single ring - provide ring size if multiple rings of this 2187 * type are supported 2188 */ 2189 .reg_size = {}, 2190 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 2191 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 2192 }, 2193 { /* REO_CMD */ 2194 .start_ring_id = HAL_SRNG_REO_CMD, 2195 .max_rings = 1, 2196 .entry_size = (sizeof(struct tlv_32_hdr) + 2197 sizeof(struct reo_get_queue_stats)) >> 2, 2198 .lmac_ring = FALSE, 2199 .ring_dir = HAL_SRNG_SRC_RING, 2200 .reg_start = { 2201 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 2202 REO_REG_REG_BASE), 2203 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 2204 REO_REG_REG_BASE), 2205 }, 2206 /* Single ring - provide ring size if multiple rings of this 2207 * type are supported 2208 */ 2209 .reg_size = {}, 2210 .max_size = 2211 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 2212 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 2213 }, 2214 { /* REO_STATUS */ 2215 .start_ring_id = HAL_SRNG_REO_STATUS, 2216 .max_rings = 1, 2217 .entry_size = (sizeof(struct tlv_32_hdr) + 2218 sizeof(struct reo_get_queue_stats_status)) >> 2, 2219 .lmac_ring = FALSE, 2220 .ring_dir = HAL_SRNG_DST_RING, 2221 .reg_start = { 2222 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2223 REO_REG_REG_BASE), 2224 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2225 REO_REG_REG_BASE), 2226 }, 2227 /* Single ring - provide ring size if multiple rings of this 2228 * type are supported 2229 */ 2230 .reg_size = {}, 2231 .max_size = 2232 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2233 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2234 }, 2235 { /* TCL_DATA */ 2236 .start_ring_id = HAL_SRNG_SW2TCL1, 2237 .max_rings = 5, 2238 .entry_size = sizeof(struct tcl_data_cmd) >> 2, 2239 .lmac_ring = FALSE, 2240 .ring_dir = HAL_SRNG_SRC_RING, 2241 .reg_start = { 2242 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2243 MAC_TCL_REG_REG_BASE), 2244 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2245 MAC_TCL_REG_REG_BASE), 2246 }, 2247 .reg_size = { 2248 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2249 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2250 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2251 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2252 }, 2253 .max_size = 2254 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2255 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2256 }, 2257 { /* TCL_CMD */ 2258 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2259 #ifndef WLAN_DP_DISABLE_TCL_CMD_CRED_SRNG 2260 .max_rings = 1, 2261 #else 2262 .max_rings = 0, 2263 #endif 2264 .entry_size = sizeof(struct tcl_gse_cmd) >> 2, 2265 .lmac_ring = FALSE, 2266 .ring_dir = HAL_SRNG_SRC_RING, 2267 .reg_start = { 2268 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2269 MAC_TCL_REG_REG_BASE), 2270 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2271 MAC_TCL_REG_REG_BASE), 2272 }, 2273 /* Single ring - provide ring size if multiple rings of this 2274 * type are supported 2275 */ 2276 .reg_size = {}, 2277 .max_size = 2278 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2279 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2280 }, 2281 { /* TCL_STATUS */ 2282 .start_ring_id = HAL_SRNG_TCL_STATUS, 2283 #ifndef WLAN_DP_DISABLE_TCL_CMD_CRED_SRNG 2284 .max_rings = 1, 2285 #else 2286 .max_rings = 0, 2287 #endif 2288 /* confirm that TLV header is needed */ 2289 .entry_size = sizeof(struct tcl_status_ring) >> 2, 2290 .lmac_ring = FALSE, 2291 .ring_dir = HAL_SRNG_DST_RING, 2292 .reg_start = { 2293 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2294 MAC_TCL_REG_REG_BASE), 2295 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2296 MAC_TCL_REG_REG_BASE), 2297 }, 2298 /* Single ring - provide ring size if multiple rings of this 2299 * type are supported 2300 */ 2301 .reg_size = {}, 2302 .max_size = 2303 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2304 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2305 }, 2306 { /* CE_SRC */ 2307 .start_ring_id = HAL_SRNG_CE_0_SRC, 2308 .max_rings = 12, 2309 .entry_size = sizeof(struct ce_src_desc) >> 2, 2310 .lmac_ring = FALSE, 2311 .ring_dir = HAL_SRNG_SRC_RING, 2312 .reg_start = { 2313 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, 2314 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, 2315 }, 2316 .reg_size = { 2317 SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 2318 SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 2319 SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE - 2320 SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE, 2321 }, 2322 .max_size = 2323 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >> 2324 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT, 2325 }, 2326 { /* CE_DST */ 2327 .start_ring_id = HAL_SRNG_CE_0_DST, 2328 .max_rings = 12, 2329 .entry_size = 8 >> 2, 2330 /*TODO: entry_size above should actually be 2331 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2332 * of struct ce_dst_desc in HW header files 2333 */ 2334 .lmac_ring = FALSE, 2335 .ring_dir = HAL_SRNG_SRC_RING, 2336 .reg_start = { 2337 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, 2338 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, 2339 }, 2340 .reg_size = { 2341 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2342 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2343 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2344 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2345 }, 2346 .max_size = 2347 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2348 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2349 }, 2350 { /* CE_DST_STATUS */ 2351 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2352 .max_rings = 12, 2353 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2354 .lmac_ring = FALSE, 2355 .ring_dir = HAL_SRNG_DST_RING, 2356 .reg_start = { 2357 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, 2358 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, 2359 }, 2360 .reg_size = { 2361 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2362 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2363 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE - 2364 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE, 2365 }, 2366 .max_size = 2367 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2368 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2369 }, 2370 { /* WBM_IDLE_LINK */ 2371 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2372 .max_rings = 1, 2373 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2374 .lmac_ring = FALSE, 2375 .ring_dir = HAL_SRNG_SRC_RING, 2376 .reg_start = { 2377 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2378 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE), 2379 }, 2380 /* Single ring - provide ring size if multiple rings of this 2381 * type are supported 2382 */ 2383 .reg_size = {}, 2384 .max_size = 2385 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2386 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2387 }, 2388 { /* SW2WBM_RELEASE */ 2389 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2390 .max_rings = 1, 2391 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2392 .lmac_ring = FALSE, 2393 .ring_dir = HAL_SRNG_SRC_RING, 2394 .reg_start = { 2395 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2396 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2397 }, 2398 /* Single ring - provide ring size if multiple rings of this 2399 * type are supported 2400 */ 2401 .reg_size = {}, 2402 .max_size = 2403 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2404 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2405 }, 2406 { /* WBM2SW_RELEASE */ 2407 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2408 .max_rings = 8, 2409 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2410 .lmac_ring = FALSE, 2411 .ring_dir = HAL_SRNG_DST_RING, 2412 .nf_irq_support = true, 2413 .reg_start = { 2414 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2415 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2416 }, 2417 .reg_size = { 2418 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE) - 2419 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), 2420 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE) - 2421 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), 2422 }, 2423 .max_size = 2424 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2425 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2426 }, 2427 { /* RXDMA_BUF */ 2428 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2429 #ifdef IPA_OFFLOAD 2430 .max_rings = 3, 2431 #else 2432 .max_rings = 2, 2433 #endif 2434 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2435 .lmac_ring = TRUE, 2436 .ring_dir = HAL_SRNG_SRC_RING, 2437 /* reg_start is not set because LMAC rings are not accessed 2438 * from host 2439 */ 2440 .reg_start = {}, 2441 .reg_size = {}, 2442 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2443 }, 2444 { /* RXDMA_DST */ 2445 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2446 .max_rings = 1, 2447 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2448 .lmac_ring = TRUE, 2449 .ring_dir = HAL_SRNG_DST_RING, 2450 /* reg_start is not set because LMAC rings are not accessed 2451 * from host 2452 */ 2453 .reg_start = {}, 2454 .reg_size = {}, 2455 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2456 }, 2457 { /* RXDMA_MONITOR_BUF */ 2458 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2459 .max_rings = 1, 2460 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2461 .lmac_ring = TRUE, 2462 .ring_dir = HAL_SRNG_SRC_RING, 2463 /* reg_start is not set because LMAC rings are not accessed 2464 * from host 2465 */ 2466 .reg_start = {}, 2467 .reg_size = {}, 2468 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2469 }, 2470 { /* RXDMA_MONITOR_STATUS */ 2471 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2472 .max_rings = 1, 2473 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2474 .lmac_ring = TRUE, 2475 .ring_dir = HAL_SRNG_SRC_RING, 2476 /* reg_start is not set because LMAC rings are not accessed 2477 * from host 2478 */ 2479 .reg_start = {}, 2480 .reg_size = {}, 2481 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2482 }, 2483 { /* RXDMA_MONITOR_DST */ 2484 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2485 .max_rings = 1, 2486 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2487 .lmac_ring = TRUE, 2488 .ring_dir = HAL_SRNG_DST_RING, 2489 /* reg_start is not set because LMAC rings are not accessed 2490 * from host 2491 */ 2492 .reg_start = {}, 2493 .reg_size = {}, 2494 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2495 }, 2496 { /* RXDMA_MONITOR_DESC */ 2497 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2498 .max_rings = 1, 2499 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2500 .lmac_ring = TRUE, 2501 .ring_dir = HAL_SRNG_SRC_RING, 2502 /* reg_start is not set because LMAC rings are not accessed 2503 * from host 2504 */ 2505 .reg_start = {}, 2506 .reg_size = {}, 2507 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2508 }, 2509 { /* DIR_BUF_RX_DMA_SRC */ 2510 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2511 /* 2512 * one ring is for spectral scan 2513 * the other is for cfr 2514 */ 2515 .max_rings = 2, 2516 .entry_size = 2, 2517 .lmac_ring = TRUE, 2518 .ring_dir = HAL_SRNG_SRC_RING, 2519 /* reg_start is not set because LMAC rings are not accessed 2520 * from host 2521 */ 2522 .reg_start = {}, 2523 .reg_size = {}, 2524 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2525 }, 2526 #ifdef WLAN_FEATURE_CIF_CFR 2527 { /* WIFI_POS_SRC */ 2528 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2529 .max_rings = 1, 2530 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2531 .lmac_ring = TRUE, 2532 .ring_dir = HAL_SRNG_SRC_RING, 2533 /* reg_start is not set because LMAC rings are not accessed 2534 * from host 2535 */ 2536 .reg_start = {}, 2537 .reg_size = {}, 2538 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2539 }, 2540 #endif 2541 { /* REO2PPE */ 0}, 2542 { /* PPE2TCL */ 0}, 2543 { /* PPE_RELEASE */ 0}, 2544 { /* TX_MONITOR_BUF */ 0}, 2545 { /* TX_MONITOR_DST */ 0}, 2546 { /* SW2RXDMA_NEW */ 0}, 2547 }; 2548 2549 /** 2550 * hal_srng_hw_reg_offset_init_kiwi() - Initialize the HW srng reg offset 2551 * applicable only for KIWI 2552 * @hal_soc: HAL Soc handle 2553 * 2554 * Return: None 2555 */ 2556 static inline void hal_srng_hw_reg_offset_init_kiwi(struct hal_soc *hal_soc) 2557 { 2558 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset; 2559 2560 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB), 2561 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB), 2562 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA), 2563 hw_reg_offset[DST_PRODUCER_INT2_SETUP] = 2564 REG_OFFSET(DST, PRODUCER_INT2_SETUP); 2565 } 2566 2567 /** 2568 * hal_kiwi_attach() - Attach kiwi target specific hal_soc ops, 2569 * offset and srng table 2570 */ 2571 void hal_kiwi_attach(struct hal_soc *hal_soc) 2572 { 2573 hal_soc->hw_srng_table = hw_srng_table_kiwi; 2574 2575 hal_srng_hw_reg_offset_init_generic(hal_soc); 2576 hal_srng_hw_reg_offset_init_kiwi(hal_soc); 2577 hal_hw_txrx_default_ops_attach_be(hal_soc); 2578 hal_hw_txrx_ops_attach_kiwi(hal_soc); 2579 } 2580