1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #if !defined(HAL_TX_H) 20 #define HAL_TX_H 21 22 /*--------------------------------------------------------------------------- 23 Include files 24 ---------------------------------------------------------------------------*/ 25 #include "hal_api.h" 26 #include "wcss_version.h" 27 28 #define WBM_RELEASE_RING_5_TX_RATE_STATS_OFFSET 0x00000014 29 #define WBM_RELEASE_RING_5_TX_RATE_STATS_LSB 0 30 #define WBM_RELEASE_RING_5_TX_RATE_STATS_MASK 0xffffffff 31 32 #define HAL_WBM_RELEASE_RING_2_BUFFER_TYPE 0 33 #define HAL_WBM_RELEASE_RING_2_DESC_TYPE 1 34 35 /*--------------------------------------------------------------------------- 36 Preprocessor definitions and constants 37 ---------------------------------------------------------------------------*/ 38 #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET 39 40 #define HAL_SET_FLD(desc, block , field) \ 41 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field))) 42 43 #define HAL_SET_FLD_OFFSET(desc, block , field, offset) \ 44 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field) + (offset))) 45 46 #define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \ 47 do { \ 48 ((struct tlv_32_hdr *) desc)->tlv_tag = (tag); \ 49 ((struct tlv_32_hdr *) desc)->tlv_len = (len); \ 50 } while (0) 51 52 #define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E 53 #define HAL_TX_TCL_CMD_TAG WIFITCL_GSE_CMD_E 54 55 #define HAL_TX_SM(block, field, value) \ 56 ((value << (block ## _ ## field ## _LSB)) & \ 57 (block ## _ ## field ## _MASK)) 58 59 #define HAL_TX_MS(block, field, value) \ 60 (((value) & (block ## _ ## field ## _MASK)) >> \ 61 (block ## _ ## field ## _LSB)) 62 63 #define HAL_TX_DESC_GET(desc, block, field) \ 64 HAL_TX_MS(block, field, HAL_SET_FLD(desc, block, field)) 65 66 #define HAL_TX_DESC_SUBBLOCK_GET(desc, block, sub, field) \ 67 HAL_TX_MS(sub, field, HAL_SET_FLD(desc, block, sub)) 68 69 #define HAL_TX_BUF_TYPE_BUFFER 0 70 #define HAL_TX_BUF_TYPE_EXT_DESC 1 71 72 #define HAL_TX_DESC_LEN_DWORDS (NUM_OF_DWORDS_TCL_DATA_CMD) 73 #define HAL_TX_DESC_LEN_BYTES (NUM_OF_DWORDS_TCL_DATA_CMD * 4) 74 #define HAL_TX_EXTENSION_DESC_LEN_DWORDS (NUM_OF_DWORDS_TX_MSDU_EXTENSION) 75 #define HAL_TX_EXTENSION_DESC_LEN_BYTES (NUM_OF_DWORDS_TX_MSDU_EXTENSION * 4) 76 77 #define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 78 #define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4) 79 #define HAL_TX_BITS_PER_TID 3 80 #define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1) 81 #define HAL_TX_NUM_DSCP_PER_REGISTER 10 82 #define HAL_MAX_HW_DSCP_TID_MAPS 2 83 #define HAL_MAX_HW_DSCP_TID_MAPS_11AX 32 84 85 #define HAL_MAX_HW_DSCP_TID_V2_MAPS 48 86 #define HTT_META_HEADER_LEN_BYTES 64 87 #define HAL_TX_EXT_DESC_WITH_META_DATA \ 88 (HTT_META_HEADER_LEN_BYTES + HAL_TX_EXTENSION_DESC_LEN_BYTES) 89 90 #define HAL_TX_NUM_PCP_PER_REGISTER 8 91 92 /* Length of WBM release ring without the status words */ 93 #define HAL_TX_COMPLETION_DESC_BASE_LEN 12 94 95 #define HAL_TX_COMP_RELEASE_SOURCE_TQM 0 96 #define HAL_TX_COMP_RELEASE_SOURCE_REO 2 97 #define HAL_TX_COMP_RELEASE_SOURCE_FW 3 98 99 /* Define a place-holder release reason for FW */ 100 #define HAL_TX_COMP_RELEASE_REASON_FW 99 101 102 /* 103 * Offset of HTT Tx Descriptor in WBM Completion 104 * HTT Tx Desc structure is passed from firmware to host overlayed 105 * on wbm_release_ring DWORDs 2,3 ,4 and 5for software based completions 106 * (Exception frames and TQM bypass frames) 107 */ 108 #define HAL_TX_COMP_HTT_STATUS_OFFSET 8 109 #define HAL_TX_COMP_HTT_STATUS_LEN 16 110 111 #define HAL_TX_BUF_TYPE_BUFFER 0 112 #define HAL_TX_BUF_TYPE_EXT_DESC 1 113 114 #define HAL_TX_EXT_DESC_BUF_OFFSET TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 115 #define HAL_TX_EXT_BUF_LOW_MASK TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 116 #define HAL_TX_EXT_BUF_HI_MASK TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 117 #define HAL_TX_EXT_BUF_LEN_MASK TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 118 #define HAL_TX_EXT_BUF_LEN_LSB TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 119 #define HAL_TX_EXT_BUF_WD_SIZE 2 120 121 #define HAL_TX_DESC_ADDRX_EN 0x1 122 #define HAL_TX_DESC_ADDRY_EN 0x2 123 #define HAL_TX_DESC_DEFAULT_LMAC_ID 0x3 124 125 #define HAL_TX_ADDR_SEARCH_DEFAULT 0x0 126 #define HAL_TX_ADDR_INDEX_SEARCH 0x1 127 #define HAL_TX_FLOW_INDEX_SEARCH 0x2 128 129 enum hal_tx_ret_buf_manager { 130 HAL_WBM_SW0_BM_ID = 3, 131 HAL_WBM_SW1_BM_ID = 4, 132 HAL_WBM_SW2_BM_ID = 5, 133 HAL_WBM_SW3_BM_ID = 6, 134 }; 135 136 /*--------------------------------------------------------------------------- 137 Structures 138 ---------------------------------------------------------------------------*/ 139 /** 140 * struct hal_tx_completion_status - HAL Tx completion descriptor contents 141 * @status: frame acked/failed 142 * @release_src: release source = TQM/FW 143 * @ack_frame_rssi: RSSI of the received ACK or BA frame 144 * @first_msdu: Indicates this MSDU is the first MSDU in AMSDU 145 * @last_msdu: Indicates this MSDU is the last MSDU in AMSDU 146 * @msdu_part_of_amsdu : Indicates this MSDU was part of an A-MSDU in MPDU 147 * @bw: Indicates the BW of the upcoming transmission - 148 * <enum 0 transmit_bw_20_MHz> 149 * <enum 1 transmit_bw_40_MHz> 150 * <enum 2 transmit_bw_80_MHz> 151 * <enum 3 transmit_bw_160_MHz> 152 * @pkt_type: Transmit Packet Type 153 * @stbc: When set, STBC transmission rate was used 154 * @ldpc: When set, use LDPC transmission rates 155 * @sgi: <enum 0 0_8_us_sgi > Legacy normal GI 156 * <enum 1 0_4_us_sgi > Legacy short GI 157 * <enum 2 1_6_us_sgi > HE related GI 158 * <enum 3 3_2_us_sgi > HE 159 * @mcs: Transmit MCS Rate 160 * @ofdma: Set when the transmission was an OFDMA transmission 161 * @tones_in_ru: The number of tones in the RU used. 162 * @tsf: Lower 32 bits of the TSF 163 * @ppdu_id: TSF, snapshot of this value when transmission of the 164 * PPDU containing the frame finished. 165 * @transmit_cnt: Number of times this frame has been transmitted 166 * @tid: TID of the flow or MPDU queue 167 * @peer_id: Peer ID of the flow or MPDU queue 168 */ 169 struct hal_tx_completion_status { 170 uint8_t status; 171 uint8_t release_src; 172 uint8_t ack_frame_rssi; 173 uint8_t first_msdu:1, 174 last_msdu:1, 175 msdu_part_of_amsdu:1; 176 uint32_t bw:2, 177 pkt_type:4, 178 stbc:1, 179 ldpc:1, 180 sgi:2, 181 mcs:4, 182 ofdma:1, 183 tones_in_ru:12, 184 valid:1; 185 uint32_t tsf; 186 uint32_t ppdu_id; 187 uint8_t transmit_cnt; 188 uint8_t tid; 189 uint16_t peer_id; 190 }; 191 192 /** 193 * struct hal_tx_desc_comp_s - hal tx completion descriptor contents 194 * @desc: Transmit status information from descriptor 195 */ 196 struct hal_tx_desc_comp_s { 197 uint32_t desc[HAL_TX_COMPLETION_DESC_LEN_DWORDS]; 198 }; 199 200 /* 201 * enum hal_tx_encrypt_type - Type of decrypt cipher used (valid only for RAW) 202 * @HAL_TX_ENCRYPT_TYPE_WEP_40: WEP 40-bit 203 * @HAL_TX_ENCRYPT_TYPE_WEP_10: WEP 10-bit 204 * @HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC: TKIP without MIC 205 * @HAL_TX_ENCRYPT_TYPE_WEP_128: WEP_128 206 * @HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC: TKIP_WITH_MIC 207 * @HAL_TX_ENCRYPT_TYPE_WAPI: WAPI 208 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_128: AES_CCMP_128 209 * @HAL_TX_ENCRYPT_TYPE_NO_CIPHER: NO CIPHER 210 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_256: AES_CCMP_256 211 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_128: AES_GCMP_128 212 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_256: AES_GCMP_256 213 * @HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4: WAPI GCM SM4 214 */ 215 enum hal_tx_encrypt_type { 216 HAL_TX_ENCRYPT_TYPE_WEP_40 = 0, 217 HAL_TX_ENCRYPT_TYPE_WEP_104 = 1 , 218 HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC = 2, 219 HAL_TX_ENCRYPT_TYPE_WEP_128 = 3, 220 HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC = 4, 221 HAL_TX_ENCRYPT_TYPE_WAPI = 5, 222 HAL_TX_ENCRYPT_TYPE_AES_CCMP_128 = 6, 223 HAL_TX_ENCRYPT_TYPE_NO_CIPHER = 7, 224 HAL_TX_ENCRYPT_TYPE_AES_CCMP_256 = 8, 225 HAL_TX_ENCRYPT_TYPE_AES_GCMP_128 = 9, 226 HAL_TX_ENCRYPT_TYPE_AES_GCMP_256 = 10, 227 HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4 = 11, 228 }; 229 230 /* 231 * enum hal_tx_encap_type - Encapsulation type that HW will perform 232 * @HAL_TX_ENCAP_TYPE_RAW: Raw Packet Type 233 * @HAL_TX_ENCAP_TYPE_NWIFI: Native WiFi Type 234 * @HAL_TX_ENCAP_TYPE_ETHERNET: Ethernet 235 * @HAL_TX_ENCAP_TYPE_802_3: 802.3 Frame 236 */ 237 enum hal_tx_encap_type { 238 HAL_TX_ENCAP_TYPE_RAW = 0, 239 HAL_TX_ENCAP_TYPE_NWIFI = 1, 240 HAL_TX_ENCAP_TYPE_ETHERNET = 2, 241 HAL_TX_ENCAP_TYPE_802_3 = 3, 242 }; 243 244 /** 245 * enum hal_tx_tqm_release_reason - TQM Release reason codes 246 * 247 * @HAL_TX_TQM_RR_FRAME_ACKED : ACK of BA for it was received 248 * @HAL_TX_TQM_RR_REM_CMD_REM : Remove cmd of type “Remove_mpdus” initiated 249 * by SW 250 * @HAL_TX_TQM_RR_REM_CMD_TX : Remove command of type Remove_transmitted_mpdus 251 * initiated by SW 252 * @HAL_TX_TQM_RR_REM_CMD_NOTX : Remove cmd of type Remove_untransmitted_mpdus 253 * initiated by SW 254 * @HAL_TX_TQM_RR_REM_CMD_AGED : Remove command of type “Remove_aged_mpdus” or 255 * “Remove_aged_msdus” initiated by SW 256 * @HAL_TX_TQM_RR_FW_REASON1 : Remove command where fw indicated that 257 * remove reason is fw_reason1 258 * @HAL_TX_TQM_RR_FW_REASON2 : Remove command where fw indicated that 259 * remove reason is fw_reason2 260 * @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that 261 * remove reason is fw_reason3 262 * @HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE : Remove command where fw indicated that 263 * remove reason is remove disable queue 264 */ 265 enum hal_tx_tqm_release_reason { 266 HAL_TX_TQM_RR_FRAME_ACKED, 267 HAL_TX_TQM_RR_REM_CMD_REM, 268 HAL_TX_TQM_RR_REM_CMD_TX, 269 HAL_TX_TQM_RR_REM_CMD_NOTX, 270 HAL_TX_TQM_RR_REM_CMD_AGED, 271 HAL_TX_TQM_RR_FW_REASON1, 272 HAL_TX_TQM_RR_FW_REASON2, 273 HAL_TX_TQM_RR_FW_REASON3, 274 HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE, 275 }; 276 277 /* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports 278 * @HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT: Default DSCP-TID mapping table 279 * @HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE: DSCP-TID map override table 280 */ 281 enum hal_tx_dscp_tid_table_id { 282 HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT, 283 HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE, 284 }; 285 286 /*--------------------------------------------------------------------------- 287 Function declarations and documentation 288 ---------------------------------------------------------------------------*/ 289 290 /*--------------------------------------------------------------------------- 291 TCL Descriptor accessor APIs 292 ---------------------------------------------------------------------------*/ 293 294 /** 295 * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor 296 * @desc: Handle to Tx Descriptor 297 * @data_length: MSDU length in case of direct descriptor. 298 * Length of link extension descriptor in case of Link extension 299 * descriptor.Includes the length of Metadata 300 * Return: None 301 */ 302 static inline void hal_tx_desc_set_buf_length(void *desc, 303 uint16_t data_length) 304 { 305 HAL_SET_FLD(desc, TCL_DATA_CMD_3, DATA_LENGTH) |= 306 HAL_TX_SM(TCL_DATA_CMD_3, DATA_LENGTH, data_length); 307 } 308 309 /** 310 * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor 311 * @desc: Handle to Tx Descriptor 312 * @offset: Packet offset from Metadata in case of direct buffer descriptor. 313 * 314 * Return: void 315 */ 316 static inline void hal_tx_desc_set_buf_offset(void *desc, 317 uint8_t offset) 318 { 319 HAL_SET_FLD(desc, TCL_DATA_CMD_3, PACKET_OFFSET) |= 320 HAL_TX_SM(TCL_DATA_CMD_3, PACKET_OFFSET, offset); 321 } 322 323 /** 324 * hal_tx_desc_set_encap_type - Set encapsulation type in Tx Descriptor 325 * @desc: Handle to Tx Descriptor 326 * @encap_type: Encapsulation that HW will perform 327 * 328 * Return: void 329 * 330 */ 331 static inline void hal_tx_desc_set_encap_type(void *desc, 332 enum hal_tx_encap_type encap_type) 333 { 334 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCAP_TYPE) |= 335 HAL_TX_SM(TCL_DATA_CMD_2, ENCAP_TYPE, encap_type); 336 } 337 338 /** 339 * hal_tx_desc_set_encrypt_type - Sets the Encrypt Type in Tx Descriptor 340 * @desc: Handle to Tx Descriptor 341 * @type: Encrypt Type 342 * 343 * Return: void 344 */ 345 static inline void hal_tx_desc_set_encrypt_type(void *desc, 346 enum hal_tx_encrypt_type type) 347 { 348 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCRYPT_TYPE) |= 349 HAL_TX_SM(TCL_DATA_CMD_2, ENCRYPT_TYPE, type); 350 } 351 352 /** 353 * hal_tx_desc_set_addr_search_flags - Enable AddrX and AddrY search flags 354 * @desc: Handle to Tx Descriptor 355 * @flags: Bit 0 - AddrY search enable, Bit 1 - AddrX search enable 356 * 357 * Return: void 358 */ 359 static inline void hal_tx_desc_set_addr_search_flags(void *desc, 360 uint8_t flags) 361 { 362 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRX_EN) |= 363 HAL_TX_SM(TCL_DATA_CMD_2, ADDRX_EN, (flags & 0x1)); 364 365 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRY_EN) |= 366 HAL_TX_SM(TCL_DATA_CMD_2, ADDRY_EN, (flags >> 1)); 367 } 368 369 /** 370 * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags 371 * Tx Descriptor for MSDU_buffer type 372 * @desc: Handle to Tx Descriptor 373 * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits) 374 * 375 * Return: void 376 */ 377 static inline void hal_tx_desc_set_l4_checksum_en(void *desc, 378 uint8_t en) 379 { 380 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 381 (HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV4_CHECKSUM_EN, en) | 382 HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV6_CHECKSUM_EN, en) | 383 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV4_CHECKSUM_EN, en) | 384 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV6_CHECKSUM_EN, en)); 385 } 386 387 /** 388 * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in 389 * Tx Descriptor for MSDU_buffer type 390 * @desc: Handle to Tx Descriptor 391 * @checksum_en_flags: ipv4 checksum enable flags 392 * 393 * Return: void 394 */ 395 static inline void hal_tx_desc_set_l3_checksum_en(void *desc, 396 uint8_t en) 397 { 398 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 399 HAL_TX_SM(TCL_DATA_CMD_3, IPV4_CHECKSUM_EN, en); 400 } 401 402 /** 403 * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor 404 * @desc:Handle to Tx Descriptor 405 * @metadata: Metadata to be sent to Firmware 406 * 407 * Return: void 408 */ 409 static inline void hal_tx_desc_set_fw_metadata(void *desc, 410 uint16_t metadata) 411 { 412 HAL_SET_FLD(desc, TCL_DATA_CMD_2, TCL_CMD_NUMBER) |= 413 HAL_TX_SM(TCL_DATA_CMD_2, TCL_CMD_NUMBER, metadata); 414 } 415 416 /** 417 * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor. 418 * @desc:Handle to Tx Descriptor 419 * @to_fw: if set, Forward packet to FW along with classification result 420 * 421 * Return: void 422 */ 423 static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw) 424 { 425 HAL_SET_FLD(desc, TCL_DATA_CMD_3, TO_FW) |= 426 HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw); 427 } 428 429 /** 430 * hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor 431 * @hal_soc_hdl: hal soc handle 432 * @desc: Handle to Tx Descriptor 433 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 434 * enabling the interpretation of the 'Mesh Control Present' bit 435 * (bit 8) of QoS Control (otherwise this bit is ignored), 436 * For native WiFi frames, this indicates that a 'Mesh Control' field 437 * is present between the header and the LLC. 438 * 439 * Return: void 440 */ 441 static inline void hal_tx_desc_set_mesh_en(hal_soc_handle_t hal_soc_hdl, 442 void *desc, uint8_t en) 443 { 444 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 445 446 hal_soc->ops->hal_tx_desc_set_mesh_en(desc, en); 447 } 448 449 /** 450 * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in 451 * frame) to be used for Tx Frame 452 * @desc: Handle to Tx Descriptor 453 * @hlos_tid: HLOS TID 454 * 455 * Return: void 456 */ 457 static inline void hal_tx_desc_set_hlos_tid(void *desc, 458 uint8_t hlos_tid) 459 { 460 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID) |= 461 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID, hlos_tid); 462 463 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |= 464 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1); 465 } 466 /** 467 * hal_tx_desc_sync - Commit the descriptor to Hardware 468 * @hal_tx_des_cached: Cached descriptor that software maintains 469 * @hw_desc: Hardware descriptor to be updated 470 */ 471 static inline void hal_tx_desc_sync(void *hal_tx_desc_cached, 472 void *hw_desc) 473 { 474 qdf_mem_copy((hw_desc + sizeof(struct tlv_32_hdr)), 475 hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES); 476 } 477 478 /*--------------------------------------------------------------------------- 479 Tx MSDU Extension Descriptor accessor APIs 480 ---------------------------------------------------------------------------*/ 481 /** 482 * hal_tx_ext_desc_set_tso_enable() - Set TSO Enable Flag 483 * @desc: Handle to Tx MSDU Extension Descriptor 484 * @tso_en: bool value set to true if TSO is enabled 485 * 486 * Return: none 487 */ 488 static inline void hal_tx_ext_desc_set_tso_enable(void *desc, 489 uint8_t tso_en) 490 { 491 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TSO_ENABLE) |= 492 HAL_TX_SM(TX_MSDU_EXTENSION_0, TSO_ENABLE, tso_en); 493 } 494 495 /** 496 * hal_tx_ext_desc_set_tso_flags() - Set TSO Flags 497 * @desc: Handle to Tx MSDU Extension Descriptor 498 * @falgs: 32-bit word with all TSO flags consolidated 499 * 500 * Return: none 501 */ 502 static inline void hal_tx_ext_desc_set_tso_flags(void *desc, 503 uint32_t tso_flags) 504 { 505 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_0, TSO_ENABLE, 0) = 506 tso_flags; 507 } 508 509 /** 510 * hal_tx_ext_desc_set_tcp_flags() - Enable HW Checksum offload 511 * @desc: Handle to Tx MSDU Extension Descriptor 512 * @tcp_flags: TCP flags {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 513 * @mask: TCP flag mask. Tcp_flag is inserted into the header 514 * based on the mask, if tso is enabled 515 * 516 * Return: none 517 */ 518 static inline void hal_tx_ext_desc_set_tcp_flags(void *desc, 519 uint16_t tcp_flags, 520 uint16_t mask) 521 { 522 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TCP_FLAG) |= 523 ((HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG, tcp_flags)) | 524 (HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG_MASK, mask))); 525 } 526 527 /** 528 * hal_tx_ext_desc_set_msdu_length() - Set L2 and IP Lengths 529 * @desc: Handle to Tx MSDU Extension Descriptor 530 * @l2_len: L2 length for the msdu, if tso is enabled 531 * @ip_len: IP length for the msdu, if tso is enabled 532 * 533 * Return: none 534 */ 535 static inline void hal_tx_ext_desc_set_msdu_length(void *desc, 536 uint16_t l2_len, 537 uint16_t ip_len) 538 { 539 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_1, L2_LENGTH) |= 540 ((HAL_TX_SM(TX_MSDU_EXTENSION_1, L2_LENGTH, l2_len)) | 541 (HAL_TX_SM(TX_MSDU_EXTENSION_1, IP_LENGTH, ip_len))); 542 } 543 544 /** 545 * hal_tx_ext_desc_set_tcp_seq() - Set TCP Sequence number 546 * @desc: Handle to Tx MSDU Extension Descriptor 547 * @seq_num: Tcp_seq_number for the msdu, if tso is enabled 548 * 549 * Return: none 550 */ 551 static inline void hal_tx_ext_desc_set_tcp_seq(void *desc, 552 uint32_t seq_num) 553 { 554 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER) |= 555 ((HAL_TX_SM(TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER, seq_num))); 556 } 557 558 559 /** 560 * hal_tx_ext_desc_set_ip_id() - Set IP Identification field 561 * @desc: Handle to Tx MSDU Extension Descriptor 562 * @id: IP Id field for the msdu, if tso is enabled 563 * 564 * Return: none 565 */ 566 static inline void hal_tx_ext_desc_set_ip_id(void *desc, 567 uint16_t id) 568 { 569 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_3, IP_IDENTIFICATION) |= 570 ((HAL_TX_SM(TX_MSDU_EXTENSION_3, IP_IDENTIFICATION, id))); 571 } 572 /** 573 * hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment 574 * @desc: Handle to Tx MSDU Extension Descriptor 575 * @frag_num: Fragment number (value can be 0 to 5) 576 * @paddr_lo: Lower 32-bit of Buffer Physical address 577 * @paddr_hi: Upper 32-bit of Buffer Physical address 578 * @length: Buffer Length 579 * 580 * Return: none 581 */ 582 static inline void hal_tx_ext_desc_set_buffer(void *desc, 583 uint8_t frag_num, 584 uint32_t paddr_lo, 585 uint16_t paddr_hi, 586 uint16_t length) 587 { 588 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, 589 (frag_num << 3)) |= 590 ((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo))); 591 592 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32, 593 (frag_num << 3)) |= 594 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_PTR_39_32, 595 (paddr_hi)))); 596 597 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_LEN, 598 (frag_num << 3)) |= 599 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length))); 600 } 601 602 /** 603 * hal_tx_ext_desc_set_buffer0_param() - Set Buffer 0 Pointer and Length 604 * @desc: Handle to Tx MSDU Extension Descriptor 605 * @paddr_lo: Lower 32-bit of Buffer Physical address 606 * @paddr_hi: Upper 32-bit of Buffer Physical address 607 * @length: Buffer 0 Length 608 * 609 * Return: none 610 */ 611 static inline void hal_tx_ext_desc_set_buffer0_param(void *desc, 612 uint32_t paddr_lo, 613 uint16_t paddr_hi, 614 uint16_t length) 615 { 616 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0) |= 617 ((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo))); 618 619 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32) |= 620 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, 621 BUF0_PTR_39_32, paddr_hi))); 622 623 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_LEN) |= 624 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length))); 625 } 626 627 /** 628 * hal_tx_ext_desc_set_buffer1_param() - Set Buffer 1 Pointer and Length 629 * @desc: Handle to Tx MSDU Extension Descriptor 630 * @paddr_lo: Lower 32-bit of Buffer Physical address 631 * @paddr_hi: Upper 32-bit of Buffer Physical address 632 * @length: Buffer 1 Length 633 * 634 * Return: none 635 */ 636 static inline void hal_tx_ext_desc_set_buffer1_param(void *desc, 637 uint32_t paddr_lo, 638 uint16_t paddr_hi, 639 uint16_t length) 640 { 641 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_8, BUF1_PTR_31_0) |= 642 ((HAL_TX_SM(TX_MSDU_EXTENSION_8, BUF1_PTR_31_0, paddr_lo))); 643 644 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_PTR_39_32) |= 645 ((HAL_TX_SM(TX_MSDU_EXTENSION_9, 646 BUF1_PTR_39_32, paddr_hi))); 647 648 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_LEN) |= 649 ((HAL_TX_SM(TX_MSDU_EXTENSION_9, BUF1_LEN, length))); 650 } 651 652 /** 653 * hal_tx_ext_desc_set_buffer2_param() - Set Buffer 2 Pointer and Length 654 * @desc: Handle to Tx MSDU Extension Descriptor 655 * @paddr_lo: Lower 32-bit of Buffer Physical address 656 * @paddr_hi: Upper 32-bit of Buffer Physical address 657 * @length: Buffer 2 Length 658 * 659 * Return: none 660 */ 661 static inline void hal_tx_ext_desc_set_buffer2_param(void *desc, 662 uint32_t paddr_lo, 663 uint16_t paddr_hi, 664 uint16_t length) 665 { 666 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_10, BUF2_PTR_31_0) |= 667 ((HAL_TX_SM(TX_MSDU_EXTENSION_10, BUF2_PTR_31_0, 668 paddr_lo))); 669 670 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_PTR_39_32) |= 671 ((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_PTR_39_32, 672 paddr_hi))); 673 674 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_LEN) |= 675 ((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_LEN, length))); 676 } 677 678 /** 679 * hal_tx_ext_desc_sync - Commit the descriptor to Hardware 680 * @desc_cached: Cached descriptor that software maintains 681 * @hw_desc: Hardware descriptor to be updated 682 * 683 * Return: none 684 */ 685 static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached, 686 uint8_t *hw_desc) 687 { 688 qdf_mem_copy(&hw_desc[0], &desc_cached[0], 689 HAL_TX_EXT_DESC_WITH_META_DATA); 690 } 691 692 /** 693 * hal_tx_ext_desc_get_tso_enable() - Set TSO Enable Flag 694 * @hal_tx_ext_desc: Handle to Tx MSDU Extension Descriptor 695 * 696 * Return: tso_enable value in the descriptor 697 */ 698 static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc) 699 { 700 uint32_t *desc = (uint32_t *) hal_tx_ext_desc; 701 return (*desc & TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK) >> 702 TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB; 703 } 704 705 /*--------------------------------------------------------------------------- 706 WBM Descriptor accessor APIs for Tx completions 707 ---------------------------------------------------------------------------*/ 708 /** 709 * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor 710 * @hal_desc: completion ring descriptor pointer 711 * 712 * This function will tx descriptor id, cookie, within hardware completion 713 * descriptor 714 * 715 * Return: cookie 716 */ 717 static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc) 718 { 719 uint32_t comp_desc = 720 *(uint32_t *) (((uint8_t *) hal_desc) + 721 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET); 722 723 /* Cookie is placed on 2nd word */ 724 return (comp_desc & BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) >> 725 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB; 726 } 727 728 /** 729 * hal_tx_comp_get_paddr() - Get paddr within comp descriptor 730 * @hal_desc: completion ring descriptor pointer 731 * 732 * This function will get buffer physical address within hardware completion 733 * descriptor 734 * 735 * Return: Buffer physical address 736 */ 737 static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc) 738 { 739 uint32_t paddr_lo; 740 uint32_t paddr_hi; 741 742 paddr_lo = *(uint32_t *) (((uint8_t *) hal_desc) + 743 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET); 744 745 paddr_hi = *(uint32_t *) (((uint8_t *) hal_desc) + 746 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET); 747 748 paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) >> 749 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB; 750 751 return (qdf_dma_addr_t) (paddr_lo | (((uint64_t) paddr_hi) << 32)); 752 } 753 754 /** 755 * hal_tx_comp_get_buffer_source() - Get buffer release source value 756 * @hal_desc: completion ring descriptor pointer 757 * 758 * This function will get buffer release source from Tx completion descriptor 759 * 760 * Return: buffer release source 761 */ 762 static inline uint32_t hal_tx_comp_get_buffer_source(void *hal_desc) 763 { 764 uint32_t comp_desc = 765 *(uint32_t *) (((uint8_t *) hal_desc) + 766 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET); 767 768 return (comp_desc & WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> 769 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB; 770 } 771 772 /** 773 * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type 774 * @hal_desc: completion ring descriptor pointer 775 * 776 * This function will return the type of pointer - buffer or descriptor 777 * 778 * Return: buffer type 779 */ 780 static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc) 781 { 782 uint32_t comp_desc = 783 *(uint32_t *) (((uint8_t *) hal_desc) + 784 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET); 785 786 return (comp_desc & WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> 787 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB; 788 } 789 790 /** 791 * hal_tx_comp_get_release_reason() - TQM Release reason 792 * @hal_desc: completion ring descriptor pointer 793 * 794 * This function will return the type of pointer - buffer or descriptor 795 * 796 * Return: buffer type 797 */ 798 static inline 799 uint8_t hal_tx_comp_get_release_reason(void *hal_desc, 800 hal_soc_handle_t hal_soc_hdl) 801 { 802 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 803 804 return hal_soc->ops->hal_tx_comp_get_release_reason(hal_desc); 805 } 806 807 /** 808 * hal_tx_comp_desc_sync() - collect hardware descriptor contents 809 * @hal_desc: hardware descriptor pointer 810 * @comp: software descriptor pointer 811 * @read_status: 0 - Do not read status words from descriptors 812 * 1 - Enable reading of status words from descriptor 813 * 814 * This function will collect hardware release ring element contents and 815 * translate to software descriptor content 816 * 817 * Return: none 818 */ 819 820 static inline void hal_tx_comp_desc_sync(void *hw_desc, 821 struct hal_tx_desc_comp_s *comp, 822 bool read_status) 823 { 824 if (!read_status) 825 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_BASE_LEN); 826 else 827 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_LEN_BYTES); 828 } 829 830 /** 831 * hal_dump_comp_desc() - dump tx completion descriptor 832 * @hal_desc: hardware descriptor pointer 833 * 834 * This function will print tx completion descriptor 835 * 836 * Return: none 837 */ 838 static inline void hal_dump_comp_desc(void *hw_desc) 839 { 840 struct hal_tx_desc_comp_s *comp = 841 (struct hal_tx_desc_comp_s *)hw_desc; 842 uint32_t i; 843 844 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 845 "Current tx completion descriptor is"); 846 847 for (i = 0; i < HAL_TX_COMPLETION_DESC_LEN_DWORDS; i++) { 848 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 849 "DWORD[i] = 0x%x", comp->desc[i]); 850 } 851 } 852 853 /** 854 * hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor 855 * @hal_desc: Hardware (WBM) descriptor pointer 856 * @htt_desc: Software HTT descriptor pointer 857 * 858 * This function will read the HTT structure overlaid on WBM descriptor 859 * into a cached software descriptor 860 * 861 */ 862 static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc) 863 { 864 uint8_t *desc = hw_desc + HAL_TX_COMP_HTT_STATUS_OFFSET; 865 866 qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN); 867 } 868 869 /** 870 * hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG 871 * @hal_soc_hdl: Handle to HAL SoC structure 872 * @hal_srng: Handle to HAL SRNG structure 873 * 874 * Return: none 875 */ 876 static inline void hal_tx_init_data_ring(hal_soc_handle_t hal_soc_hdl, 877 hal_ring_handle_t hal_ring_hdl) 878 { 879 uint8_t *desc_addr; 880 struct hal_srng_params srng_params; 881 uint32_t desc_size; 882 uint32_t num_desc; 883 884 hal_get_srng_params(hal_soc_hdl, hal_ring_hdl, &srng_params); 885 886 desc_addr = (uint8_t *)srng_params.ring_base_vaddr; 887 desc_size = sizeof(struct tcl_data_cmd); 888 num_desc = srng_params.num_entries; 889 890 while (num_desc) { 891 HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, 892 desc_size); 893 desc_addr += (desc_size + sizeof(struct tlv_32_hdr)); 894 num_desc--; 895 } 896 } 897 898 /** 899 * hal_tx_desc_set_dscp_tid_table_id() - Sets DSCP to TID conversion table ID 900 * @hal_soc: Handle to HAL SoC structure 901 * @desc: Handle to Tx Descriptor 902 * @id: DSCP to tid conversion table to be used for this frame 903 * 904 * Return: void 905 */ 906 static inline 907 void hal_tx_desc_set_dscp_tid_table_id(hal_soc_handle_t hal_soc_hdl, 908 void *desc, uint8_t id) 909 { 910 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 911 912 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id(desc, id); 913 } 914 915 /** 916 * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table 917 * 918 * @soc: HAL SoC context 919 * @map: DSCP-TID mapping table 920 * @id: mapping table ID - 0,1 921 * 922 * Return: void 923 */ 924 static inline void hal_tx_set_dscp_tid_map(hal_soc_handle_t hal_soc_hdl, 925 uint8_t *map, uint8_t id) 926 { 927 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 928 929 hal_soc->ops->hal_tx_set_dscp_tid_map(hal_soc, map, id); 930 } 931 932 /** 933 * hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user 934 * 935 * @soc: HAL SoC context 936 * @map: DSCP-TID mapping table 937 * @id : MAP ID 938 * @dscp: DSCP_TID map index 939 * 940 * Return: void 941 */ 942 static inline 943 void hal_tx_update_dscp_tid(hal_soc_handle_t hal_soc_hdl, uint8_t tid, 944 uint8_t id, uint8_t dscp) 945 { 946 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 947 948 hal_soc->ops->hal_tx_update_dscp_tid(hal_soc, tid, id, dscp); 949 } 950 951 /** 952 * hal_tx_desc_set_lmac_id - Set the lmac_id value 953 * @desc: Handle to Tx Descriptor 954 * @lmac_id: mac Id to ast matching 955 * b00 – mac 0 956 * b01 – mac 1 957 * b10 – mac 2 958 * b11 – all macs (legacy HK way) 959 * 960 * Return: void 961 */ 962 static inline void hal_tx_desc_set_lmac_id(hal_soc_handle_t hal_soc_hdl, 963 void *desc, uint8_t lmac_id) 964 { 965 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 966 967 hal_soc->ops->hal_tx_desc_set_lmac_id(desc, lmac_id); 968 } 969 970 /** 971 * hal_tx_desc_set_search_type - Set the search type value 972 * @desc: Handle to Tx Descriptor 973 * @search_type: search type 974 * 0 – Normal search 975 * 1 – Index based address search 976 * 2 – Index based flow search 977 * 978 * Return: void 979 */ 980 static inline void hal_tx_desc_set_search_type(hal_soc_handle_t hal_soc_hdl, 981 void *desc, uint8_t search_type) 982 { 983 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 984 985 hal_soc->ops->hal_tx_desc_set_search_type(desc, search_type); 986 } 987 988 /** 989 * hal_tx_desc_set_search_index - Set the search index value 990 * @desc: Handle to Tx Descriptor 991 * @search_index: The index that will be used for index based address or 992 * flow search. The field is valid when 'search_type' is 993 * 1 0r 2 994 * 995 * Return: void 996 */ 997 static inline void hal_tx_desc_set_search_index(hal_soc_handle_t hal_soc_hdl, 998 void *desc, 999 uint32_t search_index) 1000 { 1001 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1002 1003 hal_soc->ops->hal_tx_desc_set_search_index(desc, search_index); 1004 } 1005 1006 /** 1007 * hal_tx_desc_set_cache_set_num - Set the cache-set-num value 1008 * @desc: Handle to Tx Descriptor 1009 * @cache_num: Cache set number that should be used to cache the index 1010 * based search results, for address and flow search. 1011 * This value should be equal to LSB four bits of the hash value 1012 * of match data, in case of search index points to an entry 1013 * which may be used in content based search also. The value can 1014 * be anything when the entry pointed by search index will not be 1015 * used for content based search. 1016 * 1017 * Return: void 1018 */ 1019 static inline void hal_tx_desc_set_cache_set_num(hal_soc_handle_t hal_soc_hdl, 1020 void *desc, 1021 uint8_t cache_num) 1022 { 1023 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1024 1025 hal_soc->ops->hal_tx_desc_set_cache_set_num(desc, cache_num); 1026 } 1027 1028 /** 1029 * hal_tx_comp_get_status() - TQM Release reason 1030 * @hal_desc: completion ring Tx status 1031 * 1032 * This function will parse the WBM completion descriptor and populate in 1033 * HAL structure 1034 * 1035 * Return: none 1036 */ 1037 static inline void hal_tx_comp_get_status(void *desc, void *ts, 1038 hal_soc_handle_t hal_soc_hdl) 1039 { 1040 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1041 1042 hal_soc->ops->hal_tx_comp_get_status(desc, ts, hal_soc); 1043 } 1044 1045 1046 /** 1047 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 1048 * @desc: Handle to Tx Descriptor 1049 * @paddr: Physical Address 1050 * @pool_id: Return Buffer Manager ID 1051 * @desc_id: Descriptor ID 1052 * @type: 0 - Address points to a MSDU buffer 1053 * 1 - Address points to MSDU extension descriptor 1054 * 1055 * Return: void 1056 */ 1057 static inline 1058 void hal_tx_desc_set_buf_addr(void *desc, dma_addr_t paddr, 1059 uint8_t pool_id, uint32_t desc_id, 1060 uint8_t type, hal_soc_handle_t hal_soc_hdl) 1061 { 1062 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1063 1064 hal_soc->ops->hal_tx_desc_set_buf_addr(desc, paddr, pool_id, 1065 desc_id, type); 1066 1067 } 1068 1069 /** 1070 * hal_tx_set_pcp_tid_map_default() - Configure default PCP to TID map table 1071 * 1072 * @soc: HAL SoC context 1073 * @map: PCP-TID mapping table 1074 * 1075 * Return: void 1076 */ 1077 static inline void hal_tx_set_pcp_tid_map_default(hal_soc_handle_t hal_soc_hdl, 1078 uint8_t *map) 1079 { 1080 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1081 1082 hal_soc->ops->hal_tx_set_pcp_tid_map(hal_soc, map); 1083 } 1084 1085 /** 1086 * hal_tx_update_pcp_tid_map() - Update PCP to TID map table 1087 * 1088 * @soc: HAL SoC context 1089 * @pcp: pcp value 1090 * @tid: tid no 1091 * 1092 * Return: void 1093 */ 1094 static inline void hal_tx_update_pcp_tid_map(hal_soc_handle_t hal_soc_hdl, 1095 uint8_t pcp, uint8_t tid) 1096 { 1097 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1098 1099 hal_soc->ops->hal_tx_update_pcp_tid_map(hal_soc, tid, tid); 1100 } 1101 1102 /** 1103 * hal_tx_set_tidmap_prty() - Configure TIDmap priority 1104 * 1105 * @soc: HAL SoC context 1106 * @val: priority value 1107 * 1108 * Return: void 1109 */ 1110 static inline 1111 void hal_tx_set_tidmap_prty(hal_soc_handle_t hal_soc_hdl, uint8_t val) 1112 { 1113 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1114 1115 hal_soc->ops->hal_tx_set_tidmap_prty(hal_soc, val); 1116 } 1117 1118 /** 1119 * hal_get_wbm_internal_error() - wbm internal error 1120 * @hal_desc: completion ring descriptor pointer 1121 * 1122 * This function will return the type of pointer - buffer or descriptor 1123 * 1124 * Return: buffer type 1125 */ 1126 static inline 1127 uint8_t hal_get_wbm_internal_error(hal_soc_handle_t hal_soc_hdl, void *hal_desc) 1128 { 1129 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1130 1131 return hal_soc->ops->hal_get_wbm_internal_error(hal_desc); 1132 } 1133 1134 #endif /* HAL_TX_H */ 1135