1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #if !defined(HAL_TX_H) 21 #define HAL_TX_H 22 23 /*--------------------------------------------------------------------------- 24 Include files 25 ---------------------------------------------------------------------------*/ 26 #include "hal_api.h" 27 #include "wcss_version.h" 28 #include "hal_hw_headers.h" 29 #include "hal_tx_hw_defines.h" 30 31 #define HAL_WBM_RELEASE_RING_2_BUFFER_TYPE 0 32 #define HAL_WBM_RELEASE_RING_2_DESC_TYPE 1 33 34 #define HAL_TX_DESC_TLV_TAG_OFFSET 1 35 #define HAL_TX_DESC_TLV_LEN_OFFSET 10 36 37 /*--------------------------------------------------------------------------- 38 Preprocessor definitions and constants 39 ---------------------------------------------------------------------------*/ 40 #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET 41 42 #define HAL_TX_LSB(block, field) block ## _ ## field ## _LSB 43 44 #define HAL_TX_MASK(block, field) block ## _ ## field ## _MASK 45 46 #define HAL_TX_DESC_OFFSET(desc, block, field) \ 47 (((uint8_t *)desc) + HAL_OFFSET(block, field)) 48 49 #define HAL_SET_FLD(desc, block , field) \ 50 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field))) 51 52 #define HAL_SET_FLD_OFFSET(desc, block , field, offset) \ 53 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field) + (offset))) 54 55 #define HAL_SET_FLD_64(desc, block, field) \ 56 (*(uint64_t *)((uint8_t *)desc + HAL_OFFSET(block, field))) 57 58 #define HAL_SET_FLD_OFFSET_64(desc, block, field, offset) \ 59 (*(uint64_t *)((uint8_t *)desc + HAL_OFFSET(block, field) + (offset))) 60 61 #define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \ 62 do { \ 63 uint32_t temp = 0; \ 64 temp |= (tag << HAL_TX_DESC_TLV_TAG_OFFSET); \ 65 temp |= (len << HAL_TX_DESC_TLV_LEN_OFFSET); \ 66 (*(uint32_t *)desc) = temp; \ 67 } while (0) 68 69 #define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E 70 #define HAL_TX_TCL_CMD_TAG WIFITCL_GSE_CMD_E 71 72 #define HAL_TX_SM(block, field, value) \ 73 ((value << (block ## _ ## field ## _LSB)) & \ 74 (block ## _ ## field ## _MASK)) 75 76 #define HAL_TX_MS(block, field, value) \ 77 (((value) & (block ## _ ## field ## _MASK)) >> \ 78 (block ## _ ## field ## _LSB)) 79 80 #define HAL_TX_DESC_GET(desc, block, field) \ 81 HAL_TX_MS(block, field, HAL_SET_FLD(desc, block, field)) 82 83 #define HAL_TX_DESC_OFFSET_GET(desc, block, field, offset) \ 84 HAL_TX_MS(block, field, HAL_SET_FLD_OFFSET(desc, block, field, offset)) 85 86 #define HAL_TX_DESC_SUBBLOCK_GET(desc, block, sub, field) \ 87 HAL_TX_MS(sub, field, HAL_SET_FLD(desc, block, sub)) 88 89 #define HAL_TX_DESC_GET_64(desc, block, field) \ 90 HAL_TX_MS(block, field, HAL_SET_FLD_64(desc, block, field)) 91 92 #define HAL_TX_DESC_OFFSET_GET_64(desc, block, field, offset) \ 93 HAL_TX_MS(block, field, HAL_SET_FLD_OFFSET_64(desc, block, field,\ 94 offset)) 95 96 #define HAL_TX_DESC_SUBBLOCK_GET_64(desc, block, sub, field) \ 97 HAL_TX_MS(sub, field, HAL_SET_FLD_64(desc, block, sub)) 98 99 #define HAL_TX_BUF_TYPE_BUFFER 0 100 #define HAL_TX_BUF_TYPE_EXT_DESC 1 101 102 #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 103 104 #define HAL_TX_DESC_LEN_DWORDS (NUM_OF_DWORDS_TCL_DATA_CMD) 105 #define HAL_TX_DESC_LEN_BYTES (NUM_OF_DWORDS_TCL_DATA_CMD * 4) 106 #define HAL_TX_EXTENSION_DESC_LEN_DWORDS (NUM_OF_DWORDS_TX_MSDU_EXTENSION) 107 #define HAL_TX_EXTENSION_DESC_LEN_BYTES (NUM_OF_DWORDS_TX_MSDU_EXTENSION * 4) 108 109 #define NUM_OF_DWORDS_WBM_RELEASE_RING 8 110 111 #define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 112 #define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4) 113 #define HAL_TX_BITS_PER_TID 3 114 #define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1) 115 #define HAL_TX_NUM_DSCP_PER_REGISTER 10 116 #define HAL_MAX_HW_DSCP_TID_MAPS 2 117 #define HAL_MAX_HW_DSCP_TID_MAPS_11AX 32 118 119 #define HAL_MAX_HW_DSCP_TID_V2_MAPS 48 120 #define HTT_META_HEADER_LEN_BYTES 64 121 #define HAL_TX_EXT_DESC_WITH_META_DATA \ 122 (HTT_META_HEADER_LEN_BYTES + HAL_TX_EXTENSION_DESC_LEN_BYTES) 123 124 #define HAL_TX_NUM_PCP_PER_REGISTER 8 125 126 /* Length of WBM release ring without the status words */ 127 #define HAL_TX_COMPLETION_DESC_BASE_LEN 12 128 129 #define HAL_TX_COMP_RELEASE_SOURCE_TQM 0 130 #define HAL_TX_COMP_RELEASE_SOURCE_REO 2 131 #define HAL_TX_COMP_RELEASE_SOURCE_FW 3 132 133 /* Define a place-holder release reason for FW */ 134 #define HAL_TX_COMP_RELEASE_REASON_FW 99 135 136 /* 137 * Offset of HTT Tx Descriptor in WBM Completion 138 * HTT Tx Desc structure is passed from firmware to host overlayed 139 * on wbm_release_ring DWORDs 2,3 ,4 and 5for software based completions 140 * (Exception frames and TQM bypass frames) 141 */ 142 #define HAL_TX_COMP_HTT_STATUS_OFFSET 8 143 #ifdef CONFIG_BERYLLIUM 144 #define HAL_TX_COMP_HTT_STATUS_LEN 20 145 #else 146 #define HAL_TX_COMP_HTT_STATUS_LEN 16 147 #endif 148 149 #define HAL_TX_BUF_TYPE_BUFFER 0 150 #define HAL_TX_BUF_TYPE_EXT_DESC 1 151 152 #define HAL_TX_EXT_DESC_BUF_OFFSET TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 153 #define HAL_TX_EXT_BUF_LOW_MASK TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 154 #define HAL_TX_EXT_BUF_HI_MASK TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 155 #define HAL_TX_EXT_BUF_LEN_MASK TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 156 #define HAL_TX_EXT_BUF_LEN_LSB TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 157 #define HAL_TX_EXT_BUF_WD_SIZE 2 158 159 #define HAL_TX_DESC_ADDRX_EN 0x1 160 #define HAL_TX_DESC_ADDRY_EN 0x2 161 #define HAL_TX_DESC_DEFAULT_LMAC_ID 0x3 162 163 #define HAL_TX_ADDR_SEARCH_DEFAULT 0x0 164 #define HAL_TX_ADDR_INDEX_SEARCH 0x1 165 #define HAL_TX_FLOW_INDEX_SEARCH 0x2 166 167 #define HAL_WBM2SW_RELEASE_SRC_GET(wbm_desc)(((*(((uint32_t *)wbm_desc) + \ 168 (HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 169 HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_MASK) >> \ 170 HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_LSB) 171 172 #define HAL_WBM_SW0_BM_ID(sw0_bm_id) (sw0_bm_id) 173 #define HAL_WBM_SW1_BM_ID(sw0_bm_id) ((sw0_bm_id) + 1) 174 #define HAL_WBM_SW2_BM_ID(sw0_bm_id) ((sw0_bm_id) + 2) 175 #define HAL_WBM_SW3_BM_ID(sw0_bm_id) ((sw0_bm_id) + 3) 176 #define HAL_WBM_SW4_BM_ID(sw0_bm_id) ((sw0_bm_id) + 4) 177 #define HAL_WBM_SW5_BM_ID(sw0_bm_id) ((sw0_bm_id) + 5) 178 #define HAL_WBM_SW6_BM_ID(sw0_bm_id) ((sw0_bm_id) + 6) 179 180 /*--------------------------------------------------------------------------- 181 Structures 182 ---------------------------------------------------------------------------*/ 183 /** 184 * struct hal_tx_completion_status - HAL Tx completion descriptor contents 185 * @status: frame acked/failed 186 * @release_src: release source = TQM/FW 187 * @ack_frame_rssi: RSSI of the received ACK or BA frame 188 * @first_msdu: Indicates this MSDU is the first MSDU in AMSDU 189 * @last_msdu: Indicates this MSDU is the last MSDU in AMSDU 190 * @msdu_part_of_amsdu : Indicates this MSDU was part of an A-MSDU in MPDU 191 * @bw: Indicates the BW of the upcoming transmission - 192 * <enum 0 transmit_bw_20_MHz> 193 * <enum 1 transmit_bw_40_MHz> 194 * <enum 2 transmit_bw_80_MHz> 195 * <enum 3 transmit_bw_160_MHz> 196 * @pkt_type: Transmit Packet Type 197 * @stbc: When set, STBC transmission rate was used 198 * @ldpc: When set, use LDPC transmission rates 199 * @sgi: <enum 0 0_8_us_sgi > Legacy normal GI 200 * <enum 1 0_4_us_sgi > Legacy short GI 201 * <enum 2 1_6_us_sgi > HE related GI 202 * <enum 3 3_2_us_sgi > HE 203 * @mcs: Transmit MCS Rate 204 * @ofdma: Set when the transmission was an OFDMA transmission 205 * @tones_in_ru: The number of tones in the RU used. 206 * @tsf: Lower 32 bits of the TSF 207 * @ppdu_id: TSF, snapshot of this value when transmission of the 208 * PPDU containing the frame finished. 209 * @transmit_cnt: Number of times this frame has been transmitted 210 * @tid: TID of the flow or MPDU queue 211 * @peer_id: Peer ID of the flow or MPDU queue 212 * @buffer_timestamp: Frame system entrance timestamp in units of 1024 213 * microseconds 214 */ 215 struct hal_tx_completion_status { 216 uint8_t status; 217 uint8_t release_src; 218 uint8_t ack_frame_rssi; 219 uint8_t first_msdu:1, 220 last_msdu:1, 221 msdu_part_of_amsdu:1; 222 uint32_t bw:2, 223 pkt_type:4, 224 stbc:1, 225 ldpc:1, 226 sgi:2, 227 mcs:4, 228 ofdma:1, 229 tones_in_ru:12, 230 valid:1; 231 uint32_t tsf; 232 uint32_t ppdu_id; 233 uint8_t transmit_cnt; 234 uint8_t tid; 235 uint16_t peer_id; 236 #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(CONFIG_SAWF) 237 uint32_t buffer_timestamp:19; 238 #endif 239 }; 240 241 /** 242 * struct hal_tx_desc_comp_s - hal tx completion descriptor contents 243 * @desc: Transmit status information from descriptor 244 */ 245 struct hal_tx_desc_comp_s { 246 uint32_t desc[HAL_TX_COMPLETION_DESC_LEN_DWORDS]; 247 }; 248 249 /* 250 * enum hal_tx_encrypt_type - Type of decrypt cipher used (valid only for RAW) 251 * @HAL_TX_ENCRYPT_TYPE_WEP_40: WEP 40-bit 252 * @HAL_TX_ENCRYPT_TYPE_WEP_10: WEP 10-bit 253 * @HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC: TKIP without MIC 254 * @HAL_TX_ENCRYPT_TYPE_WEP_128: WEP_128 255 * @HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC: TKIP_WITH_MIC 256 * @HAL_TX_ENCRYPT_TYPE_WAPI: WAPI 257 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_128: AES_CCMP_128 258 * @HAL_TX_ENCRYPT_TYPE_NO_CIPHER: NO CIPHER 259 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_256: AES_CCMP_256 260 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_128: AES_GCMP_128 261 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_256: AES_GCMP_256 262 * @HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4: WAPI GCM SM4 263 */ 264 enum hal_tx_encrypt_type { 265 HAL_TX_ENCRYPT_TYPE_WEP_40 = 0, 266 HAL_TX_ENCRYPT_TYPE_WEP_104 = 1 , 267 HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC = 2, 268 HAL_TX_ENCRYPT_TYPE_WEP_128 = 3, 269 HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC = 4, 270 HAL_TX_ENCRYPT_TYPE_WAPI = 5, 271 HAL_TX_ENCRYPT_TYPE_AES_CCMP_128 = 6, 272 HAL_TX_ENCRYPT_TYPE_NO_CIPHER = 7, 273 HAL_TX_ENCRYPT_TYPE_AES_CCMP_256 = 8, 274 HAL_TX_ENCRYPT_TYPE_AES_GCMP_128 = 9, 275 HAL_TX_ENCRYPT_TYPE_AES_GCMP_256 = 10, 276 HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4 = 11, 277 }; 278 279 /* 280 * enum hal_tx_encap_type - Encapsulation type that HW will perform 281 * @HAL_TX_ENCAP_TYPE_RAW: Raw Packet Type 282 * @HAL_TX_ENCAP_TYPE_NWIFI: Native WiFi Type 283 * @HAL_TX_ENCAP_TYPE_ETHERNET: Ethernet 284 * @HAL_TX_ENCAP_TYPE_802_3: 802.3 Frame 285 */ 286 enum hal_tx_encap_type { 287 HAL_TX_ENCAP_TYPE_RAW = 0, 288 HAL_TX_ENCAP_TYPE_NWIFI = 1, 289 HAL_TX_ENCAP_TYPE_ETHERNET = 2, 290 HAL_TX_ENCAP_TYPE_802_3 = 3, 291 }; 292 293 /** 294 * enum hal_tx_tqm_release_reason - TQM Release reason codes 295 * 296 * @HAL_TX_TQM_RR_FRAME_ACKED : ACK of BA for it was received 297 * @HAL_TX_TQM_RR_REM_CMD_REM : Remove cmd of type “Remove_mpdus” initiated 298 * by SW 299 * @HAL_TX_TQM_RR_REM_CMD_TX : Remove command of type Remove_transmitted_mpdus 300 * initiated by SW 301 * @HAL_TX_TQM_RR_REM_CMD_NOTX : Remove cmd of type Remove_untransmitted_mpdus 302 * initiated by SW 303 * @HAL_TX_TQM_RR_REM_CMD_AGED : Remove command of type “Remove_aged_mpdus” or 304 * “Remove_aged_msdus” initiated by SW 305 * @HAL_TX_TQM_RR_FW_REASON1 : Remove command where fw indicated that 306 * remove reason is fw_reason1 307 * @HAL_TX_TQM_RR_FW_REASON2 : Remove command where fw indicated that 308 * remove reason is fw_reason2 309 * @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that 310 * remove reason is fw_reason3 311 * @HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE : Remove command where fw indicated that 312 * remove reason is remove disable queue 313 * @HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING: Remove command from fw to remove 314 * all mpdu until 1st non-match 315 * @HAL_TX_TQM_RR_DROP_THRESHOLD: Dropped due to drop threshold criteria 316 * @HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE: Dropped due to link desc not available 317 * @HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU: Dropped due drop bit set or null flow 318 * @HAL_TX_TQM_RR_MULTICAST_DROP: Dropped due mcast drop set for VDEV 319 * 320 */ 321 enum hal_tx_tqm_release_reason { 322 HAL_TX_TQM_RR_FRAME_ACKED, 323 HAL_TX_TQM_RR_REM_CMD_REM, 324 HAL_TX_TQM_RR_REM_CMD_TX, 325 HAL_TX_TQM_RR_REM_CMD_NOTX, 326 HAL_TX_TQM_RR_REM_CMD_AGED, 327 HAL_TX_TQM_RR_FW_REASON1, 328 HAL_TX_TQM_RR_FW_REASON2, 329 HAL_TX_TQM_RR_FW_REASON3, 330 HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE, 331 HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING, 332 HAL_TX_TQM_RR_DROP_THRESHOLD, 333 HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE, 334 HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU, 335 HAL_TX_TQM_RR_MULTICAST_DROP, 336 }; 337 338 /* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports 339 * @HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT: Default DSCP-TID mapping table 340 * @HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE: DSCP-TID map override table 341 */ 342 enum hal_tx_dscp_tid_table_id { 343 HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT, 344 HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE, 345 }; 346 347 /*--------------------------------------------------------------------------- 348 Function declarations and documentation 349 ---------------------------------------------------------------------------*/ 350 351 /*--------------------------------------------------------------------------- 352 Tx MSDU Extension Descriptor accessor APIs 353 ---------------------------------------------------------------------------*/ 354 /** 355 * hal_tx_ext_desc_set_tso_enable() - Set TSO Enable Flag 356 * @desc: Handle to Tx MSDU Extension Descriptor 357 * @tso_en: bool value set to true if TSO is enabled 358 * 359 * Return: none 360 */ 361 static inline void hal_tx_ext_desc_set_tso_enable(void *desc, 362 uint8_t tso_en) 363 { 364 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE) |= 365 HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TSO_ENABLE, tso_en); 366 } 367 368 /** 369 * hal_tx_ext_desc_set_tso_flags() - Set TSO Flags 370 * @desc: Handle to Tx MSDU Extension Descriptor 371 * @falgs: 32-bit word with all TSO flags consolidated 372 * 373 * Return: none 374 */ 375 static inline void hal_tx_ext_desc_set_tso_flags(void *desc, 376 uint32_t tso_flags) 377 { 378 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE, 0) = 379 tso_flags; 380 } 381 382 /** 383 * hal_tx_ext_desc_set_tcp_flags() - Enable HW Checksum offload 384 * @desc: Handle to Tx MSDU Extension Descriptor 385 * @tcp_flags: TCP flags {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 386 * @mask: TCP flag mask. Tcp_flag is inserted into the header 387 * based on the mask, if tso is enabled 388 * 389 * Return: none 390 */ 391 static inline void hal_tx_ext_desc_set_tcp_flags(void *desc, 392 uint16_t tcp_flags, 393 uint16_t mask) 394 { 395 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_FLAG) |= 396 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG, tcp_flags)) | 397 (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG_MASK, mask))); 398 } 399 400 /** 401 * hal_tx_ext_desc_set_msdu_length() - Set L2 and IP Lengths 402 * @desc: Handle to Tx MSDU Extension Descriptor 403 * @l2_len: L2 length for the msdu, if tso is enabled 404 * @ip_len: IP length for the msdu, if tso is enabled 405 * 406 * Return: none 407 */ 408 static inline void hal_tx_ext_desc_set_msdu_length(void *desc, 409 uint16_t l2_len, 410 uint16_t ip_len) 411 { 412 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, L2_LENGTH) |= 413 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, L2_LENGTH, l2_len)) | 414 (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_LENGTH, ip_len))); 415 } 416 417 /** 418 * hal_tx_ext_desc_set_tcp_seq() - Set TCP Sequence number 419 * @desc: Handle to Tx MSDU Extension Descriptor 420 * @seq_num: Tcp_seq_number for the msdu, if tso is enabled 421 * 422 * Return: none 423 */ 424 static inline void hal_tx_ext_desc_set_tcp_seq(void *desc, 425 uint32_t seq_num) 426 { 427 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER) |= 428 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER, seq_num))); 429 } 430 431 432 /** 433 * hal_tx_ext_desc_set_ip_id() - Set IP Identification field 434 * @desc: Handle to Tx MSDU Extension Descriptor 435 * @id: IP Id field for the msdu, if tso is enabled 436 * 437 * Return: none 438 */ 439 static inline void hal_tx_ext_desc_set_ip_id(void *desc, 440 uint16_t id) 441 { 442 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION) |= 443 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION, id))); 444 } 445 /** 446 * hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment 447 * @desc: Handle to Tx MSDU Extension Descriptor 448 * @frag_num: Fragment number (value can be 0 to 5) 449 * @paddr_lo: Lower 32-bit of Buffer Physical address 450 * @paddr_hi: Upper 32-bit of Buffer Physical address 451 * @length: Buffer Length 452 * 453 * Return: none 454 */ 455 static inline void hal_tx_ext_desc_set_buffer(void *desc, 456 uint8_t frag_num, 457 uint32_t paddr_lo, 458 uint16_t paddr_hi, 459 uint16_t length) 460 { 461 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, 462 (frag_num << 3)) |= 463 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo))); 464 465 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32, 466 (frag_num << 3)) |= 467 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32, 468 (paddr_hi)))); 469 470 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN, 471 (frag_num << 3)) |= 472 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length))); 473 } 474 475 /** 476 * hal_tx_ext_desc_get_frag_info() - Get the frag_num'th frag iova and len 477 * @desc: Handle to Tx MSDU Extension Descriptor 478 * @frag_num: fragment number (value can be 0 to 5) 479 * @iova: fragment dma address 480 * @len: fragement Length 481 * 482 * Return: None 483 */ 484 static inline void hal_tx_ext_desc_get_frag_info(void *desc, uint8_t frag_num, 485 qdf_dma_addr_t *iova, 486 uint32_t *len) 487 { 488 uint64_t iova_hi; 489 490 *iova = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, 491 BUF0_PTR_31_0, (frag_num << 3)); 492 493 iova_hi = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, 494 BUF0_PTR_39_32, (frag_num << 3)); 495 *iova |= (iova_hi << 32); 496 497 *len = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN, 498 (frag_num << 3)); 499 } 500 501 /** 502 * hal_tx_ext_desc_set_buffer0_param() - Set Buffer 0 Pointer and Length 503 * @desc: Handle to Tx MSDU Extension Descriptor 504 * @paddr_lo: Lower 32-bit of Buffer Physical address 505 * @paddr_hi: Upper 32-bit of Buffer Physical address 506 * @length: Buffer 0 Length 507 * 508 * Return: none 509 */ 510 static inline void hal_tx_ext_desc_set_buffer0_param(void *desc, 511 uint32_t paddr_lo, 512 uint16_t paddr_hi, 513 uint16_t length) 514 { 515 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0) |= 516 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo))); 517 518 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32) |= 519 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, 520 BUF0_PTR_39_32, paddr_hi))); 521 522 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN) |= 523 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length))); 524 } 525 526 /** 527 * hal_tx_ext_desc_set_buffer1_param() - Set Buffer 1 Pointer and Length 528 * @desc: Handle to Tx MSDU Extension Descriptor 529 * @paddr_lo: Lower 32-bit of Buffer Physical address 530 * @paddr_hi: Upper 32-bit of Buffer Physical address 531 * @length: Buffer 1 Length 532 * 533 * Return: none 534 */ 535 static inline void hal_tx_ext_desc_set_buffer1_param(void *desc, 536 uint32_t paddr_lo, 537 uint16_t paddr_hi, 538 uint16_t length) 539 { 540 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0) |= 541 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0, paddr_lo))); 542 543 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_39_32) |= 544 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, 545 BUF1_PTR_39_32, paddr_hi))); 546 547 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_LEN) |= 548 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_LEN, length))); 549 } 550 551 /** 552 * hal_tx_ext_desc_set_buffer2_param() - Set Buffer 2 Pointer and Length 553 * @desc: Handle to Tx MSDU Extension Descriptor 554 * @paddr_lo: Lower 32-bit of Buffer Physical address 555 * @paddr_hi: Upper 32-bit of Buffer Physical address 556 * @length: Buffer 2 Length 557 * 558 * Return: none 559 */ 560 static inline void hal_tx_ext_desc_set_buffer2_param(void *desc, 561 uint32_t paddr_lo, 562 uint16_t paddr_hi, 563 uint16_t length) 564 { 565 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0) |= 566 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0, 567 paddr_lo))); 568 569 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32) |= 570 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32, 571 paddr_hi))); 572 573 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_LEN) |= 574 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_LEN, length))); 575 } 576 577 /** 578 * hal_tx_ext_desc_sync - Commit the descriptor to Hardware 579 * @desc_cached: Cached descriptor that software maintains 580 * @hw_desc: Hardware descriptor to be updated 581 * 582 * Return: none 583 */ 584 static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached, 585 uint8_t *hw_desc) 586 { 587 qdf_mem_copy(&hw_desc[0], &desc_cached[0], 588 HAL_TX_EXT_DESC_WITH_META_DATA); 589 } 590 591 /** 592 * hal_tx_ext_desc_get_tso_enable() - Set TSO Enable Flag 593 * @hal_tx_ext_desc: Handle to Tx MSDU Extension Descriptor 594 * 595 * Return: tso_enable value in the descriptor 596 */ 597 static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc) 598 { 599 uint32_t *desc = (uint32_t *) hal_tx_ext_desc; 600 return (*desc & HAL_TX_MSDU_EXTENSION_TSO_ENABLE_MASK) >> 601 HAL_TX_MSDU_EXTENSION_TSO_ENABLE_LSB; 602 } 603 604 /*--------------------------------------------------------------------------- 605 WBM Descriptor accessor APIs for Tx completions 606 ---------------------------------------------------------------------------*/ 607 /** 608 * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type 609 * @hal_desc: completion ring descriptor pointer 610 * 611 * This function will return the type of pointer - buffer or descriptor 612 * 613 * Return: buffer type 614 */ 615 static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc) 616 { 617 uint32_t comp_desc = 618 *(uint32_t *) (((uint8_t *) hal_desc) + 619 HAL_TX_COMP_BUFFER_OR_DESC_TYPE_OFFSET); 620 621 return (comp_desc & HAL_TX_COMP_BUFFER_OR_DESC_TYPE_MASK) >> 622 HAL_TX_COMP_BUFFER_OR_DESC_TYPE_LSB; 623 } 624 625 #ifdef QCA_WIFI_KIWI 626 /** 627 * hal_tx_comp_get_buffer_source() - Get buffer release source value 628 * @hal_desc: completion ring descriptor pointer 629 * 630 * This function will get buffer release source from Tx completion descriptor 631 * 632 * Return: buffer release source 633 */ 634 static inline uint32_t 635 hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl, 636 void *hal_desc) 637 { 638 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 639 640 return hal_soc->ops->hal_tx_comp_get_buffer_source(hal_desc); 641 } 642 #else 643 static inline uint32_t 644 hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl, 645 void *hal_desc) 646 { 647 return HAL_WBM2SW_RELEASE_SRC_GET(hal_desc); 648 } 649 #endif 650 651 /** 652 * hal_tx_comp_get_release_reason() - TQM Release reason 653 * @hal_desc: completion ring descriptor pointer 654 * 655 * This function will return the type of pointer - buffer or descriptor 656 * 657 * Return: buffer type 658 */ 659 static inline 660 uint8_t hal_tx_comp_get_release_reason(void *hal_desc, 661 hal_soc_handle_t hal_soc_hdl) 662 { 663 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 664 665 return hal_soc->ops->hal_tx_comp_get_release_reason(hal_desc); 666 } 667 668 /** 669 * hal_tx_comp_get_peer_id() - Get peer_id value() 670 * @hal_desc: completion ring descriptor pointer 671 * 672 * This function will get peer_id value from Tx completion descriptor 673 * 674 * Return: buffer release source 675 */ 676 static inline uint16_t hal_tx_comp_get_peer_id(void *hal_desc) 677 { 678 uint32_t comp_desc = 679 *(uint32_t *)(((uint8_t *)hal_desc) + 680 HAL_TX_COMP_SW_PEER_ID_OFFSET); 681 682 return (comp_desc & HAL_TX_COMP_SW_PEER_ID_MASK) >> 683 HAL_TX_COMP_SW_PEER_ID_LSB; 684 } 685 686 /** 687 * hal_tx_comp_get_tx_status() - Get tx transmission status() 688 * @hal_desc: completion ring descriptor pointer 689 * 690 * This function will get transmit status value from Tx completion descriptor 691 * 692 * Return: buffer release source 693 */ 694 static inline uint8_t hal_tx_comp_get_tx_status(void *hal_desc) 695 { 696 uint32_t comp_desc = 697 *(uint32_t *)(((uint8_t *)hal_desc) + 698 HAL_TX_COMP_TQM_RELEASE_REASON_OFFSET); 699 700 return (comp_desc & HAL_TX_COMP_TQM_RELEASE_REASON_MASK) >> 701 HAL_TX_COMP_TQM_RELEASE_REASON_LSB; 702 } 703 704 /** 705 * hal_tx_comp_desc_sync() - collect hardware descriptor contents 706 * @hal_desc: hardware descriptor pointer 707 * @comp: software descriptor pointer 708 * @read_status: 0 - Do not read status words from descriptors 709 * 1 - Enable reading of status words from descriptor 710 * 711 * This function will collect hardware release ring element contents and 712 * translate to software descriptor content 713 * 714 * Return: none 715 */ 716 717 static inline void hal_tx_comp_desc_sync(void *hw_desc, 718 struct hal_tx_desc_comp_s *comp, 719 bool read_status) 720 { 721 if (!read_status) 722 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_BASE_LEN); 723 else 724 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_LEN_BYTES); 725 } 726 727 /** 728 * hal_dump_comp_desc() - dump tx completion descriptor 729 * @hal_desc: hardware descriptor pointer 730 * 731 * This function will print tx completion descriptor 732 * 733 * Return: none 734 */ 735 static inline void hal_dump_comp_desc(void *hw_desc) 736 { 737 struct hal_tx_desc_comp_s *comp = 738 (struct hal_tx_desc_comp_s *)hw_desc; 739 uint32_t i; 740 741 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 742 "Current tx completion descriptor is"); 743 744 for (i = 0; i < HAL_TX_COMPLETION_DESC_LEN_DWORDS; i++) { 745 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 746 "DWORD[i] = 0x%x", comp->desc[i]); 747 } 748 } 749 750 /** 751 * hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor 752 * @hal_desc: Hardware (WBM) descriptor pointer 753 * @htt_desc: Software HTT descriptor pointer 754 * 755 * This function will read the HTT structure overlaid on WBM descriptor 756 * into a cached software descriptor 757 * 758 */ 759 static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc) 760 { 761 uint8_t *desc = hw_desc + HAL_TX_COMP_HTT_STATUS_OFFSET; 762 763 qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN); 764 } 765 766 /** 767 * hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG 768 * @hal_soc_hdl: Handle to HAL SoC structure 769 * @hal_srng: Handle to HAL SRNG structure 770 * 771 * Return: none 772 */ 773 static inline void hal_tx_init_data_ring(hal_soc_handle_t hal_soc_hdl, 774 hal_ring_handle_t hal_ring_hdl) 775 { 776 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 777 778 hal_soc->ops->hal_tx_init_data_ring(hal_soc_hdl, hal_ring_hdl); 779 } 780 781 /** 782 * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table 783 * 784 * @soc: HAL SoC context 785 * @map: DSCP-TID mapping table 786 * @id: mapping table ID - 0,1 787 * 788 * Return: void 789 */ 790 static inline void hal_tx_set_dscp_tid_map(hal_soc_handle_t hal_soc_hdl, 791 uint8_t *map, uint8_t id) 792 { 793 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 794 795 hal_soc->ops->hal_tx_set_dscp_tid_map(hal_soc, map, id); 796 } 797 798 /** 799 * hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user 800 * 801 * @soc: HAL SoC context 802 * @map: DSCP-TID mapping table 803 * @id : MAP ID 804 * @dscp: DSCP_TID map index 805 * 806 * Return: void 807 */ 808 static inline 809 void hal_tx_update_dscp_tid(hal_soc_handle_t hal_soc_hdl, uint8_t tid, 810 uint8_t id, uint8_t dscp) 811 { 812 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 813 814 hal_soc->ops->hal_tx_update_dscp_tid(hal_soc, tid, id, dscp); 815 } 816 817 /** 818 * hal_tx_comp_get_status() - TQM Release reason 819 * @hal_desc: completion ring Tx status 820 * 821 * This function will parse the WBM completion descriptor and populate in 822 * HAL structure 823 * 824 * Return: none 825 */ 826 static inline void hal_tx_comp_get_status(void *desc, void *ts, 827 hal_soc_handle_t hal_soc_hdl) 828 { 829 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 830 831 hal_soc->ops->hal_tx_comp_get_status(desc, ts, hal_soc); 832 } 833 834 /** 835 * hal_tx_set_pcp_tid_map_default() - Configure default PCP to TID map table 836 * 837 * @soc: HAL SoC context 838 * @map: PCP-TID mapping table 839 * 840 * Return: void 841 */ 842 static inline void hal_tx_set_pcp_tid_map_default(hal_soc_handle_t hal_soc_hdl, 843 uint8_t *map) 844 { 845 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 846 847 hal_soc->ops->hal_tx_set_pcp_tid_map(hal_soc, map); 848 } 849 850 /** 851 * hal_tx_update_pcp_tid_map() - Update PCP to TID map table 852 * 853 * @soc: HAL SoC context 854 * @pcp: pcp value 855 * @tid: tid no 856 * 857 * Return: void 858 */ 859 static inline void hal_tx_update_pcp_tid_map(hal_soc_handle_t hal_soc_hdl, 860 uint8_t pcp, uint8_t tid) 861 { 862 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 863 864 hal_soc->ops->hal_tx_update_pcp_tid_map(hal_soc, pcp, tid); 865 } 866 867 /** 868 * hal_tx_set_tidmap_prty() - Configure TIDmap priority 869 * 870 * @soc: HAL SoC context 871 * @val: priority value 872 * 873 * Return: void 874 */ 875 static inline 876 void hal_tx_set_tidmap_prty(hal_soc_handle_t hal_soc_hdl, uint8_t val) 877 { 878 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 879 880 hal_soc->ops->hal_tx_set_tidmap_prty(hal_soc, val); 881 } 882 883 /** 884 * hal_get_wbm_internal_error() - wbm internal error 885 * @hal_desc: completion ring descriptor pointer 886 * 887 * This function will return the type of pointer - buffer or descriptor 888 * 889 * Return: buffer type 890 */ 891 static inline 892 uint8_t hal_get_wbm_internal_error(hal_soc_handle_t hal_soc_hdl, void *hal_desc) 893 { 894 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 895 896 return hal_soc->ops->hal_get_wbm_internal_error(hal_desc); 897 } 898 #endif /* HAL_TX_H */ 899