1 /* 2 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #if !defined(HAL_TX_H) 20 #define HAL_TX_H 21 22 /*--------------------------------------------------------------------------- 23 Include files 24 ---------------------------------------------------------------------------*/ 25 #include "hal_api.h" 26 #include "wcss_version.h" 27 28 #define WBM_RELEASE_RING_5_TX_RATE_STATS_OFFSET 0x00000014 29 #define WBM_RELEASE_RING_5_TX_RATE_STATS_LSB 0 30 #define WBM_RELEASE_RING_5_TX_RATE_STATS_MASK 0xffffffff 31 32 33 /*--------------------------------------------------------------------------- 34 Preprocessor definitions and constants 35 ---------------------------------------------------------------------------*/ 36 #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET 37 38 #define HAL_SET_FLD(desc, block , field) \ 39 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field))) 40 41 #define HAL_SET_FLD_OFFSET(desc, block , field, offset) \ 42 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field) + (offset))) 43 44 #define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \ 45 do { \ 46 ((struct tlv_32_hdr *) desc)->tlv_tag = (tag); \ 47 ((struct tlv_32_hdr *) desc)->tlv_len = (len); \ 48 } while (0) 49 50 #define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E 51 #define HAL_TX_TCL_CMD_TAG WIFITCL_GSE_CMD_E 52 53 #define HAL_TX_SM(block, field, value) \ 54 ((value << (block ## _ ## field ## _LSB)) & \ 55 (block ## _ ## field ## _MASK)) 56 57 #define HAL_TX_MS(block, field, value) \ 58 (((value) & (block ## _ ## field ## _MASK)) >> \ 59 (block ## _ ## field ## _LSB)) 60 61 #define HAL_TX_DESC_GET(desc, block, field) \ 62 HAL_TX_MS(block, field, HAL_SET_FLD(desc, block, field)) 63 64 #define HAL_TX_DESC_SUBBLOCK_GET(desc, block, sub, field) \ 65 HAL_TX_MS(sub, field, HAL_SET_FLD(desc, block, sub)) 66 67 #define HAL_TX_BUF_TYPE_BUFFER 0 68 #define HAL_TX_BUF_TYPE_EXT_DESC 1 69 70 #define HAL_TX_DESC_LEN_DWORDS (NUM_OF_DWORDS_TCL_DATA_CMD) 71 #define HAL_TX_DESC_LEN_BYTES (NUM_OF_DWORDS_TCL_DATA_CMD * 4) 72 #define HAL_TX_EXTENSION_DESC_LEN_DWORDS (NUM_OF_DWORDS_TX_MSDU_EXTENSION) 73 #define HAL_TX_EXTENSION_DESC_LEN_BYTES (NUM_OF_DWORDS_TX_MSDU_EXTENSION * 4) 74 75 #define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 76 #define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4) 77 #define HAL_TX_BITS_PER_TID 3 78 #define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1) 79 #define HAL_TX_NUM_DSCP_PER_REGISTER 10 80 #define HAL_MAX_HW_DSCP_TID_MAPS 2 81 #define HAL_MAX_HW_DSCP_TID_MAPS_11AX 32 82 83 #define HAL_MAX_HW_DSCP_TID_V2_MAPS 48 84 #define HTT_META_HEADER_LEN_BYTES 64 85 #define HAL_TX_EXT_DESC_WITH_META_DATA \ 86 (HTT_META_HEADER_LEN_BYTES + HAL_TX_EXTENSION_DESC_LEN_BYTES) 87 88 #define HAL_TX_NUM_PCP_PER_REGISTER 8 89 90 /* Length of WBM release ring without the status words */ 91 #define HAL_TX_COMPLETION_DESC_BASE_LEN 12 92 93 #define HAL_TX_COMP_RELEASE_SOURCE_TQM 0 94 #define HAL_TX_COMP_RELEASE_SOURCE_FW 3 95 96 /* Define a place-holder release reason for FW */ 97 #define HAL_TX_COMP_RELEASE_REASON_FW 99 98 99 /* 100 * Offset of HTT Tx Descriptor in WBM Completion 101 * HTT Tx Desc structure is passed from firmware to host overlayed 102 * on wbm_release_ring DWORDs 2,3 ,4 and 5for software based completions 103 * (Exception frames and TQM bypass frames) 104 */ 105 #define HAL_TX_COMP_HTT_STATUS_OFFSET 8 106 #define HAL_TX_COMP_HTT_STATUS_LEN 16 107 108 #define HAL_TX_BUF_TYPE_BUFFER 0 109 #define HAL_TX_BUF_TYPE_EXT_DESC 1 110 111 #define HAL_TX_EXT_DESC_BUF_OFFSET TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 112 #define HAL_TX_EXT_BUF_LOW_MASK TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 113 #define HAL_TX_EXT_BUF_HI_MASK TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 114 #define HAL_TX_EXT_BUF_LEN_MASK TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 115 #define HAL_TX_EXT_BUF_LEN_LSB TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 116 #define HAL_TX_EXT_BUF_WD_SIZE 2 117 118 #define HAL_TX_DESC_ADDRX_EN 0x1 119 #define HAL_TX_DESC_ADDRY_EN 0x2 120 #define HAL_TX_DESC_DEFAULT_LMAC_ID 0x3 121 122 #define HAL_TX_ADDR_SEARCH_DEFAULT 0x0 123 #define HAL_TX_ADDR_INDEX_SEARCH 0x1 124 #define HAL_TX_FLOW_INDEX_SEARCH 0x2 125 126 enum hal_tx_ret_buf_manager { 127 HAL_WBM_SW0_BM_ID = 3, 128 HAL_WBM_SW1_BM_ID = 4, 129 HAL_WBM_SW2_BM_ID = 5, 130 HAL_WBM_SW3_BM_ID = 6, 131 }; 132 133 /*--------------------------------------------------------------------------- 134 Structures 135 ---------------------------------------------------------------------------*/ 136 /** 137 * struct hal_tx_completion_status - HAL Tx completion descriptor contents 138 * @status: frame acked/failed 139 * @release_src: release source = TQM/FW 140 * @ack_frame_rssi: RSSI of the received ACK or BA frame 141 * @first_msdu: Indicates this MSDU is the first MSDU in AMSDU 142 * @last_msdu: Indicates this MSDU is the last MSDU in AMSDU 143 * @msdu_part_of_amsdu : Indicates this MSDU was part of an A-MSDU in MPDU 144 * @bw: Indicates the BW of the upcoming transmission - 145 * <enum 0 transmit_bw_20_MHz> 146 * <enum 1 transmit_bw_40_MHz> 147 * <enum 2 transmit_bw_80_MHz> 148 * <enum 3 transmit_bw_160_MHz> 149 * @pkt_type: Transmit Packet Type 150 * @stbc: When set, STBC transmission rate was used 151 * @ldpc: When set, use LDPC transmission rates 152 * @sgi: <enum 0 0_8_us_sgi > Legacy normal GI 153 * <enum 1 0_4_us_sgi > Legacy short GI 154 * <enum 2 1_6_us_sgi > HE related GI 155 * <enum 3 3_2_us_sgi > HE 156 * @mcs: Transmit MCS Rate 157 * @ofdma: Set when the transmission was an OFDMA transmission 158 * @tones_in_ru: The number of tones in the RU used. 159 * @tsf: Lower 32 bits of the TSF 160 * @ppdu_id: TSF, snapshot of this value when transmission of the 161 * PPDU containing the frame finished. 162 * @transmit_cnt: Number of times this frame has been transmitted 163 * @tid: TID of the flow or MPDU queue 164 * @peer_id: Peer ID of the flow or MPDU queue 165 */ 166 struct hal_tx_completion_status { 167 uint8_t status; 168 uint8_t release_src; 169 uint8_t ack_frame_rssi; 170 uint8_t first_msdu:1, 171 last_msdu:1, 172 msdu_part_of_amsdu:1; 173 uint32_t bw:2, 174 pkt_type:4, 175 stbc:1, 176 ldpc:1, 177 sgi:2, 178 mcs:4, 179 ofdma:1, 180 tones_in_ru:12, 181 valid:1; 182 uint32_t tsf; 183 uint32_t ppdu_id; 184 uint8_t transmit_cnt; 185 uint8_t tid; 186 uint16_t peer_id; 187 }; 188 189 /** 190 * struct hal_tx_desc_comp_s - hal tx completion descriptor contents 191 * @desc: Transmit status information from descriptor 192 */ 193 struct hal_tx_desc_comp_s { 194 uint32_t desc[HAL_TX_COMPLETION_DESC_LEN_DWORDS]; 195 }; 196 197 /* 198 * enum hal_tx_encrypt_type - Type of decrypt cipher used (valid only for RAW) 199 * @HAL_TX_ENCRYPT_TYPE_WEP_40: WEP 40-bit 200 * @HAL_TX_ENCRYPT_TYPE_WEP_10: WEP 10-bit 201 * @HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC: TKIP without MIC 202 * @HAL_TX_ENCRYPT_TYPE_WEP_128: WEP_128 203 * @HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC: TKIP_WITH_MIC 204 * @HAL_TX_ENCRYPT_TYPE_WAPI: WAPI 205 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_128: AES_CCMP_128 206 * @HAL_TX_ENCRYPT_TYPE_NO_CIPHER: NO CIPHER 207 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_256: AES_CCMP_256 208 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_128: AES_GCMP_128 209 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_256: AES_GCMP_256 210 * @HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4: WAPI GCM SM4 211 */ 212 enum hal_tx_encrypt_type { 213 HAL_TX_ENCRYPT_TYPE_WEP_40 = 0, 214 HAL_TX_ENCRYPT_TYPE_WEP_104 = 1 , 215 HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC = 2, 216 HAL_TX_ENCRYPT_TYPE_WEP_128 = 3, 217 HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC = 4, 218 HAL_TX_ENCRYPT_TYPE_WAPI = 5, 219 HAL_TX_ENCRYPT_TYPE_AES_CCMP_128 = 6, 220 HAL_TX_ENCRYPT_TYPE_NO_CIPHER = 7, 221 HAL_TX_ENCRYPT_TYPE_AES_CCMP_256 = 8, 222 HAL_TX_ENCRYPT_TYPE_AES_GCMP_128 = 9, 223 HAL_TX_ENCRYPT_TYPE_AES_GCMP_256 = 10, 224 HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4 = 11, 225 }; 226 227 /* 228 * enum hal_tx_encap_type - Encapsulation type that HW will perform 229 * @HAL_TX_ENCAP_TYPE_RAW: Raw Packet Type 230 * @HAL_TX_ENCAP_TYPE_NWIFI: Native WiFi Type 231 * @HAL_TX_ENCAP_TYPE_ETHERNET: Ethernet 232 * @HAL_TX_ENCAP_TYPE_802_3: 802.3 Frame 233 */ 234 enum hal_tx_encap_type { 235 HAL_TX_ENCAP_TYPE_RAW = 0, 236 HAL_TX_ENCAP_TYPE_NWIFI = 1, 237 HAL_TX_ENCAP_TYPE_ETHERNET = 2, 238 HAL_TX_ENCAP_TYPE_802_3 = 3, 239 }; 240 241 /** 242 * enum hal_tx_tqm_release_reason - TQM Release reason codes 243 * 244 * @HAL_TX_TQM_RR_FRAME_ACKED : ACK of BA for it was received 245 * @HAL_TX_TQM_RR_REM_CMD_REM : Remove cmd of type “Remove_mpdus” initiated 246 * by SW 247 * @HAL_TX_TQM_RR_REM_CMD_TX : Remove command of type Remove_transmitted_mpdus 248 * initiated by SW 249 * @HAL_TX_TQM_RR_REM_CMD_NOTX : Remove cmd of type Remove_untransmitted_mpdus 250 * initiated by SW 251 * @HAL_TX_TQM_RR_REM_CMD_AGED : Remove command of type “Remove_aged_mpdus” or 252 * “Remove_aged_msdus” initiated by SW 253 * @HAL_TX_TQM_RR_FW_REASON1 : Remove command where fw indicated that 254 * remove reason is fw_reason1 255 * @HAL_TX_TQM_RR_FW_REASON2 : Remove command where fw indicated that 256 * remove reason is fw_reason2 257 * @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that 258 * remove reason is fw_reason3 259 */ 260 enum hal_tx_tqm_release_reason { 261 HAL_TX_TQM_RR_FRAME_ACKED, 262 HAL_TX_TQM_RR_REM_CMD_REM, 263 HAL_TX_TQM_RR_REM_CMD_TX, 264 HAL_TX_TQM_RR_REM_CMD_NOTX, 265 HAL_TX_TQM_RR_REM_CMD_AGED, 266 HAL_TX_TQM_RR_FW_REASON1, 267 HAL_TX_TQM_RR_FW_REASON2, 268 HAL_TX_TQM_RR_FW_REASON3, 269 }; 270 271 /* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports 272 * @HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT: Default DSCP-TID mapping table 273 * @HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE: DSCP-TID map override table 274 */ 275 enum hal_tx_dscp_tid_table_id { 276 HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT, 277 HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE, 278 }; 279 280 /*--------------------------------------------------------------------------- 281 Function declarations and documentation 282 ---------------------------------------------------------------------------*/ 283 284 /*--------------------------------------------------------------------------- 285 TCL Descriptor accessor APIs 286 ---------------------------------------------------------------------------*/ 287 288 /** 289 * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor 290 * @desc: Handle to Tx Descriptor 291 * @data_length: MSDU length in case of direct descriptor. 292 * Length of link extension descriptor in case of Link extension 293 * descriptor.Includes the length of Metadata 294 * Return: None 295 */ 296 static inline void hal_tx_desc_set_buf_length(void *desc, 297 uint16_t data_length) 298 { 299 HAL_SET_FLD(desc, TCL_DATA_CMD_3, DATA_LENGTH) |= 300 HAL_TX_SM(TCL_DATA_CMD_3, DATA_LENGTH, data_length); 301 } 302 303 /** 304 * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor 305 * @desc: Handle to Tx Descriptor 306 * @offset: Packet offset from Metadata in case of direct buffer descriptor. 307 * 308 * Return: void 309 */ 310 static inline void hal_tx_desc_set_buf_offset(void *desc, 311 uint8_t offset) 312 { 313 HAL_SET_FLD(desc, TCL_DATA_CMD_3, PACKET_OFFSET) |= 314 HAL_TX_SM(TCL_DATA_CMD_3, PACKET_OFFSET, offset); 315 } 316 317 /** 318 * hal_tx_desc_set_encap_type - Set encapsulation type in Tx Descriptor 319 * @desc: Handle to Tx Descriptor 320 * @encap_type: Encapsulation that HW will perform 321 * 322 * Return: void 323 * 324 */ 325 static inline void hal_tx_desc_set_encap_type(void *desc, 326 enum hal_tx_encap_type encap_type) 327 { 328 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCAP_TYPE) |= 329 HAL_TX_SM(TCL_DATA_CMD_2, ENCAP_TYPE, encap_type); 330 } 331 332 /** 333 * hal_tx_desc_set_encrypt_type - Sets the Encrypt Type in Tx Descriptor 334 * @desc: Handle to Tx Descriptor 335 * @type: Encrypt Type 336 * 337 * Return: void 338 */ 339 static inline void hal_tx_desc_set_encrypt_type(void *desc, 340 enum hal_tx_encrypt_type type) 341 { 342 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCRYPT_TYPE) |= 343 HAL_TX_SM(TCL_DATA_CMD_2, ENCRYPT_TYPE, type); 344 } 345 346 /** 347 * hal_tx_desc_set_addr_search_flags - Enable AddrX and AddrY search flags 348 * @desc: Handle to Tx Descriptor 349 * @flags: Bit 0 - AddrY search enable, Bit 1 - AddrX search enable 350 * 351 * Return: void 352 */ 353 static inline void hal_tx_desc_set_addr_search_flags(void *desc, 354 uint8_t flags) 355 { 356 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRX_EN) |= 357 HAL_TX_SM(TCL_DATA_CMD_2, ADDRX_EN, (flags & 0x1)); 358 359 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRY_EN) |= 360 HAL_TX_SM(TCL_DATA_CMD_2, ADDRY_EN, (flags >> 1)); 361 } 362 363 /** 364 * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags 365 * Tx Descriptor for MSDU_buffer type 366 * @desc: Handle to Tx Descriptor 367 * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits) 368 * 369 * Return: void 370 */ 371 static inline void hal_tx_desc_set_l4_checksum_en(void *desc, 372 uint8_t en) 373 { 374 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 375 (HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV4_CHECKSUM_EN, en) | 376 HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV6_CHECKSUM_EN, en) | 377 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV4_CHECKSUM_EN, en) | 378 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV6_CHECKSUM_EN, en)); 379 } 380 381 /** 382 * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in 383 * Tx Descriptor for MSDU_buffer type 384 * @desc: Handle to Tx Descriptor 385 * @checksum_en_flags: ipv4 checksum enable flags 386 * 387 * Return: void 388 */ 389 static inline void hal_tx_desc_set_l3_checksum_en(void *desc, 390 uint8_t en) 391 { 392 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 393 HAL_TX_SM(TCL_DATA_CMD_3, IPV4_CHECKSUM_EN, en); 394 } 395 396 /** 397 * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor 398 * @desc:Handle to Tx Descriptor 399 * @metadata: Metadata to be sent to Firmware 400 * 401 * Return: void 402 */ 403 static inline void hal_tx_desc_set_fw_metadata(void *desc, 404 uint16_t metadata) 405 { 406 HAL_SET_FLD(desc, TCL_DATA_CMD_2, TCL_CMD_NUMBER) |= 407 HAL_TX_SM(TCL_DATA_CMD_2, TCL_CMD_NUMBER, metadata); 408 } 409 410 /** 411 * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor. 412 * @desc:Handle to Tx Descriptor 413 * @to_fw: if set, Forward packet to FW along with classification result 414 * 415 * Return: void 416 */ 417 static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw) 418 { 419 HAL_SET_FLD(desc, TCL_DATA_CMD_3, TO_FW) |= 420 HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw); 421 } 422 423 /** 424 * hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor 425 * @desc: Handle to Tx Descriptor 426 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 427 * enabling the interpretation of the 'Mesh Control Present' bit 428 * (bit 8) of QoS Control (otherwise this bit is ignored), 429 * For native WiFi frames, this indicates that a 'Mesh Control' field 430 * is present between the header and the LLC. 431 * 432 * Return: void 433 */ 434 static inline void hal_tx_desc_set_mesh_en(void *desc, uint8_t en) 435 { 436 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 437 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 438 } 439 440 /** 441 * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in 442 * frame) to be used for Tx Frame 443 * @desc: Handle to Tx Descriptor 444 * @hlos_tid: HLOS TID 445 * 446 * Return: void 447 */ 448 static inline void hal_tx_desc_set_hlos_tid(void *desc, 449 uint8_t hlos_tid) 450 { 451 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID) |= 452 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID, hlos_tid); 453 454 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |= 455 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1); 456 } 457 /** 458 * hal_tx_desc_sync - Commit the descriptor to Hardware 459 * @hal_tx_des_cached: Cached descriptor that software maintains 460 * @hw_desc: Hardware descriptor to be updated 461 */ 462 static inline void hal_tx_desc_sync(void *hal_tx_desc_cached, 463 void *hw_desc) 464 { 465 qdf_mem_copy((hw_desc + sizeof(struct tlv_32_hdr)), 466 hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES); 467 } 468 469 /*--------------------------------------------------------------------------- 470 Tx MSDU Extension Descriptor accessor APIs 471 ---------------------------------------------------------------------------*/ 472 /** 473 * hal_tx_ext_desc_set_tso_enable() - Set TSO Enable Flag 474 * @desc: Handle to Tx MSDU Extension Descriptor 475 * @tso_en: bool value set to true if TSO is enabled 476 * 477 * Return: none 478 */ 479 static inline void hal_tx_ext_desc_set_tso_enable(void *desc, 480 uint8_t tso_en) 481 { 482 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TSO_ENABLE) |= 483 HAL_TX_SM(TX_MSDU_EXTENSION_0, TSO_ENABLE, tso_en); 484 } 485 486 /** 487 * hal_tx_ext_desc_set_tso_flags() - Set TSO Flags 488 * @desc: Handle to Tx MSDU Extension Descriptor 489 * @falgs: 32-bit word with all TSO flags consolidated 490 * 491 * Return: none 492 */ 493 static inline void hal_tx_ext_desc_set_tso_flags(void *desc, 494 uint32_t tso_flags) 495 { 496 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_0, TSO_ENABLE, 0) = 497 tso_flags; 498 } 499 500 /** 501 * hal_tx_ext_desc_set_tcp_flags() - Enable HW Checksum offload 502 * @desc: Handle to Tx MSDU Extension Descriptor 503 * @tcp_flags: TCP flags {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 504 * @mask: TCP flag mask. Tcp_flag is inserted into the header 505 * based on the mask, if tso is enabled 506 * 507 * Return: none 508 */ 509 static inline void hal_tx_ext_desc_set_tcp_flags(void *desc, 510 uint16_t tcp_flags, 511 uint16_t mask) 512 { 513 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TCP_FLAG) |= 514 ((HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG, tcp_flags)) | 515 (HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG_MASK, mask))); 516 } 517 518 /** 519 * hal_tx_ext_desc_set_msdu_length() - Set L2 and IP Lengths 520 * @desc: Handle to Tx MSDU Extension Descriptor 521 * @l2_len: L2 length for the msdu, if tso is enabled 522 * @ip_len: IP length for the msdu, if tso is enabled 523 * 524 * Return: none 525 */ 526 static inline void hal_tx_ext_desc_set_msdu_length(void *desc, 527 uint16_t l2_len, 528 uint16_t ip_len) 529 { 530 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_1, L2_LENGTH) |= 531 ((HAL_TX_SM(TX_MSDU_EXTENSION_1, L2_LENGTH, l2_len)) | 532 (HAL_TX_SM(TX_MSDU_EXTENSION_1, IP_LENGTH, ip_len))); 533 } 534 535 /** 536 * hal_tx_ext_desc_set_tcp_seq() - Set TCP Sequence number 537 * @desc: Handle to Tx MSDU Extension Descriptor 538 * @seq_num: Tcp_seq_number for the msdu, if tso is enabled 539 * 540 * Return: none 541 */ 542 static inline void hal_tx_ext_desc_set_tcp_seq(void *desc, 543 uint32_t seq_num) 544 { 545 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER) |= 546 ((HAL_TX_SM(TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER, seq_num))); 547 } 548 549 550 /** 551 * hal_tx_ext_desc_set_ip_id() - Set IP Identification field 552 * @desc: Handle to Tx MSDU Extension Descriptor 553 * @id: IP Id field for the msdu, if tso is enabled 554 * 555 * Return: none 556 */ 557 static inline void hal_tx_ext_desc_set_ip_id(void *desc, 558 uint16_t id) 559 { 560 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_3, IP_IDENTIFICATION) |= 561 ((HAL_TX_SM(TX_MSDU_EXTENSION_3, IP_IDENTIFICATION, id))); 562 } 563 /** 564 * hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment 565 * @desc: Handle to Tx MSDU Extension Descriptor 566 * @frag_num: Fragment number (value can be 0 to 5) 567 * @paddr_lo: Lower 32-bit of Buffer Physical address 568 * @paddr_hi: Upper 32-bit of Buffer Physical address 569 * @length: Buffer Length 570 * 571 * Return: none 572 */ 573 static inline void hal_tx_ext_desc_set_buffer(void *desc, 574 uint8_t frag_num, 575 uint32_t paddr_lo, 576 uint16_t paddr_hi, 577 uint16_t length) 578 { 579 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, 580 (frag_num << 3)) |= 581 ((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo))); 582 583 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32, 584 (frag_num << 3)) |= 585 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_PTR_39_32, 586 (paddr_hi)))); 587 588 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_LEN, 589 (frag_num << 3)) |= 590 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length))); 591 } 592 593 /** 594 * hal_tx_ext_desc_set_buffer0_param() - Set Buffer 0 Pointer and Length 595 * @desc: Handle to Tx MSDU Extension Descriptor 596 * @paddr_lo: Lower 32-bit of Buffer Physical address 597 * @paddr_hi: Upper 32-bit of Buffer Physical address 598 * @length: Buffer 0 Length 599 * 600 * Return: none 601 */ 602 static inline void hal_tx_ext_desc_set_buffer0_param(void *desc, 603 uint32_t paddr_lo, 604 uint16_t paddr_hi, 605 uint16_t length) 606 { 607 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0) |= 608 ((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo))); 609 610 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32) |= 611 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, 612 BUF0_PTR_39_32, paddr_hi))); 613 614 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_LEN) |= 615 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length))); 616 } 617 618 /** 619 * hal_tx_ext_desc_set_buffer1_param() - Set Buffer 1 Pointer and Length 620 * @desc: Handle to Tx MSDU Extension Descriptor 621 * @paddr_lo: Lower 32-bit of Buffer Physical address 622 * @paddr_hi: Upper 32-bit of Buffer Physical address 623 * @length: Buffer 1 Length 624 * 625 * Return: none 626 */ 627 static inline void hal_tx_ext_desc_set_buffer1_param(void *desc, 628 uint32_t paddr_lo, 629 uint16_t paddr_hi, 630 uint16_t length) 631 { 632 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_8, BUF1_PTR_31_0) |= 633 ((HAL_TX_SM(TX_MSDU_EXTENSION_8, BUF1_PTR_31_0, paddr_lo))); 634 635 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_PTR_39_32) |= 636 ((HAL_TX_SM(TX_MSDU_EXTENSION_9, 637 BUF1_PTR_39_32, paddr_hi))); 638 639 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_LEN) |= 640 ((HAL_TX_SM(TX_MSDU_EXTENSION_9, BUF1_LEN, length))); 641 } 642 643 /** 644 * hal_tx_ext_desc_set_buffer2_param() - Set Buffer 2 Pointer and Length 645 * @desc: Handle to Tx MSDU Extension Descriptor 646 * @paddr_lo: Lower 32-bit of Buffer Physical address 647 * @paddr_hi: Upper 32-bit of Buffer Physical address 648 * @length: Buffer 2 Length 649 * 650 * Return: none 651 */ 652 static inline void hal_tx_ext_desc_set_buffer2_param(void *desc, 653 uint32_t paddr_lo, 654 uint16_t paddr_hi, 655 uint16_t length) 656 { 657 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_10, BUF2_PTR_31_0) |= 658 ((HAL_TX_SM(TX_MSDU_EXTENSION_10, BUF2_PTR_31_0, 659 paddr_lo))); 660 661 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_PTR_39_32) |= 662 ((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_PTR_39_32, 663 paddr_hi))); 664 665 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_LEN) |= 666 ((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_LEN, length))); 667 } 668 669 /** 670 * hal_tx_ext_desc_sync - Commit the descriptor to Hardware 671 * @desc_cached: Cached descriptor that software maintains 672 * @hw_desc: Hardware descriptor to be updated 673 * 674 * Return: none 675 */ 676 static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached, 677 uint8_t *hw_desc) 678 { 679 qdf_mem_copy(&hw_desc[0], &desc_cached[0], 680 HAL_TX_EXT_DESC_WITH_META_DATA); 681 } 682 683 /** 684 * hal_tx_ext_desc_get_tso_enable() - Set TSO Enable Flag 685 * @hal_tx_ext_desc: Handle to Tx MSDU Extension Descriptor 686 * 687 * Return: tso_enable value in the descriptor 688 */ 689 static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc) 690 { 691 uint32_t *desc = (uint32_t *) hal_tx_ext_desc; 692 return (*desc & TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK) >> 693 TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB; 694 } 695 696 /*--------------------------------------------------------------------------- 697 WBM Descriptor accessor APIs for Tx completions 698 ---------------------------------------------------------------------------*/ 699 /** 700 * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor 701 * @hal_desc: completion ring descriptor pointer 702 * 703 * This function will tx descriptor id, cookie, within hardware completion 704 * descriptor 705 * 706 * Return: cookie 707 */ 708 static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc) 709 { 710 uint32_t comp_desc = 711 *(uint32_t *) (((uint8_t *) hal_desc) + 712 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET); 713 714 /* Cookie is placed on 2nd word */ 715 return (comp_desc & BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) >> 716 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB; 717 } 718 719 /** 720 * hal_tx_comp_get_paddr() - Get paddr within comp descriptor 721 * @hal_desc: completion ring descriptor pointer 722 * 723 * This function will get buffer physical address within hardware completion 724 * descriptor 725 * 726 * Return: Buffer physical address 727 */ 728 static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc) 729 { 730 uint32_t paddr_lo; 731 uint32_t paddr_hi; 732 733 paddr_lo = *(uint32_t *) (((uint8_t *) hal_desc) + 734 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET); 735 736 paddr_hi = *(uint32_t *) (((uint8_t *) hal_desc) + 737 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET); 738 739 paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) >> 740 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB; 741 742 return (qdf_dma_addr_t) (paddr_lo | (((uint64_t) paddr_hi) << 32)); 743 } 744 745 /** 746 * hal_tx_comp_get_buffer_source() - Get buffer release source value 747 * @hal_desc: completion ring descriptor pointer 748 * 749 * This function will get buffer release source from Tx completion descriptor 750 * 751 * Return: buffer release source 752 */ 753 static inline uint32_t hal_tx_comp_get_buffer_source(void *hal_desc) 754 { 755 uint32_t comp_desc = 756 *(uint32_t *) (((uint8_t *) hal_desc) + 757 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET); 758 759 return (comp_desc & WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> 760 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB; 761 } 762 763 /** 764 * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type 765 * @hal_desc: completion ring descriptor pointer 766 * 767 * This function will return the type of pointer - buffer or descriptor 768 * 769 * Return: buffer type 770 */ 771 static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc) 772 { 773 uint32_t comp_desc = 774 *(uint32_t *) (((uint8_t *) hal_desc) + 775 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET); 776 777 return (comp_desc & WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> 778 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB; 779 } 780 781 /** 782 * hal_tx_comp_get_release_reason() - TQM Release reason 783 * @hal_desc: completion ring descriptor pointer 784 * 785 * This function will return the type of pointer - buffer or descriptor 786 * 787 * Return: buffer type 788 */ 789 static inline uint8_t hal_tx_comp_get_release_reason(void *hal_desc, void *hal) 790 { 791 struct hal_soc *hal_soc = hal; 792 793 return hal_soc->ops->hal_tx_comp_get_release_reason(hal_desc); 794 } 795 796 797 /** 798 * hal_tx_comp_desc_sync() - collect hardware descriptor contents 799 * @hal_desc: hardware descriptor pointer 800 * @comp: software descriptor pointer 801 * @read_status: 0 - Do not read status words from descriptors 802 * 1 - Enable reading of status words from descriptor 803 * 804 * This function will collect hardware release ring element contents and 805 * translate to software descriptor content 806 * 807 * Return: none 808 */ 809 810 static inline void hal_tx_comp_desc_sync(void *hw_desc, 811 struct hal_tx_desc_comp_s *comp, 812 bool read_status) 813 { 814 if (!read_status) 815 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_BASE_LEN); 816 else 817 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_LEN_BYTES); 818 } 819 820 /** 821 * hal_dump_comp_desc() - dump tx completion descriptor 822 * @hal_desc: hardware descriptor pointer 823 * 824 * This function will print tx completion descriptor 825 * 826 * Return: none 827 */ 828 static inline void hal_dump_comp_desc(void *hw_desc) 829 { 830 struct hal_tx_desc_comp_s *comp = 831 (struct hal_tx_desc_comp_s *)hw_desc; 832 uint32_t i; 833 834 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 835 "Current tx completion descriptor is"); 836 837 for (i = 0; i < HAL_TX_COMPLETION_DESC_LEN_DWORDS; i++) { 838 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 839 "DWORD[i] = 0x%x", comp->desc[i]); 840 } 841 } 842 843 /** 844 * hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor 845 * @hal_desc: Hardware (WBM) descriptor pointer 846 * @htt_desc: Software HTT descriptor pointer 847 * 848 * This function will read the HTT structure overlaid on WBM descriptor 849 * into a cached software descriptor 850 * 851 */ 852 static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc) 853 { 854 uint8_t *desc = hw_desc + HAL_TX_COMP_HTT_STATUS_OFFSET; 855 856 qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN); 857 } 858 859 /** 860 * hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG 861 * @hal_soc: Handle to HAL SoC structure 862 * @hal_srng: Handle to HAL SRNG structure 863 * 864 * Return: none 865 */ 866 static inline void hal_tx_init_data_ring(void *hal_soc, void *hal_srng) 867 { 868 uint8_t *desc_addr; 869 struct hal_srng_params srng_params; 870 uint32_t desc_size; 871 uint32_t num_desc; 872 873 hal_get_srng_params(hal_soc, hal_srng, &srng_params); 874 875 desc_addr = (uint8_t *)srng_params.ring_base_vaddr; 876 desc_size = sizeof(struct tcl_data_cmd); 877 num_desc = srng_params.num_entries; 878 879 while (num_desc) { 880 HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, 881 desc_size); 882 desc_addr += (desc_size + sizeof(struct tlv_32_hdr)); 883 num_desc--; 884 } 885 } 886 887 /** 888 * hal_tx_desc_set_dscp_tid_table_id() - Sets DSCP to TID conversion table ID 889 * @hal_soc: Handle to HAL SoC structure 890 * @desc: Handle to Tx Descriptor 891 * @id: DSCP to tid conversion table to be used for this frame 892 * 893 * Return: void 894 */ 895 static inline void hal_tx_desc_set_dscp_tid_table_id(struct hal_soc *hal_soc, 896 void *desc, uint8_t id) 897 { 898 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id(desc, id); 899 } 900 901 /** 902 * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table 903 * 904 * @soc: HAL SoC context 905 * @map: DSCP-TID mapping table 906 * @id: mapping table ID - 0,1 907 * 908 * Return: void 909 */ 910 static inline void hal_tx_set_dscp_tid_map(struct hal_soc *hal_soc, 911 uint8_t *map, uint8_t id) 912 { 913 hal_soc->ops->hal_tx_set_dscp_tid_map(hal_soc, map, id); 914 } 915 916 /** 917 * hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user 918 * 919 * @soc: HAL SoC context 920 * @map: DSCP-TID mapping table 921 * @id : MAP ID 922 * @dscp: DSCP_TID map index 923 * 924 * Return: void 925 */ 926 static inline void hal_tx_update_dscp_tid(struct hal_soc *hal_soc, uint8_t tid, 927 uint8_t id, uint8_t dscp) 928 { 929 hal_soc->ops->hal_tx_update_dscp_tid(hal_soc, tid, id, dscp); 930 } 931 932 /** 933 * hal_tx_desc_set_lmac_id - Set the lmac_id value 934 * @desc: Handle to Tx Descriptor 935 * @lmac_id: mac Id to ast matching 936 * b00 – mac 0 937 * b01 – mac 1 938 * b10 – mac 2 939 * b11 – all macs (legacy HK way) 940 * 941 * Return: void 942 */ 943 static inline void hal_tx_desc_set_lmac_id(struct hal_soc *hal_soc, 944 void *desc, uint8_t lmac_id) 945 { 946 hal_soc->ops->hal_tx_desc_set_lmac_id(desc, lmac_id); 947 } 948 949 /** 950 * hal_tx_desc_set_search_type - Set the search type value 951 * @desc: Handle to Tx Descriptor 952 * @search_type: search type 953 * 0 – Normal search 954 * 1 – Index based address search 955 * 2 – Index based flow search 956 * 957 * Return: void 958 */ 959 static inline void hal_tx_desc_set_search_type(struct hal_soc *hal_soc, 960 void *desc, uint8_t search_type) 961 { 962 hal_soc->ops->hal_tx_desc_set_search_type(desc, search_type); 963 } 964 965 /** 966 * hal_tx_desc_set_search_index - Set the search index value 967 * @desc: Handle to Tx Descriptor 968 * @search_index: The index that will be used for index based address or 969 * flow search. The field is valid when 'search_type' is 970 * 1 0r 2 971 * 972 * Return: void 973 */ 974 static inline void hal_tx_desc_set_search_index(struct hal_soc *hal_soc, 975 void *desc, 976 uint32_t search_index) 977 { 978 hal_soc->ops->hal_tx_desc_set_search_index(desc, search_index); 979 } 980 981 /** 982 * hal_tx_comp_get_status() - TQM Release reason 983 * @hal_desc: completion ring Tx status 984 * 985 * This function will parse the WBM completion descriptor and populate in 986 * HAL structure 987 * 988 * Return: none 989 */ 990 static inline void hal_tx_comp_get_status(void *desc, void *ts, void *hal) 991 { 992 struct hal_soc *hal_soc = hal; 993 994 hal_soc->ops->hal_tx_comp_get_status(desc, ts, hal); 995 } 996 997 998 /** 999 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 1000 * @desc: Handle to Tx Descriptor 1001 * @paddr: Physical Address 1002 * @pool_id: Return Buffer Manager ID 1003 * @desc_id: Descriptor ID 1004 * @type: 0 - Address points to a MSDU buffer 1005 * 1 - Address points to MSDU extension descriptor 1006 * 1007 * Return: void 1008 */ 1009 static inline void hal_tx_desc_set_buf_addr(void *desc, dma_addr_t paddr, 1010 uint8_t pool_id, uint32_t desc_id, uint8_t type, void *hal) 1011 { 1012 struct hal_soc *hal_soc = hal; 1013 1014 hal_soc->ops->hal_tx_desc_set_buf_addr(desc, paddr, pool_id, 1015 desc_id, type); 1016 1017 } 1018 1019 /** 1020 * hal_tx_set_pcp_tid_map_default() - Configure default PCP to TID map table 1021 * 1022 * @soc: HAL SoC context 1023 * @map: PCP-TID mapping table 1024 * 1025 * Return: void 1026 */ 1027 static inline void hal_tx_set_pcp_tid_map_default(struct hal_soc *hal_soc, 1028 uint8_t *map) 1029 { 1030 hal_soc->ops->hal_tx_set_pcp_tid_map(hal_soc, map); 1031 } 1032 1033 /** 1034 * hal_tx_update_pcp_tid_map() - Update PCP to TID map table 1035 * 1036 * @soc: HAL SoC context 1037 * @pcp: pcp value 1038 * @tid: tid no 1039 * 1040 * Return: void 1041 */ 1042 static inline void hal_tx_update_pcp_tid_map(struct hal_soc *hal_soc, 1043 uint8_t pcp, uint8_t tid) 1044 { 1045 hal_soc->ops->hal_tx_update_pcp_tid_map(hal_soc, tid, tid); 1046 } 1047 1048 /** 1049 * hal_tx_set_tidmap_prty() - Configure TIDmap priority 1050 * 1051 * @soc: HAL SoC context 1052 * @val: priority value 1053 * 1054 * Return: void 1055 */ 1056 static inline void hal_tx_set_tidmap_prty(struct hal_soc *hal_soc, uint8_t val) 1057 { 1058 hal_soc->ops->hal_tx_set_tidmap_prty(hal_soc, val); 1059 } 1060 #endif /* HAL_TX_H */ 1061