1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #if !defined(HAL_TX_H) 21 #define HAL_TX_H 22 23 /*--------------------------------------------------------------------------- 24 Include files 25 ---------------------------------------------------------------------------*/ 26 #include "hal_api.h" 27 #include "wcss_version.h" 28 #include "hal_hw_headers.h" 29 #include "hal_tx_hw_defines.h" 30 31 #define HAL_WBM_RELEASE_RING_2_BUFFER_TYPE 0 32 #define HAL_WBM_RELEASE_RING_2_DESC_TYPE 1 33 34 #define HAL_TX_DESC_TLV_TAG_OFFSET 1 35 #define HAL_TX_DESC_TLV_LEN_OFFSET 10 36 37 /*--------------------------------------------------------------------------- 38 Preprocessor definitions and constants 39 ---------------------------------------------------------------------------*/ 40 #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET 41 42 #define HAL_TX_LSB(block, field) block ## _ ## field ## _LSB 43 44 #define HAL_TX_MASK(block, field) block ## _ ## field ## _MASK 45 46 #define HAL_TX_DESC_OFFSET(desc, block, field) \ 47 (((uint8_t *)desc) + HAL_OFFSET(block, field)) 48 49 #define HAL_SET_FLD(desc, block , field) \ 50 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field))) 51 52 #define HAL_SET_FLD_OFFSET(desc, block , field, offset) \ 53 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field) + (offset))) 54 55 #define HAL_SET_FLD_64(desc, block, field) \ 56 (*(uint64_t *)((uint8_t *)desc + HAL_OFFSET(block, field))) 57 58 #define HAL_SET_FLD_OFFSET_64(desc, block, field, offset) \ 59 (*(uint64_t *)((uint8_t *)desc + HAL_OFFSET(block, field) + (offset))) 60 61 #define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \ 62 do { \ 63 uint32_t temp = 0; \ 64 temp |= (tag << HAL_TX_DESC_TLV_TAG_OFFSET); \ 65 temp |= (len << HAL_TX_DESC_TLV_LEN_OFFSET); \ 66 (*(uint32_t *)desc) = temp; \ 67 } while (0) 68 69 #define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E 70 #define HAL_TX_TCL_CMD_TAG WIFITCL_GSE_CMD_E 71 72 #define HAL_TX_SM(block, field, value) \ 73 ((value << (block ## _ ## field ## _LSB)) & \ 74 (block ## _ ## field ## _MASK)) 75 76 #define HAL_TX_MS(block, field, value) \ 77 (((value) & (block ## _ ## field ## _MASK)) >> \ 78 (block ## _ ## field ## _LSB)) 79 80 #define HAL_TX_DESC_GET(desc, block, field) \ 81 HAL_TX_MS(block, field, HAL_SET_FLD(desc, block, field)) 82 83 #define HAL_TX_DESC_OFFSET_GET(desc, block, field, offset) \ 84 HAL_TX_MS(block, field, HAL_SET_FLD_OFFSET(desc, block, field, offset)) 85 86 #define HAL_TX_DESC_SUBBLOCK_GET(desc, block, sub, field) \ 87 HAL_TX_MS(sub, field, HAL_SET_FLD(desc, block, sub)) 88 89 #define HAL_TX_DESC_GET_64(desc, block, field) \ 90 HAL_TX_MS(block, field, HAL_SET_FLD_64(desc, block, field)) 91 92 #define HAL_TX_DESC_OFFSET_GET_64(desc, block, field, offset) \ 93 HAL_TX_MS(block, field, HAL_SET_FLD_OFFSET_64(desc, block, field,\ 94 offset)) 95 96 #define HAL_TX_DESC_SUBBLOCK_GET_64(desc, block, sub, field) \ 97 HAL_TX_MS(sub, field, HAL_SET_FLD_64(desc, block, sub)) 98 99 #define HAL_TX_BUF_TYPE_BUFFER 0 100 #define HAL_TX_BUF_TYPE_EXT_DESC 1 101 102 #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 103 104 #define HAL_TX_DESC_LEN_DWORDS (NUM_OF_DWORDS_TCL_DATA_CMD) 105 #define HAL_TX_DESC_LEN_BYTES (NUM_OF_DWORDS_TCL_DATA_CMD * 4) 106 #define HAL_TX_EXTENSION_DESC_LEN_DWORDS (NUM_OF_DWORDS_TX_MSDU_EXTENSION) 107 #define HAL_TX_EXTENSION_DESC_LEN_BYTES (NUM_OF_DWORDS_TX_MSDU_EXTENSION * 4) 108 109 #define NUM_OF_DWORDS_WBM_RELEASE_RING 8 110 111 #define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 112 #define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4) 113 #define HAL_TX_BITS_PER_TID 3 114 #define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1) 115 #define HAL_TX_NUM_DSCP_PER_REGISTER 10 116 #define HAL_MAX_HW_DSCP_TID_MAPS 2 117 #define HAL_MAX_HW_DSCP_TID_MAPS_11AX 32 118 119 #define HAL_MAX_HW_DSCP_TID_V2_MAPS 48 120 #define HTT_META_HEADER_LEN_BYTES 64 121 #define HAL_TX_EXT_DESC_WITH_META_DATA \ 122 (HTT_META_HEADER_LEN_BYTES + HAL_TX_EXTENSION_DESC_LEN_BYTES) 123 124 #define HAL_TX_NUM_PCP_PER_REGISTER 8 125 126 /* Length of WBM release ring without the status words */ 127 #define HAL_TX_COMPLETION_DESC_BASE_LEN 12 128 129 #define HAL_TX_COMP_RELEASE_SOURCE_TQM 0 130 #define HAL_TX_COMP_RELEASE_SOURCE_REO 2 131 #define HAL_TX_COMP_RELEASE_SOURCE_FW 3 132 133 /* Define a place-holder release reason for FW */ 134 #define HAL_TX_COMP_RELEASE_REASON_FW 99 135 136 /* 137 * Offset of HTT Tx Descriptor in WBM Completion 138 * HTT Tx Desc structure is passed from firmware to host overlayed 139 * on wbm_release_ring DWORDs 2,3 ,4 and 5for software based completions 140 * (Exception frames and TQM bypass frames) 141 */ 142 #define HAL_TX_COMP_HTT_STATUS_OFFSET 8 143 #ifdef CONFIG_BERYLLIUM 144 #define HAL_TX_COMP_HTT_STATUS_LEN 20 145 #else 146 #define HAL_TX_COMP_HTT_STATUS_LEN 16 147 #endif 148 149 #define HAL_TX_BUF_TYPE_BUFFER 0 150 #define HAL_TX_BUF_TYPE_EXT_DESC 1 151 152 #define HAL_TX_EXT_DESC_BUF_OFFSET TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 153 #define HAL_TX_EXT_BUF_LOW_MASK TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 154 #define HAL_TX_EXT_BUF_HI_MASK TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 155 #define HAL_TX_EXT_BUF_LEN_MASK TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 156 #define HAL_TX_EXT_BUF_LEN_LSB TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 157 #define HAL_TX_EXT_BUF_WD_SIZE 2 158 159 #define HAL_TX_DESC_ADDRX_EN 0x1 160 #define HAL_TX_DESC_ADDRY_EN 0x2 161 #define HAL_TX_DESC_DEFAULT_LMAC_ID 0x3 162 163 #define HAL_TX_ADDR_SEARCH_DEFAULT 0x0 164 #define HAL_TX_ADDR_INDEX_SEARCH 0x1 165 #define HAL_TX_FLOW_INDEX_SEARCH 0x2 166 167 #define HAL_WBM2SW_RELEASE_SRC_GET(wbm_desc)(((*(((uint32_t *)wbm_desc) + \ 168 (HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 169 HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_MASK) >> \ 170 HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_LSB) 171 172 #define HAL_WBM_SW0_BM_ID(sw0_bm_id) (sw0_bm_id) 173 #define HAL_WBM_SW1_BM_ID(sw0_bm_id) ((sw0_bm_id) + 1) 174 #define HAL_WBM_SW2_BM_ID(sw0_bm_id) ((sw0_bm_id) + 2) 175 #define HAL_WBM_SW3_BM_ID(sw0_bm_id) ((sw0_bm_id) + 3) 176 #define HAL_WBM_SW4_BM_ID(sw0_bm_id) ((sw0_bm_id) + 4) 177 #define HAL_WBM_SW5_BM_ID(sw0_bm_id) ((sw0_bm_id) + 5) 178 #define HAL_WBM_SW6_BM_ID(sw0_bm_id) ((sw0_bm_id) + 6) 179 180 /*--------------------------------------------------------------------------- 181 Structures 182 ---------------------------------------------------------------------------*/ 183 /** 184 * struct hal_tx_completion_status - HAL Tx completion descriptor contents 185 * @status: frame acked/failed 186 * @release_src: release source = TQM/FW 187 * @ack_frame_rssi: RSSI of the received ACK or BA frame 188 * @first_msdu: Indicates this MSDU is the first MSDU in AMSDU 189 * @last_msdu: Indicates this MSDU is the last MSDU in AMSDU 190 * @msdu_part_of_amsdu : Indicates this MSDU was part of an A-MSDU in MPDU 191 * @bw: Indicates the BW of the upcoming transmission - 192 * <enum 0 transmit_bw_20_MHz> 193 * <enum 1 transmit_bw_40_MHz> 194 * <enum 2 transmit_bw_80_MHz> 195 * <enum 3 transmit_bw_160_MHz> 196 * @pkt_type: Transmit Packet Type 197 * @stbc: When set, STBC transmission rate was used 198 * @ldpc: When set, use LDPC transmission rates 199 * @sgi: <enum 0 0_8_us_sgi > Legacy normal GI 200 * <enum 1 0_4_us_sgi > Legacy short GI 201 * <enum 2 1_6_us_sgi > HE related GI 202 * <enum 3 3_2_us_sgi > HE 203 * @mcs: Transmit MCS Rate 204 * @ofdma: Set when the transmission was an OFDMA transmission 205 * @tones_in_ru: The number of tones in the RU used. 206 * @tsf: Lower 32 bits of the TSF 207 * @ppdu_id: TSF, snapshot of this value when transmission of the 208 * PPDU containing the frame finished. 209 * @transmit_cnt: Number of times this frame has been transmitted 210 * @tid: TID of the flow or MPDU queue 211 * @peer_id: Peer ID of the flow or MPDU queue 212 * @buffer_timestamp: Frame system entrance timestamp in units of 1024 213 * microseconds 214 */ 215 struct hal_tx_completion_status { 216 uint8_t status; 217 uint8_t release_src; 218 uint8_t ack_frame_rssi; 219 uint8_t first_msdu:1, 220 last_msdu:1, 221 msdu_part_of_amsdu:1; 222 uint32_t bw:2, 223 pkt_type:4, 224 stbc:1, 225 ldpc:1, 226 sgi:2, 227 mcs:4, 228 ofdma:1, 229 tones_in_ru:12, 230 valid:1; 231 uint32_t tsf; 232 uint32_t ppdu_id; 233 uint8_t transmit_cnt; 234 uint8_t tid; 235 uint16_t peer_id; 236 #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(CONFIG_SAWF) 237 uint32_t buffer_timestamp:19; 238 #endif 239 }; 240 241 /** 242 * struct hal_tx_desc_comp_s - hal tx completion descriptor contents 243 * @desc: Transmit status information from descriptor 244 */ 245 struct hal_tx_desc_comp_s { 246 uint32_t desc[HAL_TX_COMPLETION_DESC_LEN_DWORDS]; 247 }; 248 249 /* 250 * enum hal_tx_encrypt_type - Type of decrypt cipher used (valid only for RAW) 251 * @HAL_TX_ENCRYPT_TYPE_WEP_40: WEP 40-bit 252 * @HAL_TX_ENCRYPT_TYPE_WEP_10: WEP 10-bit 253 * @HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC: TKIP without MIC 254 * @HAL_TX_ENCRYPT_TYPE_WEP_128: WEP_128 255 * @HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC: TKIP_WITH_MIC 256 * @HAL_TX_ENCRYPT_TYPE_WAPI: WAPI 257 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_128: AES_CCMP_128 258 * @HAL_TX_ENCRYPT_TYPE_NO_CIPHER: NO CIPHER 259 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_256: AES_CCMP_256 260 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_128: AES_GCMP_128 261 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_256: AES_GCMP_256 262 * @HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4: WAPI GCM SM4 263 */ 264 enum hal_tx_encrypt_type { 265 HAL_TX_ENCRYPT_TYPE_WEP_40 = 0, 266 HAL_TX_ENCRYPT_TYPE_WEP_104 = 1 , 267 HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC = 2, 268 HAL_TX_ENCRYPT_TYPE_WEP_128 = 3, 269 HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC = 4, 270 HAL_TX_ENCRYPT_TYPE_WAPI = 5, 271 HAL_TX_ENCRYPT_TYPE_AES_CCMP_128 = 6, 272 HAL_TX_ENCRYPT_TYPE_NO_CIPHER = 7, 273 HAL_TX_ENCRYPT_TYPE_AES_CCMP_256 = 8, 274 HAL_TX_ENCRYPT_TYPE_AES_GCMP_128 = 9, 275 HAL_TX_ENCRYPT_TYPE_AES_GCMP_256 = 10, 276 HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4 = 11, 277 }; 278 279 /* 280 * enum hal_tx_encap_type - Encapsulation type that HW will perform 281 * @HAL_TX_ENCAP_TYPE_RAW: Raw Packet Type 282 * @HAL_TX_ENCAP_TYPE_NWIFI: Native WiFi Type 283 * @HAL_TX_ENCAP_TYPE_ETHERNET: Ethernet 284 * @HAL_TX_ENCAP_TYPE_802_3: 802.3 Frame 285 */ 286 enum hal_tx_encap_type { 287 HAL_TX_ENCAP_TYPE_RAW = 0, 288 HAL_TX_ENCAP_TYPE_NWIFI = 1, 289 HAL_TX_ENCAP_TYPE_ETHERNET = 2, 290 HAL_TX_ENCAP_TYPE_802_3 = 3, 291 }; 292 293 /** 294 * enum hal_tx_tqm_release_reason - TQM Release reason codes 295 * 296 * @HAL_TX_TQM_RR_FRAME_ACKED : ACK of BA for it was received 297 * @HAL_TX_TQM_RR_REM_CMD_REM : Remove cmd of type “Remove_mpdus” initiated 298 * by SW 299 * @HAL_TX_TQM_RR_REM_CMD_TX : Remove command of type Remove_transmitted_mpdus 300 * initiated by SW 301 * @HAL_TX_TQM_RR_REM_CMD_NOTX : Remove cmd of type Remove_untransmitted_mpdus 302 * initiated by SW 303 * @HAL_TX_TQM_RR_REM_CMD_AGED : Remove command of type “Remove_aged_mpdus” or 304 * “Remove_aged_msdus” initiated by SW 305 * @HAL_TX_TQM_RR_FW_REASON1 : Remove command where fw indicated that 306 * remove reason is fw_reason1 307 * @HAL_TX_TQM_RR_FW_REASON2 : Remove command where fw indicated that 308 * remove reason is fw_reason2 309 * @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that 310 * remove reason is fw_reason3 311 * @HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE : Remove command where fw indicated that 312 * remove reason is remove disable queue 313 * @HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING: Remove command from fw to remove 314 * all mpdu until 1st non-match 315 * @HAL_TX_TQM_RR_DROP_THRESHOLD: Dropped due to drop threshold criteria 316 * @HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE: Dropped due to link desc not available 317 * @HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU: Dropped due drop bit set or null flow 318 * @HAL_TX_TQM_RR_MULTICAST_DROP: Dropped due mcast drop set for VDEV 319 * @HAL_TX_TQM_RR_VDEV_MISMATCH_DROP: Dropped due to being set with 320 * 'TCL_drop_reason' 321 * 322 */ 323 enum hal_tx_tqm_release_reason { 324 HAL_TX_TQM_RR_FRAME_ACKED, 325 HAL_TX_TQM_RR_REM_CMD_REM, 326 HAL_TX_TQM_RR_REM_CMD_TX, 327 HAL_TX_TQM_RR_REM_CMD_NOTX, 328 HAL_TX_TQM_RR_REM_CMD_AGED, 329 HAL_TX_TQM_RR_FW_REASON1, 330 HAL_TX_TQM_RR_FW_REASON2, 331 HAL_TX_TQM_RR_FW_REASON3, 332 HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE, 333 HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING, 334 HAL_TX_TQM_RR_DROP_THRESHOLD, 335 HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE, 336 HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU, 337 HAL_TX_TQM_RR_MULTICAST_DROP, 338 HAL_TX_TQM_RR_VDEV_MISMATCH_DROP, 339 }; 340 341 /* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports 342 * @HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT: Default DSCP-TID mapping table 343 * @HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE: DSCP-TID map override table 344 */ 345 enum hal_tx_dscp_tid_table_id { 346 HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT, 347 HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE, 348 }; 349 350 /*--------------------------------------------------------------------------- 351 Function declarations and documentation 352 ---------------------------------------------------------------------------*/ 353 354 /*--------------------------------------------------------------------------- 355 Tx MSDU Extension Descriptor accessor APIs 356 ---------------------------------------------------------------------------*/ 357 /** 358 * hal_tx_ext_desc_set_tso_enable() - Set TSO Enable Flag 359 * @desc: Handle to Tx MSDU Extension Descriptor 360 * @tso_en: bool value set to true if TSO is enabled 361 * 362 * Return: none 363 */ 364 static inline void hal_tx_ext_desc_set_tso_enable(void *desc, 365 uint8_t tso_en) 366 { 367 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE) |= 368 HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TSO_ENABLE, tso_en); 369 } 370 371 /** 372 * hal_tx_ext_desc_set_tso_flags() - Set TSO Flags 373 * @desc: Handle to Tx MSDU Extension Descriptor 374 * @falgs: 32-bit word with all TSO flags consolidated 375 * 376 * Return: none 377 */ 378 static inline void hal_tx_ext_desc_set_tso_flags(void *desc, 379 uint32_t tso_flags) 380 { 381 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE, 0) = 382 tso_flags; 383 } 384 385 /** 386 * hal_tx_ext_desc_set_tcp_flags() - Enable HW Checksum offload 387 * @desc: Handle to Tx MSDU Extension Descriptor 388 * @tcp_flags: TCP flags {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 389 * @mask: TCP flag mask. Tcp_flag is inserted into the header 390 * based on the mask, if tso is enabled 391 * 392 * Return: none 393 */ 394 static inline void hal_tx_ext_desc_set_tcp_flags(void *desc, 395 uint16_t tcp_flags, 396 uint16_t mask) 397 { 398 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_FLAG) |= 399 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG, tcp_flags)) | 400 (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG_MASK, mask))); 401 } 402 403 /** 404 * hal_tx_ext_desc_set_msdu_length() - Set L2 and IP Lengths 405 * @desc: Handle to Tx MSDU Extension Descriptor 406 * @l2_len: L2 length for the msdu, if tso is enabled 407 * @ip_len: IP length for the msdu, if tso is enabled 408 * 409 * Return: none 410 */ 411 static inline void hal_tx_ext_desc_set_msdu_length(void *desc, 412 uint16_t l2_len, 413 uint16_t ip_len) 414 { 415 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, L2_LENGTH) |= 416 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, L2_LENGTH, l2_len)) | 417 (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_LENGTH, ip_len))); 418 } 419 420 /** 421 * hal_tx_ext_desc_set_tcp_seq() - Set TCP Sequence number 422 * @desc: Handle to Tx MSDU Extension Descriptor 423 * @seq_num: Tcp_seq_number for the msdu, if tso is enabled 424 * 425 * Return: none 426 */ 427 static inline void hal_tx_ext_desc_set_tcp_seq(void *desc, 428 uint32_t seq_num) 429 { 430 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER) |= 431 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER, seq_num))); 432 } 433 434 435 /** 436 * hal_tx_ext_desc_set_ip_id() - Set IP Identification field 437 * @desc: Handle to Tx MSDU Extension Descriptor 438 * @id: IP Id field for the msdu, if tso is enabled 439 * 440 * Return: none 441 */ 442 static inline void hal_tx_ext_desc_set_ip_id(void *desc, 443 uint16_t id) 444 { 445 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION) |= 446 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION, id))); 447 } 448 /** 449 * hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment 450 * @desc: Handle to Tx MSDU Extension Descriptor 451 * @frag_num: Fragment number (value can be 0 to 5) 452 * @paddr_lo: Lower 32-bit of Buffer Physical address 453 * @paddr_hi: Upper 32-bit of Buffer Physical address 454 * @length: Buffer Length 455 * 456 * Return: none 457 */ 458 static inline void hal_tx_ext_desc_set_buffer(void *desc, 459 uint8_t frag_num, 460 uint32_t paddr_lo, 461 uint16_t paddr_hi, 462 uint16_t length) 463 { 464 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, 465 (frag_num << 3)) |= 466 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo))); 467 468 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32, 469 (frag_num << 3)) |= 470 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32, 471 (paddr_hi)))); 472 473 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN, 474 (frag_num << 3)) |= 475 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length))); 476 } 477 478 /** 479 * hal_tx_ext_desc_get_frag_info() - Get the frag_num'th frag iova and len 480 * @desc: Handle to Tx MSDU Extension Descriptor 481 * @frag_num: fragment number (value can be 0 to 5) 482 * @iova: fragment dma address 483 * @len: fragement Length 484 * 485 * Return: None 486 */ 487 static inline void hal_tx_ext_desc_get_frag_info(void *desc, uint8_t frag_num, 488 qdf_dma_addr_t *iova, 489 uint32_t *len) 490 { 491 uint64_t iova_hi; 492 493 *iova = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, 494 BUF0_PTR_31_0, (frag_num << 3)); 495 496 iova_hi = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, 497 BUF0_PTR_39_32, (frag_num << 3)); 498 *iova |= (iova_hi << 32); 499 500 *len = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN, 501 (frag_num << 3)); 502 } 503 504 /** 505 * hal_tx_ext_desc_set_buffer0_param() - Set Buffer 0 Pointer and Length 506 * @desc: Handle to Tx MSDU Extension Descriptor 507 * @paddr_lo: Lower 32-bit of Buffer Physical address 508 * @paddr_hi: Upper 32-bit of Buffer Physical address 509 * @length: Buffer 0 Length 510 * 511 * Return: none 512 */ 513 static inline void hal_tx_ext_desc_set_buffer0_param(void *desc, 514 uint32_t paddr_lo, 515 uint16_t paddr_hi, 516 uint16_t length) 517 { 518 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0) |= 519 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo))); 520 521 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32) |= 522 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, 523 BUF0_PTR_39_32, paddr_hi))); 524 525 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN) |= 526 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length))); 527 } 528 529 /** 530 * hal_tx_ext_desc_set_buffer1_param() - Set Buffer 1 Pointer and Length 531 * @desc: Handle to Tx MSDU Extension Descriptor 532 * @paddr_lo: Lower 32-bit of Buffer Physical address 533 * @paddr_hi: Upper 32-bit of Buffer Physical address 534 * @length: Buffer 1 Length 535 * 536 * Return: none 537 */ 538 static inline void hal_tx_ext_desc_set_buffer1_param(void *desc, 539 uint32_t paddr_lo, 540 uint16_t paddr_hi, 541 uint16_t length) 542 { 543 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0) |= 544 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0, paddr_lo))); 545 546 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_39_32) |= 547 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, 548 BUF1_PTR_39_32, paddr_hi))); 549 550 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_LEN) |= 551 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_LEN, length))); 552 } 553 554 /** 555 * hal_tx_ext_desc_set_buffer2_param() - Set Buffer 2 Pointer and Length 556 * @desc: Handle to Tx MSDU Extension Descriptor 557 * @paddr_lo: Lower 32-bit of Buffer Physical address 558 * @paddr_hi: Upper 32-bit of Buffer Physical address 559 * @length: Buffer 2 Length 560 * 561 * Return: none 562 */ 563 static inline void hal_tx_ext_desc_set_buffer2_param(void *desc, 564 uint32_t paddr_lo, 565 uint16_t paddr_hi, 566 uint16_t length) 567 { 568 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0) |= 569 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0, 570 paddr_lo))); 571 572 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32) |= 573 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32, 574 paddr_hi))); 575 576 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_LEN) |= 577 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_LEN, length))); 578 } 579 580 /** 581 * hal_tx_ext_desc_sync - Commit the descriptor to Hardware 582 * @desc_cached: Cached descriptor that software maintains 583 * @hw_desc: Hardware descriptor to be updated 584 * 585 * Return: none 586 */ 587 static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached, 588 uint8_t *hw_desc) 589 { 590 qdf_mem_copy(&hw_desc[0], &desc_cached[0], 591 HAL_TX_EXT_DESC_WITH_META_DATA); 592 } 593 594 /** 595 * hal_tx_ext_desc_get_tso_enable() - Set TSO Enable Flag 596 * @hal_tx_ext_desc: Handle to Tx MSDU Extension Descriptor 597 * 598 * Return: tso_enable value in the descriptor 599 */ 600 static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc) 601 { 602 uint32_t *desc = (uint32_t *) hal_tx_ext_desc; 603 return (*desc & HAL_TX_MSDU_EXTENSION_TSO_ENABLE_MASK) >> 604 HAL_TX_MSDU_EXTENSION_TSO_ENABLE_LSB; 605 } 606 607 /*--------------------------------------------------------------------------- 608 WBM Descriptor accessor APIs for Tx completions 609 ---------------------------------------------------------------------------*/ 610 /** 611 * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type 612 * @hal_desc: completion ring descriptor pointer 613 * 614 * This function will return the type of pointer - buffer or descriptor 615 * 616 * Return: buffer type 617 */ 618 static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc) 619 { 620 uint32_t comp_desc = 621 *(uint32_t *) (((uint8_t *) hal_desc) + 622 HAL_TX_COMP_BUFFER_OR_DESC_TYPE_OFFSET); 623 624 return (comp_desc & HAL_TX_COMP_BUFFER_OR_DESC_TYPE_MASK) >> 625 HAL_TX_COMP_BUFFER_OR_DESC_TYPE_LSB; 626 } 627 628 #ifdef QCA_WIFI_KIWI 629 /** 630 * hal_tx_comp_get_buffer_source() - Get buffer release source value 631 * @hal_desc: completion ring descriptor pointer 632 * 633 * This function will get buffer release source from Tx completion descriptor 634 * 635 * Return: buffer release source 636 */ 637 static inline uint32_t 638 hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl, 639 void *hal_desc) 640 { 641 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 642 643 return hal_soc->ops->hal_tx_comp_get_buffer_source(hal_desc); 644 } 645 #else 646 static inline uint32_t 647 hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl, 648 void *hal_desc) 649 { 650 return HAL_WBM2SW_RELEASE_SRC_GET(hal_desc); 651 } 652 #endif 653 654 /** 655 * hal_tx_comp_get_release_reason() - TQM Release reason 656 * @hal_desc: completion ring descriptor pointer 657 * 658 * This function will return the type of pointer - buffer or descriptor 659 * 660 * Return: buffer type 661 */ 662 static inline 663 uint8_t hal_tx_comp_get_release_reason(void *hal_desc, 664 hal_soc_handle_t hal_soc_hdl) 665 { 666 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 667 668 return hal_soc->ops->hal_tx_comp_get_release_reason(hal_desc); 669 } 670 671 /** 672 * hal_tx_comp_get_peer_id() - Get peer_id value() 673 * @hal_desc: completion ring descriptor pointer 674 * 675 * This function will get peer_id value from Tx completion descriptor 676 * 677 * Return: buffer release source 678 */ 679 static inline uint16_t hal_tx_comp_get_peer_id(void *hal_desc) 680 { 681 uint32_t comp_desc = 682 *(uint32_t *)(((uint8_t *)hal_desc) + 683 HAL_TX_COMP_SW_PEER_ID_OFFSET); 684 685 return (comp_desc & HAL_TX_COMP_SW_PEER_ID_MASK) >> 686 HAL_TX_COMP_SW_PEER_ID_LSB; 687 } 688 689 /** 690 * hal_tx_comp_get_tx_status() - Get tx transmission status() 691 * @hal_desc: completion ring descriptor pointer 692 * 693 * This function will get transmit status value from Tx completion descriptor 694 * 695 * Return: buffer release source 696 */ 697 static inline uint8_t hal_tx_comp_get_tx_status(void *hal_desc) 698 { 699 uint32_t comp_desc = 700 *(uint32_t *)(((uint8_t *)hal_desc) + 701 HAL_TX_COMP_TQM_RELEASE_REASON_OFFSET); 702 703 return (comp_desc & HAL_TX_COMP_TQM_RELEASE_REASON_MASK) >> 704 HAL_TX_COMP_TQM_RELEASE_REASON_LSB; 705 } 706 707 /** 708 * hal_tx_comp_desc_sync() - collect hardware descriptor contents 709 * @hal_desc: hardware descriptor pointer 710 * @comp: software descriptor pointer 711 * @read_status: 0 - Do not read status words from descriptors 712 * 1 - Enable reading of status words from descriptor 713 * 714 * This function will collect hardware release ring element contents and 715 * translate to software descriptor content 716 * 717 * Return: none 718 */ 719 720 static inline void hal_tx_comp_desc_sync(void *hw_desc, 721 struct hal_tx_desc_comp_s *comp, 722 bool read_status) 723 { 724 if (!read_status) 725 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_BASE_LEN); 726 else 727 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_LEN_BYTES); 728 } 729 730 /** 731 * hal_dump_comp_desc() - dump tx completion descriptor 732 * @hal_desc: hardware descriptor pointer 733 * 734 * This function will print tx completion descriptor 735 * 736 * Return: none 737 */ 738 static inline void hal_dump_comp_desc(void *hw_desc) 739 { 740 struct hal_tx_desc_comp_s *comp = 741 (struct hal_tx_desc_comp_s *)hw_desc; 742 uint32_t i; 743 744 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 745 "Current tx completion descriptor is"); 746 747 for (i = 0; i < HAL_TX_COMPLETION_DESC_LEN_DWORDS; i++) { 748 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 749 "DWORD[i] = 0x%x", comp->desc[i]); 750 } 751 } 752 753 /** 754 * hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor 755 * @hal_desc: Hardware (WBM) descriptor pointer 756 * @htt_desc: Software HTT descriptor pointer 757 * 758 * This function will read the HTT structure overlaid on WBM descriptor 759 * into a cached software descriptor 760 * 761 */ 762 static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc) 763 { 764 uint8_t *desc = hw_desc + HAL_TX_COMP_HTT_STATUS_OFFSET; 765 766 qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN); 767 } 768 769 /** 770 * hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG 771 * @hal_soc_hdl: Handle to HAL SoC structure 772 * @hal_srng: Handle to HAL SRNG structure 773 * 774 * Return: none 775 */ 776 static inline void hal_tx_init_data_ring(hal_soc_handle_t hal_soc_hdl, 777 hal_ring_handle_t hal_ring_hdl) 778 { 779 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 780 781 hal_soc->ops->hal_tx_init_data_ring(hal_soc_hdl, hal_ring_hdl); 782 } 783 784 /** 785 * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table 786 * 787 * @soc: HAL SoC context 788 * @map: DSCP-TID mapping table 789 * @id: mapping table ID - 0,1 790 * 791 * Return: void 792 */ 793 static inline void hal_tx_set_dscp_tid_map(hal_soc_handle_t hal_soc_hdl, 794 uint8_t *map, uint8_t id) 795 { 796 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 797 798 hal_soc->ops->hal_tx_set_dscp_tid_map(hal_soc, map, id); 799 } 800 801 /** 802 * hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user 803 * 804 * @soc: HAL SoC context 805 * @map: DSCP-TID mapping table 806 * @id : MAP ID 807 * @dscp: DSCP_TID map index 808 * 809 * Return: void 810 */ 811 static inline 812 void hal_tx_update_dscp_tid(hal_soc_handle_t hal_soc_hdl, uint8_t tid, 813 uint8_t id, uint8_t dscp) 814 { 815 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 816 817 hal_soc->ops->hal_tx_update_dscp_tid(hal_soc, tid, id, dscp); 818 } 819 820 /** 821 * hal_tx_comp_get_status() - TQM Release reason 822 * @hal_desc: completion ring Tx status 823 * 824 * This function will parse the WBM completion descriptor and populate in 825 * HAL structure 826 * 827 * Return: none 828 */ 829 static inline void hal_tx_comp_get_status(void *desc, void *ts, 830 hal_soc_handle_t hal_soc_hdl) 831 { 832 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 833 834 hal_soc->ops->hal_tx_comp_get_status(desc, ts, hal_soc); 835 } 836 837 /** 838 * hal_tx_set_pcp_tid_map_default() - Configure default PCP to TID map table 839 * 840 * @soc: HAL SoC context 841 * @map: PCP-TID mapping table 842 * 843 * Return: void 844 */ 845 static inline void hal_tx_set_pcp_tid_map_default(hal_soc_handle_t hal_soc_hdl, 846 uint8_t *map) 847 { 848 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 849 850 hal_soc->ops->hal_tx_set_pcp_tid_map(hal_soc, map); 851 } 852 853 /** 854 * hal_tx_update_pcp_tid_map() - Update PCP to TID map table 855 * 856 * @soc: HAL SoC context 857 * @pcp: pcp value 858 * @tid: tid no 859 * 860 * Return: void 861 */ 862 static inline void hal_tx_update_pcp_tid_map(hal_soc_handle_t hal_soc_hdl, 863 uint8_t pcp, uint8_t tid) 864 { 865 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 866 867 hal_soc->ops->hal_tx_update_pcp_tid_map(hal_soc, pcp, tid); 868 } 869 870 /** 871 * hal_tx_set_tidmap_prty() - Configure TIDmap priority 872 * 873 * @soc: HAL SoC context 874 * @val: priority value 875 * 876 * Return: void 877 */ 878 static inline 879 void hal_tx_set_tidmap_prty(hal_soc_handle_t hal_soc_hdl, uint8_t val) 880 { 881 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 882 883 hal_soc->ops->hal_tx_set_tidmap_prty(hal_soc, val); 884 } 885 886 /** 887 * hal_get_wbm_internal_error() - wbm internal error 888 * @hal_desc: completion ring descriptor pointer 889 * 890 * This function will return the type of pointer - buffer or descriptor 891 * 892 * Return: buffer type 893 */ 894 static inline 895 uint8_t hal_get_wbm_internal_error(hal_soc_handle_t hal_soc_hdl, void *hal_desc) 896 { 897 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 898 899 return hal_soc->ops->hal_get_wbm_internal_error(hal_desc); 900 } 901 #endif /* HAL_TX_H */ 902