1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #if !defined(HAL_TX_H) 21 #define HAL_TX_H 22 23 /*--------------------------------------------------------------------------- 24 Include files 25 ---------------------------------------------------------------------------*/ 26 #include "hal_api.h" 27 #include "wcss_version.h" 28 #include "hal_hw_headers.h" 29 #include "hal_tx_hw_defines.h" 30 31 #define HAL_WBM_RELEASE_RING_2_BUFFER_TYPE 0 32 #define HAL_WBM_RELEASE_RING_2_DESC_TYPE 1 33 34 #define HAL_TX_DESC_TLV_TAG_OFFSET 1 35 #define HAL_TX_DESC_TLV_LEN_OFFSET 10 36 37 /*--------------------------------------------------------------------------- 38 Preprocessor definitions and constants 39 ---------------------------------------------------------------------------*/ 40 #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET 41 42 #define HAL_TX_LSB(block, field) block ## _ ## field ## _LSB 43 44 #define HAL_TX_MASK(block, field) block ## _ ## field ## _MASK 45 46 #define HAL_TX_DESC_OFFSET(desc, block, field) \ 47 (((uint8_t *)desc) + HAL_OFFSET(block, field)) 48 49 #define HAL_SET_FLD(desc, block , field) \ 50 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field))) 51 52 #define HAL_SET_FLD_OFFSET(desc, block , field, offset) \ 53 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field) + (offset))) 54 55 #define HAL_SET_FLD_64(desc, block, field) \ 56 (*(uint64_t *)((uint8_t *)desc + HAL_OFFSET(block, field))) 57 58 #define HAL_SET_FLD_OFFSET_64(desc, block, field, offset) \ 59 (*(uint64_t *)((uint8_t *)desc + HAL_OFFSET(block, field) + (offset))) 60 61 #define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \ 62 do { \ 63 uint32_t temp = 0; \ 64 temp |= (tag << HAL_TX_DESC_TLV_TAG_OFFSET); \ 65 temp |= (len << HAL_TX_DESC_TLV_LEN_OFFSET); \ 66 (*(uint32_t *)desc) = temp; \ 67 } while (0) 68 69 #define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E 70 #define HAL_TX_TCL_CMD_TAG WIFITCL_GSE_CMD_E 71 72 #define HAL_TX_SM(block, field, value) \ 73 ((value << (block ## _ ## field ## _LSB)) & \ 74 (block ## _ ## field ## _MASK)) 75 76 #define HAL_TX_MS(block, field, value) \ 77 (((value) & (block ## _ ## field ## _MASK)) >> \ 78 (block ## _ ## field ## _LSB)) 79 80 #define HAL_TX_DESC_GET(desc, block, field) \ 81 HAL_TX_MS(block, field, HAL_SET_FLD(desc, block, field)) 82 83 #define HAL_TX_DESC_OFFSET_GET(desc, block, field, offset) \ 84 HAL_TX_MS(block, field, HAL_SET_FLD_OFFSET(desc, block, field, offset)) 85 86 #define HAL_TX_DESC_SUBBLOCK_GET(desc, block, sub, field) \ 87 HAL_TX_MS(sub, field, HAL_SET_FLD(desc, block, sub)) 88 89 #define HAL_TX_DESC_GET_64(desc, block, field) \ 90 HAL_TX_MS(block, field, HAL_SET_FLD_64(desc, block, field)) 91 92 #define HAL_TX_DESC_OFFSET_GET_64(desc, block, field, offset) \ 93 HAL_TX_MS(block, field, HAL_SET_FLD_OFFSET_64(desc, block, field,\ 94 offset)) 95 96 #define HAL_TX_DESC_SUBBLOCK_GET_64(desc, block, sub, field) \ 97 HAL_TX_MS(sub, field, HAL_SET_FLD_64(desc, block, sub)) 98 99 #define HAL_TX_BUF_TYPE_BUFFER 0 100 #define HAL_TX_BUF_TYPE_EXT_DESC 1 101 102 #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 103 104 #define HAL_TX_DESC_LEN_DWORDS (NUM_OF_DWORDS_TCL_DATA_CMD) 105 #define HAL_TX_DESC_LEN_BYTES (NUM_OF_DWORDS_TCL_DATA_CMD * 4) 106 #define HAL_TX_EXTENSION_DESC_LEN_DWORDS (NUM_OF_DWORDS_TX_MSDU_EXTENSION) 107 #define HAL_TX_EXTENSION_DESC_LEN_BYTES (NUM_OF_DWORDS_TX_MSDU_EXTENSION * 4) 108 109 #define NUM_OF_DWORDS_WBM_RELEASE_RING 8 110 111 #define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 112 #define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4) 113 #define HAL_TX_BITS_PER_TID 3 114 #define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1) 115 #define HAL_TX_NUM_DSCP_PER_REGISTER 10 116 #define HAL_MAX_HW_DSCP_TID_MAPS 2 117 #define HAL_MAX_HW_DSCP_TID_MAPS_11AX 32 118 119 #define HAL_MAX_HW_DSCP_TID_V2_MAPS 48 120 #define HAL_MAX_HW_DSCP_TID_V2_MAPS_5332 24 121 #define HAL_MAX_HW_DSCP_TID_V2_MAPS_6432 24 122 #define HTT_META_HEADER_LEN_BYTES 64 123 #define HAL_TX_EXT_DESC_WITH_META_DATA \ 124 (HTT_META_HEADER_LEN_BYTES + HAL_TX_EXTENSION_DESC_LEN_BYTES) 125 126 #define HAL_TX_NUM_PCP_PER_REGISTER 8 127 128 /* Length of WBM release ring without the status words */ 129 #define HAL_TX_COMPLETION_DESC_BASE_LEN 12 130 131 #define HAL_TX_COMP_RELEASE_SOURCE_TQM 0 132 #define HAL_TX_COMP_RELEASE_SOURCE_REO 2 133 #define HAL_TX_COMP_RELEASE_SOURCE_FW 3 134 135 /* Define a place-holder release reason for FW */ 136 #define HAL_TX_COMP_RELEASE_REASON_FW 99 137 138 /* 139 * Offset of HTT Tx Descriptor in WBM Completion 140 * HTT Tx Desc structure is passed from firmware to host overlaid 141 * on wbm_release_ring DWORDs 2,3 ,4 and 5for software based completions 142 * (Exception frames and TQM bypass frames) 143 */ 144 #if defined(CONFIG_BERYLLIUM) || defined(CONFIG_LITHIUM) 145 #define HAL_TX_COMP_HTT_STATUS_OFFSET 8 146 #else 147 #define HAL_TX_COMP_HTT_STATUS_OFFSET 0 /* Rhine */ 148 #endif 149 150 #ifdef CONFIG_BERYLLIUM 151 #define HAL_TX_COMP_HTT_STATUS_LEN 20 152 #elif defined(CONFIG_LITHIUM) 153 #define HAL_TX_COMP_HTT_STATUS_LEN 16 154 #else 155 #define HAL_TX_COMP_HTT_STATUS_LEN 32 /* Rhine */ 156 #endif 157 158 #define HAL_TX_BUF_TYPE_BUFFER 0 159 #define HAL_TX_BUF_TYPE_EXT_DESC 1 160 161 #define HAL_TX_EXT_DESC_BUF_OFFSET TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 162 #define HAL_TX_EXT_BUF_LOW_MASK TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 163 #define HAL_TX_EXT_BUF_HI_MASK TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 164 #define HAL_TX_EXT_BUF_LEN_MASK TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 165 #define HAL_TX_EXT_BUF_LEN_LSB TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 166 #define HAL_TX_EXT_BUF_WD_SIZE 2 167 168 #define HAL_TX_DESC_ADDRX_EN 0x1 169 #define HAL_TX_DESC_ADDRY_EN 0x2 170 #define HAL_TX_DESC_DEFAULT_LMAC_ID 0x3 171 172 #define HAL_TX_ADDR_SEARCH_DEFAULT 0x0 173 #define HAL_TX_ADDR_INDEX_SEARCH 0x1 174 #define HAL_TX_FLOW_INDEX_SEARCH 0x2 175 176 #define HAL_WBM2SW_RELEASE_SRC_GET(wbm_desc)(((*(((uint32_t *)wbm_desc) + \ 177 (HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 178 HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_MASK) >> \ 179 HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_LSB) 180 181 #define HAL_WBM_SW0_BM_ID(sw0_bm_id) (sw0_bm_id) 182 #define HAL_WBM_SW1_BM_ID(sw0_bm_id) ((sw0_bm_id) + 1) 183 #define HAL_WBM_SW2_BM_ID(sw0_bm_id) ((sw0_bm_id) + 2) 184 #define HAL_WBM_SW3_BM_ID(sw0_bm_id) ((sw0_bm_id) + 3) 185 #define HAL_WBM_SW4_BM_ID(sw0_bm_id) ((sw0_bm_id) + 4) 186 #define HAL_WBM_SW5_BM_ID(sw0_bm_id) ((sw0_bm_id) + 5) 187 #define HAL_WBM_SW6_BM_ID(sw0_bm_id) ((sw0_bm_id) + 6) 188 189 /*--------------------------------------------------------------------------- 190 Structures 191 ---------------------------------------------------------------------------*/ 192 /** 193 * struct hal_tx_completion_status - HAL Tx completion descriptor contents 194 * @status: frame acked/failed 195 * @release_src: release source = TQM/FW 196 * @ack_frame_rssi: RSSI of the received ACK or BA frame 197 * @first_msdu: Indicates this MSDU is the first MSDU in AMSDU 198 * @last_msdu: Indicates this MSDU is the last MSDU in AMSDU 199 * @msdu_part_of_amsdu : Indicates this MSDU was part of an A-MSDU in MPDU 200 * @bw: Indicates the BW of the upcoming transmission - 201 * <enum 0 transmit_bw_20_MHz> 202 * <enum 1 transmit_bw_40_MHz> 203 * <enum 2 transmit_bw_80_MHz> 204 * <enum 3 transmit_bw_160_MHz> 205 * <enum 4 transmit_bw_320_MHz> 206 * <enum 5 transmit_bw_240_MHz> 207 * @pkt_type: Transmit Packet Type 208 * @stbc: When set, STBC transmission rate was used 209 * @ldpc: When set, use LDPC transmission rates 210 * @sgi: <enum 0 0_8_us_sgi > Legacy normal GI 211 * <enum 1 0_4_us_sgi > Legacy short GI 212 * <enum 2 1_6_us_sgi > HE related GI 213 * <enum 3 3_2_us_sgi > HE 214 * @mcs: Transmit MCS Rate 215 * @ofdma: Set when the transmission was an OFDMA transmission 216 * @tones_in_ru: The number of tones in the RU used. 217 * @valid: 218 * @tsf: Lower 32 bits of the TSF 219 * @ppdu_id: TSF, snapshot of this value when transmission of the 220 * PPDU containing the frame finished. 221 * @transmit_cnt: Number of times this frame has been transmitted 222 * @tid: TID of the flow or MPDU queue 223 * @peer_id: Peer ID of the flow or MPDU queue 224 * @buffer_timestamp: Frame system entrance timestamp in units of 1024 225 * microseconds 226 */ 227 struct hal_tx_completion_status { 228 uint8_t status; 229 uint8_t release_src; 230 uint8_t ack_frame_rssi; 231 uint8_t first_msdu:1, 232 last_msdu:1, 233 msdu_part_of_amsdu:1; 234 uint32_t bw:3, 235 pkt_type:4, 236 stbc:1, 237 ldpc:1, 238 sgi:2, 239 mcs:4, 240 ofdma:1, 241 tones_in_ru:12, 242 valid:1; 243 uint32_t tsf; 244 uint32_t ppdu_id; 245 uint8_t transmit_cnt; 246 uint8_t tid; 247 uint16_t peer_id; 248 #if defined(WLAN_FEATURE_TSF_AUTO_REPORT) || defined(WLAN_CONFIG_TX_DELAY) 249 uint32_t buffer_timestamp:19; 250 #endif 251 }; 252 253 /** 254 * struct hal_tx_desc_comp_s - hal tx completion descriptor contents 255 * @desc: Transmit status information from descriptor 256 */ 257 struct hal_tx_desc_comp_s { 258 uint32_t desc[HAL_TX_COMPLETION_DESC_LEN_DWORDS]; 259 }; 260 261 /* 262 * enum hal_tx_encrypt_type - Type of decrypt cipher used (valid only for RAW) 263 * @HAL_TX_ENCRYPT_TYPE_WEP_40: WEP 40-bit 264 * @HAL_TX_ENCRYPT_TYPE_WEP_10: WEP 10-bit 265 * @HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC: TKIP without MIC 266 * @HAL_TX_ENCRYPT_TYPE_WEP_128: WEP_128 267 * @HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC: TKIP_WITH_MIC 268 * @HAL_TX_ENCRYPT_TYPE_WAPI: WAPI 269 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_128: AES_CCMP_128 270 * @HAL_TX_ENCRYPT_TYPE_NO_CIPHER: NO CIPHER 271 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_256: AES_CCMP_256 272 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_128: AES_GCMP_128 273 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_256: AES_GCMP_256 274 * @HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4: WAPI GCM SM4 275 */ 276 enum hal_tx_encrypt_type { 277 HAL_TX_ENCRYPT_TYPE_WEP_40 = 0, 278 HAL_TX_ENCRYPT_TYPE_WEP_104 = 1 , 279 HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC = 2, 280 HAL_TX_ENCRYPT_TYPE_WEP_128 = 3, 281 HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC = 4, 282 HAL_TX_ENCRYPT_TYPE_WAPI = 5, 283 HAL_TX_ENCRYPT_TYPE_AES_CCMP_128 = 6, 284 HAL_TX_ENCRYPT_TYPE_NO_CIPHER = 7, 285 HAL_TX_ENCRYPT_TYPE_AES_CCMP_256 = 8, 286 HAL_TX_ENCRYPT_TYPE_AES_GCMP_128 = 9, 287 HAL_TX_ENCRYPT_TYPE_AES_GCMP_256 = 10, 288 HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4 = 11, 289 }; 290 291 /* 292 * enum hal_tx_encap_type - Encapsulation type that HW will perform 293 * @HAL_TX_ENCAP_TYPE_RAW: Raw Packet Type 294 * @HAL_TX_ENCAP_TYPE_NWIFI: Native WiFi Type 295 * @HAL_TX_ENCAP_TYPE_ETHERNET: Ethernet 296 * @HAL_TX_ENCAP_TYPE_802_3: 802.3 Frame 297 */ 298 enum hal_tx_encap_type { 299 HAL_TX_ENCAP_TYPE_RAW = 0, 300 HAL_TX_ENCAP_TYPE_NWIFI = 1, 301 HAL_TX_ENCAP_TYPE_ETHERNET = 2, 302 HAL_TX_ENCAP_TYPE_802_3 = 3, 303 }; 304 305 /** 306 * enum hal_tx_tqm_release_reason - TQM Release reason codes 307 * 308 * @HAL_TX_TQM_RR_FRAME_ACKED : ACK of BA for it was received 309 * @HAL_TX_TQM_RR_REM_CMD_REM : Remove cmd of type “Remove_mpdus” initiated 310 * by SW 311 * @HAL_TX_TQM_RR_REM_CMD_TX : Remove command of type Remove_transmitted_mpdus 312 * initiated by SW 313 * @HAL_TX_TQM_RR_REM_CMD_NOTX : Remove cmd of type Remove_untransmitted_mpdus 314 * initiated by SW 315 * @HAL_TX_TQM_RR_REM_CMD_AGED : Remove command of type “Remove_aged_mpdus” or 316 * “Remove_aged_msdus” initiated by SW 317 * @HAL_TX_TQM_RR_FW_REASON1 : Remove command where fw indicated that 318 * remove reason is fw_reason1 319 * @HAL_TX_TQM_RR_FW_REASON2 : Remove command where fw indicated that 320 * remove reason is fw_reason2 321 * @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that 322 * remove reason is fw_reason3 323 * @HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE : Remove command where fw indicated that 324 * remove reason is remove disable queue 325 * @HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING: Remove command from fw to remove 326 * all mpdu until 1st non-match 327 * @HAL_TX_TQM_RR_DROP_THRESHOLD: Dropped due to drop threshold criteria 328 * @HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE: Dropped due to link desc not available 329 * @HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU: Dropped due drop bit set or null flow 330 * @HAL_TX_TQM_RR_MULTICAST_DROP: Dropped due mcast drop set for VDEV 331 * @HAL_TX_TQM_RR_VDEV_MISMATCH_DROP: Dropped due to being set with 332 * 'TCL_drop_reason' 333 * 334 */ 335 enum hal_tx_tqm_release_reason { 336 HAL_TX_TQM_RR_FRAME_ACKED, 337 HAL_TX_TQM_RR_REM_CMD_REM, 338 HAL_TX_TQM_RR_REM_CMD_TX, 339 HAL_TX_TQM_RR_REM_CMD_NOTX, 340 HAL_TX_TQM_RR_REM_CMD_AGED, 341 HAL_TX_TQM_RR_FW_REASON1, 342 HAL_TX_TQM_RR_FW_REASON2, 343 HAL_TX_TQM_RR_FW_REASON3, 344 HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE, 345 HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING, 346 HAL_TX_TQM_RR_DROP_THRESHOLD, 347 HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE, 348 HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU, 349 HAL_TX_TQM_RR_MULTICAST_DROP, 350 HAL_TX_TQM_RR_VDEV_MISMATCH_DROP, 351 }; 352 353 /* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports 354 * @HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT: Default DSCP-TID mapping table 355 * @HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE: DSCP-TID map override table 356 */ 357 enum hal_tx_dscp_tid_table_id { 358 HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT, 359 HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE, 360 }; 361 362 /*--------------------------------------------------------------------------- 363 Function declarations and documentation 364 ---------------------------------------------------------------------------*/ 365 366 /*--------------------------------------------------------------------------- 367 Tx MSDU Extension Descriptor accessor APIs 368 ---------------------------------------------------------------------------*/ 369 /** 370 * hal_tx_ext_desc_set_tso_enable() - Set TSO Enable Flag 371 * @desc: Handle to Tx MSDU Extension Descriptor 372 * @tso_en: bool value set to true if TSO is enabled 373 * 374 * Return: none 375 */ 376 static inline void hal_tx_ext_desc_set_tso_enable(void *desc, 377 uint8_t tso_en) 378 { 379 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE) |= 380 HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TSO_ENABLE, tso_en); 381 } 382 383 /** 384 * hal_tx_ext_desc_set_tso_flags() - Set TSO Flags 385 * @desc: Handle to Tx MSDU Extension Descriptor 386 * @tso_flags: 32-bit word with all TSO flags consolidated 387 * 388 * Return: none 389 */ 390 static inline void hal_tx_ext_desc_set_tso_flags(void *desc, 391 uint32_t tso_flags) 392 { 393 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE, 0) = 394 tso_flags; 395 } 396 397 /** 398 * hal_tx_ext_desc_set_tcp_flags() - Enable HW Checksum offload 399 * @desc: Handle to Tx MSDU Extension Descriptor 400 * @tcp_flags: TCP flags {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 401 * @mask: TCP flag mask. Tcp_flag is inserted into the header 402 * based on the mask, if tso is enabled 403 * 404 * Return: none 405 */ 406 static inline void hal_tx_ext_desc_set_tcp_flags(void *desc, 407 uint16_t tcp_flags, 408 uint16_t mask) 409 { 410 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_FLAG) |= 411 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG, tcp_flags)) | 412 (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG_MASK, mask))); 413 } 414 415 /** 416 * hal_tx_ext_desc_set_msdu_length() - Set L2 and IP Lengths 417 * @desc: Handle to Tx MSDU Extension Descriptor 418 * @l2_len: L2 length for the msdu, if tso is enabled 419 * @ip_len: IP length for the msdu, if tso is enabled 420 * 421 * Return: none 422 */ 423 static inline void hal_tx_ext_desc_set_msdu_length(void *desc, 424 uint16_t l2_len, 425 uint16_t ip_len) 426 { 427 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, L2_LENGTH) |= 428 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, L2_LENGTH, l2_len)) | 429 (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_LENGTH, ip_len))); 430 } 431 432 /** 433 * hal_tx_ext_desc_set_tcp_seq() - Set TCP Sequence number 434 * @desc: Handle to Tx MSDU Extension Descriptor 435 * @seq_num: Tcp_seq_number for the msdu, if tso is enabled 436 * 437 * Return: none 438 */ 439 static inline void hal_tx_ext_desc_set_tcp_seq(void *desc, 440 uint32_t seq_num) 441 { 442 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER) |= 443 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER, seq_num))); 444 } 445 446 447 /** 448 * hal_tx_ext_desc_set_ip_id() - Set IP Identification field 449 * @desc: Handle to Tx MSDU Extension Descriptor 450 * @id: IP Id field for the msdu, if tso is enabled 451 * 452 * Return: none 453 */ 454 static inline void hal_tx_ext_desc_set_ip_id(void *desc, 455 uint16_t id) 456 { 457 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION) |= 458 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION, id))); 459 } 460 /** 461 * hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment 462 * @desc: Handle to Tx MSDU Extension Descriptor 463 * @frag_num: Fragment number (value can be 0 to 5) 464 * @paddr_lo: Lower 32-bit of Buffer Physical address 465 * @paddr_hi: Upper 32-bit of Buffer Physical address 466 * @length: Buffer Length 467 * 468 * Return: none 469 */ 470 static inline void hal_tx_ext_desc_set_buffer(void *desc, 471 uint8_t frag_num, 472 uint32_t paddr_lo, 473 uint16_t paddr_hi, 474 uint16_t length) 475 { 476 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, 477 (frag_num << 3)) |= 478 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo))); 479 480 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32, 481 (frag_num << 3)) |= 482 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32, 483 (paddr_hi)))); 484 485 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN, 486 (frag_num << 3)) |= 487 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length))); 488 } 489 490 /** 491 * hal_tx_ext_desc_get_frag_info() - Get the frag_num'th frag iova and len 492 * @desc: Handle to Tx MSDU Extension Descriptor 493 * @frag_num: fragment number (value can be 0 to 5) 494 * @iova: fragment dma address 495 * @len: fragment Length 496 * 497 * Return: None 498 */ 499 static inline void hal_tx_ext_desc_get_frag_info(void *desc, uint8_t frag_num, 500 qdf_dma_addr_t *iova, 501 uint32_t *len) 502 { 503 uint64_t iova_hi; 504 505 *iova = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, 506 BUF0_PTR_31_0, (frag_num << 3)); 507 508 iova_hi = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, 509 BUF0_PTR_39_32, (frag_num << 3)); 510 *iova |= (iova_hi << 32); 511 512 *len = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN, 513 (frag_num << 3)); 514 } 515 516 /** 517 * hal_tx_ext_desc_set_buffer0_param() - Set Buffer 0 Pointer and Length 518 * @desc: Handle to Tx MSDU Extension Descriptor 519 * @paddr_lo: Lower 32-bit of Buffer Physical address 520 * @paddr_hi: Upper 32-bit of Buffer Physical address 521 * @length: Buffer 0 Length 522 * 523 * Return: none 524 */ 525 static inline void hal_tx_ext_desc_set_buffer0_param(void *desc, 526 uint32_t paddr_lo, 527 uint16_t paddr_hi, 528 uint16_t length) 529 { 530 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0) |= 531 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo))); 532 533 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32) |= 534 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, 535 BUF0_PTR_39_32, paddr_hi))); 536 537 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN) |= 538 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length))); 539 } 540 541 /** 542 * hal_tx_ext_desc_set_buffer1_param() - Set Buffer 1 Pointer and Length 543 * @desc: Handle to Tx MSDU Extension Descriptor 544 * @paddr_lo: Lower 32-bit of Buffer Physical address 545 * @paddr_hi: Upper 32-bit of Buffer Physical address 546 * @length: Buffer 1 Length 547 * 548 * Return: none 549 */ 550 static inline void hal_tx_ext_desc_set_buffer1_param(void *desc, 551 uint32_t paddr_lo, 552 uint16_t paddr_hi, 553 uint16_t length) 554 { 555 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0) |= 556 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0, paddr_lo))); 557 558 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_39_32) |= 559 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, 560 BUF1_PTR_39_32, paddr_hi))); 561 562 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_LEN) |= 563 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_LEN, length))); 564 } 565 566 /** 567 * hal_tx_ext_desc_set_buffer2_param() - Set Buffer 2 Pointer and Length 568 * @desc: Handle to Tx MSDU Extension Descriptor 569 * @paddr_lo: Lower 32-bit of Buffer Physical address 570 * @paddr_hi: Upper 32-bit of Buffer Physical address 571 * @length: Buffer 2 Length 572 * 573 * Return: none 574 */ 575 static inline void hal_tx_ext_desc_set_buffer2_param(void *desc, 576 uint32_t paddr_lo, 577 uint16_t paddr_hi, 578 uint16_t length) 579 { 580 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0) |= 581 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0, 582 paddr_lo))); 583 584 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32) |= 585 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32, 586 paddr_hi))); 587 588 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_LEN) |= 589 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_LEN, length))); 590 } 591 592 /** 593 * hal_tx_ext_desc_sync - Commit the descriptor to Hardware 594 * @desc_cached: Cached descriptor that software maintains 595 * @hw_desc: Hardware descriptor to be updated 596 * 597 * Return: none 598 */ 599 static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached, 600 uint8_t *hw_desc) 601 { 602 qdf_mem_copy(&hw_desc[0], &desc_cached[0], 603 HAL_TX_EXT_DESC_WITH_META_DATA); 604 } 605 606 /** 607 * hal_tx_ext_desc_get_tso_enable() - Set TSO Enable Flag 608 * @hal_tx_ext_desc: Handle to Tx MSDU Extension Descriptor 609 * 610 * Return: tso_enable value in the descriptor 611 */ 612 static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc) 613 { 614 uint32_t *desc = (uint32_t *) hal_tx_ext_desc; 615 return (*desc & HAL_TX_MSDU_EXTENSION_TSO_ENABLE_MASK) >> 616 HAL_TX_MSDU_EXTENSION_TSO_ENABLE_LSB; 617 } 618 619 /*--------------------------------------------------------------------------- 620 WBM Descriptor accessor APIs for Tx completions 621 ---------------------------------------------------------------------------*/ 622 /** 623 * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type 624 * @hal_desc: completion ring descriptor pointer 625 * 626 * This function will return the type of pointer - buffer or descriptor 627 * 628 * Return: buffer type 629 */ 630 static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc) 631 { 632 uint32_t comp_desc = 633 *(uint32_t *) (((uint8_t *) hal_desc) + 634 HAL_TX_COMP_BUFFER_OR_DESC_TYPE_OFFSET); 635 636 return (comp_desc & HAL_TX_COMP_BUFFER_OR_DESC_TYPE_MASK) >> 637 HAL_TX_COMP_BUFFER_OR_DESC_TYPE_LSB; 638 } 639 640 #ifdef QCA_WIFI_KIWI 641 /** 642 * hal_tx_comp_get_buffer_source() - Get buffer release source value 643 * @hal_soc_hdl: HAL SoC context 644 * @hal_desc: completion ring descriptor pointer 645 * 646 * This function will get buffer release source from Tx completion descriptor 647 * 648 * Return: buffer release source 649 */ 650 static inline uint32_t 651 hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl, 652 void *hal_desc) 653 { 654 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 655 656 return hal_soc->ops->hal_tx_comp_get_buffer_source(hal_desc); 657 } 658 #else 659 static inline uint32_t 660 hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl, 661 void *hal_desc) 662 { 663 return HAL_WBM2SW_RELEASE_SRC_GET(hal_desc); 664 } 665 #endif 666 667 /** 668 * hal_tx_comp_get_release_reason() - TQM Release reason 669 * @hal_desc: completion ring descriptor pointer 670 * @hal_soc_hdl: HAL SoC context 671 * 672 * This function will return the type of pointer - buffer or descriptor 673 * 674 * Return: buffer type 675 */ 676 static inline 677 uint8_t hal_tx_comp_get_release_reason(void *hal_desc, 678 hal_soc_handle_t hal_soc_hdl) 679 { 680 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 681 682 return hal_soc->ops->hal_tx_comp_get_release_reason(hal_desc); 683 } 684 685 /** 686 * hal_tx_comp_get_peer_id() - Get peer_id value 687 * @hal_desc: completion ring descriptor pointer 688 * 689 * This function will get peer_id value from Tx completion descriptor 690 * 691 * Return: buffer release source 692 */ 693 static inline uint16_t hal_tx_comp_get_peer_id(void *hal_desc) 694 { 695 uint32_t comp_desc = 696 *(uint32_t *)(((uint8_t *)hal_desc) + 697 HAL_TX_COMP_SW_PEER_ID_OFFSET); 698 699 return (comp_desc & HAL_TX_COMP_SW_PEER_ID_MASK) >> 700 HAL_TX_COMP_SW_PEER_ID_LSB; 701 } 702 703 /** 704 * hal_tx_comp_get_tx_status() - Get tx transmission status() 705 * @hal_desc: completion ring descriptor pointer 706 * 707 * This function will get transmit status value from Tx completion descriptor 708 * 709 * Return: buffer release source 710 */ 711 static inline uint8_t hal_tx_comp_get_tx_status(void *hal_desc) 712 { 713 uint32_t comp_desc = 714 *(uint32_t *)(((uint8_t *)hal_desc) + 715 HAL_TX_COMP_TQM_RELEASE_REASON_OFFSET); 716 717 return (comp_desc & HAL_TX_COMP_TQM_RELEASE_REASON_MASK) >> 718 HAL_TX_COMP_TQM_RELEASE_REASON_LSB; 719 } 720 721 /** 722 * hal_tx_comp_desc_sync() - collect hardware descriptor contents 723 * @hw_desc: hardware descriptor pointer 724 * @comp: software descriptor pointer 725 * @read_status: 0 - Do not read status words from descriptors 726 * 1 - Enable reading of status words from descriptor 727 * 728 * This function will collect hardware release ring element contents and 729 * translate to software descriptor content 730 * 731 * Return: none 732 */ 733 734 static inline void hal_tx_comp_desc_sync(void *hw_desc, 735 struct hal_tx_desc_comp_s *comp, 736 bool read_status) 737 { 738 if (!read_status) 739 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_BASE_LEN); 740 else 741 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_LEN_BYTES); 742 } 743 744 /** 745 * hal_dump_comp_desc() - dump tx completion descriptor 746 * @hw_desc: hardware descriptor pointer 747 * 748 * This function will print tx completion descriptor 749 * 750 * Return: none 751 */ 752 static inline void hal_dump_comp_desc(void *hw_desc) 753 { 754 struct hal_tx_desc_comp_s *comp = 755 (struct hal_tx_desc_comp_s *)hw_desc; 756 uint32_t i; 757 758 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 759 "Current tx completion descriptor is"); 760 761 for (i = 0; i < HAL_TX_COMPLETION_DESC_LEN_DWORDS; i++) { 762 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 763 "DWORD[i] = 0x%x", comp->desc[i]); 764 } 765 } 766 767 /** 768 * hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor 769 * @hw_desc: Hardware (WBM) descriptor pointer 770 * @htt_desc: Software HTT descriptor pointer 771 * 772 * This function will read the HTT structure overlaid on WBM descriptor 773 * into a cached software descriptor 774 * 775 */ 776 static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc) 777 { 778 uint8_t *desc = hw_desc + HAL_TX_COMP_HTT_STATUS_OFFSET; 779 780 qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN); 781 } 782 783 /** 784 * hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG 785 * @hal_soc_hdl: Handle to HAL SoC structure 786 * @hal_ring_hdl: Handle to HAL SRNG structure 787 * 788 * Return: none 789 */ 790 static inline void hal_tx_init_data_ring(hal_soc_handle_t hal_soc_hdl, 791 hal_ring_handle_t hal_ring_hdl) 792 { 793 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 794 795 hal_soc->ops->hal_tx_init_data_ring(hal_soc_hdl, hal_ring_hdl); 796 } 797 798 /** 799 * hal_tx_set_dscp_tid_map() - Configure default DSCP to TID map table 800 * @hal_soc_hdl: HAL SoC context 801 * @map: DSCP-TID mapping table 802 * @id: mapping table ID - 0,1 803 * 804 * Return: void 805 */ 806 static inline void hal_tx_set_dscp_tid_map(hal_soc_handle_t hal_soc_hdl, 807 uint8_t *map, uint8_t id) 808 { 809 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 810 811 hal_soc->ops->hal_tx_set_dscp_tid_map(hal_soc, map, id); 812 } 813 814 /** 815 * hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user 816 * @hal_soc_hdl: HAL SoC context 817 * @tid: TID 818 * @id: MAP ID 819 * @dscp: DSCP 820 * 821 * Return: void 822 */ 823 static inline 824 void hal_tx_update_dscp_tid(hal_soc_handle_t hal_soc_hdl, uint8_t tid, 825 uint8_t id, uint8_t dscp) 826 { 827 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 828 829 hal_soc->ops->hal_tx_update_dscp_tid(hal_soc, tid, id, dscp); 830 } 831 832 /** 833 * hal_tx_comp_get_status() - TQM Release reason 834 * @desc: completion ring Tx status 835 * @ts: returned tx completion status 836 * @hal_soc_hdl: HAL SoC context 837 * 838 * This function will parse the WBM completion descriptor and populate in 839 * HAL structure 840 * 841 * Return: none 842 */ 843 static inline void hal_tx_comp_get_status(void *desc, void *ts, 844 hal_soc_handle_t hal_soc_hdl) 845 { 846 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 847 848 hal_soc->ops->hal_tx_comp_get_status(desc, ts, hal_soc); 849 } 850 851 /** 852 * hal_tx_set_pcp_tid_map_default() - Configure default PCP to TID map table 853 * @hal_soc_hdl: HAL SoC context 854 * @map: PCP-TID mapping table 855 * 856 * Return: void 857 */ 858 static inline void hal_tx_set_pcp_tid_map_default(hal_soc_handle_t hal_soc_hdl, 859 uint8_t *map) 860 { 861 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 862 863 hal_soc->ops->hal_tx_set_pcp_tid_map(hal_soc, map); 864 } 865 866 /** 867 * hal_tx_update_pcp_tid_map() - Update PCP to TID map table 868 * @hal_soc_hdl: HAL SoC context 869 * @pcp: pcp value 870 * @tid: tid no 871 * 872 * Return: void 873 */ 874 static inline void hal_tx_update_pcp_tid_map(hal_soc_handle_t hal_soc_hdl, 875 uint8_t pcp, uint8_t tid) 876 { 877 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 878 879 hal_soc->ops->hal_tx_update_pcp_tid_map(hal_soc, pcp, tid); 880 } 881 882 /** 883 * hal_tx_set_tidmap_prty() - Configure TIDmap priority 884 * @hal_soc_hdl: HAL SoC context 885 * @val: priority value 886 * 887 * Return: void 888 */ 889 static inline 890 void hal_tx_set_tidmap_prty(hal_soc_handle_t hal_soc_hdl, uint8_t val) 891 { 892 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 893 894 hal_soc->ops->hal_tx_set_tidmap_prty(hal_soc, val); 895 } 896 897 /** 898 * hal_get_wbm_internal_error() - wbm internal error 899 * @hal_soc_hdl: HAL SoC context 900 * @hal_desc: completion ring descriptor pointer 901 * 902 * This function will return the type of pointer - buffer or descriptor 903 * 904 * Return: buffer type 905 */ 906 static inline 907 uint8_t hal_get_wbm_internal_error(hal_soc_handle_t hal_soc_hdl, void *hal_desc) 908 { 909 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 910 911 return hal_soc->ops->hal_get_wbm_internal_error(hal_desc); 912 } 913 914 /** 915 * hal_get_tsf2_offset() - get tsf2 offset 916 * @hal_soc_hdl: HAL SoC context 917 * @mac_id: mac id 918 * @value: pointer to update tsf2 offset value 919 * 920 * Return: void 921 */ 922 static inline void 923 hal_get_tsf2_offset(hal_soc_handle_t hal_soc_hdl, uint8_t mac_id, 924 uint64_t *value) 925 { 926 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 927 928 if (hal_soc->ops->hal_get_tsf2_scratch_reg) 929 hal_soc->ops->hal_get_tsf2_scratch_reg(hal_soc_hdl, mac_id, 930 value); 931 } 932 933 /** 934 * hal_get_tqm_offset() - get tqm offset 935 * 936 * @hal_soc_hdl: HAL SoC context 937 * @value: pointer to update tqm offset value 938 * 939 * Return: void 940 */ 941 942 static inline void 943 hal_get_tqm_offset(hal_soc_handle_t hal_soc_hdl, uint64_t *value) 944 { 945 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 946 947 if (hal_soc->ops->hal_get_tqm_scratch_reg) 948 hal_soc->ops->hal_get_tqm_scratch_reg(hal_soc_hdl, value); 949 } 950 #endif /* HAL_TX_H */ 951