1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #if !defined(HAL_TX_H) 20 #define HAL_TX_H 21 22 /*--------------------------------------------------------------------------- 23 Include files 24 ---------------------------------------------------------------------------*/ 25 #include "hal_api.h" 26 #include "wcss_version.h" 27 28 #define WBM_RELEASE_RING_5_TX_RATE_STATS_OFFSET 0x00000014 29 #define WBM_RELEASE_RING_5_TX_RATE_STATS_LSB 0 30 #define WBM_RELEASE_RING_5_TX_RATE_STATS_MASK 0xffffffff 31 32 #define HAL_WBM_RELEASE_RING_2_BUFFER_TYPE 0 33 #define HAL_WBM_RELEASE_RING_2_DESC_TYPE 1 34 35 #define HAL_TX_DESC_TLV_TAG_OFFSET 1 36 #define HAL_TX_DESC_TLV_LEN_OFFSET 10 37 38 /*--------------------------------------------------------------------------- 39 Preprocessor definitions and constants 40 ---------------------------------------------------------------------------*/ 41 #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET 42 43 #define HAL_SET_FLD(desc, block , field) \ 44 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field))) 45 46 #define HAL_SET_FLD_OFFSET(desc, block , field, offset) \ 47 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field) + (offset))) 48 49 #define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \ 50 do { \ 51 uint32_t temp = 0; \ 52 temp |= (tag << HAL_TX_DESC_TLV_TAG_OFFSET); \ 53 temp |= (len << HAL_TX_DESC_TLV_LEN_OFFSET); \ 54 (*(uint32_t *)desc) = temp; \ 55 } while (0) 56 57 #define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E 58 #define HAL_TX_TCL_CMD_TAG WIFITCL_GSE_CMD_E 59 60 #define HAL_TX_SM(block, field, value) \ 61 ((value << (block ## _ ## field ## _LSB)) & \ 62 (block ## _ ## field ## _MASK)) 63 64 #define HAL_TX_MS(block, field, value) \ 65 (((value) & (block ## _ ## field ## _MASK)) >> \ 66 (block ## _ ## field ## _LSB)) 67 68 #define HAL_TX_DESC_GET(desc, block, field) \ 69 HAL_TX_MS(block, field, HAL_SET_FLD(desc, block, field)) 70 71 #define HAL_TX_DESC_SUBBLOCK_GET(desc, block, sub, field) \ 72 HAL_TX_MS(sub, field, HAL_SET_FLD(desc, block, sub)) 73 74 #define HAL_TX_BUF_TYPE_BUFFER 0 75 #define HAL_TX_BUF_TYPE_EXT_DESC 1 76 77 #define HAL_TX_DESC_LEN_DWORDS (NUM_OF_DWORDS_TCL_DATA_CMD) 78 #define HAL_TX_DESC_LEN_BYTES (NUM_OF_DWORDS_TCL_DATA_CMD * 4) 79 #define HAL_TX_EXTENSION_DESC_LEN_DWORDS (NUM_OF_DWORDS_TX_MSDU_EXTENSION) 80 #define HAL_TX_EXTENSION_DESC_LEN_BYTES (NUM_OF_DWORDS_TX_MSDU_EXTENSION * 4) 81 82 #define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 83 #define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4) 84 #define HAL_TX_BITS_PER_TID 3 85 #define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1) 86 #define HAL_TX_NUM_DSCP_PER_REGISTER 10 87 #define HAL_MAX_HW_DSCP_TID_MAPS 2 88 #define HAL_MAX_HW_DSCP_TID_MAPS_11AX 32 89 90 #define HAL_MAX_HW_DSCP_TID_V2_MAPS 48 91 #define HTT_META_HEADER_LEN_BYTES 64 92 #define HAL_TX_EXT_DESC_WITH_META_DATA \ 93 (HTT_META_HEADER_LEN_BYTES + HAL_TX_EXTENSION_DESC_LEN_BYTES) 94 95 #define HAL_TX_NUM_PCP_PER_REGISTER 8 96 97 /* Length of WBM release ring without the status words */ 98 #define HAL_TX_COMPLETION_DESC_BASE_LEN 12 99 100 #define HAL_TX_COMP_RELEASE_SOURCE_TQM 0 101 #define HAL_TX_COMP_RELEASE_SOURCE_REO 2 102 #define HAL_TX_COMP_RELEASE_SOURCE_FW 3 103 104 /* Define a place-holder release reason for FW */ 105 #define HAL_TX_COMP_RELEASE_REASON_FW 99 106 107 /* 108 * Offset of HTT Tx Descriptor in WBM Completion 109 * HTT Tx Desc structure is passed from firmware to host overlayed 110 * on wbm_release_ring DWORDs 2,3 ,4 and 5for software based completions 111 * (Exception frames and TQM bypass frames) 112 */ 113 #define HAL_TX_COMP_HTT_STATUS_OFFSET 8 114 #define HAL_TX_COMP_HTT_STATUS_LEN 16 115 116 #define HAL_TX_BUF_TYPE_BUFFER 0 117 #define HAL_TX_BUF_TYPE_EXT_DESC 1 118 119 #define HAL_TX_EXT_DESC_BUF_OFFSET TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 120 #define HAL_TX_EXT_BUF_LOW_MASK TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 121 #define HAL_TX_EXT_BUF_HI_MASK TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 122 #define HAL_TX_EXT_BUF_LEN_MASK TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 123 #define HAL_TX_EXT_BUF_LEN_LSB TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 124 #define HAL_TX_EXT_BUF_WD_SIZE 2 125 126 #define HAL_TX_DESC_ADDRX_EN 0x1 127 #define HAL_TX_DESC_ADDRY_EN 0x2 128 #define HAL_TX_DESC_DEFAULT_LMAC_ID 0x3 129 130 #define HAL_TX_ADDR_SEARCH_DEFAULT 0x0 131 #define HAL_TX_ADDR_INDEX_SEARCH 0x1 132 #define HAL_TX_FLOW_INDEX_SEARCH 0x2 133 134 enum hal_tx_ret_buf_manager { 135 HAL_WBM_SW0_BM_ID = 3, 136 HAL_WBM_SW1_BM_ID = 4, 137 HAL_WBM_SW2_BM_ID = 5, 138 HAL_WBM_SW3_BM_ID = 6, 139 }; 140 141 /*--------------------------------------------------------------------------- 142 Structures 143 ---------------------------------------------------------------------------*/ 144 /** 145 * struct hal_tx_completion_status - HAL Tx completion descriptor contents 146 * @status: frame acked/failed 147 * @release_src: release source = TQM/FW 148 * @ack_frame_rssi: RSSI of the received ACK or BA frame 149 * @first_msdu: Indicates this MSDU is the first MSDU in AMSDU 150 * @last_msdu: Indicates this MSDU is the last MSDU in AMSDU 151 * @msdu_part_of_amsdu : Indicates this MSDU was part of an A-MSDU in MPDU 152 * @bw: Indicates the BW of the upcoming transmission - 153 * <enum 0 transmit_bw_20_MHz> 154 * <enum 1 transmit_bw_40_MHz> 155 * <enum 2 transmit_bw_80_MHz> 156 * <enum 3 transmit_bw_160_MHz> 157 * @pkt_type: Transmit Packet Type 158 * @stbc: When set, STBC transmission rate was used 159 * @ldpc: When set, use LDPC transmission rates 160 * @sgi: <enum 0 0_8_us_sgi > Legacy normal GI 161 * <enum 1 0_4_us_sgi > Legacy short GI 162 * <enum 2 1_6_us_sgi > HE related GI 163 * <enum 3 3_2_us_sgi > HE 164 * @mcs: Transmit MCS Rate 165 * @ofdma: Set when the transmission was an OFDMA transmission 166 * @tones_in_ru: The number of tones in the RU used. 167 * @tsf: Lower 32 bits of the TSF 168 * @ppdu_id: TSF, snapshot of this value when transmission of the 169 * PPDU containing the frame finished. 170 * @transmit_cnt: Number of times this frame has been transmitted 171 * @tid: TID of the flow or MPDU queue 172 * @peer_id: Peer ID of the flow or MPDU queue 173 */ 174 struct hal_tx_completion_status { 175 uint8_t status; 176 uint8_t release_src; 177 uint8_t ack_frame_rssi; 178 uint8_t first_msdu:1, 179 last_msdu:1, 180 msdu_part_of_amsdu:1; 181 uint32_t bw:2, 182 pkt_type:4, 183 stbc:1, 184 ldpc:1, 185 sgi:2, 186 mcs:4, 187 ofdma:1, 188 tones_in_ru:12, 189 valid:1; 190 uint32_t tsf; 191 uint32_t ppdu_id; 192 uint8_t transmit_cnt; 193 uint8_t tid; 194 uint16_t peer_id; 195 }; 196 197 /** 198 * struct hal_tx_desc_comp_s - hal tx completion descriptor contents 199 * @desc: Transmit status information from descriptor 200 */ 201 struct hal_tx_desc_comp_s { 202 uint32_t desc[HAL_TX_COMPLETION_DESC_LEN_DWORDS]; 203 }; 204 205 /* 206 * enum hal_tx_encrypt_type - Type of decrypt cipher used (valid only for RAW) 207 * @HAL_TX_ENCRYPT_TYPE_WEP_40: WEP 40-bit 208 * @HAL_TX_ENCRYPT_TYPE_WEP_10: WEP 10-bit 209 * @HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC: TKIP without MIC 210 * @HAL_TX_ENCRYPT_TYPE_WEP_128: WEP_128 211 * @HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC: TKIP_WITH_MIC 212 * @HAL_TX_ENCRYPT_TYPE_WAPI: WAPI 213 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_128: AES_CCMP_128 214 * @HAL_TX_ENCRYPT_TYPE_NO_CIPHER: NO CIPHER 215 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_256: AES_CCMP_256 216 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_128: AES_GCMP_128 217 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_256: AES_GCMP_256 218 * @HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4: WAPI GCM SM4 219 */ 220 enum hal_tx_encrypt_type { 221 HAL_TX_ENCRYPT_TYPE_WEP_40 = 0, 222 HAL_TX_ENCRYPT_TYPE_WEP_104 = 1 , 223 HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC = 2, 224 HAL_TX_ENCRYPT_TYPE_WEP_128 = 3, 225 HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC = 4, 226 HAL_TX_ENCRYPT_TYPE_WAPI = 5, 227 HAL_TX_ENCRYPT_TYPE_AES_CCMP_128 = 6, 228 HAL_TX_ENCRYPT_TYPE_NO_CIPHER = 7, 229 HAL_TX_ENCRYPT_TYPE_AES_CCMP_256 = 8, 230 HAL_TX_ENCRYPT_TYPE_AES_GCMP_128 = 9, 231 HAL_TX_ENCRYPT_TYPE_AES_GCMP_256 = 10, 232 HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4 = 11, 233 }; 234 235 /* 236 * enum hal_tx_encap_type - Encapsulation type that HW will perform 237 * @HAL_TX_ENCAP_TYPE_RAW: Raw Packet Type 238 * @HAL_TX_ENCAP_TYPE_NWIFI: Native WiFi Type 239 * @HAL_TX_ENCAP_TYPE_ETHERNET: Ethernet 240 * @HAL_TX_ENCAP_TYPE_802_3: 802.3 Frame 241 */ 242 enum hal_tx_encap_type { 243 HAL_TX_ENCAP_TYPE_RAW = 0, 244 HAL_TX_ENCAP_TYPE_NWIFI = 1, 245 HAL_TX_ENCAP_TYPE_ETHERNET = 2, 246 HAL_TX_ENCAP_TYPE_802_3 = 3, 247 }; 248 249 /** 250 * enum hal_tx_tqm_release_reason - TQM Release reason codes 251 * 252 * @HAL_TX_TQM_RR_FRAME_ACKED : ACK of BA for it was received 253 * @HAL_TX_TQM_RR_REM_CMD_REM : Remove cmd of type “Remove_mpdus” initiated 254 * by SW 255 * @HAL_TX_TQM_RR_REM_CMD_TX : Remove command of type Remove_transmitted_mpdus 256 * initiated by SW 257 * @HAL_TX_TQM_RR_REM_CMD_NOTX : Remove cmd of type Remove_untransmitted_mpdus 258 * initiated by SW 259 * @HAL_TX_TQM_RR_REM_CMD_AGED : Remove command of type “Remove_aged_mpdus” or 260 * “Remove_aged_msdus” initiated by SW 261 * @HAL_TX_TQM_RR_FW_REASON1 : Remove command where fw indicated that 262 * remove reason is fw_reason1 263 * @HAL_TX_TQM_RR_FW_REASON2 : Remove command where fw indicated that 264 * remove reason is fw_reason2 265 * @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that 266 * remove reason is fw_reason3 267 * @HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE : Remove command where fw indicated that 268 * remove reason is remove disable queue 269 */ 270 enum hal_tx_tqm_release_reason { 271 HAL_TX_TQM_RR_FRAME_ACKED, 272 HAL_TX_TQM_RR_REM_CMD_REM, 273 HAL_TX_TQM_RR_REM_CMD_TX, 274 HAL_TX_TQM_RR_REM_CMD_NOTX, 275 HAL_TX_TQM_RR_REM_CMD_AGED, 276 HAL_TX_TQM_RR_FW_REASON1, 277 HAL_TX_TQM_RR_FW_REASON2, 278 HAL_TX_TQM_RR_FW_REASON3, 279 HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE, 280 }; 281 282 /* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports 283 * @HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT: Default DSCP-TID mapping table 284 * @HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE: DSCP-TID map override table 285 */ 286 enum hal_tx_dscp_tid_table_id { 287 HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT, 288 HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE, 289 }; 290 291 /*--------------------------------------------------------------------------- 292 Function declarations and documentation 293 ---------------------------------------------------------------------------*/ 294 295 /*--------------------------------------------------------------------------- 296 TCL Descriptor accessor APIs 297 ---------------------------------------------------------------------------*/ 298 299 /** 300 * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor 301 * @desc: Handle to Tx Descriptor 302 * @data_length: MSDU length in case of direct descriptor. 303 * Length of link extension descriptor in case of Link extension 304 * descriptor.Includes the length of Metadata 305 * Return: None 306 */ 307 static inline void hal_tx_desc_set_buf_length(void *desc, 308 uint16_t data_length) 309 { 310 HAL_SET_FLD(desc, TCL_DATA_CMD_3, DATA_LENGTH) |= 311 HAL_TX_SM(TCL_DATA_CMD_3, DATA_LENGTH, data_length); 312 } 313 314 /** 315 * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor 316 * @desc: Handle to Tx Descriptor 317 * @offset: Packet offset from Metadata in case of direct buffer descriptor. 318 * 319 * Return: void 320 */ 321 static inline void hal_tx_desc_set_buf_offset(void *desc, 322 uint8_t offset) 323 { 324 HAL_SET_FLD(desc, TCL_DATA_CMD_3, PACKET_OFFSET) |= 325 HAL_TX_SM(TCL_DATA_CMD_3, PACKET_OFFSET, offset); 326 } 327 328 /** 329 * hal_tx_desc_set_encap_type - Set encapsulation type in Tx Descriptor 330 * @desc: Handle to Tx Descriptor 331 * @encap_type: Encapsulation that HW will perform 332 * 333 * Return: void 334 * 335 */ 336 static inline void hal_tx_desc_set_encap_type(void *desc, 337 enum hal_tx_encap_type encap_type) 338 { 339 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCAP_TYPE) |= 340 HAL_TX_SM(TCL_DATA_CMD_2, ENCAP_TYPE, encap_type); 341 } 342 343 /** 344 * hal_tx_desc_set_encrypt_type - Sets the Encrypt Type in Tx Descriptor 345 * @desc: Handle to Tx Descriptor 346 * @type: Encrypt Type 347 * 348 * Return: void 349 */ 350 static inline void hal_tx_desc_set_encrypt_type(void *desc, 351 enum hal_tx_encrypt_type type) 352 { 353 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCRYPT_TYPE) |= 354 HAL_TX_SM(TCL_DATA_CMD_2, ENCRYPT_TYPE, type); 355 } 356 357 /** 358 * hal_tx_desc_set_addr_search_flags - Enable AddrX and AddrY search flags 359 * @desc: Handle to Tx Descriptor 360 * @flags: Bit 0 - AddrY search enable, Bit 1 - AddrX search enable 361 * 362 * Return: void 363 */ 364 static inline void hal_tx_desc_set_addr_search_flags(void *desc, 365 uint8_t flags) 366 { 367 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRX_EN) |= 368 HAL_TX_SM(TCL_DATA_CMD_2, ADDRX_EN, (flags & 0x1)); 369 370 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRY_EN) |= 371 HAL_TX_SM(TCL_DATA_CMD_2, ADDRY_EN, (flags >> 1)); 372 } 373 374 /** 375 * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags 376 * Tx Descriptor for MSDU_buffer type 377 * @desc: Handle to Tx Descriptor 378 * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits) 379 * 380 * Return: void 381 */ 382 static inline void hal_tx_desc_set_l4_checksum_en(void *desc, 383 uint8_t en) 384 { 385 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 386 (HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV4_CHECKSUM_EN, en) | 387 HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV6_CHECKSUM_EN, en) | 388 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV4_CHECKSUM_EN, en) | 389 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV6_CHECKSUM_EN, en)); 390 } 391 392 /** 393 * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in 394 * Tx Descriptor for MSDU_buffer type 395 * @desc: Handle to Tx Descriptor 396 * @checksum_en_flags: ipv4 checksum enable flags 397 * 398 * Return: void 399 */ 400 static inline void hal_tx_desc_set_l3_checksum_en(void *desc, 401 uint8_t en) 402 { 403 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 404 HAL_TX_SM(TCL_DATA_CMD_3, IPV4_CHECKSUM_EN, en); 405 } 406 407 /** 408 * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor 409 * @desc:Handle to Tx Descriptor 410 * @metadata: Metadata to be sent to Firmware 411 * 412 * Return: void 413 */ 414 static inline void hal_tx_desc_set_fw_metadata(void *desc, 415 uint16_t metadata) 416 { 417 HAL_SET_FLD(desc, TCL_DATA_CMD_2, TCL_CMD_NUMBER) |= 418 HAL_TX_SM(TCL_DATA_CMD_2, TCL_CMD_NUMBER, metadata); 419 } 420 421 /** 422 * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor. 423 * @desc:Handle to Tx Descriptor 424 * @to_fw: if set, Forward packet to FW along with classification result 425 * 426 * Return: void 427 */ 428 static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw) 429 { 430 HAL_SET_FLD(desc, TCL_DATA_CMD_3, TO_FW) |= 431 HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw); 432 } 433 434 /** 435 * hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor 436 * @hal_soc_hdl: hal soc handle 437 * @desc: Handle to Tx Descriptor 438 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 439 * enabling the interpretation of the 'Mesh Control Present' bit 440 * (bit 8) of QoS Control (otherwise this bit is ignored), 441 * For native WiFi frames, this indicates that a 'Mesh Control' field 442 * is present between the header and the LLC. 443 * 444 * Return: void 445 */ 446 static inline void hal_tx_desc_set_mesh_en(hal_soc_handle_t hal_soc_hdl, 447 void *desc, uint8_t en) 448 { 449 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 450 451 hal_soc->ops->hal_tx_desc_set_mesh_en(desc, en); 452 } 453 454 /** 455 * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in 456 * frame) to be used for Tx Frame 457 * @desc: Handle to Tx Descriptor 458 * @hlos_tid: HLOS TID 459 * 460 * Return: void 461 */ 462 static inline void hal_tx_desc_set_hlos_tid(void *desc, 463 uint8_t hlos_tid) 464 { 465 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID) |= 466 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID, hlos_tid); 467 468 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |= 469 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1); 470 } 471 /** 472 * hal_tx_desc_sync - Commit the descriptor to Hardware 473 * @hal_tx_des_cached: Cached descriptor that software maintains 474 * @hw_desc: Hardware descriptor to be updated 475 */ 476 static inline void hal_tx_desc_sync(void *hal_tx_desc_cached, 477 void *hw_desc) 478 { 479 qdf_mem_copy((hw_desc + sizeof(struct tlv_32_hdr)), 480 hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES); 481 } 482 483 /*--------------------------------------------------------------------------- 484 Tx MSDU Extension Descriptor accessor APIs 485 ---------------------------------------------------------------------------*/ 486 /** 487 * hal_tx_ext_desc_set_tso_enable() - Set TSO Enable Flag 488 * @desc: Handle to Tx MSDU Extension Descriptor 489 * @tso_en: bool value set to true if TSO is enabled 490 * 491 * Return: none 492 */ 493 static inline void hal_tx_ext_desc_set_tso_enable(void *desc, 494 uint8_t tso_en) 495 { 496 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TSO_ENABLE) |= 497 HAL_TX_SM(TX_MSDU_EXTENSION_0, TSO_ENABLE, tso_en); 498 } 499 500 /** 501 * hal_tx_ext_desc_set_tso_flags() - Set TSO Flags 502 * @desc: Handle to Tx MSDU Extension Descriptor 503 * @falgs: 32-bit word with all TSO flags consolidated 504 * 505 * Return: none 506 */ 507 static inline void hal_tx_ext_desc_set_tso_flags(void *desc, 508 uint32_t tso_flags) 509 { 510 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_0, TSO_ENABLE, 0) = 511 tso_flags; 512 } 513 514 /** 515 * hal_tx_ext_desc_set_tcp_flags() - Enable HW Checksum offload 516 * @desc: Handle to Tx MSDU Extension Descriptor 517 * @tcp_flags: TCP flags {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 518 * @mask: TCP flag mask. Tcp_flag is inserted into the header 519 * based on the mask, if tso is enabled 520 * 521 * Return: none 522 */ 523 static inline void hal_tx_ext_desc_set_tcp_flags(void *desc, 524 uint16_t tcp_flags, 525 uint16_t mask) 526 { 527 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TCP_FLAG) |= 528 ((HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG, tcp_flags)) | 529 (HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG_MASK, mask))); 530 } 531 532 /** 533 * hal_tx_ext_desc_set_msdu_length() - Set L2 and IP Lengths 534 * @desc: Handle to Tx MSDU Extension Descriptor 535 * @l2_len: L2 length for the msdu, if tso is enabled 536 * @ip_len: IP length for the msdu, if tso is enabled 537 * 538 * Return: none 539 */ 540 static inline void hal_tx_ext_desc_set_msdu_length(void *desc, 541 uint16_t l2_len, 542 uint16_t ip_len) 543 { 544 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_1, L2_LENGTH) |= 545 ((HAL_TX_SM(TX_MSDU_EXTENSION_1, L2_LENGTH, l2_len)) | 546 (HAL_TX_SM(TX_MSDU_EXTENSION_1, IP_LENGTH, ip_len))); 547 } 548 549 /** 550 * hal_tx_ext_desc_set_tcp_seq() - Set TCP Sequence number 551 * @desc: Handle to Tx MSDU Extension Descriptor 552 * @seq_num: Tcp_seq_number for the msdu, if tso is enabled 553 * 554 * Return: none 555 */ 556 static inline void hal_tx_ext_desc_set_tcp_seq(void *desc, 557 uint32_t seq_num) 558 { 559 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER) |= 560 ((HAL_TX_SM(TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER, seq_num))); 561 } 562 563 564 /** 565 * hal_tx_ext_desc_set_ip_id() - Set IP Identification field 566 * @desc: Handle to Tx MSDU Extension Descriptor 567 * @id: IP Id field for the msdu, if tso is enabled 568 * 569 * Return: none 570 */ 571 static inline void hal_tx_ext_desc_set_ip_id(void *desc, 572 uint16_t id) 573 { 574 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_3, IP_IDENTIFICATION) |= 575 ((HAL_TX_SM(TX_MSDU_EXTENSION_3, IP_IDENTIFICATION, id))); 576 } 577 /** 578 * hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment 579 * @desc: Handle to Tx MSDU Extension Descriptor 580 * @frag_num: Fragment number (value can be 0 to 5) 581 * @paddr_lo: Lower 32-bit of Buffer Physical address 582 * @paddr_hi: Upper 32-bit of Buffer Physical address 583 * @length: Buffer Length 584 * 585 * Return: none 586 */ 587 static inline void hal_tx_ext_desc_set_buffer(void *desc, 588 uint8_t frag_num, 589 uint32_t paddr_lo, 590 uint16_t paddr_hi, 591 uint16_t length) 592 { 593 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, 594 (frag_num << 3)) |= 595 ((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo))); 596 597 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32, 598 (frag_num << 3)) |= 599 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_PTR_39_32, 600 (paddr_hi)))); 601 602 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_LEN, 603 (frag_num << 3)) |= 604 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length))); 605 } 606 607 /** 608 * hal_tx_ext_desc_set_buffer0_param() - Set Buffer 0 Pointer and Length 609 * @desc: Handle to Tx MSDU Extension Descriptor 610 * @paddr_lo: Lower 32-bit of Buffer Physical address 611 * @paddr_hi: Upper 32-bit of Buffer Physical address 612 * @length: Buffer 0 Length 613 * 614 * Return: none 615 */ 616 static inline void hal_tx_ext_desc_set_buffer0_param(void *desc, 617 uint32_t paddr_lo, 618 uint16_t paddr_hi, 619 uint16_t length) 620 { 621 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0) |= 622 ((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo))); 623 624 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32) |= 625 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, 626 BUF0_PTR_39_32, paddr_hi))); 627 628 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_LEN) |= 629 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length))); 630 } 631 632 /** 633 * hal_tx_ext_desc_set_buffer1_param() - Set Buffer 1 Pointer and Length 634 * @desc: Handle to Tx MSDU Extension Descriptor 635 * @paddr_lo: Lower 32-bit of Buffer Physical address 636 * @paddr_hi: Upper 32-bit of Buffer Physical address 637 * @length: Buffer 1 Length 638 * 639 * Return: none 640 */ 641 static inline void hal_tx_ext_desc_set_buffer1_param(void *desc, 642 uint32_t paddr_lo, 643 uint16_t paddr_hi, 644 uint16_t length) 645 { 646 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_8, BUF1_PTR_31_0) |= 647 ((HAL_TX_SM(TX_MSDU_EXTENSION_8, BUF1_PTR_31_0, paddr_lo))); 648 649 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_PTR_39_32) |= 650 ((HAL_TX_SM(TX_MSDU_EXTENSION_9, 651 BUF1_PTR_39_32, paddr_hi))); 652 653 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_LEN) |= 654 ((HAL_TX_SM(TX_MSDU_EXTENSION_9, BUF1_LEN, length))); 655 } 656 657 /** 658 * hal_tx_ext_desc_set_buffer2_param() - Set Buffer 2 Pointer and Length 659 * @desc: Handle to Tx MSDU Extension Descriptor 660 * @paddr_lo: Lower 32-bit of Buffer Physical address 661 * @paddr_hi: Upper 32-bit of Buffer Physical address 662 * @length: Buffer 2 Length 663 * 664 * Return: none 665 */ 666 static inline void hal_tx_ext_desc_set_buffer2_param(void *desc, 667 uint32_t paddr_lo, 668 uint16_t paddr_hi, 669 uint16_t length) 670 { 671 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_10, BUF2_PTR_31_0) |= 672 ((HAL_TX_SM(TX_MSDU_EXTENSION_10, BUF2_PTR_31_0, 673 paddr_lo))); 674 675 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_PTR_39_32) |= 676 ((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_PTR_39_32, 677 paddr_hi))); 678 679 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_LEN) |= 680 ((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_LEN, length))); 681 } 682 683 /** 684 * hal_tx_ext_desc_sync - Commit the descriptor to Hardware 685 * @desc_cached: Cached descriptor that software maintains 686 * @hw_desc: Hardware descriptor to be updated 687 * 688 * Return: none 689 */ 690 static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached, 691 uint8_t *hw_desc) 692 { 693 qdf_mem_copy(&hw_desc[0], &desc_cached[0], 694 HAL_TX_EXT_DESC_WITH_META_DATA); 695 } 696 697 /** 698 * hal_tx_ext_desc_get_tso_enable() - Set TSO Enable Flag 699 * @hal_tx_ext_desc: Handle to Tx MSDU Extension Descriptor 700 * 701 * Return: tso_enable value in the descriptor 702 */ 703 static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc) 704 { 705 uint32_t *desc = (uint32_t *) hal_tx_ext_desc; 706 return (*desc & TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK) >> 707 TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB; 708 } 709 710 /*--------------------------------------------------------------------------- 711 WBM Descriptor accessor APIs for Tx completions 712 ---------------------------------------------------------------------------*/ 713 /** 714 * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor 715 * @hal_desc: completion ring descriptor pointer 716 * 717 * This function will tx descriptor id, cookie, within hardware completion 718 * descriptor 719 * 720 * Return: cookie 721 */ 722 static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc) 723 { 724 uint32_t comp_desc = 725 *(uint32_t *) (((uint8_t *) hal_desc) + 726 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET); 727 728 /* Cookie is placed on 2nd word */ 729 return (comp_desc & BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) >> 730 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB; 731 } 732 733 /** 734 * hal_tx_comp_get_paddr() - Get paddr within comp descriptor 735 * @hal_desc: completion ring descriptor pointer 736 * 737 * This function will get buffer physical address within hardware completion 738 * descriptor 739 * 740 * Return: Buffer physical address 741 */ 742 static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc) 743 { 744 uint32_t paddr_lo; 745 uint32_t paddr_hi; 746 747 paddr_lo = *(uint32_t *) (((uint8_t *) hal_desc) + 748 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET); 749 750 paddr_hi = *(uint32_t *) (((uint8_t *) hal_desc) + 751 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET); 752 753 paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) >> 754 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB; 755 756 return (qdf_dma_addr_t) (paddr_lo | (((uint64_t) paddr_hi) << 32)); 757 } 758 759 /** 760 * hal_tx_comp_get_buffer_source() - Get buffer release source value 761 * @hal_desc: completion ring descriptor pointer 762 * 763 * This function will get buffer release source from Tx completion descriptor 764 * 765 * Return: buffer release source 766 */ 767 static inline uint32_t hal_tx_comp_get_buffer_source(void *hal_desc) 768 { 769 uint32_t comp_desc = 770 *(uint32_t *) (((uint8_t *) hal_desc) + 771 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET); 772 773 return (comp_desc & WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> 774 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB; 775 } 776 777 /** 778 * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type 779 * @hal_desc: completion ring descriptor pointer 780 * 781 * This function will return the type of pointer - buffer or descriptor 782 * 783 * Return: buffer type 784 */ 785 static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc) 786 { 787 uint32_t comp_desc = 788 *(uint32_t *) (((uint8_t *) hal_desc) + 789 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET); 790 791 return (comp_desc & WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> 792 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB; 793 } 794 795 /** 796 * hal_tx_comp_get_release_reason() - TQM Release reason 797 * @hal_desc: completion ring descriptor pointer 798 * 799 * This function will return the type of pointer - buffer or descriptor 800 * 801 * Return: buffer type 802 */ 803 static inline 804 uint8_t hal_tx_comp_get_release_reason(void *hal_desc, 805 hal_soc_handle_t hal_soc_hdl) 806 { 807 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 808 809 return hal_soc->ops->hal_tx_comp_get_release_reason(hal_desc); 810 } 811 812 /** 813 * hal_tx_comp_get_peer_id() - Get peer_id value() 814 * @hal_desc: completion ring descriptor pointer 815 * 816 * This function will get peer_id value from Tx completion descriptor 817 * 818 * Return: buffer release source 819 */ 820 static inline uint16_t hal_tx_comp_get_peer_id(void *hal_desc) 821 { 822 uint32_t comp_desc = 823 *(uint32_t *)(((uint8_t *)hal_desc) + 824 WBM_RELEASE_RING_7_SW_PEER_ID_OFFSET); 825 826 return (comp_desc & WBM_RELEASE_RING_7_SW_PEER_ID_MASK) >> 827 WBM_RELEASE_RING_7_SW_PEER_ID_LSB; 828 } 829 830 /** 831 * hal_tx_comp_get_tx_status() - Get tx transmission status() 832 * @hal_desc: completion ring descriptor pointer 833 * 834 * This function will get transmit status value from Tx completion descriptor 835 * 836 * Return: buffer release source 837 */ 838 static inline uint8_t hal_tx_comp_get_tx_status(void *hal_desc) 839 { 840 uint32_t comp_desc = 841 *(uint32_t *)(((uint8_t *)hal_desc) + 842 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 843 844 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 845 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 846 } 847 848 /** 849 * hal_tx_comp_desc_sync() - collect hardware descriptor contents 850 * @hal_desc: hardware descriptor pointer 851 * @comp: software descriptor pointer 852 * @read_status: 0 - Do not read status words from descriptors 853 * 1 - Enable reading of status words from descriptor 854 * 855 * This function will collect hardware release ring element contents and 856 * translate to software descriptor content 857 * 858 * Return: none 859 */ 860 861 static inline void hal_tx_comp_desc_sync(void *hw_desc, 862 struct hal_tx_desc_comp_s *comp, 863 bool read_status) 864 { 865 if (!read_status) 866 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_BASE_LEN); 867 else 868 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_LEN_BYTES); 869 } 870 871 /** 872 * hal_dump_comp_desc() - dump tx completion descriptor 873 * @hal_desc: hardware descriptor pointer 874 * 875 * This function will print tx completion descriptor 876 * 877 * Return: none 878 */ 879 static inline void hal_dump_comp_desc(void *hw_desc) 880 { 881 struct hal_tx_desc_comp_s *comp = 882 (struct hal_tx_desc_comp_s *)hw_desc; 883 uint32_t i; 884 885 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 886 "Current tx completion descriptor is"); 887 888 for (i = 0; i < HAL_TX_COMPLETION_DESC_LEN_DWORDS; i++) { 889 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 890 "DWORD[i] = 0x%x", comp->desc[i]); 891 } 892 } 893 894 /** 895 * hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor 896 * @hal_desc: Hardware (WBM) descriptor pointer 897 * @htt_desc: Software HTT descriptor pointer 898 * 899 * This function will read the HTT structure overlaid on WBM descriptor 900 * into a cached software descriptor 901 * 902 */ 903 static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc) 904 { 905 uint8_t *desc = hw_desc + HAL_TX_COMP_HTT_STATUS_OFFSET; 906 907 qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN); 908 } 909 910 /** 911 * hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG 912 * @hal_soc_hdl: Handle to HAL SoC structure 913 * @hal_srng: Handle to HAL SRNG structure 914 * 915 * Return: none 916 */ 917 static inline void hal_tx_init_data_ring(hal_soc_handle_t hal_soc_hdl, 918 hal_ring_handle_t hal_ring_hdl) 919 { 920 uint8_t *desc_addr; 921 struct hal_srng_params srng_params; 922 uint32_t desc_size; 923 uint32_t num_desc; 924 925 hal_get_srng_params(hal_soc_hdl, hal_ring_hdl, &srng_params); 926 927 desc_addr = (uint8_t *)srng_params.ring_base_vaddr; 928 desc_size = sizeof(struct tcl_data_cmd); 929 num_desc = srng_params.num_entries; 930 931 while (num_desc) { 932 HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, 933 desc_size); 934 desc_addr += (desc_size + sizeof(struct tlv_32_hdr)); 935 num_desc--; 936 } 937 } 938 939 /** 940 * hal_tx_desc_set_dscp_tid_table_id() - Sets DSCP to TID conversion table ID 941 * @hal_soc: Handle to HAL SoC structure 942 * @desc: Handle to Tx Descriptor 943 * @id: DSCP to tid conversion table to be used for this frame 944 * 945 * Return: void 946 */ 947 static inline 948 void hal_tx_desc_set_dscp_tid_table_id(hal_soc_handle_t hal_soc_hdl, 949 void *desc, uint8_t id) 950 { 951 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 952 953 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id(desc, id); 954 } 955 956 /** 957 * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table 958 * 959 * @soc: HAL SoC context 960 * @map: DSCP-TID mapping table 961 * @id: mapping table ID - 0,1 962 * 963 * Return: void 964 */ 965 static inline void hal_tx_set_dscp_tid_map(hal_soc_handle_t hal_soc_hdl, 966 uint8_t *map, uint8_t id) 967 { 968 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 969 970 hal_soc->ops->hal_tx_set_dscp_tid_map(hal_soc, map, id); 971 } 972 973 /** 974 * hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user 975 * 976 * @soc: HAL SoC context 977 * @map: DSCP-TID mapping table 978 * @id : MAP ID 979 * @dscp: DSCP_TID map index 980 * 981 * Return: void 982 */ 983 static inline 984 void hal_tx_update_dscp_tid(hal_soc_handle_t hal_soc_hdl, uint8_t tid, 985 uint8_t id, uint8_t dscp) 986 { 987 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 988 989 hal_soc->ops->hal_tx_update_dscp_tid(hal_soc, tid, id, dscp); 990 } 991 992 /** 993 * hal_tx_desc_set_lmac_id - Set the lmac_id value 994 * @desc: Handle to Tx Descriptor 995 * @lmac_id: mac Id to ast matching 996 * b00 – mac 0 997 * b01 – mac 1 998 * b10 – mac 2 999 * b11 – all macs (legacy HK way) 1000 * 1001 * Return: void 1002 */ 1003 static inline void hal_tx_desc_set_lmac_id(hal_soc_handle_t hal_soc_hdl, 1004 void *desc, uint8_t lmac_id) 1005 { 1006 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1007 1008 hal_soc->ops->hal_tx_desc_set_lmac_id(desc, lmac_id); 1009 } 1010 1011 /** 1012 * hal_tx_desc_set_search_type - Set the search type value 1013 * @desc: Handle to Tx Descriptor 1014 * @search_type: search type 1015 * 0 – Normal search 1016 * 1 – Index based address search 1017 * 2 – Index based flow search 1018 * 1019 * Return: void 1020 */ 1021 static inline void hal_tx_desc_set_search_type(hal_soc_handle_t hal_soc_hdl, 1022 void *desc, uint8_t search_type) 1023 { 1024 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1025 1026 hal_soc->ops->hal_tx_desc_set_search_type(desc, search_type); 1027 } 1028 1029 /** 1030 * hal_tx_desc_set_search_index - Set the search index value 1031 * @desc: Handle to Tx Descriptor 1032 * @search_index: The index that will be used for index based address or 1033 * flow search. The field is valid when 'search_type' is 1034 * 1 0r 2 1035 * 1036 * Return: void 1037 */ 1038 static inline void hal_tx_desc_set_search_index(hal_soc_handle_t hal_soc_hdl, 1039 void *desc, 1040 uint32_t search_index) 1041 { 1042 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1043 1044 hal_soc->ops->hal_tx_desc_set_search_index(desc, search_index); 1045 } 1046 1047 /** 1048 * hal_tx_desc_set_cache_set_num - Set the cache-set-num value 1049 * @desc: Handle to Tx Descriptor 1050 * @cache_num: Cache set number that should be used to cache the index 1051 * based search results, for address and flow search. 1052 * This value should be equal to LSB four bits of the hash value 1053 * of match data, in case of search index points to an entry 1054 * which may be used in content based search also. The value can 1055 * be anything when the entry pointed by search index will not be 1056 * used for content based search. 1057 * 1058 * Return: void 1059 */ 1060 static inline void hal_tx_desc_set_cache_set_num(hal_soc_handle_t hal_soc_hdl, 1061 void *desc, 1062 uint8_t cache_num) 1063 { 1064 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1065 1066 hal_soc->ops->hal_tx_desc_set_cache_set_num(desc, cache_num); 1067 } 1068 1069 /** 1070 * hal_tx_comp_get_status() - TQM Release reason 1071 * @hal_desc: completion ring Tx status 1072 * 1073 * This function will parse the WBM completion descriptor and populate in 1074 * HAL structure 1075 * 1076 * Return: none 1077 */ 1078 static inline void hal_tx_comp_get_status(void *desc, void *ts, 1079 hal_soc_handle_t hal_soc_hdl) 1080 { 1081 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1082 1083 hal_soc->ops->hal_tx_comp_get_status(desc, ts, hal_soc); 1084 } 1085 1086 1087 /** 1088 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 1089 * @desc: Handle to Tx Descriptor 1090 * @paddr: Physical Address 1091 * @pool_id: Return Buffer Manager ID 1092 * @desc_id: Descriptor ID 1093 * @type: 0 - Address points to a MSDU buffer 1094 * 1 - Address points to MSDU extension descriptor 1095 * 1096 * Return: void 1097 */ 1098 static inline 1099 void hal_tx_desc_set_buf_addr(hal_soc_handle_t hal_soc_hdl, void *desc, 1100 dma_addr_t paddr, 1101 uint8_t pool_id, uint32_t desc_id, 1102 uint8_t type) 1103 { 1104 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1105 1106 hal_soc->ops->hal_tx_desc_set_buf_addr(desc, paddr, pool_id, 1107 desc_id, type); 1108 1109 } 1110 1111 /** 1112 * hal_tx_set_pcp_tid_map_default() - Configure default PCP to TID map table 1113 * 1114 * @soc: HAL SoC context 1115 * @map: PCP-TID mapping table 1116 * 1117 * Return: void 1118 */ 1119 static inline void hal_tx_set_pcp_tid_map_default(hal_soc_handle_t hal_soc_hdl, 1120 uint8_t *map) 1121 { 1122 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1123 1124 hal_soc->ops->hal_tx_set_pcp_tid_map(hal_soc, map); 1125 } 1126 1127 /** 1128 * hal_tx_update_pcp_tid_map() - Update PCP to TID map table 1129 * 1130 * @soc: HAL SoC context 1131 * @pcp: pcp value 1132 * @tid: tid no 1133 * 1134 * Return: void 1135 */ 1136 static inline void hal_tx_update_pcp_tid_map(hal_soc_handle_t hal_soc_hdl, 1137 uint8_t pcp, uint8_t tid) 1138 { 1139 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1140 1141 hal_soc->ops->hal_tx_update_pcp_tid_map(hal_soc, tid, tid); 1142 } 1143 1144 /** 1145 * hal_tx_set_tidmap_prty() - Configure TIDmap priority 1146 * 1147 * @soc: HAL SoC context 1148 * @val: priority value 1149 * 1150 * Return: void 1151 */ 1152 static inline 1153 void hal_tx_set_tidmap_prty(hal_soc_handle_t hal_soc_hdl, uint8_t val) 1154 { 1155 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1156 1157 hal_soc->ops->hal_tx_set_tidmap_prty(hal_soc, val); 1158 } 1159 1160 /** 1161 * hal_get_wbm_internal_error() - wbm internal error 1162 * @hal_desc: completion ring descriptor pointer 1163 * 1164 * This function will return the type of pointer - buffer or descriptor 1165 * 1166 * Return: buffer type 1167 */ 1168 static inline 1169 uint8_t hal_get_wbm_internal_error(hal_soc_handle_t hal_soc_hdl, void *hal_desc) 1170 { 1171 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1172 1173 return hal_soc->ops->hal_get_wbm_internal_error(hal_desc); 1174 } 1175 1176 #endif /* HAL_TX_H */ 1177