1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #if !defined(HAL_TX_H) 21 #define HAL_TX_H 22 23 /*--------------------------------------------------------------------------- 24 Include files 25 ---------------------------------------------------------------------------*/ 26 #include "hal_api.h" 27 #include "wcss_version.h" 28 #include "hal_hw_headers.h" 29 #include "hal_tx_hw_defines.h" 30 31 #define HAL_WBM_RELEASE_RING_2_BUFFER_TYPE 0 32 #define HAL_WBM_RELEASE_RING_2_DESC_TYPE 1 33 34 #define HAL_TX_DESC_TLV_TAG_OFFSET 1 35 #define HAL_TX_DESC_TLV_LEN_OFFSET 10 36 37 /*--------------------------------------------------------------------------- 38 Preprocessor definitions and constants 39 ---------------------------------------------------------------------------*/ 40 #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET 41 42 #define HAL_TX_LSB(block, field) block ## _ ## field ## _LSB 43 44 #define HAL_TX_MASK(block, field) block ## _ ## field ## _MASK 45 46 #define HAL_TX_DESC_OFFSET(desc, block, field) \ 47 (((uint8_t *)desc) + HAL_OFFSET(block, field)) 48 49 #define HAL_SET_FLD(desc, block , field) \ 50 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field))) 51 52 #define HAL_SET_FLD_OFFSET(desc, block , field, offset) \ 53 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field) + (offset))) 54 55 #define HAL_SET_FLD_64(desc, block, field) \ 56 (*(uint64_t *)((uint8_t *)desc + HAL_OFFSET(block, field))) 57 58 #define HAL_SET_FLD_OFFSET_64(desc, block, field, offset) \ 59 (*(uint64_t *)((uint8_t *)desc + HAL_OFFSET(block, field) + (offset))) 60 61 #define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \ 62 do { \ 63 uint32_t temp = 0; \ 64 temp |= (tag << HAL_TX_DESC_TLV_TAG_OFFSET); \ 65 temp |= (len << HAL_TX_DESC_TLV_LEN_OFFSET); \ 66 (*(uint32_t *)desc) = temp; \ 67 } while (0) 68 69 #define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E 70 #define HAL_TX_TCL_CMD_TAG WIFITCL_GSE_CMD_E 71 72 #define HAL_TX_SM(block, field, value) \ 73 ((value << (block ## _ ## field ## _LSB)) & \ 74 (block ## _ ## field ## _MASK)) 75 76 #define HAL_TX_MS(block, field, value) \ 77 (((value) & (block ## _ ## field ## _MASK)) >> \ 78 (block ## _ ## field ## _LSB)) 79 80 #define HAL_TX_DESC_GET(desc, block, field) \ 81 HAL_TX_MS(block, field, HAL_SET_FLD(desc, block, field)) 82 83 #define HAL_TX_DESC_OFFSET_GET(desc, block, field, offset) \ 84 HAL_TX_MS(block, field, HAL_SET_FLD_OFFSET(desc, block, field, offset)) 85 86 #define HAL_TX_DESC_SUBBLOCK_GET(desc, block, sub, field) \ 87 HAL_TX_MS(sub, field, HAL_SET_FLD(desc, block, sub)) 88 89 #define HAL_TX_DESC_GET_64(desc, block, field) \ 90 HAL_TX_MS(block, field, HAL_SET_FLD_64(desc, block, field)) 91 92 #define HAL_TX_DESC_OFFSET_GET_64(desc, block, field, offset) \ 93 HAL_TX_MS(block, field, HAL_SET_FLD_OFFSET_64(desc, block, field,\ 94 offset)) 95 96 #define HAL_TX_DESC_SUBBLOCK_GET_64(desc, block, sub, field) \ 97 HAL_TX_MS(sub, field, HAL_SET_FLD_64(desc, block, sub)) 98 99 #define HAL_TX_BUF_TYPE_BUFFER 0 100 #define HAL_TX_BUF_TYPE_EXT_DESC 1 101 102 #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 103 104 #define HAL_TX_DESC_LEN_DWORDS (NUM_OF_DWORDS_TCL_DATA_CMD) 105 #define HAL_TX_DESC_LEN_BYTES (NUM_OF_DWORDS_TCL_DATA_CMD * 4) 106 #define HAL_TX_EXTENSION_DESC_LEN_DWORDS (NUM_OF_DWORDS_TX_MSDU_EXTENSION) 107 #define HAL_TX_EXTENSION_DESC_LEN_BYTES (NUM_OF_DWORDS_TX_MSDU_EXTENSION * 4) 108 109 #define NUM_OF_DWORDS_WBM_RELEASE_RING 8 110 111 #define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 112 #define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4) 113 #define HAL_TX_BITS_PER_TID 3 114 #define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1) 115 #define HAL_TX_NUM_DSCP_PER_REGISTER 10 116 #define HAL_MAX_HW_DSCP_TID_MAPS 2 117 #define HAL_MAX_HW_DSCP_TID_MAPS_11AX 32 118 119 #define HAL_MAX_HW_DSCP_TID_V2_MAPS 48 120 #define HAL_MAX_HW_DSCP_TID_V2_MAPS_5332 24 121 #define HTT_META_HEADER_LEN_BYTES 64 122 #define HAL_TX_EXT_DESC_WITH_META_DATA \ 123 (HTT_META_HEADER_LEN_BYTES + HAL_TX_EXTENSION_DESC_LEN_BYTES) 124 125 #define HAL_TX_NUM_PCP_PER_REGISTER 8 126 127 /* Length of WBM release ring without the status words */ 128 #define HAL_TX_COMPLETION_DESC_BASE_LEN 12 129 130 #define HAL_TX_COMP_RELEASE_SOURCE_TQM 0 131 #define HAL_TX_COMP_RELEASE_SOURCE_REO 2 132 #define HAL_TX_COMP_RELEASE_SOURCE_FW 3 133 134 /* Define a place-holder release reason for FW */ 135 #define HAL_TX_COMP_RELEASE_REASON_FW 99 136 137 /* 138 * Offset of HTT Tx Descriptor in WBM Completion 139 * HTT Tx Desc structure is passed from firmware to host overlaid 140 * on wbm_release_ring DWORDs 2,3 ,4 and 5for software based completions 141 * (Exception frames and TQM bypass frames) 142 */ 143 #define HAL_TX_COMP_HTT_STATUS_OFFSET 8 144 #ifdef CONFIG_BERYLLIUM 145 #define HAL_TX_COMP_HTT_STATUS_LEN 20 146 #else 147 #define HAL_TX_COMP_HTT_STATUS_LEN 16 148 #endif 149 150 #define HAL_TX_BUF_TYPE_BUFFER 0 151 #define HAL_TX_BUF_TYPE_EXT_DESC 1 152 153 #define HAL_TX_EXT_DESC_BUF_OFFSET TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 154 #define HAL_TX_EXT_BUF_LOW_MASK TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 155 #define HAL_TX_EXT_BUF_HI_MASK TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 156 #define HAL_TX_EXT_BUF_LEN_MASK TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 157 #define HAL_TX_EXT_BUF_LEN_LSB TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 158 #define HAL_TX_EXT_BUF_WD_SIZE 2 159 160 #define HAL_TX_DESC_ADDRX_EN 0x1 161 #define HAL_TX_DESC_ADDRY_EN 0x2 162 #define HAL_TX_DESC_DEFAULT_LMAC_ID 0x3 163 164 #define HAL_TX_ADDR_SEARCH_DEFAULT 0x0 165 #define HAL_TX_ADDR_INDEX_SEARCH 0x1 166 #define HAL_TX_FLOW_INDEX_SEARCH 0x2 167 168 #define HAL_WBM2SW_RELEASE_SRC_GET(wbm_desc)(((*(((uint32_t *)wbm_desc) + \ 169 (HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 170 HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_MASK) >> \ 171 HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_LSB) 172 173 #define HAL_WBM_SW0_BM_ID(sw0_bm_id) (sw0_bm_id) 174 #define HAL_WBM_SW1_BM_ID(sw0_bm_id) ((sw0_bm_id) + 1) 175 #define HAL_WBM_SW2_BM_ID(sw0_bm_id) ((sw0_bm_id) + 2) 176 #define HAL_WBM_SW3_BM_ID(sw0_bm_id) ((sw0_bm_id) + 3) 177 #define HAL_WBM_SW4_BM_ID(sw0_bm_id) ((sw0_bm_id) + 4) 178 #define HAL_WBM_SW5_BM_ID(sw0_bm_id) ((sw0_bm_id) + 5) 179 #define HAL_WBM_SW6_BM_ID(sw0_bm_id) ((sw0_bm_id) + 6) 180 181 /*--------------------------------------------------------------------------- 182 Structures 183 ---------------------------------------------------------------------------*/ 184 /** 185 * struct hal_tx_completion_status - HAL Tx completion descriptor contents 186 * @status: frame acked/failed 187 * @release_src: release source = TQM/FW 188 * @ack_frame_rssi: RSSI of the received ACK or BA frame 189 * @first_msdu: Indicates this MSDU is the first MSDU in AMSDU 190 * @last_msdu: Indicates this MSDU is the last MSDU in AMSDU 191 * @msdu_part_of_amsdu : Indicates this MSDU was part of an A-MSDU in MPDU 192 * @bw: Indicates the BW of the upcoming transmission - 193 * <enum 0 transmit_bw_20_MHz> 194 * <enum 1 transmit_bw_40_MHz> 195 * <enum 2 transmit_bw_80_MHz> 196 * <enum 3 transmit_bw_160_MHz> 197 * @pkt_type: Transmit Packet Type 198 * @stbc: When set, STBC transmission rate was used 199 * @ldpc: When set, use LDPC transmission rates 200 * @sgi: <enum 0 0_8_us_sgi > Legacy normal GI 201 * <enum 1 0_4_us_sgi > Legacy short GI 202 * <enum 2 1_6_us_sgi > HE related GI 203 * <enum 3 3_2_us_sgi > HE 204 * @mcs: Transmit MCS Rate 205 * @ofdma: Set when the transmission was an OFDMA transmission 206 * @tones_in_ru: The number of tones in the RU used. 207 * @tsf: Lower 32 bits of the TSF 208 * @ppdu_id: TSF, snapshot of this value when transmission of the 209 * PPDU containing the frame finished. 210 * @transmit_cnt: Number of times this frame has been transmitted 211 * @tid: TID of the flow or MPDU queue 212 * @peer_id: Peer ID of the flow or MPDU queue 213 * @buffer_timestamp: Frame system entrance timestamp in units of 1024 214 * microseconds 215 */ 216 struct hal_tx_completion_status { 217 uint8_t status; 218 uint8_t release_src; 219 uint8_t ack_frame_rssi; 220 uint8_t first_msdu:1, 221 last_msdu:1, 222 msdu_part_of_amsdu:1; 223 uint32_t bw:2, 224 pkt_type:4, 225 stbc:1, 226 ldpc:1, 227 sgi:2, 228 mcs:4, 229 ofdma:1, 230 tones_in_ru:12, 231 valid:1; 232 uint32_t tsf; 233 uint32_t ppdu_id; 234 uint8_t transmit_cnt; 235 uint8_t tid; 236 uint16_t peer_id; 237 #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY) 238 uint32_t buffer_timestamp:19; 239 #endif 240 }; 241 242 /** 243 * struct hal_tx_desc_comp_s - hal tx completion descriptor contents 244 * @desc: Transmit status information from descriptor 245 */ 246 struct hal_tx_desc_comp_s { 247 uint32_t desc[HAL_TX_COMPLETION_DESC_LEN_DWORDS]; 248 }; 249 250 /* 251 * enum hal_tx_encrypt_type - Type of decrypt cipher used (valid only for RAW) 252 * @HAL_TX_ENCRYPT_TYPE_WEP_40: WEP 40-bit 253 * @HAL_TX_ENCRYPT_TYPE_WEP_10: WEP 10-bit 254 * @HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC: TKIP without MIC 255 * @HAL_TX_ENCRYPT_TYPE_WEP_128: WEP_128 256 * @HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC: TKIP_WITH_MIC 257 * @HAL_TX_ENCRYPT_TYPE_WAPI: WAPI 258 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_128: AES_CCMP_128 259 * @HAL_TX_ENCRYPT_TYPE_NO_CIPHER: NO CIPHER 260 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_256: AES_CCMP_256 261 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_128: AES_GCMP_128 262 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_256: AES_GCMP_256 263 * @HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4: WAPI GCM SM4 264 */ 265 enum hal_tx_encrypt_type { 266 HAL_TX_ENCRYPT_TYPE_WEP_40 = 0, 267 HAL_TX_ENCRYPT_TYPE_WEP_104 = 1 , 268 HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC = 2, 269 HAL_TX_ENCRYPT_TYPE_WEP_128 = 3, 270 HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC = 4, 271 HAL_TX_ENCRYPT_TYPE_WAPI = 5, 272 HAL_TX_ENCRYPT_TYPE_AES_CCMP_128 = 6, 273 HAL_TX_ENCRYPT_TYPE_NO_CIPHER = 7, 274 HAL_TX_ENCRYPT_TYPE_AES_CCMP_256 = 8, 275 HAL_TX_ENCRYPT_TYPE_AES_GCMP_128 = 9, 276 HAL_TX_ENCRYPT_TYPE_AES_GCMP_256 = 10, 277 HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4 = 11, 278 }; 279 280 /* 281 * enum hal_tx_encap_type - Encapsulation type that HW will perform 282 * @HAL_TX_ENCAP_TYPE_RAW: Raw Packet Type 283 * @HAL_TX_ENCAP_TYPE_NWIFI: Native WiFi Type 284 * @HAL_TX_ENCAP_TYPE_ETHERNET: Ethernet 285 * @HAL_TX_ENCAP_TYPE_802_3: 802.3 Frame 286 */ 287 enum hal_tx_encap_type { 288 HAL_TX_ENCAP_TYPE_RAW = 0, 289 HAL_TX_ENCAP_TYPE_NWIFI = 1, 290 HAL_TX_ENCAP_TYPE_ETHERNET = 2, 291 HAL_TX_ENCAP_TYPE_802_3 = 3, 292 }; 293 294 /** 295 * enum hal_tx_tqm_release_reason - TQM Release reason codes 296 * 297 * @HAL_TX_TQM_RR_FRAME_ACKED : ACK of BA for it was received 298 * @HAL_TX_TQM_RR_REM_CMD_REM : Remove cmd of type “Remove_mpdus” initiated 299 * by SW 300 * @HAL_TX_TQM_RR_REM_CMD_TX : Remove command of type Remove_transmitted_mpdus 301 * initiated by SW 302 * @HAL_TX_TQM_RR_REM_CMD_NOTX : Remove cmd of type Remove_untransmitted_mpdus 303 * initiated by SW 304 * @HAL_TX_TQM_RR_REM_CMD_AGED : Remove command of type “Remove_aged_mpdus” or 305 * “Remove_aged_msdus” initiated by SW 306 * @HAL_TX_TQM_RR_FW_REASON1 : Remove command where fw indicated that 307 * remove reason is fw_reason1 308 * @HAL_TX_TQM_RR_FW_REASON2 : Remove command where fw indicated that 309 * remove reason is fw_reason2 310 * @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that 311 * remove reason is fw_reason3 312 * @HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE : Remove command where fw indicated that 313 * remove reason is remove disable queue 314 * @HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING: Remove command from fw to remove 315 * all mpdu until 1st non-match 316 * @HAL_TX_TQM_RR_DROP_THRESHOLD: Dropped due to drop threshold criteria 317 * @HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE: Dropped due to link desc not available 318 * @HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU: Dropped due drop bit set or null flow 319 * @HAL_TX_TQM_RR_MULTICAST_DROP: Dropped due mcast drop set for VDEV 320 * @HAL_TX_TQM_RR_VDEV_MISMATCH_DROP: Dropped due to being set with 321 * 'TCL_drop_reason' 322 * 323 */ 324 enum hal_tx_tqm_release_reason { 325 HAL_TX_TQM_RR_FRAME_ACKED, 326 HAL_TX_TQM_RR_REM_CMD_REM, 327 HAL_TX_TQM_RR_REM_CMD_TX, 328 HAL_TX_TQM_RR_REM_CMD_NOTX, 329 HAL_TX_TQM_RR_REM_CMD_AGED, 330 HAL_TX_TQM_RR_FW_REASON1, 331 HAL_TX_TQM_RR_FW_REASON2, 332 HAL_TX_TQM_RR_FW_REASON3, 333 HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE, 334 HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING, 335 HAL_TX_TQM_RR_DROP_THRESHOLD, 336 HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE, 337 HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU, 338 HAL_TX_TQM_RR_MULTICAST_DROP, 339 HAL_TX_TQM_RR_VDEV_MISMATCH_DROP, 340 }; 341 342 /* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports 343 * @HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT: Default DSCP-TID mapping table 344 * @HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE: DSCP-TID map override table 345 */ 346 enum hal_tx_dscp_tid_table_id { 347 HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT, 348 HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE, 349 }; 350 351 /*--------------------------------------------------------------------------- 352 Function declarations and documentation 353 ---------------------------------------------------------------------------*/ 354 355 /*--------------------------------------------------------------------------- 356 Tx MSDU Extension Descriptor accessor APIs 357 ---------------------------------------------------------------------------*/ 358 /** 359 * hal_tx_ext_desc_set_tso_enable() - Set TSO Enable Flag 360 * @desc: Handle to Tx MSDU Extension Descriptor 361 * @tso_en: bool value set to true if TSO is enabled 362 * 363 * Return: none 364 */ 365 static inline void hal_tx_ext_desc_set_tso_enable(void *desc, 366 uint8_t tso_en) 367 { 368 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE) |= 369 HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TSO_ENABLE, tso_en); 370 } 371 372 /** 373 * hal_tx_ext_desc_set_tso_flags() - Set TSO Flags 374 * @desc: Handle to Tx MSDU Extension Descriptor 375 * @flags: 32-bit word with all TSO flags consolidated 376 * 377 * Return: none 378 */ 379 static inline void hal_tx_ext_desc_set_tso_flags(void *desc, 380 uint32_t tso_flags) 381 { 382 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE, 0) = 383 tso_flags; 384 } 385 386 /** 387 * hal_tx_ext_desc_set_tcp_flags() - Enable HW Checksum offload 388 * @desc: Handle to Tx MSDU Extension Descriptor 389 * @tcp_flags: TCP flags {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 390 * @mask: TCP flag mask. Tcp_flag is inserted into the header 391 * based on the mask, if tso is enabled 392 * 393 * Return: none 394 */ 395 static inline void hal_tx_ext_desc_set_tcp_flags(void *desc, 396 uint16_t tcp_flags, 397 uint16_t mask) 398 { 399 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_FLAG) |= 400 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG, tcp_flags)) | 401 (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG_MASK, mask))); 402 } 403 404 /** 405 * hal_tx_ext_desc_set_msdu_length() - Set L2 and IP Lengths 406 * @desc: Handle to Tx MSDU Extension Descriptor 407 * @l2_len: L2 length for the msdu, if tso is enabled 408 * @ip_len: IP length for the msdu, if tso is enabled 409 * 410 * Return: none 411 */ 412 static inline void hal_tx_ext_desc_set_msdu_length(void *desc, 413 uint16_t l2_len, 414 uint16_t ip_len) 415 { 416 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, L2_LENGTH) |= 417 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, L2_LENGTH, l2_len)) | 418 (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_LENGTH, ip_len))); 419 } 420 421 /** 422 * hal_tx_ext_desc_set_tcp_seq() - Set TCP Sequence number 423 * @desc: Handle to Tx MSDU Extension Descriptor 424 * @seq_num: Tcp_seq_number for the msdu, if tso is enabled 425 * 426 * Return: none 427 */ 428 static inline void hal_tx_ext_desc_set_tcp_seq(void *desc, 429 uint32_t seq_num) 430 { 431 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER) |= 432 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER, seq_num))); 433 } 434 435 436 /** 437 * hal_tx_ext_desc_set_ip_id() - Set IP Identification field 438 * @desc: Handle to Tx MSDU Extension Descriptor 439 * @id: IP Id field for the msdu, if tso is enabled 440 * 441 * Return: none 442 */ 443 static inline void hal_tx_ext_desc_set_ip_id(void *desc, 444 uint16_t id) 445 { 446 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION) |= 447 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION, id))); 448 } 449 /** 450 * hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment 451 * @desc: Handle to Tx MSDU Extension Descriptor 452 * @frag_num: Fragment number (value can be 0 to 5) 453 * @paddr_lo: Lower 32-bit of Buffer Physical address 454 * @paddr_hi: Upper 32-bit of Buffer Physical address 455 * @length: Buffer Length 456 * 457 * Return: none 458 */ 459 static inline void hal_tx_ext_desc_set_buffer(void *desc, 460 uint8_t frag_num, 461 uint32_t paddr_lo, 462 uint16_t paddr_hi, 463 uint16_t length) 464 { 465 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, 466 (frag_num << 3)) |= 467 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo))); 468 469 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32, 470 (frag_num << 3)) |= 471 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32, 472 (paddr_hi)))); 473 474 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN, 475 (frag_num << 3)) |= 476 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length))); 477 } 478 479 /** 480 * hal_tx_ext_desc_get_frag_info() - Get the frag_num'th frag iova and len 481 * @desc: Handle to Tx MSDU Extension Descriptor 482 * @frag_num: fragment number (value can be 0 to 5) 483 * @iova: fragment dma address 484 * @len: fragment Length 485 * 486 * Return: None 487 */ 488 static inline void hal_tx_ext_desc_get_frag_info(void *desc, uint8_t frag_num, 489 qdf_dma_addr_t *iova, 490 uint32_t *len) 491 { 492 uint64_t iova_hi; 493 494 *iova = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, 495 BUF0_PTR_31_0, (frag_num << 3)); 496 497 iova_hi = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, 498 BUF0_PTR_39_32, (frag_num << 3)); 499 *iova |= (iova_hi << 32); 500 501 *len = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN, 502 (frag_num << 3)); 503 } 504 505 /** 506 * hal_tx_ext_desc_set_buffer0_param() - Set Buffer 0 Pointer and Length 507 * @desc: Handle to Tx MSDU Extension Descriptor 508 * @paddr_lo: Lower 32-bit of Buffer Physical address 509 * @paddr_hi: Upper 32-bit of Buffer Physical address 510 * @length: Buffer 0 Length 511 * 512 * Return: none 513 */ 514 static inline void hal_tx_ext_desc_set_buffer0_param(void *desc, 515 uint32_t paddr_lo, 516 uint16_t paddr_hi, 517 uint16_t length) 518 { 519 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0) |= 520 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo))); 521 522 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32) |= 523 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, 524 BUF0_PTR_39_32, paddr_hi))); 525 526 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN) |= 527 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length))); 528 } 529 530 /** 531 * hal_tx_ext_desc_set_buffer1_param() - Set Buffer 1 Pointer and Length 532 * @desc: Handle to Tx MSDU Extension Descriptor 533 * @paddr_lo: Lower 32-bit of Buffer Physical address 534 * @paddr_hi: Upper 32-bit of Buffer Physical address 535 * @length: Buffer 1 Length 536 * 537 * Return: none 538 */ 539 static inline void hal_tx_ext_desc_set_buffer1_param(void *desc, 540 uint32_t paddr_lo, 541 uint16_t paddr_hi, 542 uint16_t length) 543 { 544 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0) |= 545 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0, paddr_lo))); 546 547 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_39_32) |= 548 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, 549 BUF1_PTR_39_32, paddr_hi))); 550 551 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_LEN) |= 552 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_LEN, length))); 553 } 554 555 /** 556 * hal_tx_ext_desc_set_buffer2_param() - Set Buffer 2 Pointer and Length 557 * @desc: Handle to Tx MSDU Extension Descriptor 558 * @paddr_lo: Lower 32-bit of Buffer Physical address 559 * @paddr_hi: Upper 32-bit of Buffer Physical address 560 * @length: Buffer 2 Length 561 * 562 * Return: none 563 */ 564 static inline void hal_tx_ext_desc_set_buffer2_param(void *desc, 565 uint32_t paddr_lo, 566 uint16_t paddr_hi, 567 uint16_t length) 568 { 569 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0) |= 570 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0, 571 paddr_lo))); 572 573 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32) |= 574 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32, 575 paddr_hi))); 576 577 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_LEN) |= 578 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_LEN, length))); 579 } 580 581 /** 582 * hal_tx_ext_desc_sync - Commit the descriptor to Hardware 583 * @desc_cached: Cached descriptor that software maintains 584 * @hw_desc: Hardware descriptor to be updated 585 * 586 * Return: none 587 */ 588 static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached, 589 uint8_t *hw_desc) 590 { 591 qdf_mem_copy(&hw_desc[0], &desc_cached[0], 592 HAL_TX_EXT_DESC_WITH_META_DATA); 593 } 594 595 /** 596 * hal_tx_ext_desc_get_tso_enable() - Set TSO Enable Flag 597 * @hal_tx_ext_desc: Handle to Tx MSDU Extension Descriptor 598 * 599 * Return: tso_enable value in the descriptor 600 */ 601 static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc) 602 { 603 uint32_t *desc = (uint32_t *) hal_tx_ext_desc; 604 return (*desc & HAL_TX_MSDU_EXTENSION_TSO_ENABLE_MASK) >> 605 HAL_TX_MSDU_EXTENSION_TSO_ENABLE_LSB; 606 } 607 608 /*--------------------------------------------------------------------------- 609 WBM Descriptor accessor APIs for Tx completions 610 ---------------------------------------------------------------------------*/ 611 /** 612 * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type 613 * @hal_desc: completion ring descriptor pointer 614 * 615 * This function will return the type of pointer - buffer or descriptor 616 * 617 * Return: buffer type 618 */ 619 static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc) 620 { 621 uint32_t comp_desc = 622 *(uint32_t *) (((uint8_t *) hal_desc) + 623 HAL_TX_COMP_BUFFER_OR_DESC_TYPE_OFFSET); 624 625 return (comp_desc & HAL_TX_COMP_BUFFER_OR_DESC_TYPE_MASK) >> 626 HAL_TX_COMP_BUFFER_OR_DESC_TYPE_LSB; 627 } 628 629 #ifdef QCA_WIFI_KIWI 630 /** 631 * hal_tx_comp_get_buffer_source() - Get buffer release source value 632 * @hal_desc: completion ring descriptor pointer 633 * 634 * This function will get buffer release source from Tx completion descriptor 635 * 636 * Return: buffer release source 637 */ 638 static inline uint32_t 639 hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl, 640 void *hal_desc) 641 { 642 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 643 644 return hal_soc->ops->hal_tx_comp_get_buffer_source(hal_desc); 645 } 646 #else 647 static inline uint32_t 648 hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl, 649 void *hal_desc) 650 { 651 return HAL_WBM2SW_RELEASE_SRC_GET(hal_desc); 652 } 653 #endif 654 655 /** 656 * hal_tx_comp_get_release_reason() - TQM Release reason 657 * @hal_desc: completion ring descriptor pointer 658 * 659 * This function will return the type of pointer - buffer or descriptor 660 * 661 * Return: buffer type 662 */ 663 static inline 664 uint8_t hal_tx_comp_get_release_reason(void *hal_desc, 665 hal_soc_handle_t hal_soc_hdl) 666 { 667 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 668 669 return hal_soc->ops->hal_tx_comp_get_release_reason(hal_desc); 670 } 671 672 /** 673 * hal_tx_comp_get_peer_id() - Get peer_id value() 674 * @hal_desc: completion ring descriptor pointer 675 * 676 * This function will get peer_id value from Tx completion descriptor 677 * 678 * Return: buffer release source 679 */ 680 static inline uint16_t hal_tx_comp_get_peer_id(void *hal_desc) 681 { 682 uint32_t comp_desc = 683 *(uint32_t *)(((uint8_t *)hal_desc) + 684 HAL_TX_COMP_SW_PEER_ID_OFFSET); 685 686 return (comp_desc & HAL_TX_COMP_SW_PEER_ID_MASK) >> 687 HAL_TX_COMP_SW_PEER_ID_LSB; 688 } 689 690 /** 691 * hal_tx_comp_get_tx_status() - Get tx transmission status() 692 * @hal_desc: completion ring descriptor pointer 693 * 694 * This function will get transmit status value from Tx completion descriptor 695 * 696 * Return: buffer release source 697 */ 698 static inline uint8_t hal_tx_comp_get_tx_status(void *hal_desc) 699 { 700 uint32_t comp_desc = 701 *(uint32_t *)(((uint8_t *)hal_desc) + 702 HAL_TX_COMP_TQM_RELEASE_REASON_OFFSET); 703 704 return (comp_desc & HAL_TX_COMP_TQM_RELEASE_REASON_MASK) >> 705 HAL_TX_COMP_TQM_RELEASE_REASON_LSB; 706 } 707 708 /** 709 * hal_tx_comp_desc_sync() - collect hardware descriptor contents 710 * @hal_desc: hardware descriptor pointer 711 * @comp: software descriptor pointer 712 * @read_status: 0 - Do not read status words from descriptors 713 * 1 - Enable reading of status words from descriptor 714 * 715 * This function will collect hardware release ring element contents and 716 * translate to software descriptor content 717 * 718 * Return: none 719 */ 720 721 static inline void hal_tx_comp_desc_sync(void *hw_desc, 722 struct hal_tx_desc_comp_s *comp, 723 bool read_status) 724 { 725 if (!read_status) 726 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_BASE_LEN); 727 else 728 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_LEN_BYTES); 729 } 730 731 /** 732 * hal_dump_comp_desc() - dump tx completion descriptor 733 * @hal_desc: hardware descriptor pointer 734 * 735 * This function will print tx completion descriptor 736 * 737 * Return: none 738 */ 739 static inline void hal_dump_comp_desc(void *hw_desc) 740 { 741 struct hal_tx_desc_comp_s *comp = 742 (struct hal_tx_desc_comp_s *)hw_desc; 743 uint32_t i; 744 745 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 746 "Current tx completion descriptor is"); 747 748 for (i = 0; i < HAL_TX_COMPLETION_DESC_LEN_DWORDS; i++) { 749 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 750 "DWORD[i] = 0x%x", comp->desc[i]); 751 } 752 } 753 754 /** 755 * hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor 756 * @hal_desc: Hardware (WBM) descriptor pointer 757 * @htt_desc: Software HTT descriptor pointer 758 * 759 * This function will read the HTT structure overlaid on WBM descriptor 760 * into a cached software descriptor 761 * 762 */ 763 static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc) 764 { 765 uint8_t *desc = hw_desc + HAL_TX_COMP_HTT_STATUS_OFFSET; 766 767 qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN); 768 } 769 770 /** 771 * hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG 772 * @hal_soc_hdl: Handle to HAL SoC structure 773 * @hal_srng: Handle to HAL SRNG structure 774 * 775 * Return: none 776 */ 777 static inline void hal_tx_init_data_ring(hal_soc_handle_t hal_soc_hdl, 778 hal_ring_handle_t hal_ring_hdl) 779 { 780 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 781 782 hal_soc->ops->hal_tx_init_data_ring(hal_soc_hdl, hal_ring_hdl); 783 } 784 785 /** 786 * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table 787 * 788 * @soc: HAL SoC context 789 * @map: DSCP-TID mapping table 790 * @id: mapping table ID - 0,1 791 * 792 * Return: void 793 */ 794 static inline void hal_tx_set_dscp_tid_map(hal_soc_handle_t hal_soc_hdl, 795 uint8_t *map, uint8_t id) 796 { 797 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 798 799 hal_soc->ops->hal_tx_set_dscp_tid_map(hal_soc, map, id); 800 } 801 802 /** 803 * hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user 804 * 805 * @soc: HAL SoC context 806 * @map: DSCP-TID mapping table 807 * @id : MAP ID 808 * @dscp: DSCP_TID map index 809 * 810 * Return: void 811 */ 812 static inline 813 void hal_tx_update_dscp_tid(hal_soc_handle_t hal_soc_hdl, uint8_t tid, 814 uint8_t id, uint8_t dscp) 815 { 816 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 817 818 hal_soc->ops->hal_tx_update_dscp_tid(hal_soc, tid, id, dscp); 819 } 820 821 /** 822 * hal_tx_comp_get_status() - TQM Release reason 823 * @hal_desc: completion ring Tx status 824 * 825 * This function will parse the WBM completion descriptor and populate in 826 * HAL structure 827 * 828 * Return: none 829 */ 830 static inline void hal_tx_comp_get_status(void *desc, void *ts, 831 hal_soc_handle_t hal_soc_hdl) 832 { 833 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 834 835 hal_soc->ops->hal_tx_comp_get_status(desc, ts, hal_soc); 836 } 837 838 /** 839 * hal_tx_set_pcp_tid_map_default() - Configure default PCP to TID map table 840 * 841 * @soc: HAL SoC context 842 * @map: PCP-TID mapping table 843 * 844 * Return: void 845 */ 846 static inline void hal_tx_set_pcp_tid_map_default(hal_soc_handle_t hal_soc_hdl, 847 uint8_t *map) 848 { 849 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 850 851 hal_soc->ops->hal_tx_set_pcp_tid_map(hal_soc, map); 852 } 853 854 /** 855 * hal_tx_update_pcp_tid_map() - Update PCP to TID map table 856 * 857 * @soc: HAL SoC context 858 * @pcp: pcp value 859 * @tid: tid no 860 * 861 * Return: void 862 */ 863 static inline void hal_tx_update_pcp_tid_map(hal_soc_handle_t hal_soc_hdl, 864 uint8_t pcp, uint8_t tid) 865 { 866 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 867 868 hal_soc->ops->hal_tx_update_pcp_tid_map(hal_soc, pcp, tid); 869 } 870 871 /** 872 * hal_tx_set_tidmap_prty() - Configure TIDmap priority 873 * 874 * @soc: HAL SoC context 875 * @val: priority value 876 * 877 * Return: void 878 */ 879 static inline 880 void hal_tx_set_tidmap_prty(hal_soc_handle_t hal_soc_hdl, uint8_t val) 881 { 882 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 883 884 hal_soc->ops->hal_tx_set_tidmap_prty(hal_soc, val); 885 } 886 887 /** 888 * hal_get_wbm_internal_error() - wbm internal error 889 * @hal_desc: completion ring descriptor pointer 890 * 891 * This function will return the type of pointer - buffer or descriptor 892 * 893 * Return: buffer type 894 */ 895 static inline 896 uint8_t hal_get_wbm_internal_error(hal_soc_handle_t hal_soc_hdl, void *hal_desc) 897 { 898 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 899 900 return hal_soc->ops->hal_get_wbm_internal_error(hal_desc); 901 } 902 #endif /* HAL_TX_H */ 903