1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #if !defined(HAL_TX_H) 21 #define HAL_TX_H 22 23 /*--------------------------------------------------------------------------- 24 Include files 25 ---------------------------------------------------------------------------*/ 26 #include "hal_api.h" 27 #include "wcss_version.h" 28 #include "hal_hw_headers.h" 29 #include "hal_tx_hw_defines.h" 30 31 #define HAL_WBM_RELEASE_RING_2_BUFFER_TYPE 0 32 #define HAL_WBM_RELEASE_RING_2_DESC_TYPE 1 33 34 #define HAL_TX_DESC_TLV_TAG_OFFSET 1 35 #define HAL_TX_DESC_TLV_LEN_OFFSET 10 36 37 /*--------------------------------------------------------------------------- 38 Preprocessor definitions and constants 39 ---------------------------------------------------------------------------*/ 40 #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET 41 42 #define HAL_TX_LSB(block, field) block ## _ ## field ## _LSB 43 44 #define HAL_TX_MASK(block, field) block ## _ ## field ## _MASK 45 46 #define HAL_TX_DESC_OFFSET(desc, block, field) \ 47 (((uint8_t *)desc) + HAL_OFFSET(block, field)) 48 49 #define HAL_SET_FLD(desc, block , field) \ 50 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field))) 51 52 #define HAL_SET_FLD_OFFSET(desc, block , field, offset) \ 53 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field) + (offset))) 54 55 #define HAL_SET_FLD_64(desc, block, field) \ 56 (*(uint64_t *)((uint8_t *)desc + HAL_OFFSET(block, field))) 57 58 #define HAL_SET_FLD_OFFSET_64(desc, block, field, offset) \ 59 (*(uint64_t *)((uint8_t *)desc + HAL_OFFSET(block, field) + (offset))) 60 61 #define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \ 62 do { \ 63 uint32_t temp = 0; \ 64 temp |= (tag << HAL_TX_DESC_TLV_TAG_OFFSET); \ 65 temp |= (len << HAL_TX_DESC_TLV_LEN_OFFSET); \ 66 (*(uint32_t *)desc) = temp; \ 67 } while (0) 68 69 #define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E 70 #define HAL_TX_TCL_CMD_TAG WIFITCL_GSE_CMD_E 71 72 #define HAL_TX_SM(block, field, value) \ 73 ((value << (block ## _ ## field ## _LSB)) & \ 74 (block ## _ ## field ## _MASK)) 75 76 #define HAL_TX_MS(block, field, value) \ 77 (((value) & (block ## _ ## field ## _MASK)) >> \ 78 (block ## _ ## field ## _LSB)) 79 80 #define HAL_TX_DESC_GET(desc, block, field) \ 81 HAL_TX_MS(block, field, HAL_SET_FLD(desc, block, field)) 82 83 #define HAL_TX_DESC_OFFSET_GET(desc, block, field, offset) \ 84 HAL_TX_MS(block, field, HAL_SET_FLD_OFFSET(desc, block, field, offset)) 85 86 #define HAL_TX_DESC_SUBBLOCK_GET(desc, block, sub, field) \ 87 HAL_TX_MS(sub, field, HAL_SET_FLD(desc, block, sub)) 88 89 #define HAL_TX_DESC_GET_64(desc, block, field) \ 90 HAL_TX_MS(block, field, HAL_SET_FLD_64(desc, block, field)) 91 92 #define HAL_TX_DESC_OFFSET_GET_64(desc, block, field, offset) \ 93 HAL_TX_MS(block, field, HAL_SET_FLD_OFFSET_64(desc, block, field,\ 94 offset)) 95 96 #define HAL_TX_DESC_SUBBLOCK_GET_64(desc, block, sub, field) \ 97 HAL_TX_MS(sub, field, HAL_SET_FLD_64(desc, block, sub)) 98 99 #define HAL_TX_BUF_TYPE_BUFFER 0 100 #define HAL_TX_BUF_TYPE_EXT_DESC 1 101 102 #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 103 104 #define HAL_TX_DESC_LEN_DWORDS (NUM_OF_DWORDS_TCL_DATA_CMD) 105 #define HAL_TX_DESC_LEN_BYTES (NUM_OF_DWORDS_TCL_DATA_CMD * 4) 106 #define HAL_TX_EXTENSION_DESC_LEN_DWORDS (NUM_OF_DWORDS_TX_MSDU_EXTENSION) 107 #define HAL_TX_EXTENSION_DESC_LEN_BYTES (NUM_OF_DWORDS_TX_MSDU_EXTENSION * 4) 108 109 #define NUM_OF_DWORDS_WBM_RELEASE_RING 8 110 111 #define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 112 #define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4) 113 #define HAL_TX_BITS_PER_TID 3 114 #define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1) 115 #define HAL_TX_NUM_DSCP_PER_REGISTER 10 116 #define HAL_MAX_HW_DSCP_TID_MAPS 2 117 #define HAL_MAX_HW_DSCP_TID_MAPS_11AX 32 118 119 #define HAL_MAX_HW_DSCP_TID_V2_MAPS 48 120 #define HAL_MAX_HW_DSCP_TID_V2_MAPS_5332 24 121 #define HTT_META_HEADER_LEN_BYTES 64 122 #define HAL_TX_EXT_DESC_WITH_META_DATA \ 123 (HTT_META_HEADER_LEN_BYTES + HAL_TX_EXTENSION_DESC_LEN_BYTES) 124 125 #define HAL_TX_NUM_PCP_PER_REGISTER 8 126 127 /* Length of WBM release ring without the status words */ 128 #define HAL_TX_COMPLETION_DESC_BASE_LEN 12 129 130 #define HAL_TX_COMP_RELEASE_SOURCE_TQM 0 131 #define HAL_TX_COMP_RELEASE_SOURCE_REO 2 132 #define HAL_TX_COMP_RELEASE_SOURCE_FW 3 133 134 /* Define a place-holder release reason for FW */ 135 #define HAL_TX_COMP_RELEASE_REASON_FW 99 136 137 /* 138 * Offset of HTT Tx Descriptor in WBM Completion 139 * HTT Tx Desc structure is passed from firmware to host overlaid 140 * on wbm_release_ring DWORDs 2,3 ,4 and 5for software based completions 141 * (Exception frames and TQM bypass frames) 142 */ 143 #define HAL_TX_COMP_HTT_STATUS_OFFSET 8 144 #ifdef CONFIG_BERYLLIUM 145 #define HAL_TX_COMP_HTT_STATUS_LEN 20 146 #else 147 #define HAL_TX_COMP_HTT_STATUS_LEN 16 148 #endif 149 150 #define HAL_TX_BUF_TYPE_BUFFER 0 151 #define HAL_TX_BUF_TYPE_EXT_DESC 1 152 153 #define HAL_TX_EXT_DESC_BUF_OFFSET TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 154 #define HAL_TX_EXT_BUF_LOW_MASK TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 155 #define HAL_TX_EXT_BUF_HI_MASK TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 156 #define HAL_TX_EXT_BUF_LEN_MASK TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 157 #define HAL_TX_EXT_BUF_LEN_LSB TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 158 #define HAL_TX_EXT_BUF_WD_SIZE 2 159 160 #define HAL_TX_DESC_ADDRX_EN 0x1 161 #define HAL_TX_DESC_ADDRY_EN 0x2 162 #define HAL_TX_DESC_DEFAULT_LMAC_ID 0x3 163 164 #define HAL_TX_ADDR_SEARCH_DEFAULT 0x0 165 #define HAL_TX_ADDR_INDEX_SEARCH 0x1 166 #define HAL_TX_FLOW_INDEX_SEARCH 0x2 167 168 #define HAL_WBM2SW_RELEASE_SRC_GET(wbm_desc)(((*(((uint32_t *)wbm_desc) + \ 169 (HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 170 HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_MASK) >> \ 171 HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_LSB) 172 173 #define HAL_WBM_SW0_BM_ID(sw0_bm_id) (sw0_bm_id) 174 #define HAL_WBM_SW1_BM_ID(sw0_bm_id) ((sw0_bm_id) + 1) 175 #define HAL_WBM_SW2_BM_ID(sw0_bm_id) ((sw0_bm_id) + 2) 176 #define HAL_WBM_SW3_BM_ID(sw0_bm_id) ((sw0_bm_id) + 3) 177 #define HAL_WBM_SW4_BM_ID(sw0_bm_id) ((sw0_bm_id) + 4) 178 #define HAL_WBM_SW5_BM_ID(sw0_bm_id) ((sw0_bm_id) + 5) 179 #define HAL_WBM_SW6_BM_ID(sw0_bm_id) ((sw0_bm_id) + 6) 180 181 /*--------------------------------------------------------------------------- 182 Structures 183 ---------------------------------------------------------------------------*/ 184 /** 185 * struct hal_tx_completion_status - HAL Tx completion descriptor contents 186 * @status: frame acked/failed 187 * @release_src: release source = TQM/FW 188 * @ack_frame_rssi: RSSI of the received ACK or BA frame 189 * @first_msdu: Indicates this MSDU is the first MSDU in AMSDU 190 * @last_msdu: Indicates this MSDU is the last MSDU in AMSDU 191 * @msdu_part_of_amsdu : Indicates this MSDU was part of an A-MSDU in MPDU 192 * @bw: Indicates the BW of the upcoming transmission - 193 * <enum 0 transmit_bw_20_MHz> 194 * <enum 1 transmit_bw_40_MHz> 195 * <enum 2 transmit_bw_80_MHz> 196 * <enum 3 transmit_bw_160_MHz> 197 * <enum 4 transmit_bw_320_MHz> 198 * <enum 5 transmit_bw_240_MHz> 199 * @pkt_type: Transmit Packet Type 200 * @stbc: When set, STBC transmission rate was used 201 * @ldpc: When set, use LDPC transmission rates 202 * @sgi: <enum 0 0_8_us_sgi > Legacy normal GI 203 * <enum 1 0_4_us_sgi > Legacy short GI 204 * <enum 2 1_6_us_sgi > HE related GI 205 * <enum 3 3_2_us_sgi > HE 206 * @mcs: Transmit MCS Rate 207 * @ofdma: Set when the transmission was an OFDMA transmission 208 * @tones_in_ru: The number of tones in the RU used. 209 * @tsf: Lower 32 bits of the TSF 210 * @ppdu_id: TSF, snapshot of this value when transmission of the 211 * PPDU containing the frame finished. 212 * @transmit_cnt: Number of times this frame has been transmitted 213 * @tid: TID of the flow or MPDU queue 214 * @peer_id: Peer ID of the flow or MPDU queue 215 * @buffer_timestamp: Frame system entrance timestamp in units of 1024 216 * microseconds 217 */ 218 struct hal_tx_completion_status { 219 uint8_t status; 220 uint8_t release_src; 221 uint8_t ack_frame_rssi; 222 uint8_t first_msdu:1, 223 last_msdu:1, 224 msdu_part_of_amsdu:1; 225 uint32_t bw:3, 226 pkt_type:4, 227 stbc:1, 228 ldpc:1, 229 sgi:2, 230 mcs:4, 231 ofdma:1, 232 tones_in_ru:12, 233 valid:1; 234 uint32_t tsf; 235 uint32_t ppdu_id; 236 uint8_t transmit_cnt; 237 uint8_t tid; 238 uint16_t peer_id; 239 #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY) 240 uint32_t buffer_timestamp:19; 241 #endif 242 }; 243 244 /** 245 * struct hal_tx_desc_comp_s - hal tx completion descriptor contents 246 * @desc: Transmit status information from descriptor 247 */ 248 struct hal_tx_desc_comp_s { 249 uint32_t desc[HAL_TX_COMPLETION_DESC_LEN_DWORDS]; 250 }; 251 252 /* 253 * enum hal_tx_encrypt_type - Type of decrypt cipher used (valid only for RAW) 254 * @HAL_TX_ENCRYPT_TYPE_WEP_40: WEP 40-bit 255 * @HAL_TX_ENCRYPT_TYPE_WEP_10: WEP 10-bit 256 * @HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC: TKIP without MIC 257 * @HAL_TX_ENCRYPT_TYPE_WEP_128: WEP_128 258 * @HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC: TKIP_WITH_MIC 259 * @HAL_TX_ENCRYPT_TYPE_WAPI: WAPI 260 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_128: AES_CCMP_128 261 * @HAL_TX_ENCRYPT_TYPE_NO_CIPHER: NO CIPHER 262 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_256: AES_CCMP_256 263 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_128: AES_GCMP_128 264 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_256: AES_GCMP_256 265 * @HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4: WAPI GCM SM4 266 */ 267 enum hal_tx_encrypt_type { 268 HAL_TX_ENCRYPT_TYPE_WEP_40 = 0, 269 HAL_TX_ENCRYPT_TYPE_WEP_104 = 1 , 270 HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC = 2, 271 HAL_TX_ENCRYPT_TYPE_WEP_128 = 3, 272 HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC = 4, 273 HAL_TX_ENCRYPT_TYPE_WAPI = 5, 274 HAL_TX_ENCRYPT_TYPE_AES_CCMP_128 = 6, 275 HAL_TX_ENCRYPT_TYPE_NO_CIPHER = 7, 276 HAL_TX_ENCRYPT_TYPE_AES_CCMP_256 = 8, 277 HAL_TX_ENCRYPT_TYPE_AES_GCMP_128 = 9, 278 HAL_TX_ENCRYPT_TYPE_AES_GCMP_256 = 10, 279 HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4 = 11, 280 }; 281 282 /* 283 * enum hal_tx_encap_type - Encapsulation type that HW will perform 284 * @HAL_TX_ENCAP_TYPE_RAW: Raw Packet Type 285 * @HAL_TX_ENCAP_TYPE_NWIFI: Native WiFi Type 286 * @HAL_TX_ENCAP_TYPE_ETHERNET: Ethernet 287 * @HAL_TX_ENCAP_TYPE_802_3: 802.3 Frame 288 */ 289 enum hal_tx_encap_type { 290 HAL_TX_ENCAP_TYPE_RAW = 0, 291 HAL_TX_ENCAP_TYPE_NWIFI = 1, 292 HAL_TX_ENCAP_TYPE_ETHERNET = 2, 293 HAL_TX_ENCAP_TYPE_802_3 = 3, 294 }; 295 296 /** 297 * enum hal_tx_tqm_release_reason - TQM Release reason codes 298 * 299 * @HAL_TX_TQM_RR_FRAME_ACKED : ACK of BA for it was received 300 * @HAL_TX_TQM_RR_REM_CMD_REM : Remove cmd of type “Remove_mpdus” initiated 301 * by SW 302 * @HAL_TX_TQM_RR_REM_CMD_TX : Remove command of type Remove_transmitted_mpdus 303 * initiated by SW 304 * @HAL_TX_TQM_RR_REM_CMD_NOTX : Remove cmd of type Remove_untransmitted_mpdus 305 * initiated by SW 306 * @HAL_TX_TQM_RR_REM_CMD_AGED : Remove command of type “Remove_aged_mpdus” or 307 * “Remove_aged_msdus” initiated by SW 308 * @HAL_TX_TQM_RR_FW_REASON1 : Remove command where fw indicated that 309 * remove reason is fw_reason1 310 * @HAL_TX_TQM_RR_FW_REASON2 : Remove command where fw indicated that 311 * remove reason is fw_reason2 312 * @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that 313 * remove reason is fw_reason3 314 * @HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE : Remove command where fw indicated that 315 * remove reason is remove disable queue 316 * @HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING: Remove command from fw to remove 317 * all mpdu until 1st non-match 318 * @HAL_TX_TQM_RR_DROP_THRESHOLD: Dropped due to drop threshold criteria 319 * @HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE: Dropped due to link desc not available 320 * @HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU: Dropped due drop bit set or null flow 321 * @HAL_TX_TQM_RR_MULTICAST_DROP: Dropped due mcast drop set for VDEV 322 * @HAL_TX_TQM_RR_VDEV_MISMATCH_DROP: Dropped due to being set with 323 * 'TCL_drop_reason' 324 * 325 */ 326 enum hal_tx_tqm_release_reason { 327 HAL_TX_TQM_RR_FRAME_ACKED, 328 HAL_TX_TQM_RR_REM_CMD_REM, 329 HAL_TX_TQM_RR_REM_CMD_TX, 330 HAL_TX_TQM_RR_REM_CMD_NOTX, 331 HAL_TX_TQM_RR_REM_CMD_AGED, 332 HAL_TX_TQM_RR_FW_REASON1, 333 HAL_TX_TQM_RR_FW_REASON2, 334 HAL_TX_TQM_RR_FW_REASON3, 335 HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE, 336 HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING, 337 HAL_TX_TQM_RR_DROP_THRESHOLD, 338 HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE, 339 HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU, 340 HAL_TX_TQM_RR_MULTICAST_DROP, 341 HAL_TX_TQM_RR_VDEV_MISMATCH_DROP, 342 }; 343 344 /* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports 345 * @HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT: Default DSCP-TID mapping table 346 * @HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE: DSCP-TID map override table 347 */ 348 enum hal_tx_dscp_tid_table_id { 349 HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT, 350 HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE, 351 }; 352 353 /*--------------------------------------------------------------------------- 354 Function declarations and documentation 355 ---------------------------------------------------------------------------*/ 356 357 /*--------------------------------------------------------------------------- 358 Tx MSDU Extension Descriptor accessor APIs 359 ---------------------------------------------------------------------------*/ 360 /** 361 * hal_tx_ext_desc_set_tso_enable() - Set TSO Enable Flag 362 * @desc: Handle to Tx MSDU Extension Descriptor 363 * @tso_en: bool value set to true if TSO is enabled 364 * 365 * Return: none 366 */ 367 static inline void hal_tx_ext_desc_set_tso_enable(void *desc, 368 uint8_t tso_en) 369 { 370 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE) |= 371 HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TSO_ENABLE, tso_en); 372 } 373 374 /** 375 * hal_tx_ext_desc_set_tso_flags() - Set TSO Flags 376 * @desc: Handle to Tx MSDU Extension Descriptor 377 * @flags: 32-bit word with all TSO flags consolidated 378 * 379 * Return: none 380 */ 381 static inline void hal_tx_ext_desc_set_tso_flags(void *desc, 382 uint32_t tso_flags) 383 { 384 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE, 0) = 385 tso_flags; 386 } 387 388 /** 389 * hal_tx_ext_desc_set_tcp_flags() - Enable HW Checksum offload 390 * @desc: Handle to Tx MSDU Extension Descriptor 391 * @tcp_flags: TCP flags {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 392 * @mask: TCP flag mask. Tcp_flag is inserted into the header 393 * based on the mask, if tso is enabled 394 * 395 * Return: none 396 */ 397 static inline void hal_tx_ext_desc_set_tcp_flags(void *desc, 398 uint16_t tcp_flags, 399 uint16_t mask) 400 { 401 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_FLAG) |= 402 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG, tcp_flags)) | 403 (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG_MASK, mask))); 404 } 405 406 /** 407 * hal_tx_ext_desc_set_msdu_length() - Set L2 and IP Lengths 408 * @desc: Handle to Tx MSDU Extension Descriptor 409 * @l2_len: L2 length for the msdu, if tso is enabled 410 * @ip_len: IP length for the msdu, if tso is enabled 411 * 412 * Return: none 413 */ 414 static inline void hal_tx_ext_desc_set_msdu_length(void *desc, 415 uint16_t l2_len, 416 uint16_t ip_len) 417 { 418 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, L2_LENGTH) |= 419 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, L2_LENGTH, l2_len)) | 420 (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_LENGTH, ip_len))); 421 } 422 423 /** 424 * hal_tx_ext_desc_set_tcp_seq() - Set TCP Sequence number 425 * @desc: Handle to Tx MSDU Extension Descriptor 426 * @seq_num: Tcp_seq_number for the msdu, if tso is enabled 427 * 428 * Return: none 429 */ 430 static inline void hal_tx_ext_desc_set_tcp_seq(void *desc, 431 uint32_t seq_num) 432 { 433 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER) |= 434 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER, seq_num))); 435 } 436 437 438 /** 439 * hal_tx_ext_desc_set_ip_id() - Set IP Identification field 440 * @desc: Handle to Tx MSDU Extension Descriptor 441 * @id: IP Id field for the msdu, if tso is enabled 442 * 443 * Return: none 444 */ 445 static inline void hal_tx_ext_desc_set_ip_id(void *desc, 446 uint16_t id) 447 { 448 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION) |= 449 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION, id))); 450 } 451 /** 452 * hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment 453 * @desc: Handle to Tx MSDU Extension Descriptor 454 * @frag_num: Fragment number (value can be 0 to 5) 455 * @paddr_lo: Lower 32-bit of Buffer Physical address 456 * @paddr_hi: Upper 32-bit of Buffer Physical address 457 * @length: Buffer Length 458 * 459 * Return: none 460 */ 461 static inline void hal_tx_ext_desc_set_buffer(void *desc, 462 uint8_t frag_num, 463 uint32_t paddr_lo, 464 uint16_t paddr_hi, 465 uint16_t length) 466 { 467 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, 468 (frag_num << 3)) |= 469 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo))); 470 471 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32, 472 (frag_num << 3)) |= 473 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32, 474 (paddr_hi)))); 475 476 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN, 477 (frag_num << 3)) |= 478 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length))); 479 } 480 481 /** 482 * hal_tx_ext_desc_get_frag_info() - Get the frag_num'th frag iova and len 483 * @desc: Handle to Tx MSDU Extension Descriptor 484 * @frag_num: fragment number (value can be 0 to 5) 485 * @iova: fragment dma address 486 * @len: fragment Length 487 * 488 * Return: None 489 */ 490 static inline void hal_tx_ext_desc_get_frag_info(void *desc, uint8_t frag_num, 491 qdf_dma_addr_t *iova, 492 uint32_t *len) 493 { 494 uint64_t iova_hi; 495 496 *iova = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, 497 BUF0_PTR_31_0, (frag_num << 3)); 498 499 iova_hi = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, 500 BUF0_PTR_39_32, (frag_num << 3)); 501 *iova |= (iova_hi << 32); 502 503 *len = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN, 504 (frag_num << 3)); 505 } 506 507 /** 508 * hal_tx_ext_desc_set_buffer0_param() - Set Buffer 0 Pointer and Length 509 * @desc: Handle to Tx MSDU Extension Descriptor 510 * @paddr_lo: Lower 32-bit of Buffer Physical address 511 * @paddr_hi: Upper 32-bit of Buffer Physical address 512 * @length: Buffer 0 Length 513 * 514 * Return: none 515 */ 516 static inline void hal_tx_ext_desc_set_buffer0_param(void *desc, 517 uint32_t paddr_lo, 518 uint16_t paddr_hi, 519 uint16_t length) 520 { 521 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0) |= 522 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo))); 523 524 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32) |= 525 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, 526 BUF0_PTR_39_32, paddr_hi))); 527 528 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN) |= 529 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length))); 530 } 531 532 /** 533 * hal_tx_ext_desc_set_buffer1_param() - Set Buffer 1 Pointer and Length 534 * @desc: Handle to Tx MSDU Extension Descriptor 535 * @paddr_lo: Lower 32-bit of Buffer Physical address 536 * @paddr_hi: Upper 32-bit of Buffer Physical address 537 * @length: Buffer 1 Length 538 * 539 * Return: none 540 */ 541 static inline void hal_tx_ext_desc_set_buffer1_param(void *desc, 542 uint32_t paddr_lo, 543 uint16_t paddr_hi, 544 uint16_t length) 545 { 546 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0) |= 547 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0, paddr_lo))); 548 549 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_39_32) |= 550 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, 551 BUF1_PTR_39_32, paddr_hi))); 552 553 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_LEN) |= 554 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_LEN, length))); 555 } 556 557 /** 558 * hal_tx_ext_desc_set_buffer2_param() - Set Buffer 2 Pointer and Length 559 * @desc: Handle to Tx MSDU Extension Descriptor 560 * @paddr_lo: Lower 32-bit of Buffer Physical address 561 * @paddr_hi: Upper 32-bit of Buffer Physical address 562 * @length: Buffer 2 Length 563 * 564 * Return: none 565 */ 566 static inline void hal_tx_ext_desc_set_buffer2_param(void *desc, 567 uint32_t paddr_lo, 568 uint16_t paddr_hi, 569 uint16_t length) 570 { 571 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0) |= 572 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0, 573 paddr_lo))); 574 575 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32) |= 576 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32, 577 paddr_hi))); 578 579 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_LEN) |= 580 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_LEN, length))); 581 } 582 583 /** 584 * hal_tx_ext_desc_sync - Commit the descriptor to Hardware 585 * @desc_cached: Cached descriptor that software maintains 586 * @hw_desc: Hardware descriptor to be updated 587 * 588 * Return: none 589 */ 590 static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached, 591 uint8_t *hw_desc) 592 { 593 qdf_mem_copy(&hw_desc[0], &desc_cached[0], 594 HAL_TX_EXT_DESC_WITH_META_DATA); 595 } 596 597 /** 598 * hal_tx_ext_desc_get_tso_enable() - Set TSO Enable Flag 599 * @hal_tx_ext_desc: Handle to Tx MSDU Extension Descriptor 600 * 601 * Return: tso_enable value in the descriptor 602 */ 603 static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc) 604 { 605 uint32_t *desc = (uint32_t *) hal_tx_ext_desc; 606 return (*desc & HAL_TX_MSDU_EXTENSION_TSO_ENABLE_MASK) >> 607 HAL_TX_MSDU_EXTENSION_TSO_ENABLE_LSB; 608 } 609 610 /*--------------------------------------------------------------------------- 611 WBM Descriptor accessor APIs for Tx completions 612 ---------------------------------------------------------------------------*/ 613 /** 614 * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type 615 * @hal_desc: completion ring descriptor pointer 616 * 617 * This function will return the type of pointer - buffer or descriptor 618 * 619 * Return: buffer type 620 */ 621 static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc) 622 { 623 uint32_t comp_desc = 624 *(uint32_t *) (((uint8_t *) hal_desc) + 625 HAL_TX_COMP_BUFFER_OR_DESC_TYPE_OFFSET); 626 627 return (comp_desc & HAL_TX_COMP_BUFFER_OR_DESC_TYPE_MASK) >> 628 HAL_TX_COMP_BUFFER_OR_DESC_TYPE_LSB; 629 } 630 631 #ifdef QCA_WIFI_KIWI 632 /** 633 * hal_tx_comp_get_buffer_source() - Get buffer release source value 634 * @hal_desc: completion ring descriptor pointer 635 * 636 * This function will get buffer release source from Tx completion descriptor 637 * 638 * Return: buffer release source 639 */ 640 static inline uint32_t 641 hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl, 642 void *hal_desc) 643 { 644 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 645 646 return hal_soc->ops->hal_tx_comp_get_buffer_source(hal_desc); 647 } 648 #else 649 static inline uint32_t 650 hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl, 651 void *hal_desc) 652 { 653 return HAL_WBM2SW_RELEASE_SRC_GET(hal_desc); 654 } 655 #endif 656 657 /** 658 * hal_tx_comp_get_release_reason() - TQM Release reason 659 * @hal_desc: completion ring descriptor pointer 660 * 661 * This function will return the type of pointer - buffer or descriptor 662 * 663 * Return: buffer type 664 */ 665 static inline 666 uint8_t hal_tx_comp_get_release_reason(void *hal_desc, 667 hal_soc_handle_t hal_soc_hdl) 668 { 669 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 670 671 return hal_soc->ops->hal_tx_comp_get_release_reason(hal_desc); 672 } 673 674 /** 675 * hal_tx_comp_get_peer_id() - Get peer_id value() 676 * @hal_desc: completion ring descriptor pointer 677 * 678 * This function will get peer_id value from Tx completion descriptor 679 * 680 * Return: buffer release source 681 */ 682 static inline uint16_t hal_tx_comp_get_peer_id(void *hal_desc) 683 { 684 uint32_t comp_desc = 685 *(uint32_t *)(((uint8_t *)hal_desc) + 686 HAL_TX_COMP_SW_PEER_ID_OFFSET); 687 688 return (comp_desc & HAL_TX_COMP_SW_PEER_ID_MASK) >> 689 HAL_TX_COMP_SW_PEER_ID_LSB; 690 } 691 692 /** 693 * hal_tx_comp_get_tx_status() - Get tx transmission status() 694 * @hal_desc: completion ring descriptor pointer 695 * 696 * This function will get transmit status value from Tx completion descriptor 697 * 698 * Return: buffer release source 699 */ 700 static inline uint8_t hal_tx_comp_get_tx_status(void *hal_desc) 701 { 702 uint32_t comp_desc = 703 *(uint32_t *)(((uint8_t *)hal_desc) + 704 HAL_TX_COMP_TQM_RELEASE_REASON_OFFSET); 705 706 return (comp_desc & HAL_TX_COMP_TQM_RELEASE_REASON_MASK) >> 707 HAL_TX_COMP_TQM_RELEASE_REASON_LSB; 708 } 709 710 /** 711 * hal_tx_comp_desc_sync() - collect hardware descriptor contents 712 * @hal_desc: hardware descriptor pointer 713 * @comp: software descriptor pointer 714 * @read_status: 0 - Do not read status words from descriptors 715 * 1 - Enable reading of status words from descriptor 716 * 717 * This function will collect hardware release ring element contents and 718 * translate to software descriptor content 719 * 720 * Return: none 721 */ 722 723 static inline void hal_tx_comp_desc_sync(void *hw_desc, 724 struct hal_tx_desc_comp_s *comp, 725 bool read_status) 726 { 727 if (!read_status) 728 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_BASE_LEN); 729 else 730 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_LEN_BYTES); 731 } 732 733 /** 734 * hal_dump_comp_desc() - dump tx completion descriptor 735 * @hal_desc: hardware descriptor pointer 736 * 737 * This function will print tx completion descriptor 738 * 739 * Return: none 740 */ 741 static inline void hal_dump_comp_desc(void *hw_desc) 742 { 743 struct hal_tx_desc_comp_s *comp = 744 (struct hal_tx_desc_comp_s *)hw_desc; 745 uint32_t i; 746 747 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 748 "Current tx completion descriptor is"); 749 750 for (i = 0; i < HAL_TX_COMPLETION_DESC_LEN_DWORDS; i++) { 751 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 752 "DWORD[i] = 0x%x", comp->desc[i]); 753 } 754 } 755 756 /** 757 * hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor 758 * @hal_desc: Hardware (WBM) descriptor pointer 759 * @htt_desc: Software HTT descriptor pointer 760 * 761 * This function will read the HTT structure overlaid on WBM descriptor 762 * into a cached software descriptor 763 * 764 */ 765 static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc) 766 { 767 uint8_t *desc = hw_desc + HAL_TX_COMP_HTT_STATUS_OFFSET; 768 769 qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN); 770 } 771 772 /** 773 * hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG 774 * @hal_soc_hdl: Handle to HAL SoC structure 775 * @hal_srng: Handle to HAL SRNG structure 776 * 777 * Return: none 778 */ 779 static inline void hal_tx_init_data_ring(hal_soc_handle_t hal_soc_hdl, 780 hal_ring_handle_t hal_ring_hdl) 781 { 782 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 783 784 hal_soc->ops->hal_tx_init_data_ring(hal_soc_hdl, hal_ring_hdl); 785 } 786 787 /** 788 * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table 789 * 790 * @soc: HAL SoC context 791 * @map: DSCP-TID mapping table 792 * @id: mapping table ID - 0,1 793 * 794 * Return: void 795 */ 796 static inline void hal_tx_set_dscp_tid_map(hal_soc_handle_t hal_soc_hdl, 797 uint8_t *map, uint8_t id) 798 { 799 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 800 801 hal_soc->ops->hal_tx_set_dscp_tid_map(hal_soc, map, id); 802 } 803 804 /** 805 * hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user 806 * 807 * @soc: HAL SoC context 808 * @map: DSCP-TID mapping table 809 * @id : MAP ID 810 * @dscp: DSCP_TID map index 811 * 812 * Return: void 813 */ 814 static inline 815 void hal_tx_update_dscp_tid(hal_soc_handle_t hal_soc_hdl, uint8_t tid, 816 uint8_t id, uint8_t dscp) 817 { 818 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 819 820 hal_soc->ops->hal_tx_update_dscp_tid(hal_soc, tid, id, dscp); 821 } 822 823 /** 824 * hal_tx_comp_get_status() - TQM Release reason 825 * @hal_desc: completion ring Tx status 826 * 827 * This function will parse the WBM completion descriptor and populate in 828 * HAL structure 829 * 830 * Return: none 831 */ 832 static inline void hal_tx_comp_get_status(void *desc, void *ts, 833 hal_soc_handle_t hal_soc_hdl) 834 { 835 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 836 837 hal_soc->ops->hal_tx_comp_get_status(desc, ts, hal_soc); 838 } 839 840 /** 841 * hal_tx_set_pcp_tid_map_default() - Configure default PCP to TID map table 842 * 843 * @soc: HAL SoC context 844 * @map: PCP-TID mapping table 845 * 846 * Return: void 847 */ 848 static inline void hal_tx_set_pcp_tid_map_default(hal_soc_handle_t hal_soc_hdl, 849 uint8_t *map) 850 { 851 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 852 853 hal_soc->ops->hal_tx_set_pcp_tid_map(hal_soc, map); 854 } 855 856 /** 857 * hal_tx_update_pcp_tid_map() - Update PCP to TID map table 858 * 859 * @soc: HAL SoC context 860 * @pcp: pcp value 861 * @tid: tid no 862 * 863 * Return: void 864 */ 865 static inline void hal_tx_update_pcp_tid_map(hal_soc_handle_t hal_soc_hdl, 866 uint8_t pcp, uint8_t tid) 867 { 868 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 869 870 hal_soc->ops->hal_tx_update_pcp_tid_map(hal_soc, pcp, tid); 871 } 872 873 /** 874 * hal_tx_set_tidmap_prty() - Configure TIDmap priority 875 * 876 * @soc: HAL SoC context 877 * @val: priority value 878 * 879 * Return: void 880 */ 881 static inline 882 void hal_tx_set_tidmap_prty(hal_soc_handle_t hal_soc_hdl, uint8_t val) 883 { 884 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 885 886 hal_soc->ops->hal_tx_set_tidmap_prty(hal_soc, val); 887 } 888 889 /** 890 * hal_get_wbm_internal_error() - wbm internal error 891 * @hal_desc: completion ring descriptor pointer 892 * 893 * This function will return the type of pointer - buffer or descriptor 894 * 895 * Return: buffer type 896 */ 897 static inline 898 uint8_t hal_get_wbm_internal_error(hal_soc_handle_t hal_soc_hdl, void *hal_desc) 899 { 900 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 901 902 return hal_soc->ops->hal_get_wbm_internal_error(hal_desc); 903 } 904 905 /** 906 * hal_get_tsf2_offset() - get tsf2 offset 907 * 908 * @hal_soc_hdl: HAL SoC context 909 * @mac_id: mac id 910 * @value: pointer to update tsf2 offset value 911 * 912 * Return: void 913 */ 914 static inline void 915 hal_get_tsf2_offset(hal_soc_handle_t hal_soc_hdl, uint8_t mac_id, 916 uint64_t *value) 917 { 918 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 919 920 if (hal_soc->ops->hal_get_tsf2_scratch_reg) 921 hal_soc->ops->hal_get_tsf2_scratch_reg(hal_soc_hdl, mac_id, 922 value); 923 } 924 925 /** 926 * hal_get_tqm_offset() - get tqm offset 927 * 928 * @hal_soc_hdl: HAL SoC context 929 * @value: pointer to update tqm offset value 930 * 931 * Return: void 932 */ 933 934 static inline void 935 hal_get_tqm_offset(hal_soc_handle_t hal_soc_hdl, uint64_t *value) 936 { 937 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 938 939 if (hal_soc->ops->hal_get_tqm_scratch_reg) 940 hal_soc->ops->hal_get_tqm_scratch_reg(hal_soc_hdl, value); 941 } 942 #endif /* HAL_TX_H */ 943