1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #if !defined(HAL_TX_H) 20 #define HAL_TX_H 21 22 /*--------------------------------------------------------------------------- 23 Include files 24 ---------------------------------------------------------------------------*/ 25 #include "hal_api.h" 26 #include "wcss_version.h" 27 28 /*--------------------------------------------------------------------------- 29 Preprocessor definitions and constants 30 ---------------------------------------------------------------------------*/ 31 #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET 32 33 #define HAL_SET_FLD(desc, block , field) \ 34 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field))) 35 36 #define HAL_SET_FLD_OFFSET(desc, block , field, offset) \ 37 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field) + (offset))) 38 39 #define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \ 40 do { \ 41 ((struct tlv_32_hdr *) desc)->tlv_tag = (tag); \ 42 ((struct tlv_32_hdr *) desc)->tlv_len = (len); \ 43 } while (0) 44 45 #define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E 46 #define HAL_TX_TCL_CMD_TAG WIFITCL_GSE_CMD_E 47 48 #define HAL_TX_SM(block, field, value) \ 49 ((value << (block ## _ ## field ## _LSB)) & \ 50 (block ## _ ## field ## _MASK)) 51 52 #define HAL_TX_MS(block, field, value) \ 53 (((value) & (block ## _ ## field ## _MASK)) >> \ 54 (block ## _ ## field ## _LSB)) 55 56 #define HAL_TX_DESC_GET(desc, block, field) \ 57 HAL_TX_MS(block, field, HAL_SET_FLD(desc, block, field)) 58 59 #define HAL_TX_DESC_SUBBLOCK_GET(desc, block, sub, field) \ 60 HAL_TX_MS(sub, field, HAL_SET_FLD(desc, block, sub)) 61 62 #define HAL_TX_BUF_TYPE_BUFFER 0 63 #define HAL_TX_BUF_TYPE_EXT_DESC 1 64 65 #define HAL_TX_DESC_LEN_DWORDS (NUM_OF_DWORDS_TCL_DATA_CMD) 66 #define HAL_TX_DESC_LEN_BYTES (NUM_OF_DWORDS_TCL_DATA_CMD * 4) 67 #define HAL_TX_EXTENSION_DESC_LEN_DWORDS (NUM_OF_DWORDS_TX_MSDU_EXTENSION) 68 #define HAL_TX_EXTENSION_DESC_LEN_BYTES (NUM_OF_DWORDS_TX_MSDU_EXTENSION * 4) 69 70 #define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 71 #define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4) 72 73 /* Length of WBM release ring without the status words */ 74 #define HAL_TX_COMPLETION_DESC_BASE_LEN 12 75 76 #define HAL_TX_COMP_RELEASE_SOURCE_TQM 0 77 #define HAL_TX_COMP_RELEASE_SOURCE_FW 3 78 79 /* Define a place-holder release reason for FW */ 80 #define HAL_TX_COMP_RELEASE_REASON_FW 99 81 82 /* 83 * Offset of HTT Tx Descriptor in WBM Completion 84 * HTT Tx Desc structure is passed from firmware to host overlayed 85 * on wbm_release_ring DWORD 3 and 4 for software based completions 86 * (Exception frames and TQM bypass frames) 87 */ 88 #define HAL_TX_COMP_HTT_STATUS_OFFSET 12 89 #define HAL_TX_COMP_HTT_STATUS_LEN 8 90 91 #define HAL_TX_BUF_TYPE_BUFFER 0 92 #define HAL_TX_BUF_TYPE_EXT_DESC 1 93 94 #define HAL_TX_EXT_DESC_BUF_OFFSET TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 95 #define HAL_TX_EXT_BUF_LOW_MASK TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 96 #define HAL_TX_EXT_BUF_HI_MASK TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 97 #define HAL_TX_EXT_BUF_LEN_MASK TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 98 #define HAL_TX_EXT_BUF_LEN_LSB TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 99 #define HAL_TX_EXT_BUF_WD_SIZE 2 100 101 #define HAL_TX_DESC_ADDRX_EN 0x1 102 #define HAL_TX_DESC_ADDRY_EN 0x2 103 104 enum hal_tx_ret_buf_manager { 105 HAL_WBM_SW0_BM_ID = 3, 106 HAL_WBM_SW1_BM_ID = 4, 107 HAL_WBM_SW2_BM_ID = 5, 108 HAL_WBM_SW3_BM_ID = 6, 109 }; 110 111 /*--------------------------------------------------------------------------- 112 Structures 113 ---------------------------------------------------------------------------*/ 114 /** 115 * struct hal_tx_completion_status - HAL Tx completion descriptor contents 116 * @ack_frame_rssi: RSSI of the received ACK or BA frame 117 * @first_msdu: Indicates this MSDU is the first MSDU in AMSDU 118 * @last_msdu: Indicates this MSDU is the last MSDU in AMSDU 119 * @msdu_part_of_amsdu : Indicates this MSDU was part of an A-MSDU in MPDU 120 * @bw: Indicates the BW of the upcoming transmission - 121 * <enum 0 transmit_bw_20_MHz> 122 * <enum 1 transmit_bw_40_MHz> 123 * <enum 2 transmit_bw_80_MHz> 124 * <enum 3 transmit_bw_160_MHz> 125 * @pkt_type: Transmit Packet Type 126 * @stbc: When set, STBC transmission rate was used 127 * @ldpc: When set, use LDPC transmission rates 128 * @sgi: <enum 0 0_8_us_sgi > Legacy normal GI 129 * <enum 1 0_4_us_sgi > Legacy short GI 130 * <enum 2 1_6_us_sgi > HE related GI 131 * <enum 3 3_2_us_sgi > HE 132 * @mcs: Transmit MCS Rate 133 * @ofdma: Set when the transmission was an OFDMA transmission 134 * @tones_in_ru: The number of tones in the RU used. 135 * @tsf: Lower 32 bits of the TSF 136 * @ppdu_id: TSF, snapshot of this value when transmission of the 137 * PPDU containing the frame finished. 138 * @transmit_cnt: Number of times this frame has been transmitted 139 * @tid: TID of the flow or MPDU queue 140 * @peer_id: Peer ID of the flow or MPDU queue 141 */ 142 struct hal_tx_completion_status { 143 uint8_t ack_frame_rssi; 144 uint8_t first_msdu:1, 145 last_msdu:1, 146 msdu_part_of_amsdu:1; 147 uint32_t bw:2, 148 pkt_type:4, 149 stbc:1, 150 ldpc:1, 151 sgi:2, 152 mcs:2, 153 ofdma:1, 154 tones_in_ru:10; 155 uint32_t tsf; 156 uint32_t ppdu_id; 157 uint8_t transmit_cnt; 158 uint8_t tid; 159 uint16_t peer_id; 160 }; 161 162 /** 163 * struct hal_tx_desc_comp_s - hal tx completion descriptor contents 164 * @desc: Transmit status information from descriptor 165 */ 166 struct hal_tx_desc_comp_s { 167 uint32_t desc[HAL_TX_COMPLETION_DESC_LEN_DWORDS]; 168 }; 169 170 /* 171 * enum hal_tx_encrypt_type - Type of decrypt cipher used (valid only for RAW) 172 * @HAL_TX_ENCRYPT_TYPE_WEP_40: WEP 40-bit 173 * @HAL_TX_ENCRYPT_TYPE_WEP_10: WEP 10-bit 174 * @HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC: TKIP without MIC 175 * @HAL_TX_ENCRYPT_TYPE_WEP_128: WEP_128 176 * @HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC: TKIP_WITH_MIC 177 * @HAL_TX_ENCRYPT_TYPE_WAPI: WAPI 178 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_128: AES_CCMP_128 179 * @HAL_TX_ENCRYPT_TYPE_NO_CIPHER: NO CIPHER 180 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_256: AES_CCMP_256 181 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_128: AES_GCMP_128 182 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_256: AES_GCMP_256 183 * @HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4: WAPI GCM SM4 184 */ 185 enum hal_tx_encrypt_type { 186 HAL_TX_ENCRYPT_TYPE_WEP_40 = 0, 187 HAL_TX_ENCRYPT_TYPE_WEP_104 = 1 , 188 HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC = 2, 189 HAL_TX_ENCRYPT_TYPE_WEP_128 = 3, 190 HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC = 4, 191 HAL_TX_ENCRYPT_TYPE_WAPI = 5, 192 HAL_TX_ENCRYPT_TYPE_AES_CCMP_128 = 6, 193 HAL_TX_ENCRYPT_TYPE_NO_CIPHER = 7, 194 HAL_TX_ENCRYPT_TYPE_AES_CCMP_256 = 8, 195 HAL_TX_ENCRYPT_TYPE_AES_GCMP_128 = 9, 196 HAL_TX_ENCRYPT_TYPE_AES_GCMP_256 = 10, 197 HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4 = 11, 198 }; 199 200 /* 201 * enum hal_tx_encap_type - Encapsulation type that HW will perform 202 * @HAL_TX_ENCAP_TYPE_RAW: Raw Packet Type 203 * @HAL_TX_ENCAP_TYPE_NWIFI: Native WiFi Type 204 * @HAL_TX_ENCAP_TYPE_ETHERNET: Ethernet 205 * @HAL_TX_ENCAP_TYPE_802_3: 802.3 Frame 206 */ 207 enum hal_tx_encap_type { 208 HAL_TX_ENCAP_TYPE_RAW = 0, 209 HAL_TX_ENCAP_TYPE_NWIFI = 1, 210 HAL_TX_ENCAP_TYPE_ETHERNET = 2, 211 HAL_TX_ENCAP_TYPE_802_3 = 3, 212 }; 213 214 /** 215 * enum hal_tx_tqm_release_reason - TQM Release reason codes 216 * 217 * @HAL_TX_TQM_RR_FRAME_ACKED : ACK of BA for it was received 218 * @HAL_TX_TQM_RR_REM_CMD_REM : Remove cmd of type “Remove_mpdus” initiated 219 * by SW 220 * @HAL_TX_TQM_RR_REM_CMD_TX : Remove command of type Remove_transmitted_mpdus 221 * initiated by SW 222 * @HAL_TX_TQM_RR_REM_CMD_NOTX : Remove cmd of type Remove_untransmitted_mpdus 223 * initiated by SW 224 * @HAL_TX_TQM_RR_REM_CMD_AGED : Remove command of type “Remove_aged_mpdus” or 225 * “Remove_aged_msdus” initiated by SW 226 * @HAL_TX_TQM_RR_FW_REASON1 : Remove command where fw indicated that 227 * remove reason is fw_reason1 228 * @HAL_TX_TQM_RR_FW_REASON2 : Remove command where fw indicated that 229 * remove reason is fw_reason2 230 * @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that 231 * remove reason is fw_reason3 232 */ 233 enum hal_tx_tqm_release_reason { 234 HAL_TX_TQM_RR_FRAME_ACKED, 235 HAL_TX_TQM_RR_REM_CMD_REM, 236 HAL_TX_TQM_RR_REM_CMD_TX, 237 HAL_TX_TQM_RR_REM_CMD_NOTX, 238 HAL_TX_TQM_RR_REM_CMD_AGED, 239 HAL_TX_TQM_RR_FW_REASON1, 240 HAL_TX_TQM_RR_FW_REASON2, 241 HAL_TX_TQM_RR_FW_REASON3, 242 }; 243 244 /* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports 245 * @HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT: Default DSCP-TID mapping table 246 * @HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE: DSCP-TID map override table 247 */ 248 enum hal_tx_dscp_tid_table_id { 249 HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT, 250 HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE, 251 }; 252 253 /*--------------------------------------------------------------------------- 254 Function declarations and documentation 255 ---------------------------------------------------------------------------*/ 256 257 /*--------------------------------------------------------------------------- 258 TCL Descriptor accessor APIs 259 ---------------------------------------------------------------------------*/ 260 /** 261 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 262 * @desc: Handle to Tx Descriptor 263 * @paddr: Physical Address 264 * @pool_id: Return Buffer Manager ID 265 * @desc_id: Descriptor ID 266 * @type: 0 - Address points to a MSDU buffer 267 * 1 - Address points to MSDU extension descriptor 268 * 269 * Return: void 270 */ 271 static inline void hal_tx_desc_set_buf_addr(void *desc, 272 dma_addr_t paddr, uint8_t pool_id, 273 uint32_t desc_id, uint8_t type) 274 { 275 /* Set buffer_addr_info.buffer_addr_31_0 */ 276 HAL_SET_FLD(desc, TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 277 HAL_TX_SM(BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 278 279 /* Set buffer_addr_info.buffer_addr_39_32 */ 280 HAL_SET_FLD(desc, TCL_DATA_CMD_1, 281 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 282 HAL_TX_SM(BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 283 (((uint64_t) paddr) << 32)); 284 285 /* Set buffer_addr_info.return_buffer_manager = pool id */ 286 HAL_SET_FLD(desc, TCL_DATA_CMD_1, 287 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 288 HAL_TX_SM(BUFFER_ADDR_INFO_1, 289 RETURN_BUFFER_MANAGER, (pool_id + HAL_WBM_SW0_BM_ID)); 290 291 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 292 HAL_SET_FLD(desc, TCL_DATA_CMD_1, 293 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 294 HAL_TX_SM(BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id); 295 296 /* Set Buffer or Ext Descriptor Type */ 297 HAL_SET_FLD(desc, TCL_DATA_CMD_2, 298 BUF_OR_EXT_DESC_TYPE) |= 299 HAL_TX_SM(TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 300 } 301 302 /** 303 * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor 304 * @desc: Handle to Tx Descriptor 305 * @data_length: MSDU length in case of direct descriptor. 306 * Length of link extension descriptor in case of Link extension 307 * descriptor.Includes the length of Metadata 308 * Return: None 309 */ 310 static inline void hal_tx_desc_set_buf_length(void *desc, 311 uint16_t data_length) 312 { 313 HAL_SET_FLD(desc, TCL_DATA_CMD_3, DATA_LENGTH) |= 314 HAL_TX_SM(TCL_DATA_CMD_3, DATA_LENGTH, data_length); 315 } 316 317 /** 318 * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor 319 * @desc: Handle to Tx Descriptor 320 * @offset: Packet offset from Metadata in case of direct buffer descriptor. 321 * 322 * Return: void 323 */ 324 static inline void hal_tx_desc_set_buf_offset(void *desc, 325 uint8_t offset) 326 { 327 HAL_SET_FLD(desc, TCL_DATA_CMD_3, PACKET_OFFSET) |= 328 HAL_TX_SM(TCL_DATA_CMD_3, PACKET_OFFSET, offset); 329 } 330 331 /** 332 * hal_tx_desc_set_encap_type - Set encapsulation type in Tx Descriptor 333 * @desc: Handle to Tx Descriptor 334 * @encap_type: Encapsulation that HW will perform 335 * 336 * Return: void 337 * 338 */ 339 static inline void hal_tx_desc_set_encap_type(void *desc, 340 enum hal_tx_encap_type encap_type) 341 { 342 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCAP_TYPE) |= 343 HAL_TX_SM(TCL_DATA_CMD_2, ENCAP_TYPE, encap_type); 344 } 345 346 /** 347 * hal_tx_desc_set_encrypt_type - Sets the Encrypt Type in Tx Descriptor 348 * @desc: Handle to Tx Descriptor 349 * @type: Encrypt Type 350 * 351 * Return: void 352 */ 353 static inline void hal_tx_desc_set_encrypt_type(void *desc, 354 enum hal_tx_encrypt_type type) 355 { 356 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCRYPT_TYPE) |= 357 HAL_TX_SM(TCL_DATA_CMD_2, ENCRYPT_TYPE, type); 358 } 359 360 /** 361 * hal_tx_desc_set_addr_search_flags - Enable AddrX and AddrY search flags 362 * @desc: Handle to Tx Descriptor 363 * @flags: Bit 0 - AddrY search enable, Bit 1 - AddrX search enable 364 * 365 * Return: void 366 */ 367 static inline void hal_tx_desc_set_addr_search_flags(void *desc, 368 uint8_t flags) 369 { 370 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRX_EN) |= 371 HAL_TX_SM(TCL_DATA_CMD_2, ADDRX_EN, (flags & 0x1)); 372 373 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRY_EN) |= 374 HAL_TX_SM(TCL_DATA_CMD_2, ADDRY_EN, (flags >> 1)); 375 } 376 377 /** 378 * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags 379 * Tx Descriptor for MSDU_buffer type 380 * @desc: Handle to Tx Descriptor 381 * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits) 382 * 383 * Return: void 384 */ 385 static inline void hal_tx_desc_set_l4_checksum_en(void *desc, 386 uint8_t en) 387 { 388 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 389 (HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV4_CHECKSUM_EN, en) | 390 HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV6_CHECKSUM_EN, en) | 391 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV4_CHECKSUM_EN, en) | 392 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV6_CHECKSUM_EN, en)); 393 } 394 395 /** 396 * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in 397 * Tx Descriptor for MSDU_buffer type 398 * @desc: Handle to Tx Descriptor 399 * @checksum_en_flags: ipv4 checksum enable flags 400 * 401 * Return: void 402 */ 403 static inline void hal_tx_desc_set_l3_checksum_en(void *desc, 404 uint8_t en) 405 { 406 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 407 HAL_TX_SM(TCL_DATA_CMD_3, IPV4_CHECKSUM_EN, en); 408 } 409 410 /** 411 * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor 412 * @desc:Handle to Tx Descriptor 413 * @metadata: Metadata to be sent to Firmware 414 * 415 * Return: void 416 */ 417 static inline void hal_tx_desc_set_fw_metadata(void *desc, 418 uint16_t metadata) 419 { 420 HAL_SET_FLD(desc, TCL_DATA_CMD_2, TCL_CMD_NUMBER) |= 421 HAL_TX_SM(TCL_DATA_CMD_2, TCL_CMD_NUMBER, metadata); 422 } 423 424 /** 425 * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor. 426 * @desc:Handle to Tx Descriptor 427 * @to_fw: if set, Forward packet to FW along with classification result 428 * 429 * Return: void 430 */ 431 static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw) 432 { 433 HAL_SET_FLD(desc, TCL_DATA_CMD_3, TO_FW) |= 434 HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw); 435 } 436 437 /** 438 * hal_tx_desc_set_dscp_tid_table_id - Sets DSCP to TID conversion table ID 439 * @desc: Handle to Tx Descriptor 440 * @id: DSCP to tid conversion table to be used for this frame 441 * 442 * Return: void 443 */ 444 static inline void hal_tx_desc_set_dscp_tid_table_id(void *desc, 445 uint8_t id) 446 { 447 HAL_SET_FLD(desc, TCL_DATA_CMD_3, 448 DSCP_TO_TID_PRIORITY_TABLE_ID) |= 449 HAL_TX_SM(TCL_DATA_CMD_3, 450 DSCP_TO_TID_PRIORITY_TABLE_ID, id); 451 } 452 453 /** 454 * hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor 455 * @desc: Handle to Tx Descriptor 456 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 457 * enabling the interpretation of the 'Mesh Control Present' bit 458 * (bit 8) of QoS Control (otherwise this bit is ignored), 459 * For native WiFi frames, this indicates that a 'Mesh Control' field 460 * is present between the header and the LLC. 461 * 462 * Return: void 463 */ 464 static inline void hal_tx_desc_set_mesh_en(void *desc, uint8_t en) 465 { 466 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 467 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 468 } 469 470 /** 471 * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in 472 * frame) to be used for Tx Frame 473 * @desc: Handle to Tx Descriptor 474 * @hlos_tid: HLOS TID 475 * 476 * Return: void 477 */ 478 static inline void hal_tx_desc_set_hlos_tid(void *desc, 479 uint8_t hlos_tid) 480 { 481 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID) |= 482 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID, hlos_tid); 483 484 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |= 485 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1); 486 } 487 488 /** 489 * hal_tx_desc_sync - Commit the descriptor to Hardware 490 * @hal_tx_des_cached: Cached descriptor that software maintains 491 * @hw_desc: Hardware descriptor to be updated 492 */ 493 static inline void hal_tx_desc_sync(void *hal_tx_desc_cached, 494 void *hw_desc) 495 { 496 qdf_mem_copy((hw_desc + sizeof(struct tlv_32_hdr)), 497 hal_tx_desc_cached, 20); 498 } 499 500 /*--------------------------------------------------------------------------- 501 Tx MSDU Extension Descriptor accessor APIs 502 ---------------------------------------------------------------------------*/ 503 /** 504 * hal_tx_ext_desc_set_tso_enable() - Set TSO Enable Flag 505 * @desc: Handle to Tx MSDU Extension Descriptor 506 * @tso_en: bool value set to true if TSO is enabled 507 * 508 * Return: none 509 */ 510 static inline void hal_tx_ext_desc_set_tso_enable(void *desc, 511 uint8_t tso_en) 512 { 513 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TSO_ENABLE) |= 514 HAL_TX_SM(TX_MSDU_EXTENSION_0, TSO_ENABLE, tso_en); 515 } 516 517 /** 518 * hal_tx_ext_desc_set_checksum_en() - Enable HW Checksum offload 519 * @desc: Handle to Tx MSDU Extension Descriptor 520 * @en: Checksum offload enable 521 * 522 * Return: none 523 */ 524 static inline void hal_tx_ext_desc_set_checksum_en(void *desc, 525 uint8_t en) 526 { 527 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, IPV4_CHECKSUM_EN) |= 528 ((HAL_TX_SM(TX_MSDU_EXTENSION_0, IPV4_CHECKSUM_EN, en)) | 529 (HAL_TX_SM(TX_MSDU_EXTENSION_0, UDP_OVER_IPV4_CHECKSUM_EN, en)) | 530 (HAL_TX_SM(TX_MSDU_EXTENSION_0, UDP_OVER_IPV6_CHECKSUM_EN, en)) | 531 (HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_OVER_IPV4_CHECKSUM_EN, en)) | 532 (HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_OVER_IPV6_CHECKSUM_EN, en))); 533 } 534 535 /** 536 * hal_tx_ext_desc_set_tcp_flags() - Enable HW Checksum offload 537 * @desc: Handle to Tx MSDU Extension Descriptor 538 * @tcp_flags: TCP flags {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 539 * @mask: TCP flag mask. Tcp_flag is inserted into the header 540 * based on the mask, if tso is enabled 541 * 542 * Return: none 543 */ 544 static inline void hal_tx_ext_desc_set_tcp_flags(void *desc, 545 uint16_t tcp_flags, 546 uint16_t mask) 547 { 548 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TCP_FLAG) |= 549 ((HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG, tcp_flags)) | 550 (HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG_MASK, mask))); 551 } 552 553 /** 554 * hal_tx_ext_desc_set_msdu_length() - Set L2 and IP Lengths 555 * @desc: Handle to Tx MSDU Extension Descriptor 556 * @l2_len: L2 length for the msdu, if tso is enabled 557 * @ip_len: IP length for the msdu, if tso is enabled 558 * 559 * Return: none 560 */ 561 static inline void hal_tx_ext_desc_set_msdu_length(void *desc, 562 uint16_t l2_len, 563 uint16_t ip_len) 564 { 565 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_1, L2_LENGTH) |= 566 ((HAL_TX_SM(TX_MSDU_EXTENSION_1, L2_LENGTH, l2_len)) | 567 (HAL_TX_SM(TX_MSDU_EXTENSION_1, IP_LENGTH, ip_len))); 568 } 569 570 /** 571 * hal_tx_ext_desc_set_tcp_seq() - Set TCP Sequence number 572 * @desc: Handle to Tx MSDU Extension Descriptor 573 * @seq_num: Tcp_seq_number for the msdu, if tso is enabled 574 * 575 * Return: none 576 */ 577 static inline void hal_tx_ext_desc_set_tcp_seq(void *desc, 578 uint32_t seq_num) 579 { 580 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER) |= 581 ((HAL_TX_SM(TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER, seq_num))); 582 } 583 584 /** 585 * hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment 586 * @desc: Handle to Tx MSDU Extension Descriptor 587 * @frag_num: Fragment number (value can be 0 to 5) 588 * @paddr_lo: Lower 32-bit of Buffer Physical address 589 * @paddr_hi: Upper 32-bit of Buffer Physical address 590 * @length: Buffer Length 591 * 592 * Return: none 593 */ 594 static inline void hal_tx_ext_desc_set_buffer(void *desc, 595 uint8_t frag_num, 596 uint32_t paddr_lo, 597 uint16_t paddr_hi, 598 uint16_t length) 599 { 600 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, 601 (frag_num << 3)) |= 602 ((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo))); 603 604 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32, 605 (frag_num << 3)) |= 606 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_PTR_39_32, 607 (paddr_hi)))); 608 609 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_LEN, 610 (frag_num << 3)) |= 611 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length))); 612 } 613 614 /** 615 * hal_tx_ext_desc_set_buffer0_param() - Set Buffer 0 Pointer and Length 616 * @desc: Handle to Tx MSDU Extension Descriptor 617 * @paddr_lo: Lower 32-bit of Buffer Physical address 618 * @paddr_hi: Upper 32-bit of Buffer Physical address 619 * @length: Buffer 0 Length 620 * 621 * Return: none 622 */ 623 static inline void hal_tx_ext_desc_set_buffer0_param(void *desc, 624 uint32_t paddr_lo, 625 uint16_t paddr_hi, 626 uint16_t length) 627 { 628 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0) |= 629 ((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo))); 630 631 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32) |= 632 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, 633 BUF0_PTR_39_32, paddr_hi))); 634 635 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_LEN) |= 636 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length))); 637 } 638 639 /** 640 * hal_tx_ext_desc_set_buffer1_param() - Set Buffer 1 Pointer and Length 641 * @desc: Handle to Tx MSDU Extension Descriptor 642 * @paddr_lo: Lower 32-bit of Buffer Physical address 643 * @paddr_hi: Upper 32-bit of Buffer Physical address 644 * @length: Buffer 1 Length 645 * 646 * Return: none 647 */ 648 static inline void hal_tx_ext_desc_set_buffer1_param(void *desc, 649 uint32_t paddr_lo, 650 uint16_t paddr_hi, 651 uint16_t length) 652 { 653 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_8, BUF1_PTR_31_0) |= 654 ((HAL_TX_SM(TX_MSDU_EXTENSION_8, BUF1_PTR_31_0, paddr_lo))); 655 656 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_PTR_39_32) |= 657 ((HAL_TX_SM(TX_MSDU_EXTENSION_9, 658 BUF1_PTR_39_32, paddr_hi))); 659 660 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_LEN) |= 661 ((HAL_TX_SM(TX_MSDU_EXTENSION_9, BUF1_LEN, length))); 662 } 663 664 /** 665 * hal_tx_ext_desc_set_buffer2_param() - Set Buffer 2 Pointer and Length 666 * @desc: Handle to Tx MSDU Extension Descriptor 667 * @paddr_lo: Lower 32-bit of Buffer Physical address 668 * @paddr_hi: Upper 32-bit of Buffer Physical address 669 * @length: Buffer 2 Length 670 * 671 * Return: none 672 */ 673 static inline void hal_tx_ext_desc_set_buffer2_param(void *desc, 674 uint32_t paddr_lo, 675 uint16_t paddr_hi, 676 uint16_t length) 677 { 678 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_10, BUF2_PTR_31_0) |= 679 ((HAL_TX_SM(TX_MSDU_EXTENSION_10, BUF2_PTR_31_0, 680 paddr_lo))); 681 682 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_PTR_39_32) |= 683 ((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_PTR_39_32, 684 paddr_hi))); 685 686 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_LEN) |= 687 ((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_LEN, length))); 688 } 689 690 /** 691 * hal_tx_ext_desc_sync - Commit the descriptor to Hardware 692 * @desc_cached: Cached descriptor that software maintains 693 * @hw_desc: Hardware descriptor to be updated 694 * 695 * Return: none 696 */ 697 static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached, 698 uint8_t *hw_desc) 699 { 700 qdf_mem_copy(&hw_desc[0], &desc_cached[0], 701 HAL_TX_EXTENSION_DESC_LEN_BYTES); 702 } 703 704 /** 705 * hal_tx_ext_desc_get_tso_enable() - Set TSO Enable Flag 706 * @hal_tx_ext_desc: Handle to Tx MSDU Extension Descriptor 707 * 708 * Return: tso_enable value in the descriptor 709 */ 710 static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc) 711 { 712 uint32_t *desc = (uint32_t *) hal_tx_ext_desc; 713 return (*desc & TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK) >> 714 TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB; 715 } 716 717 /*--------------------------------------------------------------------------- 718 WBM Descriptor accessor APIs for Tx completions 719 ---------------------------------------------------------------------------*/ 720 /** 721 * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor 722 * @hal_desc: completion ring descriptor pointer 723 * 724 * This function will tx descriptor id, cookie, within hardware completion 725 * descriptor 726 * 727 * Return: cookie 728 */ 729 static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc) 730 { 731 uint32_t comp_desc = 732 *(uint32_t *) (((uint8_t *) hal_desc) + 733 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET); 734 735 /* Cookie is placed on 2nd word */ 736 return (comp_desc & BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) >> 737 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB; 738 } 739 740 /** 741 * hal_tx_comp_get_paddr() - Get paddr within comp descriptor 742 * @hal_desc: completion ring descriptor pointer 743 * 744 * This function will get buffer physical address within hardware completion 745 * descriptor 746 * 747 * Return: Buffer physical address 748 */ 749 static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc) 750 { 751 uint32_t paddr_lo; 752 uint32_t paddr_hi; 753 754 paddr_lo = *(uint32_t *) (((uint8_t *) hal_desc) + 755 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET); 756 757 paddr_hi = *(uint32_t *) (((uint8_t *) hal_desc) + 758 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET); 759 760 paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) >> 761 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB; 762 763 return (qdf_dma_addr_t) (paddr_lo | (((uint64_t) paddr_hi) << 32)); 764 } 765 766 /** 767 * hal_tx_comp_get_buffer_source() - Get buffer release source value 768 * @hal_desc: completion ring descriptor pointer 769 * 770 * This function will get buffer release source from Tx completion descriptor 771 * 772 * Return: buffer release source 773 */ 774 static inline uint32_t hal_tx_comp_get_buffer_source(void *hal_desc) 775 { 776 uint32_t comp_desc = 777 *(uint32_t *) (((uint8_t *) hal_desc) + 778 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET); 779 780 return (comp_desc & WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> 781 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB; 782 } 783 784 /** 785 * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type 786 * @hal_desc: completion ring descriptor pointer 787 * 788 * This function will return the type of pointer - buffer or descriptor 789 * 790 * Return: buffer type 791 */ 792 static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc) 793 { 794 uint32_t comp_desc = 795 *(uint32_t *) (((uint8_t *) hal_desc) + 796 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET); 797 798 return (comp_desc & WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> 799 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB; 800 } 801 802 /** 803 * hal_tx_comp_get_release_reason() - TQM Release reason 804 * @hal_desc: completion ring descriptor pointer 805 * 806 * This function will return the type of pointer - buffer or descriptor 807 * 808 * Return: buffer type 809 */ 810 static inline uint8_t hal_tx_comp_get_release_reason(void *hal_desc) 811 { 812 uint32_t comp_desc = 813 *(uint32_t *) (((uint8_t *) hal_desc) + 814 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 815 816 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 817 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 818 } 819 820 /** 821 * hal_tx_comp_get_status() - TQM Release reason 822 * @hal_desc: completion ring Tx status 823 * 824 * This function will parse the WBM completion descriptor and populate in 825 * HAL structure 826 * 827 * Return: none 828 */ 829 #if defined(WCSS_VERSION) && \ 830 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 831 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 832 static inline void hal_tx_comp_get_status(void *desc, 833 struct hal_tx_completion_status *ts) 834 { 835 836 uint8_t rate_stats_valid = 0; 837 uint32_t rate_stats = 0; 838 839 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 840 TQM_STATUS_NUMBER); 841 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 842 ACK_FRAME_RSSI); 843 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 844 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 845 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 846 MSDU_PART_OF_AMSDU); 847 848 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 849 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 850 851 rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_6, 852 TX_RATE_STATS_INFO_TX_RATE_STATS); 853 854 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 855 TX_RATE_STATS_INFO_VALID, rate_stats); 856 857 if (rate_stats_valid) { 858 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 859 rate_stats); 860 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 861 TRANSMIT_PKT_TYPE, rate_stats); 862 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 863 TRANSMIT_STBC, rate_stats); 864 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 865 rate_stats); 866 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 867 rate_stats); 868 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 869 rate_stats); 870 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 871 rate_stats); 872 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 873 rate_stats); 874 } 875 876 ts->tsf = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_6, 877 TX_RATE_STATS_INFO_TX_RATE_STATS); 878 } 879 #else 880 static inline void hal_tx_comp_get_status(void *desc, 881 struct hal_tx_completion_status *ts) 882 { 883 884 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 885 TQM_STATUS_NUMBER); 886 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 887 ACK_FRAME_RSSI); 888 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 889 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 890 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 891 MSDU_PART_OF_AMSDU); 892 } 893 #endif 894 895 /** 896 * hal_tx_comp_desc_sync() - collect hardware descriptor contents 897 * @hal_desc: hardware descriptor pointer 898 * @comp: software descriptor pointer 899 * @read_status: 0 - Do not read status words from descriptors 900 * 1 - Enable reading of status words from descriptor 901 * 902 * This function will collect hardware release ring element contents and 903 * translate to software descriptor content 904 * 905 * Return: none 906 */ 907 908 static inline void hal_tx_comp_desc_sync(void *hw_desc, 909 struct hal_tx_desc_comp_s *comp, 910 bool read_status) 911 { 912 if (!read_status) 913 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_BASE_LEN); 914 else 915 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_LEN_BYTES); 916 } 917 918 /** 919 * hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor 920 * @hal_desc: Hardware (WBM) descriptor pointer 921 * @htt_desc: Software HTT descriptor pointer 922 * 923 * This function will read the HTT structure overlaid on WBM descriptor 924 * into a cached software descriptor 925 * 926 */ 927 static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc) 928 { 929 uint8_t *desc = hw_desc + HAL_TX_COMP_HTT_STATUS_OFFSET; 930 931 qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN); 932 } 933 934 /** 935 * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table 936 * @soc: HAL SoC context 937 * @map: DSCP-TID mapping table 938 * @id: mapping table ID - 0,1 939 * 940 * DSCP are mapped to 8 TID values using TID values programmed 941 * in two set of mapping registers DSCP_TID1_MAP_<0 to 6> (id = 0) 942 * and DSCP_TID2_MAP_<0 to 6> (id = 1) 943 * Each mapping register has TID mapping for 10 DSCP values 944 * 945 * Return: none 946 */ 947 static inline void hal_tx_set_dscp_tid_map(void *hal_soc, uint8_t *map, 948 uint8_t id) 949 { 950 int i; 951 uint32_t addr; 952 uint32_t value; 953 954 struct hal_soc *soc = (struct hal_soc *)hal_soc; 955 956 if (id == HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT) { 957 addr = 958 HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR( 959 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 960 } else { 961 addr = 962 HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR( 963 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 964 } 965 966 for (i = 0; i < 64; i += 10) { 967 value = (map[i] | 968 (map[i+1] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_1_SHFT) | 969 (map[i+2] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_2_SHFT) | 970 (map[i+3] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_3_SHFT) | 971 (map[i+4] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_4_SHFT) | 972 (map[i+5] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_5_SHFT) | 973 (map[i+6] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_6_SHFT) | 974 (map[i+7] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_7_SHFT) | 975 (map[i+8] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_8_SHFT) | 976 (map[i+9] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_SHFT)); 977 978 HAL_REG_WRITE(soc, addr, 979 (value & HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK)); 980 981 addr += 4; 982 } 983 } 984 985 /** 986 * hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG 987 * @hal_soc: Handle to HAL SoC structure 988 * @hal_srng: Handle to HAL SRNG structure 989 * 990 * Return: none 991 */ 992 static inline void hal_tx_init_data_ring(void *hal_soc, void *hal_srng) 993 { 994 uint8_t *desc_addr; 995 struct hal_srng_params srng_params; 996 uint32_t desc_size; 997 uint32_t num_desc; 998 999 hal_get_srng_params(hal_soc, hal_srng, &srng_params); 1000 1001 desc_addr = (uint8_t *) srng_params.ring_base_vaddr; 1002 desc_size = sizeof(struct tcl_data_cmd); 1003 num_desc = srng_params.num_entries; 1004 1005 while (num_desc) { 1006 HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, 1007 desc_size); 1008 desc_addr += (desc_size + sizeof(struct tlv_32_hdr)); 1009 num_desc--; 1010 } 1011 } 1012 #endif /* HAL_TX_H */ 1013