1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #if !defined(HAL_TX_H) 20 #define HAL_TX_H 21 22 /*--------------------------------------------------------------------------- 23 Include files 24 ---------------------------------------------------------------------------*/ 25 #include "hal_api.h" 26 #include "wcss_version.h" 27 28 #define WBM_RELEASE_RING_5_TX_RATE_STATS_OFFSET 0x00000014 29 #define WBM_RELEASE_RING_5_TX_RATE_STATS_LSB 0 30 #define WBM_RELEASE_RING_5_TX_RATE_STATS_MASK 0xffffffff 31 32 33 /*--------------------------------------------------------------------------- 34 Preprocessor definitions and constants 35 ---------------------------------------------------------------------------*/ 36 #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET 37 38 #define HAL_SET_FLD(desc, block , field) \ 39 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field))) 40 41 #define HAL_SET_FLD_OFFSET(desc, block , field, offset) \ 42 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field) + (offset))) 43 44 #define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \ 45 do { \ 46 ((struct tlv_32_hdr *) desc)->tlv_tag = (tag); \ 47 ((struct tlv_32_hdr *) desc)->tlv_len = (len); \ 48 } while (0) 49 50 #define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E 51 #define HAL_TX_TCL_CMD_TAG WIFITCL_GSE_CMD_E 52 53 #define HAL_TX_SM(block, field, value) \ 54 ((value << (block ## _ ## field ## _LSB)) & \ 55 (block ## _ ## field ## _MASK)) 56 57 #define HAL_TX_MS(block, field, value) \ 58 (((value) & (block ## _ ## field ## _MASK)) >> \ 59 (block ## _ ## field ## _LSB)) 60 61 #define HAL_TX_DESC_GET(desc, block, field) \ 62 HAL_TX_MS(block, field, HAL_SET_FLD(desc, block, field)) 63 64 #define HAL_TX_DESC_SUBBLOCK_GET(desc, block, sub, field) \ 65 HAL_TX_MS(sub, field, HAL_SET_FLD(desc, block, sub)) 66 67 #define HAL_TX_BUF_TYPE_BUFFER 0 68 #define HAL_TX_BUF_TYPE_EXT_DESC 1 69 70 #define HAL_TX_DESC_LEN_DWORDS (NUM_OF_DWORDS_TCL_DATA_CMD) 71 #define HAL_TX_DESC_LEN_BYTES (NUM_OF_DWORDS_TCL_DATA_CMD * 4) 72 #define HAL_TX_EXTENSION_DESC_LEN_DWORDS (NUM_OF_DWORDS_TX_MSDU_EXTENSION) 73 #define HAL_TX_EXTENSION_DESC_LEN_BYTES (NUM_OF_DWORDS_TX_MSDU_EXTENSION * 4) 74 75 #define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 76 #define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4) 77 #define HAL_TX_BITS_PER_TID 3 78 #define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1) 79 #define HAL_TX_NUM_DSCP_PER_REGISTER 10 80 #define HAL_MAX_HW_DSCP_TID_MAPS 2 81 #define HAL_MAX_HW_DSCP_TID_MAPS_11AX 32 82 83 #define HTT_META_HEADER_LEN_BYTES 64 84 #define HAL_TX_EXT_DESC_WITH_META_DATA \ 85 (HTT_META_HEADER_LEN_BYTES + HAL_TX_EXTENSION_DESC_LEN_BYTES) 86 87 /* Length of WBM release ring without the status words */ 88 #define HAL_TX_COMPLETION_DESC_BASE_LEN 12 89 90 #define HAL_TX_COMP_RELEASE_SOURCE_TQM 0 91 #define HAL_TX_COMP_RELEASE_SOURCE_FW 3 92 93 /* Define a place-holder release reason for FW */ 94 #define HAL_TX_COMP_RELEASE_REASON_FW 99 95 96 /* 97 * Offset of HTT Tx Descriptor in WBM Completion 98 * HTT Tx Desc structure is passed from firmware to host overlayed 99 * on wbm_release_ring DWORDs 2,3 ,4 and 5for software based completions 100 * (Exception frames and TQM bypass frames) 101 */ 102 #define HAL_TX_COMP_HTT_STATUS_OFFSET 8 103 #define HAL_TX_COMP_HTT_STATUS_LEN 16 104 105 #define HAL_TX_BUF_TYPE_BUFFER 0 106 #define HAL_TX_BUF_TYPE_EXT_DESC 1 107 108 #define HAL_TX_EXT_DESC_BUF_OFFSET TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 109 #define HAL_TX_EXT_BUF_LOW_MASK TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 110 #define HAL_TX_EXT_BUF_HI_MASK TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 111 #define HAL_TX_EXT_BUF_LEN_MASK TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 112 #define HAL_TX_EXT_BUF_LEN_LSB TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 113 #define HAL_TX_EXT_BUF_WD_SIZE 2 114 115 #define HAL_TX_DESC_ADDRX_EN 0x1 116 #define HAL_TX_DESC_ADDRY_EN 0x2 117 #define HAL_TX_DESC_DEFAULT_LMAC_ID 0x3 118 119 enum hal_tx_ret_buf_manager { 120 HAL_WBM_SW0_BM_ID = 3, 121 HAL_WBM_SW1_BM_ID = 4, 122 HAL_WBM_SW2_BM_ID = 5, 123 HAL_WBM_SW3_BM_ID = 6, 124 }; 125 126 /*--------------------------------------------------------------------------- 127 Structures 128 ---------------------------------------------------------------------------*/ 129 /** 130 * struct hal_tx_completion_status - HAL Tx completion descriptor contents 131 * @status: frame acked/failed 132 * @release_src: release source = TQM/FW 133 * @ack_frame_rssi: RSSI of the received ACK or BA frame 134 * @first_msdu: Indicates this MSDU is the first MSDU in AMSDU 135 * @last_msdu: Indicates this MSDU is the last MSDU in AMSDU 136 * @msdu_part_of_amsdu : Indicates this MSDU was part of an A-MSDU in MPDU 137 * @bw: Indicates the BW of the upcoming transmission - 138 * <enum 0 transmit_bw_20_MHz> 139 * <enum 1 transmit_bw_40_MHz> 140 * <enum 2 transmit_bw_80_MHz> 141 * <enum 3 transmit_bw_160_MHz> 142 * @pkt_type: Transmit Packet Type 143 * @stbc: When set, STBC transmission rate was used 144 * @ldpc: When set, use LDPC transmission rates 145 * @sgi: <enum 0 0_8_us_sgi > Legacy normal GI 146 * <enum 1 0_4_us_sgi > Legacy short GI 147 * <enum 2 1_6_us_sgi > HE related GI 148 * <enum 3 3_2_us_sgi > HE 149 * @mcs: Transmit MCS Rate 150 * @ofdma: Set when the transmission was an OFDMA transmission 151 * @tones_in_ru: The number of tones in the RU used. 152 * @tsf: Lower 32 bits of the TSF 153 * @ppdu_id: TSF, snapshot of this value when transmission of the 154 * PPDU containing the frame finished. 155 * @transmit_cnt: Number of times this frame has been transmitted 156 * @tid: TID of the flow or MPDU queue 157 * @peer_id: Peer ID of the flow or MPDU queue 158 */ 159 struct hal_tx_completion_status { 160 uint8_t status; 161 uint8_t release_src; 162 uint8_t ack_frame_rssi; 163 uint8_t first_msdu:1, 164 last_msdu:1, 165 msdu_part_of_amsdu:1; 166 uint32_t bw:2, 167 pkt_type:4, 168 stbc:1, 169 ldpc:1, 170 sgi:2, 171 mcs:4, 172 ofdma:1, 173 tones_in_ru:12, 174 valid:1; 175 uint32_t tsf; 176 uint32_t ppdu_id; 177 uint8_t transmit_cnt; 178 uint8_t tid; 179 uint16_t peer_id; 180 }; 181 182 /** 183 * struct hal_tx_desc_comp_s - hal tx completion descriptor contents 184 * @desc: Transmit status information from descriptor 185 */ 186 struct hal_tx_desc_comp_s { 187 uint32_t desc[HAL_TX_COMPLETION_DESC_LEN_DWORDS]; 188 }; 189 190 /* 191 * enum hal_tx_encrypt_type - Type of decrypt cipher used (valid only for RAW) 192 * @HAL_TX_ENCRYPT_TYPE_WEP_40: WEP 40-bit 193 * @HAL_TX_ENCRYPT_TYPE_WEP_10: WEP 10-bit 194 * @HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC: TKIP without MIC 195 * @HAL_TX_ENCRYPT_TYPE_WEP_128: WEP_128 196 * @HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC: TKIP_WITH_MIC 197 * @HAL_TX_ENCRYPT_TYPE_WAPI: WAPI 198 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_128: AES_CCMP_128 199 * @HAL_TX_ENCRYPT_TYPE_NO_CIPHER: NO CIPHER 200 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_256: AES_CCMP_256 201 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_128: AES_GCMP_128 202 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_256: AES_GCMP_256 203 * @HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4: WAPI GCM SM4 204 */ 205 enum hal_tx_encrypt_type { 206 HAL_TX_ENCRYPT_TYPE_WEP_40 = 0, 207 HAL_TX_ENCRYPT_TYPE_WEP_104 = 1 , 208 HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC = 2, 209 HAL_TX_ENCRYPT_TYPE_WEP_128 = 3, 210 HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC = 4, 211 HAL_TX_ENCRYPT_TYPE_WAPI = 5, 212 HAL_TX_ENCRYPT_TYPE_AES_CCMP_128 = 6, 213 HAL_TX_ENCRYPT_TYPE_NO_CIPHER = 7, 214 HAL_TX_ENCRYPT_TYPE_AES_CCMP_256 = 8, 215 HAL_TX_ENCRYPT_TYPE_AES_GCMP_128 = 9, 216 HAL_TX_ENCRYPT_TYPE_AES_GCMP_256 = 10, 217 HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4 = 11, 218 }; 219 220 /* 221 * enum hal_tx_encap_type - Encapsulation type that HW will perform 222 * @HAL_TX_ENCAP_TYPE_RAW: Raw Packet Type 223 * @HAL_TX_ENCAP_TYPE_NWIFI: Native WiFi Type 224 * @HAL_TX_ENCAP_TYPE_ETHERNET: Ethernet 225 * @HAL_TX_ENCAP_TYPE_802_3: 802.3 Frame 226 */ 227 enum hal_tx_encap_type { 228 HAL_TX_ENCAP_TYPE_RAW = 0, 229 HAL_TX_ENCAP_TYPE_NWIFI = 1, 230 HAL_TX_ENCAP_TYPE_ETHERNET = 2, 231 HAL_TX_ENCAP_TYPE_802_3 = 3, 232 }; 233 234 /** 235 * enum hal_tx_tqm_release_reason - TQM Release reason codes 236 * 237 * @HAL_TX_TQM_RR_FRAME_ACKED : ACK of BA for it was received 238 * @HAL_TX_TQM_RR_REM_CMD_REM : Remove cmd of type “Remove_mpdus” initiated 239 * by SW 240 * @HAL_TX_TQM_RR_REM_CMD_TX : Remove command of type Remove_transmitted_mpdus 241 * initiated by SW 242 * @HAL_TX_TQM_RR_REM_CMD_NOTX : Remove cmd of type Remove_untransmitted_mpdus 243 * initiated by SW 244 * @HAL_TX_TQM_RR_REM_CMD_AGED : Remove command of type “Remove_aged_mpdus” or 245 * “Remove_aged_msdus” initiated by SW 246 * @HAL_TX_TQM_RR_FW_REASON1 : Remove command where fw indicated that 247 * remove reason is fw_reason1 248 * @HAL_TX_TQM_RR_FW_REASON2 : Remove command where fw indicated that 249 * remove reason is fw_reason2 250 * @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that 251 * remove reason is fw_reason3 252 */ 253 enum hal_tx_tqm_release_reason { 254 HAL_TX_TQM_RR_FRAME_ACKED, 255 HAL_TX_TQM_RR_REM_CMD_REM, 256 HAL_TX_TQM_RR_REM_CMD_TX, 257 HAL_TX_TQM_RR_REM_CMD_NOTX, 258 HAL_TX_TQM_RR_REM_CMD_AGED, 259 HAL_TX_TQM_RR_FW_REASON1, 260 HAL_TX_TQM_RR_FW_REASON2, 261 HAL_TX_TQM_RR_FW_REASON3, 262 }; 263 264 /* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports 265 * @HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT: Default DSCP-TID mapping table 266 * @HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE: DSCP-TID map override table 267 */ 268 enum hal_tx_dscp_tid_table_id { 269 HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT, 270 HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE, 271 }; 272 273 /*--------------------------------------------------------------------------- 274 Function declarations and documentation 275 ---------------------------------------------------------------------------*/ 276 277 /*--------------------------------------------------------------------------- 278 TCL Descriptor accessor APIs 279 ---------------------------------------------------------------------------*/ 280 /** 281 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 282 * @desc: Handle to Tx Descriptor 283 * @paddr: Physical Address 284 * @pool_id: Return Buffer Manager ID 285 * @desc_id: Descriptor ID 286 * @type: 0 - Address points to a MSDU buffer 287 * 1 - Address points to MSDU extension descriptor 288 * 289 * Return: void 290 */ 291 static inline void hal_tx_desc_set_buf_addr(void *desc, 292 dma_addr_t paddr, uint8_t pool_id, 293 uint32_t desc_id, uint8_t type) 294 { 295 /* Set buffer_addr_info.buffer_addr_31_0 */ 296 HAL_SET_FLD(desc, TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) = 297 HAL_TX_SM(BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); 298 299 /* Set buffer_addr_info.buffer_addr_39_32 */ 300 HAL_SET_FLD(desc, TCL_DATA_CMD_1, 301 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 302 HAL_TX_SM(BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 303 (((uint64_t) paddr) >> 32)); 304 305 /* Set buffer_addr_info.return_buffer_manager = pool id */ 306 HAL_SET_FLD(desc, TCL_DATA_CMD_1, 307 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 308 HAL_TX_SM(BUFFER_ADDR_INFO_1, 309 RETURN_BUFFER_MANAGER, (pool_id + HAL_WBM_SW0_BM_ID)); 310 311 /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ 312 HAL_SET_FLD(desc, TCL_DATA_CMD_1, 313 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= 314 HAL_TX_SM(BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id); 315 316 /* Set Buffer or Ext Descriptor Type */ 317 HAL_SET_FLD(desc, TCL_DATA_CMD_2, 318 BUF_OR_EXT_DESC_TYPE) |= 319 HAL_TX_SM(TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); 320 } 321 322 /** 323 * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor 324 * @desc: Handle to Tx Descriptor 325 * @data_length: MSDU length in case of direct descriptor. 326 * Length of link extension descriptor in case of Link extension 327 * descriptor.Includes the length of Metadata 328 * Return: None 329 */ 330 static inline void hal_tx_desc_set_buf_length(void *desc, 331 uint16_t data_length) 332 { 333 HAL_SET_FLD(desc, TCL_DATA_CMD_3, DATA_LENGTH) |= 334 HAL_TX_SM(TCL_DATA_CMD_3, DATA_LENGTH, data_length); 335 } 336 337 /** 338 * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor 339 * @desc: Handle to Tx Descriptor 340 * @offset: Packet offset from Metadata in case of direct buffer descriptor. 341 * 342 * Return: void 343 */ 344 static inline void hal_tx_desc_set_buf_offset(void *desc, 345 uint8_t offset) 346 { 347 HAL_SET_FLD(desc, TCL_DATA_CMD_3, PACKET_OFFSET) |= 348 HAL_TX_SM(TCL_DATA_CMD_3, PACKET_OFFSET, offset); 349 } 350 351 /** 352 * hal_tx_desc_set_encap_type - Set encapsulation type in Tx Descriptor 353 * @desc: Handle to Tx Descriptor 354 * @encap_type: Encapsulation that HW will perform 355 * 356 * Return: void 357 * 358 */ 359 static inline void hal_tx_desc_set_encap_type(void *desc, 360 enum hal_tx_encap_type encap_type) 361 { 362 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCAP_TYPE) |= 363 HAL_TX_SM(TCL_DATA_CMD_2, ENCAP_TYPE, encap_type); 364 } 365 366 /** 367 * hal_tx_desc_set_encrypt_type - Sets the Encrypt Type in Tx Descriptor 368 * @desc: Handle to Tx Descriptor 369 * @type: Encrypt Type 370 * 371 * Return: void 372 */ 373 static inline void hal_tx_desc_set_encrypt_type(void *desc, 374 enum hal_tx_encrypt_type type) 375 { 376 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCRYPT_TYPE) |= 377 HAL_TX_SM(TCL_DATA_CMD_2, ENCRYPT_TYPE, type); 378 } 379 380 /** 381 * hal_tx_desc_set_addr_search_flags - Enable AddrX and AddrY search flags 382 * @desc: Handle to Tx Descriptor 383 * @flags: Bit 0 - AddrY search enable, Bit 1 - AddrX search enable 384 * 385 * Return: void 386 */ 387 static inline void hal_tx_desc_set_addr_search_flags(void *desc, 388 uint8_t flags) 389 { 390 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRX_EN) |= 391 HAL_TX_SM(TCL_DATA_CMD_2, ADDRX_EN, (flags & 0x1)); 392 393 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRY_EN) |= 394 HAL_TX_SM(TCL_DATA_CMD_2, ADDRY_EN, (flags >> 1)); 395 } 396 397 /** 398 * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags 399 * Tx Descriptor for MSDU_buffer type 400 * @desc: Handle to Tx Descriptor 401 * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits) 402 * 403 * Return: void 404 */ 405 static inline void hal_tx_desc_set_l4_checksum_en(void *desc, 406 uint8_t en) 407 { 408 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 409 (HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV4_CHECKSUM_EN, en) | 410 HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV6_CHECKSUM_EN, en) | 411 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV4_CHECKSUM_EN, en) | 412 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV6_CHECKSUM_EN, en)); 413 } 414 415 /** 416 * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in 417 * Tx Descriptor for MSDU_buffer type 418 * @desc: Handle to Tx Descriptor 419 * @checksum_en_flags: ipv4 checksum enable flags 420 * 421 * Return: void 422 */ 423 static inline void hal_tx_desc_set_l3_checksum_en(void *desc, 424 uint8_t en) 425 { 426 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 427 HAL_TX_SM(TCL_DATA_CMD_3, IPV4_CHECKSUM_EN, en); 428 } 429 430 /** 431 * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor 432 * @desc:Handle to Tx Descriptor 433 * @metadata: Metadata to be sent to Firmware 434 * 435 * Return: void 436 */ 437 static inline void hal_tx_desc_set_fw_metadata(void *desc, 438 uint16_t metadata) 439 { 440 HAL_SET_FLD(desc, TCL_DATA_CMD_2, TCL_CMD_NUMBER) |= 441 HAL_TX_SM(TCL_DATA_CMD_2, TCL_CMD_NUMBER, metadata); 442 } 443 444 /** 445 * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor. 446 * @desc:Handle to Tx Descriptor 447 * @to_fw: if set, Forward packet to FW along with classification result 448 * 449 * Return: void 450 */ 451 static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw) 452 { 453 HAL_SET_FLD(desc, TCL_DATA_CMD_3, TO_FW) |= 454 HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw); 455 } 456 457 /** 458 * hal_tx_desc_set_dscp_tid_table_id - Sets DSCP to TID conversion table ID 459 * @desc: Handle to Tx Descriptor 460 * @id: DSCP to tid conversion table to be used for this frame 461 * 462 * Return: void 463 */ 464 #if !defined(QCA_WIFI_QCA6290_11AX) 465 static inline void hal_tx_desc_set_dscp_tid_table_id(void *desc, 466 uint8_t id) 467 { 468 HAL_SET_FLD(desc, TCL_DATA_CMD_3, 469 DSCP_TO_TID_PRIORITY_TABLE_ID) |= 470 HAL_TX_SM(TCL_DATA_CMD_3, 471 DSCP_TO_TID_PRIORITY_TABLE_ID, id); 472 } 473 #else 474 static inline void hal_tx_desc_set_dscp_tid_table_id(void *desc, 475 uint8_t id) 476 { 477 HAL_SET_FLD(desc, TCL_DATA_CMD_5, 478 DSCP_TID_TABLE_NUM) |= 479 HAL_TX_SM(TCL_DATA_CMD_5, 480 DSCP_TID_TABLE_NUM, id); 481 } 482 #endif 483 484 /** 485 * hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor 486 * @desc: Handle to Tx Descriptor 487 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 488 * enabling the interpretation of the 'Mesh Control Present' bit 489 * (bit 8) of QoS Control (otherwise this bit is ignored), 490 * For native WiFi frames, this indicates that a 'Mesh Control' field 491 * is present between the header and the LLC. 492 * 493 * Return: void 494 */ 495 static inline void hal_tx_desc_set_mesh_en(void *desc, uint8_t en) 496 { 497 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 498 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 499 } 500 501 /** 502 * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in 503 * frame) to be used for Tx Frame 504 * @desc: Handle to Tx Descriptor 505 * @hlos_tid: HLOS TID 506 * 507 * Return: void 508 */ 509 static inline void hal_tx_desc_set_hlos_tid(void *desc, 510 uint8_t hlos_tid) 511 { 512 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID) |= 513 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID, hlos_tid); 514 515 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |= 516 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1); 517 } 518 519 #ifdef QCA_WIFI_QCA6290_11AX 520 /** 521 * hal_tx_desc_set_lmac_id - Set the lmac_id value 522 * @desc: Handle to Tx Descriptor 523 * @lmac_id: mac Id to ast matching 524 * b00 – mac 0 525 * b01 – mac 1 526 * b10 – mac 2 527 * b11 – all macs (legacy HK way) 528 * 529 * Return: void 530 */ 531 static inline void hal_tx_desc_set_lmac_id(void *desc, 532 uint8_t lmac_id) 533 { 534 HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |= 535 HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id); 536 } 537 #else 538 static inline void hal_tx_desc_set_lmac_id(void *desc, 539 uint8_t lmac_id) 540 { 541 } 542 #endif 543 /** 544 * hal_tx_desc_sync - Commit the descriptor to Hardware 545 * @hal_tx_des_cached: Cached descriptor that software maintains 546 * @hw_desc: Hardware descriptor to be updated 547 */ 548 static inline void hal_tx_desc_sync(void *hal_tx_desc_cached, 549 void *hw_desc) 550 { 551 qdf_mem_copy((hw_desc + sizeof(struct tlv_32_hdr)), 552 hal_tx_desc_cached, 20); 553 } 554 555 /*--------------------------------------------------------------------------- 556 Tx MSDU Extension Descriptor accessor APIs 557 ---------------------------------------------------------------------------*/ 558 /** 559 * hal_tx_ext_desc_set_tso_enable() - Set TSO Enable Flag 560 * @desc: Handle to Tx MSDU Extension Descriptor 561 * @tso_en: bool value set to true if TSO is enabled 562 * 563 * Return: none 564 */ 565 static inline void hal_tx_ext_desc_set_tso_enable(void *desc, 566 uint8_t tso_en) 567 { 568 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TSO_ENABLE) |= 569 HAL_TX_SM(TX_MSDU_EXTENSION_0, TSO_ENABLE, tso_en); 570 } 571 572 /** 573 * hal_tx_ext_desc_set_tso_flags() - Set TSO Flags 574 * @desc: Handle to Tx MSDU Extension Descriptor 575 * @falgs: 32-bit word with all TSO flags consolidated 576 * 577 * Return: none 578 */ 579 static inline void hal_tx_ext_desc_set_tso_flags(void *desc, 580 uint32_t tso_flags) 581 { 582 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_0, TSO_ENABLE, 0) = 583 tso_flags; 584 } 585 586 /** 587 * hal_tx_ext_desc_set_tcp_flags() - Enable HW Checksum offload 588 * @desc: Handle to Tx MSDU Extension Descriptor 589 * @tcp_flags: TCP flags {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 590 * @mask: TCP flag mask. Tcp_flag is inserted into the header 591 * based on the mask, if tso is enabled 592 * 593 * Return: none 594 */ 595 static inline void hal_tx_ext_desc_set_tcp_flags(void *desc, 596 uint16_t tcp_flags, 597 uint16_t mask) 598 { 599 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TCP_FLAG) |= 600 ((HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG, tcp_flags)) | 601 (HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG_MASK, mask))); 602 } 603 604 /** 605 * hal_tx_ext_desc_set_msdu_length() - Set L2 and IP Lengths 606 * @desc: Handle to Tx MSDU Extension Descriptor 607 * @l2_len: L2 length for the msdu, if tso is enabled 608 * @ip_len: IP length for the msdu, if tso is enabled 609 * 610 * Return: none 611 */ 612 static inline void hal_tx_ext_desc_set_msdu_length(void *desc, 613 uint16_t l2_len, 614 uint16_t ip_len) 615 { 616 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_1, L2_LENGTH) |= 617 ((HAL_TX_SM(TX_MSDU_EXTENSION_1, L2_LENGTH, l2_len)) | 618 (HAL_TX_SM(TX_MSDU_EXTENSION_1, IP_LENGTH, ip_len))); 619 } 620 621 /** 622 * hal_tx_ext_desc_set_tcp_seq() - Set TCP Sequence number 623 * @desc: Handle to Tx MSDU Extension Descriptor 624 * @seq_num: Tcp_seq_number for the msdu, if tso is enabled 625 * 626 * Return: none 627 */ 628 static inline void hal_tx_ext_desc_set_tcp_seq(void *desc, 629 uint32_t seq_num) 630 { 631 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER) |= 632 ((HAL_TX_SM(TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER, seq_num))); 633 } 634 635 636 /** 637 * hal_tx_ext_desc_set_ip_id() - Set IP Identification field 638 * @desc: Handle to Tx MSDU Extension Descriptor 639 * @id: IP Id field for the msdu, if tso is enabled 640 * 641 * Return: none 642 */ 643 static inline void hal_tx_ext_desc_set_ip_id(void *desc, 644 uint16_t id) 645 { 646 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_3, IP_IDENTIFICATION) |= 647 ((HAL_TX_SM(TX_MSDU_EXTENSION_3, IP_IDENTIFICATION, id))); 648 } 649 /** 650 * hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment 651 * @desc: Handle to Tx MSDU Extension Descriptor 652 * @frag_num: Fragment number (value can be 0 to 5) 653 * @paddr_lo: Lower 32-bit of Buffer Physical address 654 * @paddr_hi: Upper 32-bit of Buffer Physical address 655 * @length: Buffer Length 656 * 657 * Return: none 658 */ 659 static inline void hal_tx_ext_desc_set_buffer(void *desc, 660 uint8_t frag_num, 661 uint32_t paddr_lo, 662 uint16_t paddr_hi, 663 uint16_t length) 664 { 665 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, 666 (frag_num << 3)) |= 667 ((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo))); 668 669 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32, 670 (frag_num << 3)) |= 671 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_PTR_39_32, 672 (paddr_hi)))); 673 674 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_LEN, 675 (frag_num << 3)) |= 676 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length))); 677 } 678 679 /** 680 * hal_tx_ext_desc_set_buffer0_param() - Set Buffer 0 Pointer and Length 681 * @desc: Handle to Tx MSDU Extension Descriptor 682 * @paddr_lo: Lower 32-bit of Buffer Physical address 683 * @paddr_hi: Upper 32-bit of Buffer Physical address 684 * @length: Buffer 0 Length 685 * 686 * Return: none 687 */ 688 static inline void hal_tx_ext_desc_set_buffer0_param(void *desc, 689 uint32_t paddr_lo, 690 uint16_t paddr_hi, 691 uint16_t length) 692 { 693 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0) |= 694 ((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo))); 695 696 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32) |= 697 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, 698 BUF0_PTR_39_32, paddr_hi))); 699 700 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_LEN) |= 701 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length))); 702 } 703 704 /** 705 * hal_tx_ext_desc_set_buffer1_param() - Set Buffer 1 Pointer and Length 706 * @desc: Handle to Tx MSDU Extension Descriptor 707 * @paddr_lo: Lower 32-bit of Buffer Physical address 708 * @paddr_hi: Upper 32-bit of Buffer Physical address 709 * @length: Buffer 1 Length 710 * 711 * Return: none 712 */ 713 static inline void hal_tx_ext_desc_set_buffer1_param(void *desc, 714 uint32_t paddr_lo, 715 uint16_t paddr_hi, 716 uint16_t length) 717 { 718 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_8, BUF1_PTR_31_0) |= 719 ((HAL_TX_SM(TX_MSDU_EXTENSION_8, BUF1_PTR_31_0, paddr_lo))); 720 721 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_PTR_39_32) |= 722 ((HAL_TX_SM(TX_MSDU_EXTENSION_9, 723 BUF1_PTR_39_32, paddr_hi))); 724 725 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_LEN) |= 726 ((HAL_TX_SM(TX_MSDU_EXTENSION_9, BUF1_LEN, length))); 727 } 728 729 /** 730 * hal_tx_ext_desc_set_buffer2_param() - Set Buffer 2 Pointer and Length 731 * @desc: Handle to Tx MSDU Extension Descriptor 732 * @paddr_lo: Lower 32-bit of Buffer Physical address 733 * @paddr_hi: Upper 32-bit of Buffer Physical address 734 * @length: Buffer 2 Length 735 * 736 * Return: none 737 */ 738 static inline void hal_tx_ext_desc_set_buffer2_param(void *desc, 739 uint32_t paddr_lo, 740 uint16_t paddr_hi, 741 uint16_t length) 742 { 743 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_10, BUF2_PTR_31_0) |= 744 ((HAL_TX_SM(TX_MSDU_EXTENSION_10, BUF2_PTR_31_0, 745 paddr_lo))); 746 747 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_PTR_39_32) |= 748 ((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_PTR_39_32, 749 paddr_hi))); 750 751 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_LEN) |= 752 ((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_LEN, length))); 753 } 754 755 /** 756 * hal_tx_ext_desc_sync - Commit the descriptor to Hardware 757 * @desc_cached: Cached descriptor that software maintains 758 * @hw_desc: Hardware descriptor to be updated 759 * 760 * Return: none 761 */ 762 static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached, 763 uint8_t *hw_desc) 764 { 765 qdf_mem_copy(&hw_desc[0], &desc_cached[0], 766 HAL_TX_EXT_DESC_WITH_META_DATA); 767 } 768 769 /** 770 * hal_tx_ext_desc_get_tso_enable() - Set TSO Enable Flag 771 * @hal_tx_ext_desc: Handle to Tx MSDU Extension Descriptor 772 * 773 * Return: tso_enable value in the descriptor 774 */ 775 static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc) 776 { 777 uint32_t *desc = (uint32_t *) hal_tx_ext_desc; 778 return (*desc & TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK) >> 779 TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB; 780 } 781 782 /*--------------------------------------------------------------------------- 783 WBM Descriptor accessor APIs for Tx completions 784 ---------------------------------------------------------------------------*/ 785 /** 786 * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor 787 * @hal_desc: completion ring descriptor pointer 788 * 789 * This function will tx descriptor id, cookie, within hardware completion 790 * descriptor 791 * 792 * Return: cookie 793 */ 794 static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc) 795 { 796 uint32_t comp_desc = 797 *(uint32_t *) (((uint8_t *) hal_desc) + 798 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET); 799 800 /* Cookie is placed on 2nd word */ 801 return (comp_desc & BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) >> 802 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB; 803 } 804 805 /** 806 * hal_tx_comp_get_paddr() - Get paddr within comp descriptor 807 * @hal_desc: completion ring descriptor pointer 808 * 809 * This function will get buffer physical address within hardware completion 810 * descriptor 811 * 812 * Return: Buffer physical address 813 */ 814 static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc) 815 { 816 uint32_t paddr_lo; 817 uint32_t paddr_hi; 818 819 paddr_lo = *(uint32_t *) (((uint8_t *) hal_desc) + 820 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET); 821 822 paddr_hi = *(uint32_t *) (((uint8_t *) hal_desc) + 823 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET); 824 825 paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) >> 826 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB; 827 828 return (qdf_dma_addr_t) (paddr_lo | (((uint64_t) paddr_hi) << 32)); 829 } 830 831 /** 832 * hal_tx_comp_get_buffer_source() - Get buffer release source value 833 * @hal_desc: completion ring descriptor pointer 834 * 835 * This function will get buffer release source from Tx completion descriptor 836 * 837 * Return: buffer release source 838 */ 839 static inline uint32_t hal_tx_comp_get_buffer_source(void *hal_desc) 840 { 841 uint32_t comp_desc = 842 *(uint32_t *) (((uint8_t *) hal_desc) + 843 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET); 844 845 return (comp_desc & WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> 846 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB; 847 } 848 849 /** 850 * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type 851 * @hal_desc: completion ring descriptor pointer 852 * 853 * This function will return the type of pointer - buffer or descriptor 854 * 855 * Return: buffer type 856 */ 857 static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc) 858 { 859 uint32_t comp_desc = 860 *(uint32_t *) (((uint8_t *) hal_desc) + 861 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET); 862 863 return (comp_desc & WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> 864 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB; 865 } 866 867 /** 868 * hal_tx_comp_get_release_reason() - TQM Release reason 869 * @hal_desc: completion ring descriptor pointer 870 * 871 * This function will return the type of pointer - buffer or descriptor 872 * 873 * Return: buffer type 874 */ 875 static inline uint8_t hal_tx_comp_get_release_reason(void *hal_desc) 876 { 877 uint32_t comp_desc = 878 *(uint32_t *) (((uint8_t *) hal_desc) + 879 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 880 881 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 882 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 883 } 884 885 /** 886 * hal_tx_comp_get_status() - TQM Release reason 887 * @hal_desc: completion ring Tx status 888 * 889 * This function will parse the WBM completion descriptor and populate in 890 * HAL structure 891 * 892 * Return: none 893 */ 894 #if defined(WCSS_VERSION) && \ 895 ((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \ 896 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72))) 897 static inline void hal_tx_comp_get_status(void *desc, 898 struct hal_tx_completion_status *ts) 899 { 900 uint8_t rate_stats_valid = 0; 901 uint32_t rate_stats = 0; 902 903 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 904 TQM_STATUS_NUMBER); 905 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 906 ACK_FRAME_RSSI); 907 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 908 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 909 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 910 MSDU_PART_OF_AMSDU); 911 912 ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID); 913 ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID); 914 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 915 TRANSMIT_COUNT); 916 917 rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_5, 918 TX_RATE_STATS); 919 920 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0, 921 TX_RATE_STATS_INFO_VALID, rate_stats); 922 923 ts->valid = rate_stats_valid; 924 925 if (rate_stats_valid) { 926 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW, 927 rate_stats); 928 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0, 929 TRANSMIT_PKT_TYPE, rate_stats); 930 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0, 931 TRANSMIT_STBC, rate_stats); 932 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC, 933 rate_stats); 934 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI, 935 rate_stats); 936 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS, 937 rate_stats); 938 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION, 939 rate_stats); 940 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU, 941 rate_stats); 942 } 943 944 ts->release_src = hal_tx_comp_get_buffer_source(desc); 945 ts->status = hal_tx_comp_get_release_reason(desc); 946 947 ts->tsf = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_6, 948 TX_RATE_STATS_INFO_TX_RATE_STATS); 949 } 950 #else 951 static inline void hal_tx_comp_get_status(void *desc, 952 struct hal_tx_completion_status *ts) 953 { 954 955 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3, 956 TQM_STATUS_NUMBER); 957 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 958 ACK_FRAME_RSSI); 959 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU); 960 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU); 961 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, 962 MSDU_PART_OF_AMSDU); 963 964 ts->release_src = hal_tx_comp_get_buffer_source(desc); 965 ts->status = hal_tx_comp_get_release_reason(desc); 966 } 967 #endif 968 969 /** 970 * hal_tx_comp_desc_sync() - collect hardware descriptor contents 971 * @hal_desc: hardware descriptor pointer 972 * @comp: software descriptor pointer 973 * @read_status: 0 - Do not read status words from descriptors 974 * 1 - Enable reading of status words from descriptor 975 * 976 * This function will collect hardware release ring element contents and 977 * translate to software descriptor content 978 * 979 * Return: none 980 */ 981 982 static inline void hal_tx_comp_desc_sync(void *hw_desc, 983 struct hal_tx_desc_comp_s *comp, 984 bool read_status) 985 { 986 if (!read_status) 987 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_BASE_LEN); 988 else 989 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_LEN_BYTES); 990 } 991 992 /** 993 * hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor 994 * @hal_desc: Hardware (WBM) descriptor pointer 995 * @htt_desc: Software HTT descriptor pointer 996 * 997 * This function will read the HTT structure overlaid on WBM descriptor 998 * into a cached software descriptor 999 * 1000 */ 1001 static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc) 1002 { 1003 uint8_t *desc = hw_desc + HAL_TX_COMP_HTT_STATUS_OFFSET; 1004 1005 qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN); 1006 } 1007 1008 #if !defined(QCA_WIFI_QCA6290_11AX) 1009 /** 1010 * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table 1011 * @soc: HAL SoC context 1012 * @map: DSCP-TID mapping table 1013 * @id: mapping table ID - 0,1 1014 * 1015 * DSCP are mapped to 8 TID values using TID values programmed 1016 * in two set of mapping registers DSCP_TID1_MAP_<0 to 6> (id = 0) 1017 * and DSCP_TID2_MAP_<0 to 6> (id = 1) 1018 * Each mapping register has TID mapping for 10 DSCP values 1019 * 1020 * Return: none 1021 */ 1022 static inline void hal_tx_set_dscp_tid_map(void *hal_soc, uint8_t *map, 1023 uint8_t id) 1024 { 1025 int i; 1026 uint32_t addr; 1027 uint32_t value; 1028 1029 struct hal_soc *soc = (struct hal_soc *)hal_soc; 1030 1031 if (id == HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT) { 1032 addr = 1033 HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR( 1034 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 1035 } else { 1036 addr = 1037 HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR( 1038 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 1039 } 1040 1041 for (i = 0; i < 64; i += 10) { 1042 value = (map[i] | 1043 (map[i+1] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_1_SHFT) | 1044 (map[i+2] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_2_SHFT) | 1045 (map[i+3] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_3_SHFT) | 1046 (map[i+4] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_4_SHFT) | 1047 (map[i+5] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_5_SHFT) | 1048 (map[i+6] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_6_SHFT) | 1049 (map[i+7] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_7_SHFT) | 1050 (map[i+8] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_8_SHFT) | 1051 (map[i+9] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_SHFT)); 1052 1053 HAL_REG_WRITE(soc, addr, 1054 (value & HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK)); 1055 1056 addr += 4; 1057 } 1058 } 1059 1060 /** 1061 * hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user 1062 * @soc: HAL SoC context 1063 * @map: DSCP-TID mapping table 1064 * @id : MAP ID 1065 * @dscp: DSCP_TID map index 1066 * 1067 * Return: void 1068 */ 1069 static inline void hal_tx_update_dscp_tid(void *hal_soc, uint8_t tid, 1070 uint8_t id, uint8_t dscp) 1071 { 1072 int index; 1073 uint32_t addr; 1074 uint32_t value; 1075 uint32_t regval; 1076 1077 struct hal_soc *soc = (struct hal_soc *)hal_soc; 1078 1079 if (id == HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT) 1080 addr = 1081 HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR( 1082 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 1083 else 1084 addr = 1085 HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR( 1086 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); 1087 1088 index = dscp % HAL_TX_NUM_DSCP_PER_REGISTER; 1089 addr += 4 * (dscp/HAL_TX_NUM_DSCP_PER_REGISTER); 1090 value = tid << (HAL_TX_BITS_PER_TID * index); 1091 1092 /* Read back previous DSCP TID config and update 1093 * with new config. 1094 */ 1095 regval = HAL_REG_READ(soc, addr); 1096 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * index)); 1097 regval |= value; 1098 1099 HAL_REG_WRITE(soc, addr, 1100 (regval & HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK)); 1101 } 1102 #else 1103 /** 1104 * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table 1105 * @soc: HAL SoC context 1106 * @map: DSCP-TID mapping table 1107 * @id: mapping table ID - 0-31 1108 * 1109 * DSCP are mapped to 8 TID values using TID values programmed 1110 * in any of the 32 DSCP_TID_MAPS (id = 0-31). 1111 * 1112 * Return: none 1113 */ 1114 static inline void hal_tx_set_dscp_tid_map(void *hal_soc, uint8_t *map, 1115 uint8_t id) 1116 { 1117 int i; 1118 uint32_t addr; 1119 uint32_t value; 1120 1121 struct hal_soc *soc = (struct hal_soc *)hal_soc; 1122 1123 if (id >= HAL_MAX_HW_DSCP_TID_MAPS_11AX) { 1124 return; 1125 } 1126 1127 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( 1128 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, id); 1129 1130 for (i = 0; i < 64; i += 10) { 1131 value = (map[i] | 1132 (map[i+1] << 0x3) | 1133 (map[i+2] << 0x6) | 1134 (map[i+3] << 0x9) | 1135 (map[i+4] << 0xc) | 1136 (map[i+5] << 0xf) | 1137 (map[i+6] << 0x12) | 1138 (map[i+7] << 0x15) | 1139 (map[i+8] << 0x18) | 1140 (map[i+9] << 0x1b)); 1141 1142 HAL_REG_WRITE(soc, addr, 1143 (value & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 1144 1145 addr += 4; 1146 } 1147 } 1148 static inline void hal_tx_update_dscp_tid(void *hal_soc, uint8_t tid, 1149 uint8_t id, uint8_t dscp) 1150 { 1151 int index; 1152 uint32_t addr; 1153 uint32_t value; 1154 uint32_t regval; 1155 1156 struct hal_soc *soc = (struct hal_soc *)hal_soc; 1157 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( 1158 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, id); 1159 1160 index = dscp % HAL_TX_NUM_DSCP_PER_REGISTER; 1161 addr += 4 * (dscp/HAL_TX_NUM_DSCP_PER_REGISTER); 1162 value = tid << (HAL_TX_BITS_PER_TID * index); 1163 1164 regval = HAL_REG_READ(soc, addr); 1165 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * index)); 1166 regval |= value; 1167 1168 HAL_REG_WRITE(soc, addr, 1169 (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 1170 } 1171 #endif 1172 1173 /** 1174 * hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG 1175 * @hal_soc: Handle to HAL SoC structure 1176 * @hal_srng: Handle to HAL SRNG structure 1177 * 1178 * Return: none 1179 */ 1180 static inline void hal_tx_init_data_ring(void *hal_soc, void *hal_srng) 1181 { 1182 uint8_t *desc_addr; 1183 struct hal_srng_params srng_params; 1184 uint32_t desc_size; 1185 uint32_t num_desc; 1186 1187 hal_get_srng_params(hal_soc, hal_srng, &srng_params); 1188 1189 desc_addr = (uint8_t *) srng_params.ring_base_vaddr; 1190 desc_size = sizeof(struct tcl_data_cmd); 1191 num_desc = srng_params.num_entries; 1192 1193 while (num_desc) { 1194 HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, 1195 desc_size); 1196 desc_addr += (desc_size + sizeof(struct tlv_32_hdr)); 1197 num_desc--; 1198 } 1199 } 1200 #endif /* HAL_TX_H */ 1201