1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #if !defined(HAL_TX_H) 20 #define HAL_TX_H 21 22 /*--------------------------------------------------------------------------- 23 Include files 24 ---------------------------------------------------------------------------*/ 25 #include "hal_api.h" 26 #include "wcss_version.h" 27 28 #define WBM_RELEASE_RING_5_TX_RATE_STATS_OFFSET 0x00000014 29 #define WBM_RELEASE_RING_5_TX_RATE_STATS_LSB 0 30 #define WBM_RELEASE_RING_5_TX_RATE_STATS_MASK 0xffffffff 31 32 33 /*--------------------------------------------------------------------------- 34 Preprocessor definitions and constants 35 ---------------------------------------------------------------------------*/ 36 #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET 37 38 #define HAL_SET_FLD(desc, block , field) \ 39 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field))) 40 41 #define HAL_SET_FLD_OFFSET(desc, block , field, offset) \ 42 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field) + (offset))) 43 44 #define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \ 45 do { \ 46 ((struct tlv_32_hdr *) desc)->tlv_tag = (tag); \ 47 ((struct tlv_32_hdr *) desc)->tlv_len = (len); \ 48 } while (0) 49 50 #define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E 51 #define HAL_TX_TCL_CMD_TAG WIFITCL_GSE_CMD_E 52 53 #define HAL_TX_SM(block, field, value) \ 54 ((value << (block ## _ ## field ## _LSB)) & \ 55 (block ## _ ## field ## _MASK)) 56 57 #define HAL_TX_MS(block, field, value) \ 58 (((value) & (block ## _ ## field ## _MASK)) >> \ 59 (block ## _ ## field ## _LSB)) 60 61 #define HAL_TX_DESC_GET(desc, block, field) \ 62 HAL_TX_MS(block, field, HAL_SET_FLD(desc, block, field)) 63 64 #define HAL_TX_DESC_SUBBLOCK_GET(desc, block, sub, field) \ 65 HAL_TX_MS(sub, field, HAL_SET_FLD(desc, block, sub)) 66 67 #define HAL_TX_BUF_TYPE_BUFFER 0 68 #define HAL_TX_BUF_TYPE_EXT_DESC 1 69 70 #define HAL_TX_DESC_LEN_DWORDS (NUM_OF_DWORDS_TCL_DATA_CMD) 71 #define HAL_TX_DESC_LEN_BYTES (NUM_OF_DWORDS_TCL_DATA_CMD * 4) 72 #define HAL_TX_EXTENSION_DESC_LEN_DWORDS (NUM_OF_DWORDS_TX_MSDU_EXTENSION) 73 #define HAL_TX_EXTENSION_DESC_LEN_BYTES (NUM_OF_DWORDS_TX_MSDU_EXTENSION * 4) 74 75 #define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 76 #define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4) 77 #define HAL_TX_BITS_PER_TID 3 78 #define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1) 79 #define HAL_TX_NUM_DSCP_PER_REGISTER 10 80 #define HAL_MAX_HW_DSCP_TID_MAPS 2 81 #define HAL_MAX_HW_DSCP_TID_MAPS_11AX 32 82 83 #define HTT_META_HEADER_LEN_BYTES 64 84 #define HAL_TX_EXT_DESC_WITH_META_DATA \ 85 (HTT_META_HEADER_LEN_BYTES + HAL_TX_EXTENSION_DESC_LEN_BYTES) 86 87 /* Length of WBM release ring without the status words */ 88 #define HAL_TX_COMPLETION_DESC_BASE_LEN 12 89 90 #define HAL_TX_COMP_RELEASE_SOURCE_TQM 0 91 #define HAL_TX_COMP_RELEASE_SOURCE_FW 3 92 93 /* Define a place-holder release reason for FW */ 94 #define HAL_TX_COMP_RELEASE_REASON_FW 99 95 96 /* 97 * Offset of HTT Tx Descriptor in WBM Completion 98 * HTT Tx Desc structure is passed from firmware to host overlayed 99 * on wbm_release_ring DWORDs 2,3 ,4 and 5for software based completions 100 * (Exception frames and TQM bypass frames) 101 */ 102 #define HAL_TX_COMP_HTT_STATUS_OFFSET 8 103 #define HAL_TX_COMP_HTT_STATUS_LEN 16 104 105 #define HAL_TX_BUF_TYPE_BUFFER 0 106 #define HAL_TX_BUF_TYPE_EXT_DESC 1 107 108 #define HAL_TX_EXT_DESC_BUF_OFFSET TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 109 #define HAL_TX_EXT_BUF_LOW_MASK TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 110 #define HAL_TX_EXT_BUF_HI_MASK TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 111 #define HAL_TX_EXT_BUF_LEN_MASK TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 112 #define HAL_TX_EXT_BUF_LEN_LSB TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 113 #define HAL_TX_EXT_BUF_WD_SIZE 2 114 115 #define HAL_TX_DESC_ADDRX_EN 0x1 116 #define HAL_TX_DESC_ADDRY_EN 0x2 117 #define HAL_TX_DESC_DEFAULT_LMAC_ID 0x3 118 119 enum hal_tx_ret_buf_manager { 120 HAL_WBM_SW0_BM_ID = 3, 121 HAL_WBM_SW1_BM_ID = 4, 122 HAL_WBM_SW2_BM_ID = 5, 123 HAL_WBM_SW3_BM_ID = 6, 124 }; 125 126 /*--------------------------------------------------------------------------- 127 Structures 128 ---------------------------------------------------------------------------*/ 129 /** 130 * struct hal_tx_completion_status - HAL Tx completion descriptor contents 131 * @status: frame acked/failed 132 * @release_src: release source = TQM/FW 133 * @ack_frame_rssi: RSSI of the received ACK or BA frame 134 * @first_msdu: Indicates this MSDU is the first MSDU in AMSDU 135 * @last_msdu: Indicates this MSDU is the last MSDU in AMSDU 136 * @msdu_part_of_amsdu : Indicates this MSDU was part of an A-MSDU in MPDU 137 * @bw: Indicates the BW of the upcoming transmission - 138 * <enum 0 transmit_bw_20_MHz> 139 * <enum 1 transmit_bw_40_MHz> 140 * <enum 2 transmit_bw_80_MHz> 141 * <enum 3 transmit_bw_160_MHz> 142 * @pkt_type: Transmit Packet Type 143 * @stbc: When set, STBC transmission rate was used 144 * @ldpc: When set, use LDPC transmission rates 145 * @sgi: <enum 0 0_8_us_sgi > Legacy normal GI 146 * <enum 1 0_4_us_sgi > Legacy short GI 147 * <enum 2 1_6_us_sgi > HE related GI 148 * <enum 3 3_2_us_sgi > HE 149 * @mcs: Transmit MCS Rate 150 * @ofdma: Set when the transmission was an OFDMA transmission 151 * @tones_in_ru: The number of tones in the RU used. 152 * @tsf: Lower 32 bits of the TSF 153 * @ppdu_id: TSF, snapshot of this value when transmission of the 154 * PPDU containing the frame finished. 155 * @transmit_cnt: Number of times this frame has been transmitted 156 * @tid: TID of the flow or MPDU queue 157 * @peer_id: Peer ID of the flow or MPDU queue 158 */ 159 struct hal_tx_completion_status { 160 uint8_t status; 161 uint8_t release_src; 162 uint8_t ack_frame_rssi; 163 uint8_t first_msdu:1, 164 last_msdu:1, 165 msdu_part_of_amsdu:1; 166 uint32_t bw:2, 167 pkt_type:4, 168 stbc:1, 169 ldpc:1, 170 sgi:2, 171 mcs:4, 172 ofdma:1, 173 tones_in_ru:12, 174 valid:1; 175 uint32_t tsf; 176 uint32_t ppdu_id; 177 uint8_t transmit_cnt; 178 uint8_t tid; 179 uint16_t peer_id; 180 }; 181 182 /** 183 * struct hal_tx_desc_comp_s - hal tx completion descriptor contents 184 * @desc: Transmit status information from descriptor 185 */ 186 struct hal_tx_desc_comp_s { 187 uint32_t desc[HAL_TX_COMPLETION_DESC_LEN_DWORDS]; 188 }; 189 190 /* 191 * enum hal_tx_encrypt_type - Type of decrypt cipher used (valid only for RAW) 192 * @HAL_TX_ENCRYPT_TYPE_WEP_40: WEP 40-bit 193 * @HAL_TX_ENCRYPT_TYPE_WEP_10: WEP 10-bit 194 * @HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC: TKIP without MIC 195 * @HAL_TX_ENCRYPT_TYPE_WEP_128: WEP_128 196 * @HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC: TKIP_WITH_MIC 197 * @HAL_TX_ENCRYPT_TYPE_WAPI: WAPI 198 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_128: AES_CCMP_128 199 * @HAL_TX_ENCRYPT_TYPE_NO_CIPHER: NO CIPHER 200 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_256: AES_CCMP_256 201 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_128: AES_GCMP_128 202 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_256: AES_GCMP_256 203 * @HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4: WAPI GCM SM4 204 */ 205 enum hal_tx_encrypt_type { 206 HAL_TX_ENCRYPT_TYPE_WEP_40 = 0, 207 HAL_TX_ENCRYPT_TYPE_WEP_104 = 1 , 208 HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC = 2, 209 HAL_TX_ENCRYPT_TYPE_WEP_128 = 3, 210 HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC = 4, 211 HAL_TX_ENCRYPT_TYPE_WAPI = 5, 212 HAL_TX_ENCRYPT_TYPE_AES_CCMP_128 = 6, 213 HAL_TX_ENCRYPT_TYPE_NO_CIPHER = 7, 214 HAL_TX_ENCRYPT_TYPE_AES_CCMP_256 = 8, 215 HAL_TX_ENCRYPT_TYPE_AES_GCMP_128 = 9, 216 HAL_TX_ENCRYPT_TYPE_AES_GCMP_256 = 10, 217 HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4 = 11, 218 }; 219 220 /* 221 * enum hal_tx_encap_type - Encapsulation type that HW will perform 222 * @HAL_TX_ENCAP_TYPE_RAW: Raw Packet Type 223 * @HAL_TX_ENCAP_TYPE_NWIFI: Native WiFi Type 224 * @HAL_TX_ENCAP_TYPE_ETHERNET: Ethernet 225 * @HAL_TX_ENCAP_TYPE_802_3: 802.3 Frame 226 */ 227 enum hal_tx_encap_type { 228 HAL_TX_ENCAP_TYPE_RAW = 0, 229 HAL_TX_ENCAP_TYPE_NWIFI = 1, 230 HAL_TX_ENCAP_TYPE_ETHERNET = 2, 231 HAL_TX_ENCAP_TYPE_802_3 = 3, 232 }; 233 234 /** 235 * enum hal_tx_tqm_release_reason - TQM Release reason codes 236 * 237 * @HAL_TX_TQM_RR_FRAME_ACKED : ACK of BA for it was received 238 * @HAL_TX_TQM_RR_REM_CMD_REM : Remove cmd of type “Remove_mpdus” initiated 239 * by SW 240 * @HAL_TX_TQM_RR_REM_CMD_TX : Remove command of type Remove_transmitted_mpdus 241 * initiated by SW 242 * @HAL_TX_TQM_RR_REM_CMD_NOTX : Remove cmd of type Remove_untransmitted_mpdus 243 * initiated by SW 244 * @HAL_TX_TQM_RR_REM_CMD_AGED : Remove command of type “Remove_aged_mpdus” or 245 * “Remove_aged_msdus” initiated by SW 246 * @HAL_TX_TQM_RR_FW_REASON1 : Remove command where fw indicated that 247 * remove reason is fw_reason1 248 * @HAL_TX_TQM_RR_FW_REASON2 : Remove command where fw indicated that 249 * remove reason is fw_reason2 250 * @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that 251 * remove reason is fw_reason3 252 */ 253 enum hal_tx_tqm_release_reason { 254 HAL_TX_TQM_RR_FRAME_ACKED, 255 HAL_TX_TQM_RR_REM_CMD_REM, 256 HAL_TX_TQM_RR_REM_CMD_TX, 257 HAL_TX_TQM_RR_REM_CMD_NOTX, 258 HAL_TX_TQM_RR_REM_CMD_AGED, 259 HAL_TX_TQM_RR_FW_REASON1, 260 HAL_TX_TQM_RR_FW_REASON2, 261 HAL_TX_TQM_RR_FW_REASON3, 262 }; 263 264 /* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports 265 * @HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT: Default DSCP-TID mapping table 266 * @HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE: DSCP-TID map override table 267 */ 268 enum hal_tx_dscp_tid_table_id { 269 HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT, 270 HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE, 271 }; 272 273 /*--------------------------------------------------------------------------- 274 Function declarations and documentation 275 ---------------------------------------------------------------------------*/ 276 277 /*--------------------------------------------------------------------------- 278 TCL Descriptor accessor APIs 279 ---------------------------------------------------------------------------*/ 280 281 /** 282 * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor 283 * @desc: Handle to Tx Descriptor 284 * @data_length: MSDU length in case of direct descriptor. 285 * Length of link extension descriptor in case of Link extension 286 * descriptor.Includes the length of Metadata 287 * Return: None 288 */ 289 static inline void hal_tx_desc_set_buf_length(void *desc, 290 uint16_t data_length) 291 { 292 HAL_SET_FLD(desc, TCL_DATA_CMD_3, DATA_LENGTH) |= 293 HAL_TX_SM(TCL_DATA_CMD_3, DATA_LENGTH, data_length); 294 } 295 296 /** 297 * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor 298 * @desc: Handle to Tx Descriptor 299 * @offset: Packet offset from Metadata in case of direct buffer descriptor. 300 * 301 * Return: void 302 */ 303 static inline void hal_tx_desc_set_buf_offset(void *desc, 304 uint8_t offset) 305 { 306 HAL_SET_FLD(desc, TCL_DATA_CMD_3, PACKET_OFFSET) |= 307 HAL_TX_SM(TCL_DATA_CMD_3, PACKET_OFFSET, offset); 308 } 309 310 /** 311 * hal_tx_desc_set_encap_type - Set encapsulation type in Tx Descriptor 312 * @desc: Handle to Tx Descriptor 313 * @encap_type: Encapsulation that HW will perform 314 * 315 * Return: void 316 * 317 */ 318 static inline void hal_tx_desc_set_encap_type(void *desc, 319 enum hal_tx_encap_type encap_type) 320 { 321 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCAP_TYPE) |= 322 HAL_TX_SM(TCL_DATA_CMD_2, ENCAP_TYPE, encap_type); 323 } 324 325 /** 326 * hal_tx_desc_set_encrypt_type - Sets the Encrypt Type in Tx Descriptor 327 * @desc: Handle to Tx Descriptor 328 * @type: Encrypt Type 329 * 330 * Return: void 331 */ 332 static inline void hal_tx_desc_set_encrypt_type(void *desc, 333 enum hal_tx_encrypt_type type) 334 { 335 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCRYPT_TYPE) |= 336 HAL_TX_SM(TCL_DATA_CMD_2, ENCRYPT_TYPE, type); 337 } 338 339 /** 340 * hal_tx_desc_set_addr_search_flags - Enable AddrX and AddrY search flags 341 * @desc: Handle to Tx Descriptor 342 * @flags: Bit 0 - AddrY search enable, Bit 1 - AddrX search enable 343 * 344 * Return: void 345 */ 346 static inline void hal_tx_desc_set_addr_search_flags(void *desc, 347 uint8_t flags) 348 { 349 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRX_EN) |= 350 HAL_TX_SM(TCL_DATA_CMD_2, ADDRX_EN, (flags & 0x1)); 351 352 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRY_EN) |= 353 HAL_TX_SM(TCL_DATA_CMD_2, ADDRY_EN, (flags >> 1)); 354 } 355 356 /** 357 * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags 358 * Tx Descriptor for MSDU_buffer type 359 * @desc: Handle to Tx Descriptor 360 * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits) 361 * 362 * Return: void 363 */ 364 static inline void hal_tx_desc_set_l4_checksum_en(void *desc, 365 uint8_t en) 366 { 367 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 368 (HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV4_CHECKSUM_EN, en) | 369 HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV6_CHECKSUM_EN, en) | 370 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV4_CHECKSUM_EN, en) | 371 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV6_CHECKSUM_EN, en)); 372 } 373 374 /** 375 * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in 376 * Tx Descriptor for MSDU_buffer type 377 * @desc: Handle to Tx Descriptor 378 * @checksum_en_flags: ipv4 checksum enable flags 379 * 380 * Return: void 381 */ 382 static inline void hal_tx_desc_set_l3_checksum_en(void *desc, 383 uint8_t en) 384 { 385 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 386 HAL_TX_SM(TCL_DATA_CMD_3, IPV4_CHECKSUM_EN, en); 387 } 388 389 /** 390 * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor 391 * @desc:Handle to Tx Descriptor 392 * @metadata: Metadata to be sent to Firmware 393 * 394 * Return: void 395 */ 396 static inline void hal_tx_desc_set_fw_metadata(void *desc, 397 uint16_t metadata) 398 { 399 HAL_SET_FLD(desc, TCL_DATA_CMD_2, TCL_CMD_NUMBER) |= 400 HAL_TX_SM(TCL_DATA_CMD_2, TCL_CMD_NUMBER, metadata); 401 } 402 403 /** 404 * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor. 405 * @desc:Handle to Tx Descriptor 406 * @to_fw: if set, Forward packet to FW along with classification result 407 * 408 * Return: void 409 */ 410 static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw) 411 { 412 HAL_SET_FLD(desc, TCL_DATA_CMD_3, TO_FW) |= 413 HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw); 414 } 415 416 /** 417 * hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor 418 * @desc: Handle to Tx Descriptor 419 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 420 * enabling the interpretation of the 'Mesh Control Present' bit 421 * (bit 8) of QoS Control (otherwise this bit is ignored), 422 * For native WiFi frames, this indicates that a 'Mesh Control' field 423 * is present between the header and the LLC. 424 * 425 * Return: void 426 */ 427 static inline void hal_tx_desc_set_mesh_en(void *desc, uint8_t en) 428 { 429 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 430 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 431 } 432 433 /** 434 * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in 435 * frame) to be used for Tx Frame 436 * @desc: Handle to Tx Descriptor 437 * @hlos_tid: HLOS TID 438 * 439 * Return: void 440 */ 441 static inline void hal_tx_desc_set_hlos_tid(void *desc, 442 uint8_t hlos_tid) 443 { 444 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID) |= 445 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID, hlos_tid); 446 447 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |= 448 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1); 449 } 450 /** 451 * hal_tx_desc_sync - Commit the descriptor to Hardware 452 * @hal_tx_des_cached: Cached descriptor that software maintains 453 * @hw_desc: Hardware descriptor to be updated 454 */ 455 static inline void hal_tx_desc_sync(void *hal_tx_desc_cached, 456 void *hw_desc) 457 { 458 qdf_mem_copy((hw_desc + sizeof(struct tlv_32_hdr)), 459 hal_tx_desc_cached, 20); 460 } 461 462 /*--------------------------------------------------------------------------- 463 Tx MSDU Extension Descriptor accessor APIs 464 ---------------------------------------------------------------------------*/ 465 /** 466 * hal_tx_ext_desc_set_tso_enable() - Set TSO Enable Flag 467 * @desc: Handle to Tx MSDU Extension Descriptor 468 * @tso_en: bool value set to true if TSO is enabled 469 * 470 * Return: none 471 */ 472 static inline void hal_tx_ext_desc_set_tso_enable(void *desc, 473 uint8_t tso_en) 474 { 475 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TSO_ENABLE) |= 476 HAL_TX_SM(TX_MSDU_EXTENSION_0, TSO_ENABLE, tso_en); 477 } 478 479 /** 480 * hal_tx_ext_desc_set_tso_flags() - Set TSO Flags 481 * @desc: Handle to Tx MSDU Extension Descriptor 482 * @falgs: 32-bit word with all TSO flags consolidated 483 * 484 * Return: none 485 */ 486 static inline void hal_tx_ext_desc_set_tso_flags(void *desc, 487 uint32_t tso_flags) 488 { 489 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_0, TSO_ENABLE, 0) = 490 tso_flags; 491 } 492 493 /** 494 * hal_tx_ext_desc_set_tcp_flags() - Enable HW Checksum offload 495 * @desc: Handle to Tx MSDU Extension Descriptor 496 * @tcp_flags: TCP flags {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 497 * @mask: TCP flag mask. Tcp_flag is inserted into the header 498 * based on the mask, if tso is enabled 499 * 500 * Return: none 501 */ 502 static inline void hal_tx_ext_desc_set_tcp_flags(void *desc, 503 uint16_t tcp_flags, 504 uint16_t mask) 505 { 506 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TCP_FLAG) |= 507 ((HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG, tcp_flags)) | 508 (HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG_MASK, mask))); 509 } 510 511 /** 512 * hal_tx_ext_desc_set_msdu_length() - Set L2 and IP Lengths 513 * @desc: Handle to Tx MSDU Extension Descriptor 514 * @l2_len: L2 length for the msdu, if tso is enabled 515 * @ip_len: IP length for the msdu, if tso is enabled 516 * 517 * Return: none 518 */ 519 static inline void hal_tx_ext_desc_set_msdu_length(void *desc, 520 uint16_t l2_len, 521 uint16_t ip_len) 522 { 523 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_1, L2_LENGTH) |= 524 ((HAL_TX_SM(TX_MSDU_EXTENSION_1, L2_LENGTH, l2_len)) | 525 (HAL_TX_SM(TX_MSDU_EXTENSION_1, IP_LENGTH, ip_len))); 526 } 527 528 /** 529 * hal_tx_ext_desc_set_tcp_seq() - Set TCP Sequence number 530 * @desc: Handle to Tx MSDU Extension Descriptor 531 * @seq_num: Tcp_seq_number for the msdu, if tso is enabled 532 * 533 * Return: none 534 */ 535 static inline void hal_tx_ext_desc_set_tcp_seq(void *desc, 536 uint32_t seq_num) 537 { 538 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER) |= 539 ((HAL_TX_SM(TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER, seq_num))); 540 } 541 542 543 /** 544 * hal_tx_ext_desc_set_ip_id() - Set IP Identification field 545 * @desc: Handle to Tx MSDU Extension Descriptor 546 * @id: IP Id field for the msdu, if tso is enabled 547 * 548 * Return: none 549 */ 550 static inline void hal_tx_ext_desc_set_ip_id(void *desc, 551 uint16_t id) 552 { 553 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_3, IP_IDENTIFICATION) |= 554 ((HAL_TX_SM(TX_MSDU_EXTENSION_3, IP_IDENTIFICATION, id))); 555 } 556 /** 557 * hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment 558 * @desc: Handle to Tx MSDU Extension Descriptor 559 * @frag_num: Fragment number (value can be 0 to 5) 560 * @paddr_lo: Lower 32-bit of Buffer Physical address 561 * @paddr_hi: Upper 32-bit of Buffer Physical address 562 * @length: Buffer Length 563 * 564 * Return: none 565 */ 566 static inline void hal_tx_ext_desc_set_buffer(void *desc, 567 uint8_t frag_num, 568 uint32_t paddr_lo, 569 uint16_t paddr_hi, 570 uint16_t length) 571 { 572 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, 573 (frag_num << 3)) |= 574 ((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo))); 575 576 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32, 577 (frag_num << 3)) |= 578 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_PTR_39_32, 579 (paddr_hi)))); 580 581 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_LEN, 582 (frag_num << 3)) |= 583 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length))); 584 } 585 586 /** 587 * hal_tx_ext_desc_set_buffer0_param() - Set Buffer 0 Pointer and Length 588 * @desc: Handle to Tx MSDU Extension Descriptor 589 * @paddr_lo: Lower 32-bit of Buffer Physical address 590 * @paddr_hi: Upper 32-bit of Buffer Physical address 591 * @length: Buffer 0 Length 592 * 593 * Return: none 594 */ 595 static inline void hal_tx_ext_desc_set_buffer0_param(void *desc, 596 uint32_t paddr_lo, 597 uint16_t paddr_hi, 598 uint16_t length) 599 { 600 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0) |= 601 ((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo))); 602 603 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32) |= 604 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, 605 BUF0_PTR_39_32, paddr_hi))); 606 607 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_LEN) |= 608 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length))); 609 } 610 611 /** 612 * hal_tx_ext_desc_set_buffer1_param() - Set Buffer 1 Pointer and Length 613 * @desc: Handle to Tx MSDU Extension Descriptor 614 * @paddr_lo: Lower 32-bit of Buffer Physical address 615 * @paddr_hi: Upper 32-bit of Buffer Physical address 616 * @length: Buffer 1 Length 617 * 618 * Return: none 619 */ 620 static inline void hal_tx_ext_desc_set_buffer1_param(void *desc, 621 uint32_t paddr_lo, 622 uint16_t paddr_hi, 623 uint16_t length) 624 { 625 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_8, BUF1_PTR_31_0) |= 626 ((HAL_TX_SM(TX_MSDU_EXTENSION_8, BUF1_PTR_31_0, paddr_lo))); 627 628 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_PTR_39_32) |= 629 ((HAL_TX_SM(TX_MSDU_EXTENSION_9, 630 BUF1_PTR_39_32, paddr_hi))); 631 632 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_LEN) |= 633 ((HAL_TX_SM(TX_MSDU_EXTENSION_9, BUF1_LEN, length))); 634 } 635 636 /** 637 * hal_tx_ext_desc_set_buffer2_param() - Set Buffer 2 Pointer and Length 638 * @desc: Handle to Tx MSDU Extension Descriptor 639 * @paddr_lo: Lower 32-bit of Buffer Physical address 640 * @paddr_hi: Upper 32-bit of Buffer Physical address 641 * @length: Buffer 2 Length 642 * 643 * Return: none 644 */ 645 static inline void hal_tx_ext_desc_set_buffer2_param(void *desc, 646 uint32_t paddr_lo, 647 uint16_t paddr_hi, 648 uint16_t length) 649 { 650 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_10, BUF2_PTR_31_0) |= 651 ((HAL_TX_SM(TX_MSDU_EXTENSION_10, BUF2_PTR_31_0, 652 paddr_lo))); 653 654 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_PTR_39_32) |= 655 ((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_PTR_39_32, 656 paddr_hi))); 657 658 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_LEN) |= 659 ((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_LEN, length))); 660 } 661 662 /** 663 * hal_tx_ext_desc_sync - Commit the descriptor to Hardware 664 * @desc_cached: Cached descriptor that software maintains 665 * @hw_desc: Hardware descriptor to be updated 666 * 667 * Return: none 668 */ 669 static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached, 670 uint8_t *hw_desc) 671 { 672 qdf_mem_copy(&hw_desc[0], &desc_cached[0], 673 HAL_TX_EXT_DESC_WITH_META_DATA); 674 } 675 676 /** 677 * hal_tx_ext_desc_get_tso_enable() - Set TSO Enable Flag 678 * @hal_tx_ext_desc: Handle to Tx MSDU Extension Descriptor 679 * 680 * Return: tso_enable value in the descriptor 681 */ 682 static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc) 683 { 684 uint32_t *desc = (uint32_t *) hal_tx_ext_desc; 685 return (*desc & TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK) >> 686 TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB; 687 } 688 689 /*--------------------------------------------------------------------------- 690 WBM Descriptor accessor APIs for Tx completions 691 ---------------------------------------------------------------------------*/ 692 /** 693 * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor 694 * @hal_desc: completion ring descriptor pointer 695 * 696 * This function will tx descriptor id, cookie, within hardware completion 697 * descriptor 698 * 699 * Return: cookie 700 */ 701 static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc) 702 { 703 uint32_t comp_desc = 704 *(uint32_t *) (((uint8_t *) hal_desc) + 705 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET); 706 707 /* Cookie is placed on 2nd word */ 708 return (comp_desc & BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) >> 709 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB; 710 } 711 712 /** 713 * hal_tx_comp_get_paddr() - Get paddr within comp descriptor 714 * @hal_desc: completion ring descriptor pointer 715 * 716 * This function will get buffer physical address within hardware completion 717 * descriptor 718 * 719 * Return: Buffer physical address 720 */ 721 static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc) 722 { 723 uint32_t paddr_lo; 724 uint32_t paddr_hi; 725 726 paddr_lo = *(uint32_t *) (((uint8_t *) hal_desc) + 727 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET); 728 729 paddr_hi = *(uint32_t *) (((uint8_t *) hal_desc) + 730 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET); 731 732 paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) >> 733 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB; 734 735 return (qdf_dma_addr_t) (paddr_lo | (((uint64_t) paddr_hi) << 32)); 736 } 737 738 /** 739 * hal_tx_comp_get_buffer_source() - Get buffer release source value 740 * @hal_desc: completion ring descriptor pointer 741 * 742 * This function will get buffer release source from Tx completion descriptor 743 * 744 * Return: buffer release source 745 */ 746 static inline uint32_t hal_tx_comp_get_buffer_source(void *hal_desc) 747 { 748 uint32_t comp_desc = 749 *(uint32_t *) (((uint8_t *) hal_desc) + 750 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET); 751 752 return (comp_desc & WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> 753 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB; 754 } 755 756 /** 757 * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type 758 * @hal_desc: completion ring descriptor pointer 759 * 760 * This function will return the type of pointer - buffer or descriptor 761 * 762 * Return: buffer type 763 */ 764 static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc) 765 { 766 uint32_t comp_desc = 767 *(uint32_t *) (((uint8_t *) hal_desc) + 768 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET); 769 770 return (comp_desc & WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> 771 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB; 772 } 773 774 /** 775 * hal_tx_comp_get_release_reason() - TQM Release reason 776 * @hal_desc: completion ring descriptor pointer 777 * 778 * This function will return the type of pointer - buffer or descriptor 779 * 780 * Return: buffer type 781 */ 782 static inline uint8_t hal_tx_comp_get_release_reason(void *hal_desc) 783 { 784 uint32_t comp_desc = 785 *(uint32_t *) (((uint8_t *) hal_desc) + 786 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 787 788 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 789 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 790 } 791 792 /** 793 * hal_tx_comp_desc_sync() - collect hardware descriptor contents 794 * @hal_desc: hardware descriptor pointer 795 * @comp: software descriptor pointer 796 * @read_status: 0 - Do not read status words from descriptors 797 * 1 - Enable reading of status words from descriptor 798 * 799 * This function will collect hardware release ring element contents and 800 * translate to software descriptor content 801 * 802 * Return: none 803 */ 804 805 static inline void hal_tx_comp_desc_sync(void *hw_desc, 806 struct hal_tx_desc_comp_s *comp, 807 bool read_status) 808 { 809 if (!read_status) 810 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_BASE_LEN); 811 else 812 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_LEN_BYTES); 813 } 814 815 /** 816 * hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor 817 * @hal_desc: Hardware (WBM) descriptor pointer 818 * @htt_desc: Software HTT descriptor pointer 819 * 820 * This function will read the HTT structure overlaid on WBM descriptor 821 * into a cached software descriptor 822 * 823 */ 824 static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc) 825 { 826 uint8_t *desc = hw_desc + HAL_TX_COMP_HTT_STATUS_OFFSET; 827 828 qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN); 829 } 830 831 /** 832 * hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG 833 * @hal_soc: Handle to HAL SoC structure 834 * @hal_srng: Handle to HAL SRNG structure 835 * 836 * Return: none 837 */ 838 static inline void hal_tx_init_data_ring(void *hal_soc, void *hal_srng) 839 { 840 uint8_t *desc_addr; 841 struct hal_srng_params srng_params; 842 uint32_t desc_size; 843 uint32_t num_desc; 844 845 hal_get_srng_params(hal_soc, hal_srng, &srng_params); 846 847 desc_addr = (uint8_t *)srng_params.ring_base_vaddr; 848 desc_size = sizeof(struct tcl_data_cmd); 849 num_desc = srng_params.num_entries; 850 851 while (num_desc) { 852 HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, 853 desc_size); 854 desc_addr += (desc_size + sizeof(struct tlv_32_hdr)); 855 num_desc--; 856 } 857 } 858 859 /** 860 * hal_tx_desc_set_dscp_tid_table_id() - Sets DSCP to TID conversion table ID 861 * @hal_soc: Handle to HAL SoC structure 862 * @desc: Handle to Tx Descriptor 863 * @id: DSCP to tid conversion table to be used for this frame 864 * 865 * Return: void 866 */ 867 static inline void hal_tx_desc_set_dscp_tid_table_id(struct hal_soc *hal_soc, 868 void *desc, uint8_t id) 869 { 870 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id(desc, id); 871 } 872 873 /** 874 * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table 875 * 876 * @soc: HAL SoC context 877 * @map: DSCP-TID mapping table 878 * @id: mapping table ID - 0,1 879 * 880 * Return: void 881 */ 882 static inline void hal_tx_set_dscp_tid_map(struct hal_soc *hal_soc, 883 uint8_t *map, uint8_t id) 884 { 885 hal_soc->ops->hal_tx_set_dscp_tid_map(hal_soc, map, id); 886 } 887 888 /** 889 * hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user 890 * 891 * @soc: HAL SoC context 892 * @map: DSCP-TID mapping table 893 * @id : MAP ID 894 * @dscp: DSCP_TID map index 895 * 896 * Return: void 897 */ 898 static inline void hal_tx_update_dscp_tid(struct hal_soc *hal_soc, uint8_t tid, 899 uint8_t id, uint8_t dscp) 900 { 901 hal_soc->ops->hal_tx_update_dscp_tid(hal_soc, tid, id, dscp); 902 } 903 904 /** 905 * hal_tx_desc_set_lmac_id - Set the lmac_id value 906 * @desc: Handle to Tx Descriptor 907 * @lmac_id: mac Id to ast matching 908 * b00 – mac 0 909 * b01 – mac 1 910 * b10 – mac 2 911 * b11 – all macs (legacy HK way) 912 * 913 * Return: void 914 */ 915 static inline void hal_tx_desc_set_lmac_id(struct hal_soc *hal_soc, 916 void *desc, uint8_t lmac_id) 917 { 918 hal_soc->ops->hal_tx_desc_set_lmac_id(desc, lmac_id); 919 } 920 921 /** 922 * hal_tx_comp_get_status() - TQM Release reason 923 * @hal_desc: completion ring Tx status 924 * 925 * This function will parse the WBM completion descriptor and populate in 926 * HAL structure 927 * 928 * Return: none 929 */ 930 static inline void hal_tx_comp_get_status(void *desc, void *ts, void *hal) 931 { 932 struct hal_soc *hal_soc = hal; 933 934 hal_soc->ops->hal_tx_comp_get_status(desc, ts); 935 } 936 937 938 /** 939 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 940 * @desc: Handle to Tx Descriptor 941 * @paddr: Physical Address 942 * @pool_id: Return Buffer Manager ID 943 * @desc_id: Descriptor ID 944 * @type: 0 - Address points to a MSDU buffer 945 * 1 - Address points to MSDU extension descriptor 946 * 947 * Return: void 948 */ 949 static inline void hal_tx_desc_set_buf_addr(void *desc, dma_addr_t paddr, 950 uint8_t pool_id, uint32_t desc_id, uint8_t type, void *hal) 951 { 952 struct hal_soc *hal_soc = hal; 953 954 hal_soc->ops->hal_tx_desc_set_buf_addr(desc, paddr, pool_id, 955 desc_id, type); 956 957 } 958 #endif /* HAL_TX_H */ 959