1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #if !defined(HAL_TX_H) 20 #define HAL_TX_H 21 22 /*--------------------------------------------------------------------------- 23 Include files 24 ---------------------------------------------------------------------------*/ 25 #include "hal_api.h" 26 #include "wcss_version.h" 27 #include "hal_hw_headers.h" 28 #include "hal_tx_hw_defines.h" 29 30 #define HAL_WBM_RELEASE_RING_2_BUFFER_TYPE 0 31 #define HAL_WBM_RELEASE_RING_2_DESC_TYPE 1 32 33 #define HAL_TX_DESC_TLV_TAG_OFFSET 1 34 #define HAL_TX_DESC_TLV_LEN_OFFSET 10 35 36 /*--------------------------------------------------------------------------- 37 Preprocessor definitions and constants 38 ---------------------------------------------------------------------------*/ 39 #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET 40 41 #define HAL_SET_FLD(desc, block , field) \ 42 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field))) 43 44 #define HAL_SET_FLD_OFFSET(desc, block , field, offset) \ 45 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field) + (offset))) 46 47 #define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \ 48 do { \ 49 uint32_t temp = 0; \ 50 temp |= (tag << HAL_TX_DESC_TLV_TAG_OFFSET); \ 51 temp |= (len << HAL_TX_DESC_TLV_LEN_OFFSET); \ 52 (*(uint32_t *)desc) = temp; \ 53 } while (0) 54 55 #define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E 56 #define HAL_TX_TCL_CMD_TAG WIFITCL_GSE_CMD_E 57 58 #define HAL_TX_SM(block, field, value) \ 59 ((value << (block ## _ ## field ## _LSB)) & \ 60 (block ## _ ## field ## _MASK)) 61 62 #define HAL_TX_MS(block, field, value) \ 63 (((value) & (block ## _ ## field ## _MASK)) >> \ 64 (block ## _ ## field ## _LSB)) 65 66 #define HAL_TX_DESC_GET(desc, block, field) \ 67 HAL_TX_MS(block, field, HAL_SET_FLD(desc, block, field)) 68 69 #define HAL_TX_DESC_SUBBLOCK_GET(desc, block, sub, field) \ 70 HAL_TX_MS(sub, field, HAL_SET_FLD(desc, block, sub)) 71 72 #define HAL_TX_BUF_TYPE_BUFFER 0 73 #define HAL_TX_BUF_TYPE_EXT_DESC 1 74 75 #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 76 77 #define HAL_TX_DESC_LEN_DWORDS (NUM_OF_DWORDS_TCL_DATA_CMD) 78 #define HAL_TX_DESC_LEN_BYTES (NUM_OF_DWORDS_TCL_DATA_CMD * 4) 79 #define HAL_TX_EXTENSION_DESC_LEN_DWORDS (NUM_OF_DWORDS_TX_MSDU_EXTENSION) 80 #define HAL_TX_EXTENSION_DESC_LEN_BYTES (NUM_OF_DWORDS_TX_MSDU_EXTENSION * 4) 81 82 #define NUM_OF_DWORDS_WBM_RELEASE_RING 8 83 84 #define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 85 #define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4) 86 #define HAL_TX_BITS_PER_TID 3 87 #define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1) 88 #define HAL_TX_NUM_DSCP_PER_REGISTER 10 89 #define HAL_MAX_HW_DSCP_TID_MAPS 2 90 #define HAL_MAX_HW_DSCP_TID_MAPS_11AX 32 91 92 #define HAL_MAX_HW_DSCP_TID_V2_MAPS 48 93 #define HTT_META_HEADER_LEN_BYTES 64 94 #define HAL_TX_EXT_DESC_WITH_META_DATA \ 95 (HTT_META_HEADER_LEN_BYTES + HAL_TX_EXTENSION_DESC_LEN_BYTES) 96 97 #define HAL_TX_NUM_PCP_PER_REGISTER 8 98 99 /* Length of WBM release ring without the status words */ 100 #define HAL_TX_COMPLETION_DESC_BASE_LEN 12 101 102 #define HAL_TX_COMP_RELEASE_SOURCE_TQM 0 103 #define HAL_TX_COMP_RELEASE_SOURCE_REO 2 104 #define HAL_TX_COMP_RELEASE_SOURCE_FW 3 105 106 /* Define a place-holder release reason for FW */ 107 #define HAL_TX_COMP_RELEASE_REASON_FW 99 108 109 /* 110 * Offset of HTT Tx Descriptor in WBM Completion 111 * HTT Tx Desc structure is passed from firmware to host overlayed 112 * on wbm_release_ring DWORDs 2,3 ,4 and 5for software based completions 113 * (Exception frames and TQM bypass frames) 114 */ 115 #define HAL_TX_COMP_HTT_STATUS_OFFSET 8 116 #define HAL_TX_COMP_HTT_STATUS_LEN 16 117 118 #define HAL_TX_BUF_TYPE_BUFFER 0 119 #define HAL_TX_BUF_TYPE_EXT_DESC 1 120 121 #define HAL_TX_EXT_DESC_BUF_OFFSET TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 122 #define HAL_TX_EXT_BUF_LOW_MASK TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 123 #define HAL_TX_EXT_BUF_HI_MASK TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 124 #define HAL_TX_EXT_BUF_LEN_MASK TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 125 #define HAL_TX_EXT_BUF_LEN_LSB TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 126 #define HAL_TX_EXT_BUF_WD_SIZE 2 127 128 #define HAL_TX_DESC_ADDRX_EN 0x1 129 #define HAL_TX_DESC_ADDRY_EN 0x2 130 #define HAL_TX_DESC_DEFAULT_LMAC_ID 0x3 131 132 #define HAL_TX_ADDR_SEARCH_DEFAULT 0x0 133 #define HAL_TX_ADDR_INDEX_SEARCH 0x1 134 #define HAL_TX_FLOW_INDEX_SEARCH 0x2 135 136 #define HAL_WBM2SW_RELEASE_SRC_GET(wbm_desc)(((*(((uint32_t *)wbm_desc) + \ 137 (HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 138 HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_MASK) >> \ 139 HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_LSB) 140 141 #define HAL_WBM_SW0_BM_ID(sw0_bm_id) (sw0_bm_id) 142 #define HAL_WBM_SW1_BM_ID(sw0_bm_id) ((sw0_bm_id) + 1) 143 #define HAL_WBM_SW2_BM_ID(sw0_bm_id) ((sw0_bm_id) + 2) 144 #define HAL_WBM_SW3_BM_ID(sw0_bm_id) ((sw0_bm_id) + 3) 145 #define HAL_WBM_SW4_BM_ID(sw0_bm_id) ((sw0_bm_id) + 4) 146 #define HAL_WBM_SW5_BM_ID(sw0_bm_id) ((sw0_bm_id) + 5) 147 #define HAL_WBM_SW6_BM_ID(sw0_bm_id) ((sw0_bm_id) + 6) 148 149 /*--------------------------------------------------------------------------- 150 Structures 151 ---------------------------------------------------------------------------*/ 152 /** 153 * struct hal_tx_completion_status - HAL Tx completion descriptor contents 154 * @status: frame acked/failed 155 * @release_src: release source = TQM/FW 156 * @ack_frame_rssi: RSSI of the received ACK or BA frame 157 * @first_msdu: Indicates this MSDU is the first MSDU in AMSDU 158 * @last_msdu: Indicates this MSDU is the last MSDU in AMSDU 159 * @msdu_part_of_amsdu : Indicates this MSDU was part of an A-MSDU in MPDU 160 * @bw: Indicates the BW of the upcoming transmission - 161 * <enum 0 transmit_bw_20_MHz> 162 * <enum 1 transmit_bw_40_MHz> 163 * <enum 2 transmit_bw_80_MHz> 164 * <enum 3 transmit_bw_160_MHz> 165 * @pkt_type: Transmit Packet Type 166 * @stbc: When set, STBC transmission rate was used 167 * @ldpc: When set, use LDPC transmission rates 168 * @sgi: <enum 0 0_8_us_sgi > Legacy normal GI 169 * <enum 1 0_4_us_sgi > Legacy short GI 170 * <enum 2 1_6_us_sgi > HE related GI 171 * <enum 3 3_2_us_sgi > HE 172 * @mcs: Transmit MCS Rate 173 * @ofdma: Set when the transmission was an OFDMA transmission 174 * @tones_in_ru: The number of tones in the RU used. 175 * @tsf: Lower 32 bits of the TSF 176 * @ppdu_id: TSF, snapshot of this value when transmission of the 177 * PPDU containing the frame finished. 178 * @transmit_cnt: Number of times this frame has been transmitted 179 * @tid: TID of the flow or MPDU queue 180 * @peer_id: Peer ID of the flow or MPDU queue 181 * @buffer_timestamp: Frame system entrance timestamp in units of 1024 182 * microseconds 183 */ 184 struct hal_tx_completion_status { 185 uint8_t status; 186 uint8_t release_src; 187 uint8_t ack_frame_rssi; 188 uint8_t first_msdu:1, 189 last_msdu:1, 190 msdu_part_of_amsdu:1; 191 uint32_t bw:2, 192 pkt_type:4, 193 stbc:1, 194 ldpc:1, 195 sgi:2, 196 mcs:4, 197 ofdma:1, 198 tones_in_ru:12, 199 valid:1; 200 uint32_t tsf; 201 uint32_t ppdu_id; 202 uint8_t transmit_cnt; 203 uint8_t tid; 204 uint16_t peer_id; 205 #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY 206 uint32_t buffer_timestamp:19; 207 #endif 208 }; 209 210 /** 211 * struct hal_tx_desc_comp_s - hal tx completion descriptor contents 212 * @desc: Transmit status information from descriptor 213 */ 214 struct hal_tx_desc_comp_s { 215 uint32_t desc[HAL_TX_COMPLETION_DESC_LEN_DWORDS]; 216 }; 217 218 /* 219 * enum hal_tx_encrypt_type - Type of decrypt cipher used (valid only for RAW) 220 * @HAL_TX_ENCRYPT_TYPE_WEP_40: WEP 40-bit 221 * @HAL_TX_ENCRYPT_TYPE_WEP_10: WEP 10-bit 222 * @HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC: TKIP without MIC 223 * @HAL_TX_ENCRYPT_TYPE_WEP_128: WEP_128 224 * @HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC: TKIP_WITH_MIC 225 * @HAL_TX_ENCRYPT_TYPE_WAPI: WAPI 226 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_128: AES_CCMP_128 227 * @HAL_TX_ENCRYPT_TYPE_NO_CIPHER: NO CIPHER 228 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_256: AES_CCMP_256 229 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_128: AES_GCMP_128 230 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_256: AES_GCMP_256 231 * @HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4: WAPI GCM SM4 232 */ 233 enum hal_tx_encrypt_type { 234 HAL_TX_ENCRYPT_TYPE_WEP_40 = 0, 235 HAL_TX_ENCRYPT_TYPE_WEP_104 = 1 , 236 HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC = 2, 237 HAL_TX_ENCRYPT_TYPE_WEP_128 = 3, 238 HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC = 4, 239 HAL_TX_ENCRYPT_TYPE_WAPI = 5, 240 HAL_TX_ENCRYPT_TYPE_AES_CCMP_128 = 6, 241 HAL_TX_ENCRYPT_TYPE_NO_CIPHER = 7, 242 HAL_TX_ENCRYPT_TYPE_AES_CCMP_256 = 8, 243 HAL_TX_ENCRYPT_TYPE_AES_GCMP_128 = 9, 244 HAL_TX_ENCRYPT_TYPE_AES_GCMP_256 = 10, 245 HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4 = 11, 246 }; 247 248 /* 249 * enum hal_tx_encap_type - Encapsulation type that HW will perform 250 * @HAL_TX_ENCAP_TYPE_RAW: Raw Packet Type 251 * @HAL_TX_ENCAP_TYPE_NWIFI: Native WiFi Type 252 * @HAL_TX_ENCAP_TYPE_ETHERNET: Ethernet 253 * @HAL_TX_ENCAP_TYPE_802_3: 802.3 Frame 254 */ 255 enum hal_tx_encap_type { 256 HAL_TX_ENCAP_TYPE_RAW = 0, 257 HAL_TX_ENCAP_TYPE_NWIFI = 1, 258 HAL_TX_ENCAP_TYPE_ETHERNET = 2, 259 HAL_TX_ENCAP_TYPE_802_3 = 3, 260 }; 261 262 /** 263 * enum hal_tx_tqm_release_reason - TQM Release reason codes 264 * 265 * @HAL_TX_TQM_RR_FRAME_ACKED : ACK of BA for it was received 266 * @HAL_TX_TQM_RR_REM_CMD_REM : Remove cmd of type “Remove_mpdus” initiated 267 * by SW 268 * @HAL_TX_TQM_RR_REM_CMD_TX : Remove command of type Remove_transmitted_mpdus 269 * initiated by SW 270 * @HAL_TX_TQM_RR_REM_CMD_NOTX : Remove cmd of type Remove_untransmitted_mpdus 271 * initiated by SW 272 * @HAL_TX_TQM_RR_REM_CMD_AGED : Remove command of type “Remove_aged_mpdus” or 273 * “Remove_aged_msdus” initiated by SW 274 * @HAL_TX_TQM_RR_FW_REASON1 : Remove command where fw indicated that 275 * remove reason is fw_reason1 276 * @HAL_TX_TQM_RR_FW_REASON2 : Remove command where fw indicated that 277 * remove reason is fw_reason2 278 * @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that 279 * remove reason is fw_reason3 280 * @HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE : Remove command where fw indicated that 281 * remove reason is remove disable queue 282 */ 283 enum hal_tx_tqm_release_reason { 284 HAL_TX_TQM_RR_FRAME_ACKED, 285 HAL_TX_TQM_RR_REM_CMD_REM, 286 HAL_TX_TQM_RR_REM_CMD_TX, 287 HAL_TX_TQM_RR_REM_CMD_NOTX, 288 HAL_TX_TQM_RR_REM_CMD_AGED, 289 HAL_TX_TQM_RR_FW_REASON1, 290 HAL_TX_TQM_RR_FW_REASON2, 291 HAL_TX_TQM_RR_FW_REASON3, 292 HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE, 293 }; 294 295 /* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports 296 * @HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT: Default DSCP-TID mapping table 297 * @HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE: DSCP-TID map override table 298 */ 299 enum hal_tx_dscp_tid_table_id { 300 HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT, 301 HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE, 302 }; 303 304 /*--------------------------------------------------------------------------- 305 Function declarations and documentation 306 ---------------------------------------------------------------------------*/ 307 308 /*--------------------------------------------------------------------------- 309 Tx MSDU Extension Descriptor accessor APIs 310 ---------------------------------------------------------------------------*/ 311 /** 312 * hal_tx_ext_desc_set_tso_enable() - Set TSO Enable Flag 313 * @desc: Handle to Tx MSDU Extension Descriptor 314 * @tso_en: bool value set to true if TSO is enabled 315 * 316 * Return: none 317 */ 318 static inline void hal_tx_ext_desc_set_tso_enable(void *desc, 319 uint8_t tso_en) 320 { 321 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE) |= 322 HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TSO_ENABLE, tso_en); 323 } 324 325 /** 326 * hal_tx_ext_desc_set_tso_flags() - Set TSO Flags 327 * @desc: Handle to Tx MSDU Extension Descriptor 328 * @falgs: 32-bit word with all TSO flags consolidated 329 * 330 * Return: none 331 */ 332 static inline void hal_tx_ext_desc_set_tso_flags(void *desc, 333 uint32_t tso_flags) 334 { 335 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE, 0) = 336 tso_flags; 337 } 338 339 /** 340 * hal_tx_ext_desc_set_tcp_flags() - Enable HW Checksum offload 341 * @desc: Handle to Tx MSDU Extension Descriptor 342 * @tcp_flags: TCP flags {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 343 * @mask: TCP flag mask. Tcp_flag is inserted into the header 344 * based on the mask, if tso is enabled 345 * 346 * Return: none 347 */ 348 static inline void hal_tx_ext_desc_set_tcp_flags(void *desc, 349 uint16_t tcp_flags, 350 uint16_t mask) 351 { 352 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_FLAG) |= 353 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG, tcp_flags)) | 354 (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG_MASK, mask))); 355 } 356 357 /** 358 * hal_tx_ext_desc_set_msdu_length() - Set L2 and IP Lengths 359 * @desc: Handle to Tx MSDU Extension Descriptor 360 * @l2_len: L2 length for the msdu, if tso is enabled 361 * @ip_len: IP length for the msdu, if tso is enabled 362 * 363 * Return: none 364 */ 365 static inline void hal_tx_ext_desc_set_msdu_length(void *desc, 366 uint16_t l2_len, 367 uint16_t ip_len) 368 { 369 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, L2_LENGTH) |= 370 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, L2_LENGTH, l2_len)) | 371 (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_LENGTH, ip_len))); 372 } 373 374 /** 375 * hal_tx_ext_desc_set_tcp_seq() - Set TCP Sequence number 376 * @desc: Handle to Tx MSDU Extension Descriptor 377 * @seq_num: Tcp_seq_number for the msdu, if tso is enabled 378 * 379 * Return: none 380 */ 381 static inline void hal_tx_ext_desc_set_tcp_seq(void *desc, 382 uint32_t seq_num) 383 { 384 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER) |= 385 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER, seq_num))); 386 } 387 388 389 /** 390 * hal_tx_ext_desc_set_ip_id() - Set IP Identification field 391 * @desc: Handle to Tx MSDU Extension Descriptor 392 * @id: IP Id field for the msdu, if tso is enabled 393 * 394 * Return: none 395 */ 396 static inline void hal_tx_ext_desc_set_ip_id(void *desc, 397 uint16_t id) 398 { 399 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION) |= 400 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION, id))); 401 } 402 /** 403 * hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment 404 * @desc: Handle to Tx MSDU Extension Descriptor 405 * @frag_num: Fragment number (value can be 0 to 5) 406 * @paddr_lo: Lower 32-bit of Buffer Physical address 407 * @paddr_hi: Upper 32-bit of Buffer Physical address 408 * @length: Buffer Length 409 * 410 * Return: none 411 */ 412 static inline void hal_tx_ext_desc_set_buffer(void *desc, 413 uint8_t frag_num, 414 uint32_t paddr_lo, 415 uint16_t paddr_hi, 416 uint16_t length) 417 { 418 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, 419 (frag_num << 3)) |= 420 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo))); 421 422 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32, 423 (frag_num << 3)) |= 424 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32, 425 (paddr_hi)))); 426 427 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN, 428 (frag_num << 3)) |= 429 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length))); 430 } 431 432 /** 433 * hal_tx_ext_desc_set_buffer0_param() - Set Buffer 0 Pointer and Length 434 * @desc: Handle to Tx MSDU Extension Descriptor 435 * @paddr_lo: Lower 32-bit of Buffer Physical address 436 * @paddr_hi: Upper 32-bit of Buffer Physical address 437 * @length: Buffer 0 Length 438 * 439 * Return: none 440 */ 441 static inline void hal_tx_ext_desc_set_buffer0_param(void *desc, 442 uint32_t paddr_lo, 443 uint16_t paddr_hi, 444 uint16_t length) 445 { 446 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0) |= 447 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo))); 448 449 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32) |= 450 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, 451 BUF0_PTR_39_32, paddr_hi))); 452 453 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN) |= 454 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length))); 455 } 456 457 /** 458 * hal_tx_ext_desc_set_buffer1_param() - Set Buffer 1 Pointer and Length 459 * @desc: Handle to Tx MSDU Extension Descriptor 460 * @paddr_lo: Lower 32-bit of Buffer Physical address 461 * @paddr_hi: Upper 32-bit of Buffer Physical address 462 * @length: Buffer 1 Length 463 * 464 * Return: none 465 */ 466 static inline void hal_tx_ext_desc_set_buffer1_param(void *desc, 467 uint32_t paddr_lo, 468 uint16_t paddr_hi, 469 uint16_t length) 470 { 471 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0) |= 472 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0, paddr_lo))); 473 474 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_39_32) |= 475 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, 476 BUF1_PTR_39_32, paddr_hi))); 477 478 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_LEN) |= 479 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_LEN, length))); 480 } 481 482 /** 483 * hal_tx_ext_desc_set_buffer2_param() - Set Buffer 2 Pointer and Length 484 * @desc: Handle to Tx MSDU Extension Descriptor 485 * @paddr_lo: Lower 32-bit of Buffer Physical address 486 * @paddr_hi: Upper 32-bit of Buffer Physical address 487 * @length: Buffer 2 Length 488 * 489 * Return: none 490 */ 491 static inline void hal_tx_ext_desc_set_buffer2_param(void *desc, 492 uint32_t paddr_lo, 493 uint16_t paddr_hi, 494 uint16_t length) 495 { 496 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0) |= 497 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0, 498 paddr_lo))); 499 500 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32) |= 501 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32, 502 paddr_hi))); 503 504 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_LEN) |= 505 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_LEN, length))); 506 } 507 508 /** 509 * hal_tx_ext_desc_sync - Commit the descriptor to Hardware 510 * @desc_cached: Cached descriptor that software maintains 511 * @hw_desc: Hardware descriptor to be updated 512 * 513 * Return: none 514 */ 515 static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached, 516 uint8_t *hw_desc) 517 { 518 qdf_mem_copy(&hw_desc[0], &desc_cached[0], 519 HAL_TX_EXT_DESC_WITH_META_DATA); 520 } 521 522 /** 523 * hal_tx_ext_desc_get_tso_enable() - Set TSO Enable Flag 524 * @hal_tx_ext_desc: Handle to Tx MSDU Extension Descriptor 525 * 526 * Return: tso_enable value in the descriptor 527 */ 528 static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc) 529 { 530 uint32_t *desc = (uint32_t *) hal_tx_ext_desc; 531 return (*desc & HAL_TX_MSDU_EXTENSION_TSO_ENABLE_MASK) >> 532 HAL_TX_MSDU_EXTENSION_TSO_ENABLE_LSB; 533 } 534 535 /*--------------------------------------------------------------------------- 536 WBM Descriptor accessor APIs for Tx completions 537 ---------------------------------------------------------------------------*/ 538 /** 539 * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type 540 * @hal_desc: completion ring descriptor pointer 541 * 542 * This function will return the type of pointer - buffer or descriptor 543 * 544 * Return: buffer type 545 */ 546 static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc) 547 { 548 uint32_t comp_desc = 549 *(uint32_t *) (((uint8_t *) hal_desc) + 550 HAL_TX_COMP_BUFFER_OR_DESC_TYPE_OFFSET); 551 552 return (comp_desc & HAL_TX_COMP_BUFFER_OR_DESC_TYPE_MASK) >> 553 HAL_TX_COMP_BUFFER_OR_DESC_TYPE_LSB; 554 } 555 556 #ifdef QCA_WIFI_WCN7850 557 /** 558 * hal_tx_comp_get_buffer_source() - Get buffer release source value 559 * @hal_desc: completion ring descriptor pointer 560 * 561 * This function will get buffer release source from Tx completion descriptor 562 * 563 * Return: buffer release source 564 */ 565 static inline uint32_t 566 hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl, 567 void *hal_desc) 568 { 569 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 570 571 return hal_soc->ops->hal_tx_comp_get_buffer_source(hal_desc); 572 } 573 #else 574 static inline uint32_t 575 hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl, 576 void *hal_desc) 577 { 578 return HAL_WBM2SW_RELEASE_SRC_GET(hal_desc); 579 } 580 #endif 581 582 /** 583 * hal_tx_comp_get_release_reason() - TQM Release reason 584 * @hal_desc: completion ring descriptor pointer 585 * 586 * This function will return the type of pointer - buffer or descriptor 587 * 588 * Return: buffer type 589 */ 590 static inline 591 uint8_t hal_tx_comp_get_release_reason(void *hal_desc, 592 hal_soc_handle_t hal_soc_hdl) 593 { 594 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 595 596 return hal_soc->ops->hal_tx_comp_get_release_reason(hal_desc); 597 } 598 599 /** 600 * hal_tx_comp_get_peer_id() - Get peer_id value() 601 * @hal_desc: completion ring descriptor pointer 602 * 603 * This function will get peer_id value from Tx completion descriptor 604 * 605 * Return: buffer release source 606 */ 607 static inline uint16_t hal_tx_comp_get_peer_id(void *hal_desc) 608 { 609 uint32_t comp_desc = 610 *(uint32_t *)(((uint8_t *)hal_desc) + 611 HAL_TX_COMP_SW_PEER_ID_OFFSET); 612 613 return (comp_desc & HAL_TX_COMP_SW_PEER_ID_MASK) >> 614 HAL_TX_COMP_SW_PEER_ID_LSB; 615 } 616 617 /** 618 * hal_tx_comp_get_tx_status() - Get tx transmission status() 619 * @hal_desc: completion ring descriptor pointer 620 * 621 * This function will get transmit status value from Tx completion descriptor 622 * 623 * Return: buffer release source 624 */ 625 static inline uint8_t hal_tx_comp_get_tx_status(void *hal_desc) 626 { 627 uint32_t comp_desc = 628 *(uint32_t *)(((uint8_t *)hal_desc) + 629 HAL_TX_COMP_TQM_RELEASE_REASON_OFFSET); 630 631 return (comp_desc & HAL_TX_COMP_TQM_RELEASE_REASON_MASK) >> 632 HAL_TX_COMP_TQM_RELEASE_REASON_LSB; 633 } 634 635 /** 636 * hal_tx_comp_desc_sync() - collect hardware descriptor contents 637 * @hal_desc: hardware descriptor pointer 638 * @comp: software descriptor pointer 639 * @read_status: 0 - Do not read status words from descriptors 640 * 1 - Enable reading of status words from descriptor 641 * 642 * This function will collect hardware release ring element contents and 643 * translate to software descriptor content 644 * 645 * Return: none 646 */ 647 648 static inline void hal_tx_comp_desc_sync(void *hw_desc, 649 struct hal_tx_desc_comp_s *comp, 650 bool read_status) 651 { 652 if (!read_status) 653 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_BASE_LEN); 654 else 655 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_LEN_BYTES); 656 } 657 658 /** 659 * hal_dump_comp_desc() - dump tx completion descriptor 660 * @hal_desc: hardware descriptor pointer 661 * 662 * This function will print tx completion descriptor 663 * 664 * Return: none 665 */ 666 static inline void hal_dump_comp_desc(void *hw_desc) 667 { 668 struct hal_tx_desc_comp_s *comp = 669 (struct hal_tx_desc_comp_s *)hw_desc; 670 uint32_t i; 671 672 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 673 "Current tx completion descriptor is"); 674 675 for (i = 0; i < HAL_TX_COMPLETION_DESC_LEN_DWORDS; i++) { 676 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 677 "DWORD[i] = 0x%x", comp->desc[i]); 678 } 679 } 680 681 /** 682 * hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor 683 * @hal_desc: Hardware (WBM) descriptor pointer 684 * @htt_desc: Software HTT descriptor pointer 685 * 686 * This function will read the HTT structure overlaid on WBM descriptor 687 * into a cached software descriptor 688 * 689 */ 690 static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc) 691 { 692 uint8_t *desc = hw_desc + HAL_TX_COMP_HTT_STATUS_OFFSET; 693 694 qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN); 695 } 696 697 /** 698 * hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG 699 * @hal_soc_hdl: Handle to HAL SoC structure 700 * @hal_srng: Handle to HAL SRNG structure 701 * 702 * Return: none 703 */ 704 static inline void hal_tx_init_data_ring(hal_soc_handle_t hal_soc_hdl, 705 hal_ring_handle_t hal_ring_hdl) 706 { 707 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 708 709 hal_soc->ops->hal_tx_init_data_ring(hal_soc_hdl, hal_ring_hdl); 710 } 711 712 /** 713 * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table 714 * 715 * @soc: HAL SoC context 716 * @map: DSCP-TID mapping table 717 * @id: mapping table ID - 0,1 718 * 719 * Return: void 720 */ 721 static inline void hal_tx_set_dscp_tid_map(hal_soc_handle_t hal_soc_hdl, 722 uint8_t *map, uint8_t id) 723 { 724 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 725 726 hal_soc->ops->hal_tx_set_dscp_tid_map(hal_soc, map, id); 727 } 728 729 /** 730 * hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user 731 * 732 * @soc: HAL SoC context 733 * @map: DSCP-TID mapping table 734 * @id : MAP ID 735 * @dscp: DSCP_TID map index 736 * 737 * Return: void 738 */ 739 static inline 740 void hal_tx_update_dscp_tid(hal_soc_handle_t hal_soc_hdl, uint8_t tid, 741 uint8_t id, uint8_t dscp) 742 { 743 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 744 745 hal_soc->ops->hal_tx_update_dscp_tid(hal_soc, tid, id, dscp); 746 } 747 748 /** 749 * hal_tx_comp_get_status() - TQM Release reason 750 * @hal_desc: completion ring Tx status 751 * 752 * This function will parse the WBM completion descriptor and populate in 753 * HAL structure 754 * 755 * Return: none 756 */ 757 static inline void hal_tx_comp_get_status(void *desc, void *ts, 758 hal_soc_handle_t hal_soc_hdl) 759 { 760 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 761 762 hal_soc->ops->hal_tx_comp_get_status(desc, ts, hal_soc); 763 } 764 765 /** 766 * hal_tx_set_pcp_tid_map_default() - Configure default PCP to TID map table 767 * 768 * @soc: HAL SoC context 769 * @map: PCP-TID mapping table 770 * 771 * Return: void 772 */ 773 static inline void hal_tx_set_pcp_tid_map_default(hal_soc_handle_t hal_soc_hdl, 774 uint8_t *map) 775 { 776 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 777 778 hal_soc->ops->hal_tx_set_pcp_tid_map(hal_soc, map); 779 } 780 781 /** 782 * hal_tx_update_pcp_tid_map() - Update PCP to TID map table 783 * 784 * @soc: HAL SoC context 785 * @pcp: pcp value 786 * @tid: tid no 787 * 788 * Return: void 789 */ 790 static inline void hal_tx_update_pcp_tid_map(hal_soc_handle_t hal_soc_hdl, 791 uint8_t pcp, uint8_t tid) 792 { 793 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 794 795 hal_soc->ops->hal_tx_update_pcp_tid_map(hal_soc, tid, tid); 796 } 797 798 /** 799 * hal_tx_set_tidmap_prty() - Configure TIDmap priority 800 * 801 * @soc: HAL SoC context 802 * @val: priority value 803 * 804 * Return: void 805 */ 806 static inline 807 void hal_tx_set_tidmap_prty(hal_soc_handle_t hal_soc_hdl, uint8_t val) 808 { 809 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 810 811 hal_soc->ops->hal_tx_set_tidmap_prty(hal_soc, val); 812 } 813 814 /** 815 * hal_get_wbm_internal_error() - wbm internal error 816 * @hal_desc: completion ring descriptor pointer 817 * 818 * This function will return the type of pointer - buffer or descriptor 819 * 820 * Return: buffer type 821 */ 822 static inline 823 uint8_t hal_get_wbm_internal_error(hal_soc_handle_t hal_soc_hdl, void *hal_desc) 824 { 825 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 826 827 return hal_soc->ops->hal_get_wbm_internal_error(hal_desc); 828 } 829 #endif /* HAL_TX_H */ 830