1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #if !defined(HAL_TX_H) 21 #define HAL_TX_H 22 23 /*--------------------------------------------------------------------------- 24 Include files 25 ---------------------------------------------------------------------------*/ 26 #include "hal_api.h" 27 #include "wcss_version.h" 28 #include "hal_hw_headers.h" 29 #include "hal_tx_hw_defines.h" 30 31 #define HAL_WBM_RELEASE_RING_2_BUFFER_TYPE 0 32 #define HAL_WBM_RELEASE_RING_2_DESC_TYPE 1 33 34 #define HAL_TX_DESC_TLV_TAG_OFFSET 1 35 #define HAL_TX_DESC_TLV_LEN_OFFSET 10 36 37 /*--------------------------------------------------------------------------- 38 Preprocessor definitions and constants 39 ---------------------------------------------------------------------------*/ 40 #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET 41 42 #define HAL_TX_LSB(block, field) block ## _ ## field ## _LSB 43 44 #define HAL_TX_MASK(block, field) block ## _ ## field ## _MASK 45 46 #define HAL_TX_DESC_OFFSET(desc, block, field) \ 47 (((uint8_t *)desc) + HAL_OFFSET(block, field)) 48 49 #define HAL_SET_FLD(desc, block , field) \ 50 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field))) 51 52 #define HAL_SET_FLD_OFFSET(desc, block , field, offset) \ 53 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field) + (offset))) 54 55 #define HAL_SET_FLD_64(desc, block, field) \ 56 (*(uint64_t *)((uint8_t *)desc + HAL_OFFSET(block, field))) 57 58 #define HAL_SET_FLD_OFFSET_64(desc, block, field, offset) \ 59 (*(uint64_t *)((uint8_t *)desc + HAL_OFFSET(block, field) + (offset))) 60 61 #define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \ 62 do { \ 63 uint32_t temp = 0; \ 64 temp |= (tag << HAL_TX_DESC_TLV_TAG_OFFSET); \ 65 temp |= (len << HAL_TX_DESC_TLV_LEN_OFFSET); \ 66 (*(uint32_t *)desc) = temp; \ 67 } while (0) 68 69 #define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E 70 #define HAL_TX_TCL_CMD_TAG WIFITCL_GSE_CMD_E 71 72 #define HAL_TX_SM(block, field, value) \ 73 ((value << (block ## _ ## field ## _LSB)) & \ 74 (block ## _ ## field ## _MASK)) 75 76 #define HAL_TX_MS(block, field, value) \ 77 (((value) & (block ## _ ## field ## _MASK)) >> \ 78 (block ## _ ## field ## _LSB)) 79 80 #define HAL_TX_DESC_GET(desc, block, field) \ 81 HAL_TX_MS(block, field, HAL_SET_FLD(desc, block, field)) 82 83 #define HAL_TX_DESC_OFFSET_GET(desc, block, field, offset) \ 84 HAL_TX_MS(block, field, HAL_SET_FLD_OFFSET(desc, block, field, offset)) 85 86 #define HAL_TX_DESC_SUBBLOCK_GET(desc, block, sub, field) \ 87 HAL_TX_MS(sub, field, HAL_SET_FLD(desc, block, sub)) 88 89 #define HAL_TX_DESC_GET_64(desc, block, field) \ 90 HAL_TX_MS(block, field, HAL_SET_FLD_64(desc, block, field)) 91 92 #define HAL_TX_DESC_OFFSET_GET_64(desc, block, field, offset) \ 93 HAL_TX_MS(block, field, HAL_SET_FLD_OFFSET_64(desc, block, field,\ 94 offset)) 95 96 #define HAL_TX_DESC_SUBBLOCK_GET_64(desc, block, sub, field) \ 97 HAL_TX_MS(sub, field, HAL_SET_FLD_64(desc, block, sub)) 98 99 #define HAL_TX_BUF_TYPE_BUFFER 0 100 #define HAL_TX_BUF_TYPE_EXT_DESC 1 101 102 #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 103 104 #define HAL_TX_DESC_LEN_DWORDS (NUM_OF_DWORDS_TCL_DATA_CMD) 105 #define HAL_TX_DESC_LEN_BYTES (NUM_OF_DWORDS_TCL_DATA_CMD * 4) 106 #define HAL_TX_EXTENSION_DESC_LEN_DWORDS (NUM_OF_DWORDS_TX_MSDU_EXTENSION) 107 #define HAL_TX_EXTENSION_DESC_LEN_BYTES (NUM_OF_DWORDS_TX_MSDU_EXTENSION * 4) 108 109 #define NUM_OF_DWORDS_WBM_RELEASE_RING 8 110 111 #define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 112 #define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4) 113 #define HAL_TX_BITS_PER_TID 3 114 #define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1) 115 #define HAL_TX_NUM_DSCP_PER_REGISTER 10 116 #define HAL_MAX_HW_DSCP_TID_MAPS 2 117 #define HAL_MAX_HW_DSCP_TID_MAPS_11AX 32 118 119 #define HAL_MAX_HW_DSCP_TID_V2_MAPS 48 120 #define HTT_META_HEADER_LEN_BYTES 64 121 #define HAL_TX_EXT_DESC_WITH_META_DATA \ 122 (HTT_META_HEADER_LEN_BYTES + HAL_TX_EXTENSION_DESC_LEN_BYTES) 123 124 #define HAL_TX_NUM_PCP_PER_REGISTER 8 125 126 /* Length of WBM release ring without the status words */ 127 #define HAL_TX_COMPLETION_DESC_BASE_LEN 12 128 129 #define HAL_TX_COMP_RELEASE_SOURCE_TQM 0 130 #define HAL_TX_COMP_RELEASE_SOURCE_REO 2 131 #define HAL_TX_COMP_RELEASE_SOURCE_FW 3 132 133 /* Define a place-holder release reason for FW */ 134 #define HAL_TX_COMP_RELEASE_REASON_FW 99 135 136 /* 137 * Offset of HTT Tx Descriptor in WBM Completion 138 * HTT Tx Desc structure is passed from firmware to host overlayed 139 * on wbm_release_ring DWORDs 2,3 ,4 and 5for software based completions 140 * (Exception frames and TQM bypass frames) 141 */ 142 #define HAL_TX_COMP_HTT_STATUS_OFFSET 8 143 #define HAL_TX_COMP_HTT_STATUS_LEN 16 144 145 #define HAL_TX_BUF_TYPE_BUFFER 0 146 #define HAL_TX_BUF_TYPE_EXT_DESC 1 147 148 #define HAL_TX_EXT_DESC_BUF_OFFSET TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 149 #define HAL_TX_EXT_BUF_LOW_MASK TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 150 #define HAL_TX_EXT_BUF_HI_MASK TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 151 #define HAL_TX_EXT_BUF_LEN_MASK TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 152 #define HAL_TX_EXT_BUF_LEN_LSB TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 153 #define HAL_TX_EXT_BUF_WD_SIZE 2 154 155 #define HAL_TX_DESC_ADDRX_EN 0x1 156 #define HAL_TX_DESC_ADDRY_EN 0x2 157 #define HAL_TX_DESC_DEFAULT_LMAC_ID 0x3 158 159 #define HAL_TX_ADDR_SEARCH_DEFAULT 0x0 160 #define HAL_TX_ADDR_INDEX_SEARCH 0x1 161 #define HAL_TX_FLOW_INDEX_SEARCH 0x2 162 163 #define HAL_WBM2SW_RELEASE_SRC_GET(wbm_desc)(((*(((uint32_t *)wbm_desc) + \ 164 (HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \ 165 HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_MASK) >> \ 166 HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_LSB) 167 168 #define HAL_WBM_SW0_BM_ID(sw0_bm_id) (sw0_bm_id) 169 #define HAL_WBM_SW1_BM_ID(sw0_bm_id) ((sw0_bm_id) + 1) 170 #define HAL_WBM_SW2_BM_ID(sw0_bm_id) ((sw0_bm_id) + 2) 171 #define HAL_WBM_SW3_BM_ID(sw0_bm_id) ((sw0_bm_id) + 3) 172 #define HAL_WBM_SW4_BM_ID(sw0_bm_id) ((sw0_bm_id) + 4) 173 #define HAL_WBM_SW5_BM_ID(sw0_bm_id) ((sw0_bm_id) + 5) 174 #define HAL_WBM_SW6_BM_ID(sw0_bm_id) ((sw0_bm_id) + 6) 175 176 /*--------------------------------------------------------------------------- 177 Structures 178 ---------------------------------------------------------------------------*/ 179 /** 180 * struct hal_tx_completion_status - HAL Tx completion descriptor contents 181 * @status: frame acked/failed 182 * @release_src: release source = TQM/FW 183 * @ack_frame_rssi: RSSI of the received ACK or BA frame 184 * @first_msdu: Indicates this MSDU is the first MSDU in AMSDU 185 * @last_msdu: Indicates this MSDU is the last MSDU in AMSDU 186 * @msdu_part_of_amsdu : Indicates this MSDU was part of an A-MSDU in MPDU 187 * @bw: Indicates the BW of the upcoming transmission - 188 * <enum 0 transmit_bw_20_MHz> 189 * <enum 1 transmit_bw_40_MHz> 190 * <enum 2 transmit_bw_80_MHz> 191 * <enum 3 transmit_bw_160_MHz> 192 * @pkt_type: Transmit Packet Type 193 * @stbc: When set, STBC transmission rate was used 194 * @ldpc: When set, use LDPC transmission rates 195 * @sgi: <enum 0 0_8_us_sgi > Legacy normal GI 196 * <enum 1 0_4_us_sgi > Legacy short GI 197 * <enum 2 1_6_us_sgi > HE related GI 198 * <enum 3 3_2_us_sgi > HE 199 * @mcs: Transmit MCS Rate 200 * @ofdma: Set when the transmission was an OFDMA transmission 201 * @tones_in_ru: The number of tones in the RU used. 202 * @tsf: Lower 32 bits of the TSF 203 * @ppdu_id: TSF, snapshot of this value when transmission of the 204 * PPDU containing the frame finished. 205 * @transmit_cnt: Number of times this frame has been transmitted 206 * @tid: TID of the flow or MPDU queue 207 * @peer_id: Peer ID of the flow or MPDU queue 208 * @buffer_timestamp: Frame system entrance timestamp in units of 1024 209 * microseconds 210 */ 211 struct hal_tx_completion_status { 212 uint8_t status; 213 uint8_t release_src; 214 uint8_t ack_frame_rssi; 215 uint8_t first_msdu:1, 216 last_msdu:1, 217 msdu_part_of_amsdu:1; 218 uint32_t bw:2, 219 pkt_type:4, 220 stbc:1, 221 ldpc:1, 222 sgi:2, 223 mcs:4, 224 ofdma:1, 225 tones_in_ru:12, 226 valid:1; 227 uint32_t tsf; 228 uint32_t ppdu_id; 229 uint8_t transmit_cnt; 230 uint8_t tid; 231 uint16_t peer_id; 232 #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(CONFIG_SAWF) 233 uint32_t buffer_timestamp:19; 234 #endif 235 }; 236 237 /** 238 * struct hal_tx_desc_comp_s - hal tx completion descriptor contents 239 * @desc: Transmit status information from descriptor 240 */ 241 struct hal_tx_desc_comp_s { 242 uint32_t desc[HAL_TX_COMPLETION_DESC_LEN_DWORDS]; 243 }; 244 245 /* 246 * enum hal_tx_encrypt_type - Type of decrypt cipher used (valid only for RAW) 247 * @HAL_TX_ENCRYPT_TYPE_WEP_40: WEP 40-bit 248 * @HAL_TX_ENCRYPT_TYPE_WEP_10: WEP 10-bit 249 * @HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC: TKIP without MIC 250 * @HAL_TX_ENCRYPT_TYPE_WEP_128: WEP_128 251 * @HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC: TKIP_WITH_MIC 252 * @HAL_TX_ENCRYPT_TYPE_WAPI: WAPI 253 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_128: AES_CCMP_128 254 * @HAL_TX_ENCRYPT_TYPE_NO_CIPHER: NO CIPHER 255 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_256: AES_CCMP_256 256 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_128: AES_GCMP_128 257 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_256: AES_GCMP_256 258 * @HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4: WAPI GCM SM4 259 */ 260 enum hal_tx_encrypt_type { 261 HAL_TX_ENCRYPT_TYPE_WEP_40 = 0, 262 HAL_TX_ENCRYPT_TYPE_WEP_104 = 1 , 263 HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC = 2, 264 HAL_TX_ENCRYPT_TYPE_WEP_128 = 3, 265 HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC = 4, 266 HAL_TX_ENCRYPT_TYPE_WAPI = 5, 267 HAL_TX_ENCRYPT_TYPE_AES_CCMP_128 = 6, 268 HAL_TX_ENCRYPT_TYPE_NO_CIPHER = 7, 269 HAL_TX_ENCRYPT_TYPE_AES_CCMP_256 = 8, 270 HAL_TX_ENCRYPT_TYPE_AES_GCMP_128 = 9, 271 HAL_TX_ENCRYPT_TYPE_AES_GCMP_256 = 10, 272 HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4 = 11, 273 }; 274 275 /* 276 * enum hal_tx_encap_type - Encapsulation type that HW will perform 277 * @HAL_TX_ENCAP_TYPE_RAW: Raw Packet Type 278 * @HAL_TX_ENCAP_TYPE_NWIFI: Native WiFi Type 279 * @HAL_TX_ENCAP_TYPE_ETHERNET: Ethernet 280 * @HAL_TX_ENCAP_TYPE_802_3: 802.3 Frame 281 */ 282 enum hal_tx_encap_type { 283 HAL_TX_ENCAP_TYPE_RAW = 0, 284 HAL_TX_ENCAP_TYPE_NWIFI = 1, 285 HAL_TX_ENCAP_TYPE_ETHERNET = 2, 286 HAL_TX_ENCAP_TYPE_802_3 = 3, 287 }; 288 289 /** 290 * enum hal_tx_tqm_release_reason - TQM Release reason codes 291 * 292 * @HAL_TX_TQM_RR_FRAME_ACKED : ACK of BA for it was received 293 * @HAL_TX_TQM_RR_REM_CMD_REM : Remove cmd of type “Remove_mpdus” initiated 294 * by SW 295 * @HAL_TX_TQM_RR_REM_CMD_TX : Remove command of type Remove_transmitted_mpdus 296 * initiated by SW 297 * @HAL_TX_TQM_RR_REM_CMD_NOTX : Remove cmd of type Remove_untransmitted_mpdus 298 * initiated by SW 299 * @HAL_TX_TQM_RR_REM_CMD_AGED : Remove command of type “Remove_aged_mpdus” or 300 * “Remove_aged_msdus” initiated by SW 301 * @HAL_TX_TQM_RR_FW_REASON1 : Remove command where fw indicated that 302 * remove reason is fw_reason1 303 * @HAL_TX_TQM_RR_FW_REASON2 : Remove command where fw indicated that 304 * remove reason is fw_reason2 305 * @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that 306 * remove reason is fw_reason3 307 * @HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE : Remove command where fw indicated that 308 * remove reason is remove disable queue 309 * @HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING: Remove command from fw to remove 310 * all mpdu until 1st non-match 311 * @HAL_TX_TQM_RR_DROP_THRESHOLD: Dropped due to drop threshold criteria 312 * @HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE: Dropped due to link desc not available 313 * @HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU: Dropped due drop bit set or null flow 314 * @HAL_TX_TQM_RR_MULTICAST_DROP: Dropped due mcast drop set for VDEV 315 * 316 */ 317 enum hal_tx_tqm_release_reason { 318 HAL_TX_TQM_RR_FRAME_ACKED, 319 HAL_TX_TQM_RR_REM_CMD_REM, 320 HAL_TX_TQM_RR_REM_CMD_TX, 321 HAL_TX_TQM_RR_REM_CMD_NOTX, 322 HAL_TX_TQM_RR_REM_CMD_AGED, 323 HAL_TX_TQM_RR_FW_REASON1, 324 HAL_TX_TQM_RR_FW_REASON2, 325 HAL_TX_TQM_RR_FW_REASON3, 326 HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE, 327 HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING, 328 HAL_TX_TQM_RR_DROP_THRESHOLD, 329 HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE, 330 HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU, 331 HAL_TX_TQM_RR_MULTICAST_DROP, 332 }; 333 334 /* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports 335 * @HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT: Default DSCP-TID mapping table 336 * @HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE: DSCP-TID map override table 337 */ 338 enum hal_tx_dscp_tid_table_id { 339 HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT, 340 HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE, 341 }; 342 343 /*--------------------------------------------------------------------------- 344 Function declarations and documentation 345 ---------------------------------------------------------------------------*/ 346 347 /*--------------------------------------------------------------------------- 348 Tx MSDU Extension Descriptor accessor APIs 349 ---------------------------------------------------------------------------*/ 350 /** 351 * hal_tx_ext_desc_set_tso_enable() - Set TSO Enable Flag 352 * @desc: Handle to Tx MSDU Extension Descriptor 353 * @tso_en: bool value set to true if TSO is enabled 354 * 355 * Return: none 356 */ 357 static inline void hal_tx_ext_desc_set_tso_enable(void *desc, 358 uint8_t tso_en) 359 { 360 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE) |= 361 HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TSO_ENABLE, tso_en); 362 } 363 364 /** 365 * hal_tx_ext_desc_set_tso_flags() - Set TSO Flags 366 * @desc: Handle to Tx MSDU Extension Descriptor 367 * @falgs: 32-bit word with all TSO flags consolidated 368 * 369 * Return: none 370 */ 371 static inline void hal_tx_ext_desc_set_tso_flags(void *desc, 372 uint32_t tso_flags) 373 { 374 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE, 0) = 375 tso_flags; 376 } 377 378 /** 379 * hal_tx_ext_desc_set_tcp_flags() - Enable HW Checksum offload 380 * @desc: Handle to Tx MSDU Extension Descriptor 381 * @tcp_flags: TCP flags {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 382 * @mask: TCP flag mask. Tcp_flag is inserted into the header 383 * based on the mask, if tso is enabled 384 * 385 * Return: none 386 */ 387 static inline void hal_tx_ext_desc_set_tcp_flags(void *desc, 388 uint16_t tcp_flags, 389 uint16_t mask) 390 { 391 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_FLAG) |= 392 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG, tcp_flags)) | 393 (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG_MASK, mask))); 394 } 395 396 /** 397 * hal_tx_ext_desc_set_msdu_length() - Set L2 and IP Lengths 398 * @desc: Handle to Tx MSDU Extension Descriptor 399 * @l2_len: L2 length for the msdu, if tso is enabled 400 * @ip_len: IP length for the msdu, if tso is enabled 401 * 402 * Return: none 403 */ 404 static inline void hal_tx_ext_desc_set_msdu_length(void *desc, 405 uint16_t l2_len, 406 uint16_t ip_len) 407 { 408 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, L2_LENGTH) |= 409 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, L2_LENGTH, l2_len)) | 410 (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_LENGTH, ip_len))); 411 } 412 413 /** 414 * hal_tx_ext_desc_set_tcp_seq() - Set TCP Sequence number 415 * @desc: Handle to Tx MSDU Extension Descriptor 416 * @seq_num: Tcp_seq_number for the msdu, if tso is enabled 417 * 418 * Return: none 419 */ 420 static inline void hal_tx_ext_desc_set_tcp_seq(void *desc, 421 uint32_t seq_num) 422 { 423 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER) |= 424 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER, seq_num))); 425 } 426 427 428 /** 429 * hal_tx_ext_desc_set_ip_id() - Set IP Identification field 430 * @desc: Handle to Tx MSDU Extension Descriptor 431 * @id: IP Id field for the msdu, if tso is enabled 432 * 433 * Return: none 434 */ 435 static inline void hal_tx_ext_desc_set_ip_id(void *desc, 436 uint16_t id) 437 { 438 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION) |= 439 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION, id))); 440 } 441 /** 442 * hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment 443 * @desc: Handle to Tx MSDU Extension Descriptor 444 * @frag_num: Fragment number (value can be 0 to 5) 445 * @paddr_lo: Lower 32-bit of Buffer Physical address 446 * @paddr_hi: Upper 32-bit of Buffer Physical address 447 * @length: Buffer Length 448 * 449 * Return: none 450 */ 451 static inline void hal_tx_ext_desc_set_buffer(void *desc, 452 uint8_t frag_num, 453 uint32_t paddr_lo, 454 uint16_t paddr_hi, 455 uint16_t length) 456 { 457 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, 458 (frag_num << 3)) |= 459 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo))); 460 461 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32, 462 (frag_num << 3)) |= 463 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32, 464 (paddr_hi)))); 465 466 HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN, 467 (frag_num << 3)) |= 468 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length))); 469 } 470 471 /** 472 * hal_tx_ext_desc_get_frag_info() - Get the frag_num'th frag iova and len 473 * @desc: Handle to Tx MSDU Extension Descriptor 474 * @frag_num: fragment number (value can be 0 to 5) 475 * @iova: fragment dma address 476 * @len: fragement Length 477 * 478 * Return: None 479 */ 480 static inline void hal_tx_ext_desc_get_frag_info(void *desc, uint8_t frag_num, 481 qdf_dma_addr_t *iova, 482 uint32_t *len) 483 { 484 uint64_t iova_hi; 485 486 *iova = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, 487 BUF0_PTR_31_0, (frag_num << 3)); 488 489 iova_hi = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, 490 BUF0_PTR_39_32, (frag_num << 3)); 491 *iova |= (iova_hi << 32); 492 493 *len = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN, 494 (frag_num << 3)); 495 } 496 497 /** 498 * hal_tx_ext_desc_set_buffer0_param() - Set Buffer 0 Pointer and Length 499 * @desc: Handle to Tx MSDU Extension Descriptor 500 * @paddr_lo: Lower 32-bit of Buffer Physical address 501 * @paddr_hi: Upper 32-bit of Buffer Physical address 502 * @length: Buffer 0 Length 503 * 504 * Return: none 505 */ 506 static inline void hal_tx_ext_desc_set_buffer0_param(void *desc, 507 uint32_t paddr_lo, 508 uint16_t paddr_hi, 509 uint16_t length) 510 { 511 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0) |= 512 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo))); 513 514 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32) |= 515 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, 516 BUF0_PTR_39_32, paddr_hi))); 517 518 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN) |= 519 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length))); 520 } 521 522 /** 523 * hal_tx_ext_desc_set_buffer1_param() - Set Buffer 1 Pointer and Length 524 * @desc: Handle to Tx MSDU Extension Descriptor 525 * @paddr_lo: Lower 32-bit of Buffer Physical address 526 * @paddr_hi: Upper 32-bit of Buffer Physical address 527 * @length: Buffer 1 Length 528 * 529 * Return: none 530 */ 531 static inline void hal_tx_ext_desc_set_buffer1_param(void *desc, 532 uint32_t paddr_lo, 533 uint16_t paddr_hi, 534 uint16_t length) 535 { 536 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0) |= 537 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0, paddr_lo))); 538 539 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_39_32) |= 540 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, 541 BUF1_PTR_39_32, paddr_hi))); 542 543 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_LEN) |= 544 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_LEN, length))); 545 } 546 547 /** 548 * hal_tx_ext_desc_set_buffer2_param() - Set Buffer 2 Pointer and Length 549 * @desc: Handle to Tx MSDU Extension Descriptor 550 * @paddr_lo: Lower 32-bit of Buffer Physical address 551 * @paddr_hi: Upper 32-bit of Buffer Physical address 552 * @length: Buffer 2 Length 553 * 554 * Return: none 555 */ 556 static inline void hal_tx_ext_desc_set_buffer2_param(void *desc, 557 uint32_t paddr_lo, 558 uint16_t paddr_hi, 559 uint16_t length) 560 { 561 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0) |= 562 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0, 563 paddr_lo))); 564 565 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32) |= 566 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32, 567 paddr_hi))); 568 569 HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_LEN) |= 570 ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_LEN, length))); 571 } 572 573 /** 574 * hal_tx_ext_desc_sync - Commit the descriptor to Hardware 575 * @desc_cached: Cached descriptor that software maintains 576 * @hw_desc: Hardware descriptor to be updated 577 * 578 * Return: none 579 */ 580 static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached, 581 uint8_t *hw_desc) 582 { 583 qdf_mem_copy(&hw_desc[0], &desc_cached[0], 584 HAL_TX_EXT_DESC_WITH_META_DATA); 585 } 586 587 /** 588 * hal_tx_ext_desc_get_tso_enable() - Set TSO Enable Flag 589 * @hal_tx_ext_desc: Handle to Tx MSDU Extension Descriptor 590 * 591 * Return: tso_enable value in the descriptor 592 */ 593 static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc) 594 { 595 uint32_t *desc = (uint32_t *) hal_tx_ext_desc; 596 return (*desc & HAL_TX_MSDU_EXTENSION_TSO_ENABLE_MASK) >> 597 HAL_TX_MSDU_EXTENSION_TSO_ENABLE_LSB; 598 } 599 600 /*--------------------------------------------------------------------------- 601 WBM Descriptor accessor APIs for Tx completions 602 ---------------------------------------------------------------------------*/ 603 /** 604 * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type 605 * @hal_desc: completion ring descriptor pointer 606 * 607 * This function will return the type of pointer - buffer or descriptor 608 * 609 * Return: buffer type 610 */ 611 static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc) 612 { 613 uint32_t comp_desc = 614 *(uint32_t *) (((uint8_t *) hal_desc) + 615 HAL_TX_COMP_BUFFER_OR_DESC_TYPE_OFFSET); 616 617 return (comp_desc & HAL_TX_COMP_BUFFER_OR_DESC_TYPE_MASK) >> 618 HAL_TX_COMP_BUFFER_OR_DESC_TYPE_LSB; 619 } 620 621 #ifdef QCA_WIFI_KIWI 622 /** 623 * hal_tx_comp_get_buffer_source() - Get buffer release source value 624 * @hal_desc: completion ring descriptor pointer 625 * 626 * This function will get buffer release source from Tx completion descriptor 627 * 628 * Return: buffer release source 629 */ 630 static inline uint32_t 631 hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl, 632 void *hal_desc) 633 { 634 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 635 636 return hal_soc->ops->hal_tx_comp_get_buffer_source(hal_desc); 637 } 638 #else 639 static inline uint32_t 640 hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl, 641 void *hal_desc) 642 { 643 return HAL_WBM2SW_RELEASE_SRC_GET(hal_desc); 644 } 645 #endif 646 647 /** 648 * hal_tx_comp_get_release_reason() - TQM Release reason 649 * @hal_desc: completion ring descriptor pointer 650 * 651 * This function will return the type of pointer - buffer or descriptor 652 * 653 * Return: buffer type 654 */ 655 static inline 656 uint8_t hal_tx_comp_get_release_reason(void *hal_desc, 657 hal_soc_handle_t hal_soc_hdl) 658 { 659 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 660 661 return hal_soc->ops->hal_tx_comp_get_release_reason(hal_desc); 662 } 663 664 /** 665 * hal_tx_comp_get_peer_id() - Get peer_id value() 666 * @hal_desc: completion ring descriptor pointer 667 * 668 * This function will get peer_id value from Tx completion descriptor 669 * 670 * Return: buffer release source 671 */ 672 static inline uint16_t hal_tx_comp_get_peer_id(void *hal_desc) 673 { 674 uint32_t comp_desc = 675 *(uint32_t *)(((uint8_t *)hal_desc) + 676 HAL_TX_COMP_SW_PEER_ID_OFFSET); 677 678 return (comp_desc & HAL_TX_COMP_SW_PEER_ID_MASK) >> 679 HAL_TX_COMP_SW_PEER_ID_LSB; 680 } 681 682 /** 683 * hal_tx_comp_get_tx_status() - Get tx transmission status() 684 * @hal_desc: completion ring descriptor pointer 685 * 686 * This function will get transmit status value from Tx completion descriptor 687 * 688 * Return: buffer release source 689 */ 690 static inline uint8_t hal_tx_comp_get_tx_status(void *hal_desc) 691 { 692 uint32_t comp_desc = 693 *(uint32_t *)(((uint8_t *)hal_desc) + 694 HAL_TX_COMP_TQM_RELEASE_REASON_OFFSET); 695 696 return (comp_desc & HAL_TX_COMP_TQM_RELEASE_REASON_MASK) >> 697 HAL_TX_COMP_TQM_RELEASE_REASON_LSB; 698 } 699 700 /** 701 * hal_tx_comp_desc_sync() - collect hardware descriptor contents 702 * @hal_desc: hardware descriptor pointer 703 * @comp: software descriptor pointer 704 * @read_status: 0 - Do not read status words from descriptors 705 * 1 - Enable reading of status words from descriptor 706 * 707 * This function will collect hardware release ring element contents and 708 * translate to software descriptor content 709 * 710 * Return: none 711 */ 712 713 static inline void hal_tx_comp_desc_sync(void *hw_desc, 714 struct hal_tx_desc_comp_s *comp, 715 bool read_status) 716 { 717 if (!read_status) 718 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_BASE_LEN); 719 else 720 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_LEN_BYTES); 721 } 722 723 /** 724 * hal_dump_comp_desc() - dump tx completion descriptor 725 * @hal_desc: hardware descriptor pointer 726 * 727 * This function will print tx completion descriptor 728 * 729 * Return: none 730 */ 731 static inline void hal_dump_comp_desc(void *hw_desc) 732 { 733 struct hal_tx_desc_comp_s *comp = 734 (struct hal_tx_desc_comp_s *)hw_desc; 735 uint32_t i; 736 737 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 738 "Current tx completion descriptor is"); 739 740 for (i = 0; i < HAL_TX_COMPLETION_DESC_LEN_DWORDS; i++) { 741 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL, 742 "DWORD[i] = 0x%x", comp->desc[i]); 743 } 744 } 745 746 /** 747 * hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor 748 * @hal_desc: Hardware (WBM) descriptor pointer 749 * @htt_desc: Software HTT descriptor pointer 750 * 751 * This function will read the HTT structure overlaid on WBM descriptor 752 * into a cached software descriptor 753 * 754 */ 755 static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc) 756 { 757 uint8_t *desc = hw_desc + HAL_TX_COMP_HTT_STATUS_OFFSET; 758 759 qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN); 760 } 761 762 /** 763 * hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG 764 * @hal_soc_hdl: Handle to HAL SoC structure 765 * @hal_srng: Handle to HAL SRNG structure 766 * 767 * Return: none 768 */ 769 static inline void hal_tx_init_data_ring(hal_soc_handle_t hal_soc_hdl, 770 hal_ring_handle_t hal_ring_hdl) 771 { 772 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 773 774 hal_soc->ops->hal_tx_init_data_ring(hal_soc_hdl, hal_ring_hdl); 775 } 776 777 /** 778 * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table 779 * 780 * @soc: HAL SoC context 781 * @map: DSCP-TID mapping table 782 * @id: mapping table ID - 0,1 783 * 784 * Return: void 785 */ 786 static inline void hal_tx_set_dscp_tid_map(hal_soc_handle_t hal_soc_hdl, 787 uint8_t *map, uint8_t id) 788 { 789 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 790 791 hal_soc->ops->hal_tx_set_dscp_tid_map(hal_soc, map, id); 792 } 793 794 /** 795 * hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user 796 * 797 * @soc: HAL SoC context 798 * @map: DSCP-TID mapping table 799 * @id : MAP ID 800 * @dscp: DSCP_TID map index 801 * 802 * Return: void 803 */ 804 static inline 805 void hal_tx_update_dscp_tid(hal_soc_handle_t hal_soc_hdl, uint8_t tid, 806 uint8_t id, uint8_t dscp) 807 { 808 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 809 810 hal_soc->ops->hal_tx_update_dscp_tid(hal_soc, tid, id, dscp); 811 } 812 813 /** 814 * hal_tx_comp_get_status() - TQM Release reason 815 * @hal_desc: completion ring Tx status 816 * 817 * This function will parse the WBM completion descriptor and populate in 818 * HAL structure 819 * 820 * Return: none 821 */ 822 static inline void hal_tx_comp_get_status(void *desc, void *ts, 823 hal_soc_handle_t hal_soc_hdl) 824 { 825 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 826 827 hal_soc->ops->hal_tx_comp_get_status(desc, ts, hal_soc); 828 } 829 830 /** 831 * hal_tx_set_pcp_tid_map_default() - Configure default PCP to TID map table 832 * 833 * @soc: HAL SoC context 834 * @map: PCP-TID mapping table 835 * 836 * Return: void 837 */ 838 static inline void hal_tx_set_pcp_tid_map_default(hal_soc_handle_t hal_soc_hdl, 839 uint8_t *map) 840 { 841 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 842 843 hal_soc->ops->hal_tx_set_pcp_tid_map(hal_soc, map); 844 } 845 846 /** 847 * hal_tx_update_pcp_tid_map() - Update PCP to TID map table 848 * 849 * @soc: HAL SoC context 850 * @pcp: pcp value 851 * @tid: tid no 852 * 853 * Return: void 854 */ 855 static inline void hal_tx_update_pcp_tid_map(hal_soc_handle_t hal_soc_hdl, 856 uint8_t pcp, uint8_t tid) 857 { 858 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 859 860 hal_soc->ops->hal_tx_update_pcp_tid_map(hal_soc, tid, tid); 861 } 862 863 /** 864 * hal_tx_set_tidmap_prty() - Configure TIDmap priority 865 * 866 * @soc: HAL SoC context 867 * @val: priority value 868 * 869 * Return: void 870 */ 871 static inline 872 void hal_tx_set_tidmap_prty(hal_soc_handle_t hal_soc_hdl, uint8_t val) 873 { 874 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 875 876 hal_soc->ops->hal_tx_set_tidmap_prty(hal_soc, val); 877 } 878 879 /** 880 * hal_get_wbm_internal_error() - wbm internal error 881 * @hal_desc: completion ring descriptor pointer 882 * 883 * This function will return the type of pointer - buffer or descriptor 884 * 885 * Return: buffer type 886 */ 887 static inline 888 uint8_t hal_get_wbm_internal_error(hal_soc_handle_t hal_soc_hdl, void *hal_desc) 889 { 890 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 891 892 return hal_soc->ops->hal_get_wbm_internal_error(hal_desc); 893 } 894 #endif /* HAL_TX_H */ 895