1 /* 2 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #if !defined(HAL_TX_H) 20 #define HAL_TX_H 21 22 /*--------------------------------------------------------------------------- 23 Include files 24 ---------------------------------------------------------------------------*/ 25 #include "hal_api.h" 26 #include "wcss_version.h" 27 28 #define WBM_RELEASE_RING_5_TX_RATE_STATS_OFFSET 0x00000014 29 #define WBM_RELEASE_RING_5_TX_RATE_STATS_LSB 0 30 #define WBM_RELEASE_RING_5_TX_RATE_STATS_MASK 0xffffffff 31 32 33 /*--------------------------------------------------------------------------- 34 Preprocessor definitions and constants 35 ---------------------------------------------------------------------------*/ 36 #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET 37 38 #define HAL_SET_FLD(desc, block , field) \ 39 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field))) 40 41 #define HAL_SET_FLD_OFFSET(desc, block , field, offset) \ 42 (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field) + (offset))) 43 44 #define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \ 45 do { \ 46 ((struct tlv_32_hdr *) desc)->tlv_tag = (tag); \ 47 ((struct tlv_32_hdr *) desc)->tlv_len = (len); \ 48 } while (0) 49 50 #define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E 51 #define HAL_TX_TCL_CMD_TAG WIFITCL_GSE_CMD_E 52 53 #define HAL_TX_SM(block, field, value) \ 54 ((value << (block ## _ ## field ## _LSB)) & \ 55 (block ## _ ## field ## _MASK)) 56 57 #define HAL_TX_MS(block, field, value) \ 58 (((value) & (block ## _ ## field ## _MASK)) >> \ 59 (block ## _ ## field ## _LSB)) 60 61 #define HAL_TX_DESC_GET(desc, block, field) \ 62 HAL_TX_MS(block, field, HAL_SET_FLD(desc, block, field)) 63 64 #define HAL_TX_DESC_SUBBLOCK_GET(desc, block, sub, field) \ 65 HAL_TX_MS(sub, field, HAL_SET_FLD(desc, block, sub)) 66 67 #define HAL_TX_BUF_TYPE_BUFFER 0 68 #define HAL_TX_BUF_TYPE_EXT_DESC 1 69 70 #define HAL_TX_DESC_LEN_DWORDS (NUM_OF_DWORDS_TCL_DATA_CMD) 71 #define HAL_TX_DESC_LEN_BYTES (NUM_OF_DWORDS_TCL_DATA_CMD * 4) 72 #define HAL_TX_EXTENSION_DESC_LEN_DWORDS (NUM_OF_DWORDS_TX_MSDU_EXTENSION) 73 #define HAL_TX_EXTENSION_DESC_LEN_BYTES (NUM_OF_DWORDS_TX_MSDU_EXTENSION * 4) 74 75 #define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING) 76 #define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4) 77 #define HAL_TX_BITS_PER_TID 3 78 #define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1) 79 #define HAL_TX_NUM_DSCP_PER_REGISTER 10 80 #define HAL_MAX_HW_DSCP_TID_MAPS 2 81 #define HAL_MAX_HW_DSCP_TID_MAPS_11AX 32 82 83 #define HAL_MAX_HW_DSCP_TID_V2_MAPS 48 84 #define HTT_META_HEADER_LEN_BYTES 64 85 #define HAL_TX_EXT_DESC_WITH_META_DATA \ 86 (HTT_META_HEADER_LEN_BYTES + HAL_TX_EXTENSION_DESC_LEN_BYTES) 87 88 /* Length of WBM release ring without the status words */ 89 #define HAL_TX_COMPLETION_DESC_BASE_LEN 12 90 91 #define HAL_TX_COMP_RELEASE_SOURCE_TQM 0 92 #define HAL_TX_COMP_RELEASE_SOURCE_FW 3 93 94 /* Define a place-holder release reason for FW */ 95 #define HAL_TX_COMP_RELEASE_REASON_FW 99 96 97 /* 98 * Offset of HTT Tx Descriptor in WBM Completion 99 * HTT Tx Desc structure is passed from firmware to host overlayed 100 * on wbm_release_ring DWORDs 2,3 ,4 and 5for software based completions 101 * (Exception frames and TQM bypass frames) 102 */ 103 #define HAL_TX_COMP_HTT_STATUS_OFFSET 8 104 #define HAL_TX_COMP_HTT_STATUS_LEN 16 105 106 #define HAL_TX_BUF_TYPE_BUFFER 0 107 #define HAL_TX_BUF_TYPE_EXT_DESC 1 108 109 #define HAL_TX_EXT_DESC_BUF_OFFSET TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 110 #define HAL_TX_EXT_BUF_LOW_MASK TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 111 #define HAL_TX_EXT_BUF_HI_MASK TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 112 #define HAL_TX_EXT_BUF_LEN_MASK TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 113 #define HAL_TX_EXT_BUF_LEN_LSB TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 114 #define HAL_TX_EXT_BUF_WD_SIZE 2 115 116 #define HAL_TX_DESC_ADDRX_EN 0x1 117 #define HAL_TX_DESC_ADDRY_EN 0x2 118 #define HAL_TX_DESC_DEFAULT_LMAC_ID 0x3 119 120 #define HAL_TX_ADDR_SEARCH_DEFAULT 0x0 121 #define HAL_TX_ADDR_INDEX_SEARCH 0x1 122 #define HAL_TX_FLOW_INDEX_SEARCH 0x2 123 124 enum hal_tx_ret_buf_manager { 125 HAL_WBM_SW0_BM_ID = 3, 126 HAL_WBM_SW1_BM_ID = 4, 127 HAL_WBM_SW2_BM_ID = 5, 128 HAL_WBM_SW3_BM_ID = 6, 129 }; 130 131 /*--------------------------------------------------------------------------- 132 Structures 133 ---------------------------------------------------------------------------*/ 134 /** 135 * struct hal_tx_completion_status - HAL Tx completion descriptor contents 136 * @status: frame acked/failed 137 * @release_src: release source = TQM/FW 138 * @ack_frame_rssi: RSSI of the received ACK or BA frame 139 * @first_msdu: Indicates this MSDU is the first MSDU in AMSDU 140 * @last_msdu: Indicates this MSDU is the last MSDU in AMSDU 141 * @msdu_part_of_amsdu : Indicates this MSDU was part of an A-MSDU in MPDU 142 * @bw: Indicates the BW of the upcoming transmission - 143 * <enum 0 transmit_bw_20_MHz> 144 * <enum 1 transmit_bw_40_MHz> 145 * <enum 2 transmit_bw_80_MHz> 146 * <enum 3 transmit_bw_160_MHz> 147 * @pkt_type: Transmit Packet Type 148 * @stbc: When set, STBC transmission rate was used 149 * @ldpc: When set, use LDPC transmission rates 150 * @sgi: <enum 0 0_8_us_sgi > Legacy normal GI 151 * <enum 1 0_4_us_sgi > Legacy short GI 152 * <enum 2 1_6_us_sgi > HE related GI 153 * <enum 3 3_2_us_sgi > HE 154 * @mcs: Transmit MCS Rate 155 * @ofdma: Set when the transmission was an OFDMA transmission 156 * @tones_in_ru: The number of tones in the RU used. 157 * @tsf: Lower 32 bits of the TSF 158 * @ppdu_id: TSF, snapshot of this value when transmission of the 159 * PPDU containing the frame finished. 160 * @transmit_cnt: Number of times this frame has been transmitted 161 * @tid: TID of the flow or MPDU queue 162 * @peer_id: Peer ID of the flow or MPDU queue 163 */ 164 struct hal_tx_completion_status { 165 uint8_t status; 166 uint8_t release_src; 167 uint8_t ack_frame_rssi; 168 uint8_t first_msdu:1, 169 last_msdu:1, 170 msdu_part_of_amsdu:1; 171 uint32_t bw:2, 172 pkt_type:4, 173 stbc:1, 174 ldpc:1, 175 sgi:2, 176 mcs:4, 177 ofdma:1, 178 tones_in_ru:12, 179 valid:1; 180 uint32_t tsf; 181 uint32_t ppdu_id; 182 uint8_t transmit_cnt; 183 uint8_t tid; 184 uint16_t peer_id; 185 }; 186 187 /** 188 * struct hal_tx_desc_comp_s - hal tx completion descriptor contents 189 * @desc: Transmit status information from descriptor 190 */ 191 struct hal_tx_desc_comp_s { 192 uint32_t desc[HAL_TX_COMPLETION_DESC_LEN_DWORDS]; 193 }; 194 195 /* 196 * enum hal_tx_encrypt_type - Type of decrypt cipher used (valid only for RAW) 197 * @HAL_TX_ENCRYPT_TYPE_WEP_40: WEP 40-bit 198 * @HAL_TX_ENCRYPT_TYPE_WEP_10: WEP 10-bit 199 * @HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC: TKIP without MIC 200 * @HAL_TX_ENCRYPT_TYPE_WEP_128: WEP_128 201 * @HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC: TKIP_WITH_MIC 202 * @HAL_TX_ENCRYPT_TYPE_WAPI: WAPI 203 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_128: AES_CCMP_128 204 * @HAL_TX_ENCRYPT_TYPE_NO_CIPHER: NO CIPHER 205 * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_256: AES_CCMP_256 206 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_128: AES_GCMP_128 207 * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_256: AES_GCMP_256 208 * @HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4: WAPI GCM SM4 209 */ 210 enum hal_tx_encrypt_type { 211 HAL_TX_ENCRYPT_TYPE_WEP_40 = 0, 212 HAL_TX_ENCRYPT_TYPE_WEP_104 = 1 , 213 HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC = 2, 214 HAL_TX_ENCRYPT_TYPE_WEP_128 = 3, 215 HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC = 4, 216 HAL_TX_ENCRYPT_TYPE_WAPI = 5, 217 HAL_TX_ENCRYPT_TYPE_AES_CCMP_128 = 6, 218 HAL_TX_ENCRYPT_TYPE_NO_CIPHER = 7, 219 HAL_TX_ENCRYPT_TYPE_AES_CCMP_256 = 8, 220 HAL_TX_ENCRYPT_TYPE_AES_GCMP_128 = 9, 221 HAL_TX_ENCRYPT_TYPE_AES_GCMP_256 = 10, 222 HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4 = 11, 223 }; 224 225 /* 226 * enum hal_tx_encap_type - Encapsulation type that HW will perform 227 * @HAL_TX_ENCAP_TYPE_RAW: Raw Packet Type 228 * @HAL_TX_ENCAP_TYPE_NWIFI: Native WiFi Type 229 * @HAL_TX_ENCAP_TYPE_ETHERNET: Ethernet 230 * @HAL_TX_ENCAP_TYPE_802_3: 802.3 Frame 231 */ 232 enum hal_tx_encap_type { 233 HAL_TX_ENCAP_TYPE_RAW = 0, 234 HAL_TX_ENCAP_TYPE_NWIFI = 1, 235 HAL_TX_ENCAP_TYPE_ETHERNET = 2, 236 HAL_TX_ENCAP_TYPE_802_3 = 3, 237 }; 238 239 /** 240 * enum hal_tx_tqm_release_reason - TQM Release reason codes 241 * 242 * @HAL_TX_TQM_RR_FRAME_ACKED : ACK of BA for it was received 243 * @HAL_TX_TQM_RR_REM_CMD_REM : Remove cmd of type “Remove_mpdus” initiated 244 * by SW 245 * @HAL_TX_TQM_RR_REM_CMD_TX : Remove command of type Remove_transmitted_mpdus 246 * initiated by SW 247 * @HAL_TX_TQM_RR_REM_CMD_NOTX : Remove cmd of type Remove_untransmitted_mpdus 248 * initiated by SW 249 * @HAL_TX_TQM_RR_REM_CMD_AGED : Remove command of type “Remove_aged_mpdus” or 250 * “Remove_aged_msdus” initiated by SW 251 * @HAL_TX_TQM_RR_FW_REASON1 : Remove command where fw indicated that 252 * remove reason is fw_reason1 253 * @HAL_TX_TQM_RR_FW_REASON2 : Remove command where fw indicated that 254 * remove reason is fw_reason2 255 * @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that 256 * remove reason is fw_reason3 257 */ 258 enum hal_tx_tqm_release_reason { 259 HAL_TX_TQM_RR_FRAME_ACKED, 260 HAL_TX_TQM_RR_REM_CMD_REM, 261 HAL_TX_TQM_RR_REM_CMD_TX, 262 HAL_TX_TQM_RR_REM_CMD_NOTX, 263 HAL_TX_TQM_RR_REM_CMD_AGED, 264 HAL_TX_TQM_RR_FW_REASON1, 265 HAL_TX_TQM_RR_FW_REASON2, 266 HAL_TX_TQM_RR_FW_REASON3, 267 }; 268 269 /* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports 270 * @HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT: Default DSCP-TID mapping table 271 * @HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE: DSCP-TID map override table 272 */ 273 enum hal_tx_dscp_tid_table_id { 274 HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT, 275 HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE, 276 }; 277 278 /*--------------------------------------------------------------------------- 279 Function declarations and documentation 280 ---------------------------------------------------------------------------*/ 281 282 /*--------------------------------------------------------------------------- 283 TCL Descriptor accessor APIs 284 ---------------------------------------------------------------------------*/ 285 286 /** 287 * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor 288 * @desc: Handle to Tx Descriptor 289 * @data_length: MSDU length in case of direct descriptor. 290 * Length of link extension descriptor in case of Link extension 291 * descriptor.Includes the length of Metadata 292 * Return: None 293 */ 294 static inline void hal_tx_desc_set_buf_length(void *desc, 295 uint16_t data_length) 296 { 297 HAL_SET_FLD(desc, TCL_DATA_CMD_3, DATA_LENGTH) |= 298 HAL_TX_SM(TCL_DATA_CMD_3, DATA_LENGTH, data_length); 299 } 300 301 /** 302 * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor 303 * @desc: Handle to Tx Descriptor 304 * @offset: Packet offset from Metadata in case of direct buffer descriptor. 305 * 306 * Return: void 307 */ 308 static inline void hal_tx_desc_set_buf_offset(void *desc, 309 uint8_t offset) 310 { 311 HAL_SET_FLD(desc, TCL_DATA_CMD_3, PACKET_OFFSET) |= 312 HAL_TX_SM(TCL_DATA_CMD_3, PACKET_OFFSET, offset); 313 } 314 315 /** 316 * hal_tx_desc_set_encap_type - Set encapsulation type in Tx Descriptor 317 * @desc: Handle to Tx Descriptor 318 * @encap_type: Encapsulation that HW will perform 319 * 320 * Return: void 321 * 322 */ 323 static inline void hal_tx_desc_set_encap_type(void *desc, 324 enum hal_tx_encap_type encap_type) 325 { 326 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCAP_TYPE) |= 327 HAL_TX_SM(TCL_DATA_CMD_2, ENCAP_TYPE, encap_type); 328 } 329 330 /** 331 * hal_tx_desc_set_encrypt_type - Sets the Encrypt Type in Tx Descriptor 332 * @desc: Handle to Tx Descriptor 333 * @type: Encrypt Type 334 * 335 * Return: void 336 */ 337 static inline void hal_tx_desc_set_encrypt_type(void *desc, 338 enum hal_tx_encrypt_type type) 339 { 340 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCRYPT_TYPE) |= 341 HAL_TX_SM(TCL_DATA_CMD_2, ENCRYPT_TYPE, type); 342 } 343 344 /** 345 * hal_tx_desc_set_addr_search_flags - Enable AddrX and AddrY search flags 346 * @desc: Handle to Tx Descriptor 347 * @flags: Bit 0 - AddrY search enable, Bit 1 - AddrX search enable 348 * 349 * Return: void 350 */ 351 static inline void hal_tx_desc_set_addr_search_flags(void *desc, 352 uint8_t flags) 353 { 354 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRX_EN) |= 355 HAL_TX_SM(TCL_DATA_CMD_2, ADDRX_EN, (flags & 0x1)); 356 357 HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRY_EN) |= 358 HAL_TX_SM(TCL_DATA_CMD_2, ADDRY_EN, (flags >> 1)); 359 } 360 361 /** 362 * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags 363 * Tx Descriptor for MSDU_buffer type 364 * @desc: Handle to Tx Descriptor 365 * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits) 366 * 367 * Return: void 368 */ 369 static inline void hal_tx_desc_set_l4_checksum_en(void *desc, 370 uint8_t en) 371 { 372 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 373 (HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV4_CHECKSUM_EN, en) | 374 HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV6_CHECKSUM_EN, en) | 375 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV4_CHECKSUM_EN, en) | 376 HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV6_CHECKSUM_EN, en)); 377 } 378 379 /** 380 * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in 381 * Tx Descriptor for MSDU_buffer type 382 * @desc: Handle to Tx Descriptor 383 * @checksum_en_flags: ipv4 checksum enable flags 384 * 385 * Return: void 386 */ 387 static inline void hal_tx_desc_set_l3_checksum_en(void *desc, 388 uint8_t en) 389 { 390 HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= 391 HAL_TX_SM(TCL_DATA_CMD_3, IPV4_CHECKSUM_EN, en); 392 } 393 394 /** 395 * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor 396 * @desc:Handle to Tx Descriptor 397 * @metadata: Metadata to be sent to Firmware 398 * 399 * Return: void 400 */ 401 static inline void hal_tx_desc_set_fw_metadata(void *desc, 402 uint16_t metadata) 403 { 404 HAL_SET_FLD(desc, TCL_DATA_CMD_2, TCL_CMD_NUMBER) |= 405 HAL_TX_SM(TCL_DATA_CMD_2, TCL_CMD_NUMBER, metadata); 406 } 407 408 /** 409 * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor. 410 * @desc:Handle to Tx Descriptor 411 * @to_fw: if set, Forward packet to FW along with classification result 412 * 413 * Return: void 414 */ 415 static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw) 416 { 417 HAL_SET_FLD(desc, TCL_DATA_CMD_3, TO_FW) |= 418 HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw); 419 } 420 421 /** 422 * hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor 423 * @desc: Handle to Tx Descriptor 424 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 425 * enabling the interpretation of the 'Mesh Control Present' bit 426 * (bit 8) of QoS Control (otherwise this bit is ignored), 427 * For native WiFi frames, this indicates that a 'Mesh Control' field 428 * is present between the header and the LLC. 429 * 430 * Return: void 431 */ 432 static inline void hal_tx_desc_set_mesh_en(void *desc, uint8_t en) 433 { 434 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 435 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 436 } 437 438 /** 439 * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in 440 * frame) to be used for Tx Frame 441 * @desc: Handle to Tx Descriptor 442 * @hlos_tid: HLOS TID 443 * 444 * Return: void 445 */ 446 static inline void hal_tx_desc_set_hlos_tid(void *desc, 447 uint8_t hlos_tid) 448 { 449 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID) |= 450 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID, hlos_tid); 451 452 HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |= 453 HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1); 454 } 455 /** 456 * hal_tx_desc_sync - Commit the descriptor to Hardware 457 * @hal_tx_des_cached: Cached descriptor that software maintains 458 * @hw_desc: Hardware descriptor to be updated 459 */ 460 static inline void hal_tx_desc_sync(void *hal_tx_desc_cached, 461 void *hw_desc) 462 { 463 qdf_mem_copy((hw_desc + sizeof(struct tlv_32_hdr)), 464 hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES); 465 } 466 467 /*--------------------------------------------------------------------------- 468 Tx MSDU Extension Descriptor accessor APIs 469 ---------------------------------------------------------------------------*/ 470 /** 471 * hal_tx_ext_desc_set_tso_enable() - Set TSO Enable Flag 472 * @desc: Handle to Tx MSDU Extension Descriptor 473 * @tso_en: bool value set to true if TSO is enabled 474 * 475 * Return: none 476 */ 477 static inline void hal_tx_ext_desc_set_tso_enable(void *desc, 478 uint8_t tso_en) 479 { 480 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TSO_ENABLE) |= 481 HAL_TX_SM(TX_MSDU_EXTENSION_0, TSO_ENABLE, tso_en); 482 } 483 484 /** 485 * hal_tx_ext_desc_set_tso_flags() - Set TSO Flags 486 * @desc: Handle to Tx MSDU Extension Descriptor 487 * @falgs: 32-bit word with all TSO flags consolidated 488 * 489 * Return: none 490 */ 491 static inline void hal_tx_ext_desc_set_tso_flags(void *desc, 492 uint32_t tso_flags) 493 { 494 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_0, TSO_ENABLE, 0) = 495 tso_flags; 496 } 497 498 /** 499 * hal_tx_ext_desc_set_tcp_flags() - Enable HW Checksum offload 500 * @desc: Handle to Tx MSDU Extension Descriptor 501 * @tcp_flags: TCP flags {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 502 * @mask: TCP flag mask. Tcp_flag is inserted into the header 503 * based on the mask, if tso is enabled 504 * 505 * Return: none 506 */ 507 static inline void hal_tx_ext_desc_set_tcp_flags(void *desc, 508 uint16_t tcp_flags, 509 uint16_t mask) 510 { 511 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_0, TCP_FLAG) |= 512 ((HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG, tcp_flags)) | 513 (HAL_TX_SM(TX_MSDU_EXTENSION_0, TCP_FLAG_MASK, mask))); 514 } 515 516 /** 517 * hal_tx_ext_desc_set_msdu_length() - Set L2 and IP Lengths 518 * @desc: Handle to Tx MSDU Extension Descriptor 519 * @l2_len: L2 length for the msdu, if tso is enabled 520 * @ip_len: IP length for the msdu, if tso is enabled 521 * 522 * Return: none 523 */ 524 static inline void hal_tx_ext_desc_set_msdu_length(void *desc, 525 uint16_t l2_len, 526 uint16_t ip_len) 527 { 528 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_1, L2_LENGTH) |= 529 ((HAL_TX_SM(TX_MSDU_EXTENSION_1, L2_LENGTH, l2_len)) | 530 (HAL_TX_SM(TX_MSDU_EXTENSION_1, IP_LENGTH, ip_len))); 531 } 532 533 /** 534 * hal_tx_ext_desc_set_tcp_seq() - Set TCP Sequence number 535 * @desc: Handle to Tx MSDU Extension Descriptor 536 * @seq_num: Tcp_seq_number for the msdu, if tso is enabled 537 * 538 * Return: none 539 */ 540 static inline void hal_tx_ext_desc_set_tcp_seq(void *desc, 541 uint32_t seq_num) 542 { 543 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER) |= 544 ((HAL_TX_SM(TX_MSDU_EXTENSION_2, TCP_SEQ_NUMBER, seq_num))); 545 } 546 547 548 /** 549 * hal_tx_ext_desc_set_ip_id() - Set IP Identification field 550 * @desc: Handle to Tx MSDU Extension Descriptor 551 * @id: IP Id field for the msdu, if tso is enabled 552 * 553 * Return: none 554 */ 555 static inline void hal_tx_ext_desc_set_ip_id(void *desc, 556 uint16_t id) 557 { 558 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_3, IP_IDENTIFICATION) |= 559 ((HAL_TX_SM(TX_MSDU_EXTENSION_3, IP_IDENTIFICATION, id))); 560 } 561 /** 562 * hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment 563 * @desc: Handle to Tx MSDU Extension Descriptor 564 * @frag_num: Fragment number (value can be 0 to 5) 565 * @paddr_lo: Lower 32-bit of Buffer Physical address 566 * @paddr_hi: Upper 32-bit of Buffer Physical address 567 * @length: Buffer Length 568 * 569 * Return: none 570 */ 571 static inline void hal_tx_ext_desc_set_buffer(void *desc, 572 uint8_t frag_num, 573 uint32_t paddr_lo, 574 uint16_t paddr_hi, 575 uint16_t length) 576 { 577 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, 578 (frag_num << 3)) |= 579 ((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo))); 580 581 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32, 582 (frag_num << 3)) |= 583 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_PTR_39_32, 584 (paddr_hi)))); 585 586 HAL_SET_FLD_OFFSET(desc, TX_MSDU_EXTENSION_7, BUF0_LEN, 587 (frag_num << 3)) |= 588 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length))); 589 } 590 591 /** 592 * hal_tx_ext_desc_set_buffer0_param() - Set Buffer 0 Pointer and Length 593 * @desc: Handle to Tx MSDU Extension Descriptor 594 * @paddr_lo: Lower 32-bit of Buffer Physical address 595 * @paddr_hi: Upper 32-bit of Buffer Physical address 596 * @length: Buffer 0 Length 597 * 598 * Return: none 599 */ 600 static inline void hal_tx_ext_desc_set_buffer0_param(void *desc, 601 uint32_t paddr_lo, 602 uint16_t paddr_hi, 603 uint16_t length) 604 { 605 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_6, BUF0_PTR_31_0) |= 606 ((HAL_TX_SM(TX_MSDU_EXTENSION_6, BUF0_PTR_31_0, paddr_lo))); 607 608 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_PTR_39_32) |= 609 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, 610 BUF0_PTR_39_32, paddr_hi))); 611 612 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_7, BUF0_LEN) |= 613 ((HAL_TX_SM(TX_MSDU_EXTENSION_7, BUF0_LEN, length))); 614 } 615 616 /** 617 * hal_tx_ext_desc_set_buffer1_param() - Set Buffer 1 Pointer and Length 618 * @desc: Handle to Tx MSDU Extension Descriptor 619 * @paddr_lo: Lower 32-bit of Buffer Physical address 620 * @paddr_hi: Upper 32-bit of Buffer Physical address 621 * @length: Buffer 1 Length 622 * 623 * Return: none 624 */ 625 static inline void hal_tx_ext_desc_set_buffer1_param(void *desc, 626 uint32_t paddr_lo, 627 uint16_t paddr_hi, 628 uint16_t length) 629 { 630 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_8, BUF1_PTR_31_0) |= 631 ((HAL_TX_SM(TX_MSDU_EXTENSION_8, BUF1_PTR_31_0, paddr_lo))); 632 633 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_PTR_39_32) |= 634 ((HAL_TX_SM(TX_MSDU_EXTENSION_9, 635 BUF1_PTR_39_32, paddr_hi))); 636 637 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_9, BUF1_LEN) |= 638 ((HAL_TX_SM(TX_MSDU_EXTENSION_9, BUF1_LEN, length))); 639 } 640 641 /** 642 * hal_tx_ext_desc_set_buffer2_param() - Set Buffer 2 Pointer and Length 643 * @desc: Handle to Tx MSDU Extension Descriptor 644 * @paddr_lo: Lower 32-bit of Buffer Physical address 645 * @paddr_hi: Upper 32-bit of Buffer Physical address 646 * @length: Buffer 2 Length 647 * 648 * Return: none 649 */ 650 static inline void hal_tx_ext_desc_set_buffer2_param(void *desc, 651 uint32_t paddr_lo, 652 uint16_t paddr_hi, 653 uint16_t length) 654 { 655 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_10, BUF2_PTR_31_0) |= 656 ((HAL_TX_SM(TX_MSDU_EXTENSION_10, BUF2_PTR_31_0, 657 paddr_lo))); 658 659 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_PTR_39_32) |= 660 ((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_PTR_39_32, 661 paddr_hi))); 662 663 HAL_SET_FLD(desc, TX_MSDU_EXTENSION_11, BUF2_LEN) |= 664 ((HAL_TX_SM(TX_MSDU_EXTENSION_11, BUF2_LEN, length))); 665 } 666 667 /** 668 * hal_tx_ext_desc_sync - Commit the descriptor to Hardware 669 * @desc_cached: Cached descriptor that software maintains 670 * @hw_desc: Hardware descriptor to be updated 671 * 672 * Return: none 673 */ 674 static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached, 675 uint8_t *hw_desc) 676 { 677 qdf_mem_copy(&hw_desc[0], &desc_cached[0], 678 HAL_TX_EXT_DESC_WITH_META_DATA); 679 } 680 681 /** 682 * hal_tx_ext_desc_get_tso_enable() - Set TSO Enable Flag 683 * @hal_tx_ext_desc: Handle to Tx MSDU Extension Descriptor 684 * 685 * Return: tso_enable value in the descriptor 686 */ 687 static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc) 688 { 689 uint32_t *desc = (uint32_t *) hal_tx_ext_desc; 690 return (*desc & TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK) >> 691 TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB; 692 } 693 694 /*--------------------------------------------------------------------------- 695 WBM Descriptor accessor APIs for Tx completions 696 ---------------------------------------------------------------------------*/ 697 /** 698 * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor 699 * @hal_desc: completion ring descriptor pointer 700 * 701 * This function will tx descriptor id, cookie, within hardware completion 702 * descriptor 703 * 704 * Return: cookie 705 */ 706 static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc) 707 { 708 uint32_t comp_desc = 709 *(uint32_t *) (((uint8_t *) hal_desc) + 710 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET); 711 712 /* Cookie is placed on 2nd word */ 713 return (comp_desc & BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) >> 714 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB; 715 } 716 717 /** 718 * hal_tx_comp_get_paddr() - Get paddr within comp descriptor 719 * @hal_desc: completion ring descriptor pointer 720 * 721 * This function will get buffer physical address within hardware completion 722 * descriptor 723 * 724 * Return: Buffer physical address 725 */ 726 static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc) 727 { 728 uint32_t paddr_lo; 729 uint32_t paddr_hi; 730 731 paddr_lo = *(uint32_t *) (((uint8_t *) hal_desc) + 732 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET); 733 734 paddr_hi = *(uint32_t *) (((uint8_t *) hal_desc) + 735 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET); 736 737 paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) >> 738 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB; 739 740 return (qdf_dma_addr_t) (paddr_lo | (((uint64_t) paddr_hi) << 32)); 741 } 742 743 /** 744 * hal_tx_comp_get_buffer_source() - Get buffer release source value 745 * @hal_desc: completion ring descriptor pointer 746 * 747 * This function will get buffer release source from Tx completion descriptor 748 * 749 * Return: buffer release source 750 */ 751 static inline uint32_t hal_tx_comp_get_buffer_source(void *hal_desc) 752 { 753 uint32_t comp_desc = 754 *(uint32_t *) (((uint8_t *) hal_desc) + 755 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET); 756 757 return (comp_desc & WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK) >> 758 WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB; 759 } 760 761 /** 762 * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type 763 * @hal_desc: completion ring descriptor pointer 764 * 765 * This function will return the type of pointer - buffer or descriptor 766 * 767 * Return: buffer type 768 */ 769 static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc) 770 { 771 uint32_t comp_desc = 772 *(uint32_t *) (((uint8_t *) hal_desc) + 773 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET); 774 775 return (comp_desc & WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> 776 WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB; 777 } 778 779 /** 780 * hal_tx_comp_get_release_reason() - TQM Release reason 781 * @hal_desc: completion ring descriptor pointer 782 * 783 * This function will return the type of pointer - buffer or descriptor 784 * 785 * Return: buffer type 786 */ 787 static inline uint8_t hal_tx_comp_get_release_reason(void *hal_desc) 788 { 789 uint32_t comp_desc = 790 *(uint32_t *) (((uint8_t *) hal_desc) + 791 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET); 792 793 return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >> 794 WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB; 795 } 796 797 /** 798 * hal_tx_comp_desc_sync() - collect hardware descriptor contents 799 * @hal_desc: hardware descriptor pointer 800 * @comp: software descriptor pointer 801 * @read_status: 0 - Do not read status words from descriptors 802 * 1 - Enable reading of status words from descriptor 803 * 804 * This function will collect hardware release ring element contents and 805 * translate to software descriptor content 806 * 807 * Return: none 808 */ 809 810 static inline void hal_tx_comp_desc_sync(void *hw_desc, 811 struct hal_tx_desc_comp_s *comp, 812 bool read_status) 813 { 814 if (!read_status) 815 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_BASE_LEN); 816 else 817 qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_LEN_BYTES); 818 } 819 820 /** 821 * hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor 822 * @hal_desc: Hardware (WBM) descriptor pointer 823 * @htt_desc: Software HTT descriptor pointer 824 * 825 * This function will read the HTT structure overlaid on WBM descriptor 826 * into a cached software descriptor 827 * 828 */ 829 static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc) 830 { 831 uint8_t *desc = hw_desc + HAL_TX_COMP_HTT_STATUS_OFFSET; 832 833 qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN); 834 } 835 836 /** 837 * hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG 838 * @hal_soc: Handle to HAL SoC structure 839 * @hal_srng: Handle to HAL SRNG structure 840 * 841 * Return: none 842 */ 843 static inline void hal_tx_init_data_ring(void *hal_soc, void *hal_srng) 844 { 845 uint8_t *desc_addr; 846 struct hal_srng_params srng_params; 847 uint32_t desc_size; 848 uint32_t num_desc; 849 850 hal_get_srng_params(hal_soc, hal_srng, &srng_params); 851 852 desc_addr = (uint8_t *)srng_params.ring_base_vaddr; 853 desc_size = sizeof(struct tcl_data_cmd); 854 num_desc = srng_params.num_entries; 855 856 while (num_desc) { 857 HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, 858 desc_size); 859 desc_addr += (desc_size + sizeof(struct tlv_32_hdr)); 860 num_desc--; 861 } 862 } 863 864 /** 865 * hal_tx_desc_set_dscp_tid_table_id() - Sets DSCP to TID conversion table ID 866 * @hal_soc: Handle to HAL SoC structure 867 * @desc: Handle to Tx Descriptor 868 * @id: DSCP to tid conversion table to be used for this frame 869 * 870 * Return: void 871 */ 872 static inline void hal_tx_desc_set_dscp_tid_table_id(struct hal_soc *hal_soc, 873 void *desc, uint8_t id) 874 { 875 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id(desc, id); 876 } 877 878 /** 879 * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table 880 * 881 * @soc: HAL SoC context 882 * @map: DSCP-TID mapping table 883 * @id: mapping table ID - 0,1 884 * 885 * Return: void 886 */ 887 static inline void hal_tx_set_dscp_tid_map(struct hal_soc *hal_soc, 888 uint8_t *map, uint8_t id) 889 { 890 hal_soc->ops->hal_tx_set_dscp_tid_map(hal_soc, map, id); 891 } 892 893 /** 894 * hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user 895 * 896 * @soc: HAL SoC context 897 * @map: DSCP-TID mapping table 898 * @id : MAP ID 899 * @dscp: DSCP_TID map index 900 * 901 * Return: void 902 */ 903 static inline void hal_tx_update_dscp_tid(struct hal_soc *hal_soc, uint8_t tid, 904 uint8_t id, uint8_t dscp) 905 { 906 hal_soc->ops->hal_tx_update_dscp_tid(hal_soc, tid, id, dscp); 907 } 908 909 /** 910 * hal_tx_desc_set_lmac_id - Set the lmac_id value 911 * @desc: Handle to Tx Descriptor 912 * @lmac_id: mac Id to ast matching 913 * b00 – mac 0 914 * b01 – mac 1 915 * b10 – mac 2 916 * b11 – all macs (legacy HK way) 917 * 918 * Return: void 919 */ 920 static inline void hal_tx_desc_set_lmac_id(struct hal_soc *hal_soc, 921 void *desc, uint8_t lmac_id) 922 { 923 hal_soc->ops->hal_tx_desc_set_lmac_id(desc, lmac_id); 924 } 925 926 /** 927 * hal_tx_desc_set_search_type - Set the search type value 928 * @desc: Handle to Tx Descriptor 929 * @search_type: search type 930 * 0 – Normal search 931 * 1 – Index based address search 932 * 2 – Index based flow search 933 * 934 * Return: void 935 */ 936 static inline void hal_tx_desc_set_search_type(struct hal_soc *hal_soc, 937 void *desc, uint8_t search_type) 938 { 939 hal_soc->ops->hal_tx_desc_set_search_type(desc, search_type); 940 } 941 942 /** 943 * hal_tx_desc_set_search_index - Set the search index value 944 * @desc: Handle to Tx Descriptor 945 * @search_index: The index that will be used for index based address or 946 * flow search. The field is valid when 'search_type' is 947 * 1 0r 2 948 * 949 * Return: void 950 */ 951 static inline void hal_tx_desc_set_search_index(struct hal_soc *hal_soc, 952 void *desc, 953 uint32_t search_index) 954 { 955 hal_soc->ops->hal_tx_desc_set_search_index(desc, search_index); 956 } 957 958 /** 959 * hal_tx_comp_get_status() - TQM Release reason 960 * @hal_desc: completion ring Tx status 961 * 962 * This function will parse the WBM completion descriptor and populate in 963 * HAL structure 964 * 965 * Return: none 966 */ 967 static inline void hal_tx_comp_get_status(void *desc, void *ts, void *hal) 968 { 969 struct hal_soc *hal_soc = hal; 970 971 hal_soc->ops->hal_tx_comp_get_status(desc, ts); 972 } 973 974 975 /** 976 * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor 977 * @desc: Handle to Tx Descriptor 978 * @paddr: Physical Address 979 * @pool_id: Return Buffer Manager ID 980 * @desc_id: Descriptor ID 981 * @type: 0 - Address points to a MSDU buffer 982 * 1 - Address points to MSDU extension descriptor 983 * 984 * Return: void 985 */ 986 static inline void hal_tx_desc_set_buf_addr(void *desc, dma_addr_t paddr, 987 uint8_t pool_id, uint32_t desc_id, uint8_t type, void *hal) 988 { 989 struct hal_soc *hal_soc = hal; 990 991 hal_soc->ops->hal_tx_desc_set_buf_addr(desc, paddr, pool_id, 992 desc_id, type); 993 994 } 995 #endif /* HAL_TX_H */ 996