1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "hal_hw_headers.h" 21 #include "hal_api.h" 22 #include "hal_reo.h" 23 #include "target_type.h" 24 #include "qdf_module.h" 25 #include "wcss_version.h" 26 #include <qdf_tracepoint.h> 27 #include "qdf_ssr_driver_dump.h" 28 29 struct tcl_data_cmd gtcl_data_symbol __attribute__((used)); 30 31 #ifdef QCA_WIFI_QCA8074 32 void hal_qca6290_attach(struct hal_soc *hal); 33 #endif 34 #ifdef QCA_WIFI_QCA8074 35 void hal_qca8074_attach(struct hal_soc *hal); 36 #endif 37 #if defined(QCA_WIFI_QCA8074V2) || defined(QCA_WIFI_QCA6018) || \ 38 defined(QCA_WIFI_QCA9574) 39 void hal_qca8074v2_attach(struct hal_soc *hal); 40 #endif 41 #ifdef QCA_WIFI_QCA6390 42 void hal_qca6390_attach(struct hal_soc *hal); 43 #endif 44 #ifdef QCA_WIFI_QCA6490 45 void hal_qca6490_attach(struct hal_soc *hal); 46 #endif 47 #ifdef QCA_WIFI_QCN9000 48 void hal_qcn9000_attach(struct hal_soc *hal); 49 #endif 50 #ifdef QCA_WIFI_QCN9224 51 void hal_qcn9224v2_attach(struct hal_soc *hal); 52 #endif 53 #if defined(QCA_WIFI_QCN6122) || defined(QCA_WIFI_QCN9160) 54 void hal_qcn6122_attach(struct hal_soc *hal); 55 #endif 56 #ifdef QCA_WIFI_QCN6432 57 void hal_qcn6432_attach(struct hal_soc *hal); 58 #endif 59 #ifdef QCA_WIFI_QCA6750 60 void hal_qca6750_attach(struct hal_soc *hal); 61 #endif 62 #ifdef QCA_WIFI_QCA5018 63 void hal_qca5018_attach(struct hal_soc *hal); 64 #endif 65 #ifdef QCA_WIFI_QCA5332 66 void hal_qca5332_attach(struct hal_soc *hal); 67 #endif 68 #ifdef QCA_WIFI_KIWI 69 void hal_kiwi_attach(struct hal_soc *hal); 70 #endif 71 72 #ifdef ENABLE_VERBOSE_DEBUG 73 bool is_hal_verbose_debug_enabled; 74 #endif 75 76 #define HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(x) ((x) + 0x4) 77 #define HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR(x) ((x) + 0x8) 78 #define HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc) 79 #define HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10) 80 81 #ifdef ENABLE_HAL_REG_WR_HISTORY 82 struct hal_reg_write_fail_history hal_reg_wr_hist; 83 84 void hal_reg_wr_fail_history_add(struct hal_soc *hal_soc, 85 uint32_t offset, 86 uint32_t wr_val, uint32_t rd_val) 87 { 88 struct hal_reg_write_fail_entry *record; 89 int idx; 90 91 idx = hal_history_get_next_index(&hal_soc->reg_wr_fail_hist->index, 92 HAL_REG_WRITE_HIST_SIZE); 93 94 record = &hal_soc->reg_wr_fail_hist->record[idx]; 95 96 record->timestamp = qdf_get_log_timestamp(); 97 record->reg_offset = offset; 98 record->write_val = wr_val; 99 record->read_val = rd_val; 100 } 101 102 static void hal_reg_write_fail_history_init(struct hal_soc *hal) 103 { 104 hal->reg_wr_fail_hist = &hal_reg_wr_hist; 105 106 qdf_atomic_set(&hal->reg_wr_fail_hist->index, -1); 107 } 108 #else 109 static void hal_reg_write_fail_history_init(struct hal_soc *hal) 110 { 111 } 112 #endif 113 114 /** 115 * hal_get_srng_ring_id() - get the ring id of a described ring 116 * @hal: hal_soc data structure 117 * @ring_type: type enum describing the ring 118 * @ring_num: which ring of the ring type 119 * @mac_id: which mac does the ring belong to (or 0 for non-lmac rings) 120 * 121 * Return: the ring id or -EINVAL if the ring does not exist. 122 */ 123 static int hal_get_srng_ring_id(struct hal_soc *hal, int ring_type, 124 int ring_num, int mac_id) 125 { 126 struct hal_hw_srng_config *ring_config = 127 HAL_SRNG_CONFIG(hal, ring_type); 128 int ring_id; 129 130 if (ring_num >= ring_config->max_rings) { 131 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_INFO, 132 "%s: ring_num exceeded maximum no. of supported rings", 133 __func__); 134 /* TODO: This is a programming error. Assert if this happens */ 135 return -EINVAL; 136 } 137 138 /* 139 * Some DMAC rings share a common source ring, hence don't provide them 140 * with separate ring IDs per LMAC. 141 */ 142 if (ring_config->lmac_ring && !ring_config->dmac_cmn_ring) { 143 ring_id = (ring_config->start_ring_id + ring_num + 144 (mac_id * HAL_MAX_RINGS_PER_LMAC)); 145 } else { 146 ring_id = ring_config->start_ring_id + ring_num; 147 } 148 149 return ring_id; 150 } 151 152 static struct hal_srng *hal_get_srng(struct hal_soc *hal, int ring_id) 153 { 154 /* TODO: Should we allocate srng structures dynamically? */ 155 return &(hal->srng_list[ring_id]); 156 } 157 158 #ifndef SHADOW_REG_CONFIG_DISABLED 159 #define HP_OFFSET_IN_REG_START 1 160 #define OFFSET_FROM_HP_TO_TP 4 161 static void hal_update_srng_hp_tp_address(struct hal_soc *hal_soc, 162 int shadow_config_index, 163 int ring_type, 164 int ring_num) 165 { 166 struct hal_srng *srng; 167 int ring_id; 168 struct hal_hw_srng_config *ring_config = 169 HAL_SRNG_CONFIG(hal_soc, ring_type); 170 171 ring_id = hal_get_srng_ring_id(hal_soc, ring_type, ring_num, 0); 172 if (ring_id < 0) 173 return; 174 175 srng = hal_get_srng(hal_soc, ring_id); 176 177 if (ring_config->ring_dir == HAL_SRNG_DST_RING) { 178 srng->u.dst_ring.tp_addr = SHADOW_REGISTER(shadow_config_index) 179 + hal_soc->dev_base_addr; 180 hal_debug("tp_addr=%pK dev base addr %pK index %u", 181 srng->u.dst_ring.tp_addr, hal_soc->dev_base_addr, 182 shadow_config_index); 183 } else { 184 srng->u.src_ring.hp_addr = SHADOW_REGISTER(shadow_config_index) 185 + hal_soc->dev_base_addr; 186 hal_debug("hp_addr=%pK dev base addr %pK index %u", 187 srng->u.src_ring.hp_addr, 188 hal_soc->dev_base_addr, shadow_config_index); 189 } 190 191 } 192 #endif 193 194 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE 195 void hal_set_one_target_reg_config(struct hal_soc *hal, 196 uint32_t target_reg_offset, 197 int list_index) 198 { 199 int i = list_index; 200 201 qdf_assert_always(i < MAX_GENERIC_SHADOW_REG); 202 hal->list_shadow_reg_config[i].target_register = 203 target_reg_offset; 204 hal->num_generic_shadow_regs_configured++; 205 } 206 207 qdf_export_symbol(hal_set_one_target_reg_config); 208 209 #define REO_R0_DESTINATION_RING_CTRL_ADDR_OFFSET 0x4 210 #define MAX_REO_REMAP_SHADOW_REGS 4 211 QDF_STATUS hal_set_shadow_regs(void *hal_soc) 212 { 213 uint32_t target_reg_offset; 214 struct hal_soc *hal = (struct hal_soc *)hal_soc; 215 int i; 216 struct hal_hw_srng_config *srng_config = 217 &hal->hw_srng_table[WBM2SW_RELEASE]; 218 uint32_t reo_reg_base; 219 220 reo_reg_base = hal_get_reo_reg_base_offset(hal_soc); 221 222 target_reg_offset = 223 HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(reo_reg_base); 224 225 for (i = 0; i < MAX_REO_REMAP_SHADOW_REGS; i++) { 226 hal_set_one_target_reg_config(hal, target_reg_offset, i); 227 target_reg_offset += REO_R0_DESTINATION_RING_CTRL_ADDR_OFFSET; 228 } 229 230 target_reg_offset = srng_config->reg_start[HP_OFFSET_IN_REG_START]; 231 target_reg_offset += (srng_config->reg_size[HP_OFFSET_IN_REG_START] 232 * HAL_IPA_TX_COMP_RING_IDX); 233 234 hal_set_one_target_reg_config(hal, target_reg_offset, i); 235 return QDF_STATUS_SUCCESS; 236 } 237 238 qdf_export_symbol(hal_set_shadow_regs); 239 240 QDF_STATUS hal_construct_shadow_regs(void *hal_soc) 241 { 242 struct hal_soc *hal = (struct hal_soc *)hal_soc; 243 int shadow_config_index = hal->num_shadow_registers_configured; 244 int i; 245 int num_regs = hal->num_generic_shadow_regs_configured; 246 247 for (i = 0; i < num_regs; i++) { 248 qdf_assert_always(shadow_config_index < MAX_SHADOW_REGISTERS); 249 hal->shadow_config[shadow_config_index].addr = 250 hal->list_shadow_reg_config[i].target_register; 251 hal->list_shadow_reg_config[i].shadow_config_index = 252 shadow_config_index; 253 hal->list_shadow_reg_config[i].va = 254 SHADOW_REGISTER(shadow_config_index) + 255 (uintptr_t)hal->dev_base_addr; 256 hal_debug("target_reg %x, shadow register 0x%x shadow_index 0x%x", 257 hal->shadow_config[shadow_config_index].addr, 258 SHADOW_REGISTER(shadow_config_index), 259 shadow_config_index); 260 shadow_config_index++; 261 hal->num_shadow_registers_configured++; 262 } 263 return QDF_STATUS_SUCCESS; 264 } 265 266 qdf_export_symbol(hal_construct_shadow_regs); 267 #endif 268 269 #ifndef SHADOW_REG_CONFIG_DISABLED 270 271 QDF_STATUS hal_set_one_shadow_config(void *hal_soc, 272 int ring_type, 273 int ring_num) 274 { 275 uint32_t target_register; 276 struct hal_soc *hal = (struct hal_soc *)hal_soc; 277 struct hal_hw_srng_config *srng_config = &hal->hw_srng_table[ring_type]; 278 int shadow_config_index = hal->num_shadow_registers_configured; 279 280 if (shadow_config_index >= MAX_SHADOW_REGISTERS) { 281 QDF_ASSERT(0); 282 return QDF_STATUS_E_RESOURCES; 283 } 284 285 hal->num_shadow_registers_configured++; 286 287 target_register = srng_config->reg_start[HP_OFFSET_IN_REG_START]; 288 target_register += (srng_config->reg_size[HP_OFFSET_IN_REG_START] 289 *ring_num); 290 291 /* if the ring is a dst ring, we need to shadow the tail pointer */ 292 if (srng_config->ring_dir == HAL_SRNG_DST_RING) 293 target_register += OFFSET_FROM_HP_TO_TP; 294 295 hal->shadow_config[shadow_config_index].addr = target_register; 296 297 /* update hp/tp addr in the hal_soc structure*/ 298 hal_update_srng_hp_tp_address(hal_soc, shadow_config_index, ring_type, 299 ring_num); 300 301 hal_debug("target_reg %x, shadow register 0x%x shadow_index 0x%x, ring_type %d, ring num %d", 302 target_register, 303 SHADOW_REGISTER(shadow_config_index), 304 shadow_config_index, 305 ring_type, ring_num); 306 307 return QDF_STATUS_SUCCESS; 308 } 309 310 qdf_export_symbol(hal_set_one_shadow_config); 311 312 QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc) 313 { 314 int ring_type, ring_num; 315 struct hal_soc *hal = (struct hal_soc *)hal_soc; 316 317 for (ring_type = 0; ring_type < MAX_RING_TYPES; ring_type++) { 318 struct hal_hw_srng_config *srng_config = 319 &hal->hw_srng_table[ring_type]; 320 321 if (ring_type == CE_SRC || 322 ring_type == CE_DST || 323 ring_type == CE_DST_STATUS) 324 continue; 325 326 if (srng_config->lmac_ring) 327 continue; 328 329 for (ring_num = 0; ring_num < srng_config->max_rings; 330 ring_num++) 331 hal_set_one_shadow_config(hal_soc, ring_type, ring_num); 332 } 333 334 return QDF_STATUS_SUCCESS; 335 } 336 337 qdf_export_symbol(hal_construct_srng_shadow_regs); 338 #else 339 340 QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc) 341 { 342 return QDF_STATUS_SUCCESS; 343 } 344 345 qdf_export_symbol(hal_construct_srng_shadow_regs); 346 347 QDF_STATUS hal_set_one_shadow_config(void *hal_soc, int ring_type, 348 int ring_num) 349 { 350 return QDF_STATUS_SUCCESS; 351 } 352 qdf_export_symbol(hal_set_one_shadow_config); 353 #endif 354 355 void hal_get_shadow_config(void *hal_soc, 356 struct pld_shadow_reg_v2_cfg **shadow_config, 357 int *num_shadow_registers_configured) 358 { 359 struct hal_soc *hal = (struct hal_soc *)hal_soc; 360 361 *shadow_config = &hal->shadow_config[0].v2; 362 *num_shadow_registers_configured = 363 hal->num_shadow_registers_configured; 364 } 365 qdf_export_symbol(hal_get_shadow_config); 366 367 #ifdef CONFIG_SHADOW_V3 368 void hal_get_shadow_v3_config(void *hal_soc, 369 struct pld_shadow_reg_v3_cfg **shadow_config, 370 int *num_shadow_registers_configured) 371 { 372 struct hal_soc *hal = (struct hal_soc *)hal_soc; 373 374 *shadow_config = &hal->shadow_config[0].v3; 375 *num_shadow_registers_configured = 376 hal->num_shadow_registers_configured; 377 } 378 qdf_export_symbol(hal_get_shadow_v3_config); 379 #endif 380 381 static bool hal_validate_shadow_register(struct hal_soc *hal, 382 uint32_t *destination, 383 uint32_t *shadow_address) 384 { 385 unsigned int index; 386 uint32_t *shadow_0_offset = SHADOW_REGISTER(0) + hal->dev_base_addr; 387 int destination_ba_offset = 388 ((char *)destination) - (char *)hal->dev_base_addr; 389 390 index = shadow_address - shadow_0_offset; 391 392 if (index >= MAX_SHADOW_REGISTERS) { 393 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 394 "%s: index %x out of bounds", __func__, index); 395 goto error; 396 } else if (hal->shadow_config[index].addr != destination_ba_offset) { 397 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 398 "%s: sanity check failure, expected %x, found %x", 399 __func__, destination_ba_offset, 400 hal->shadow_config[index].addr); 401 goto error; 402 } 403 return true; 404 error: 405 qdf_print("baddr %pK, destination %pK, shadow_address %pK s0offset %pK index %x", 406 hal->dev_base_addr, destination, shadow_address, 407 shadow_0_offset, index); 408 QDF_BUG(0); 409 return false; 410 } 411 412 static void hal_target_based_configure(struct hal_soc *hal) 413 { 414 /* 415 * Indicate Initialization of srngs to avoid force wake 416 * as umac power collapse is not enabled yet 417 */ 418 hal->init_phase = true; 419 420 switch (hal->target_type) { 421 #ifdef QCA_WIFI_QCA6290 422 case TARGET_TYPE_QCA6290: 423 hal->use_register_windowing = true; 424 hal_qca6290_attach(hal); 425 break; 426 #endif 427 #ifdef QCA_WIFI_QCA6390 428 case TARGET_TYPE_QCA6390: 429 hal->use_register_windowing = true; 430 hal_qca6390_attach(hal); 431 break; 432 #endif 433 #ifdef QCA_WIFI_QCA6490 434 case TARGET_TYPE_QCA6490: 435 hal->use_register_windowing = true; 436 hal_qca6490_attach(hal); 437 break; 438 #endif 439 #ifdef QCA_WIFI_QCA6750 440 case TARGET_TYPE_QCA6750: 441 hal->use_register_windowing = true; 442 hal->static_window_map = true; 443 hal_qca6750_attach(hal); 444 break; 445 #endif 446 #ifdef QCA_WIFI_KIWI 447 case TARGET_TYPE_KIWI: 448 case TARGET_TYPE_MANGO: 449 case TARGET_TYPE_PEACH: 450 hal->use_register_windowing = true; 451 hal_kiwi_attach(hal); 452 break; 453 #endif 454 #if defined(QCA_WIFI_QCA8074) && defined(WIFI_TARGET_TYPE_3_0) 455 case TARGET_TYPE_QCA8074: 456 hal_qca8074_attach(hal); 457 break; 458 #endif 459 460 #if defined(QCA_WIFI_QCA8074V2) 461 case TARGET_TYPE_QCA8074V2: 462 hal_qca8074v2_attach(hal); 463 break; 464 #endif 465 466 #if defined(QCA_WIFI_QCA6018) 467 case TARGET_TYPE_QCA6018: 468 hal_qca8074v2_attach(hal); 469 break; 470 #endif 471 472 #if defined(QCA_WIFI_QCA9574) 473 case TARGET_TYPE_QCA9574: 474 hal_qca8074v2_attach(hal); 475 break; 476 #endif 477 478 #if defined(QCA_WIFI_QCN6122) 479 case TARGET_TYPE_QCN6122: 480 hal->use_register_windowing = true; 481 /* 482 * Static window map is enabled for qcn9000 to use 2mb bar 483 * size and use multiple windows to write into registers. 484 */ 485 hal->static_window_map = true; 486 hal_qcn6122_attach(hal); 487 break; 488 #endif 489 490 #if defined(QCA_WIFI_QCN9160) 491 case TARGET_TYPE_QCN9160: 492 hal->use_register_windowing = true; 493 /* 494 * Static window map is enabled for qcn9160 to use 2mb bar 495 * size and use multiple windows to write into registers. 496 */ 497 hal->static_window_map = true; 498 hal_qcn6122_attach(hal); 499 break; 500 #endif 501 502 #if defined(QCA_WIFI_QCN6432) 503 case TARGET_TYPE_QCN6432: 504 hal->use_register_windowing = true; 505 /* 506 * Static window map is enabled for qcn6432 to use 2mb bar 507 * size and use multiple windows to write into registers. 508 */ 509 hal->static_window_map = true; 510 hal_qcn6432_attach(hal); 511 break; 512 #endif 513 514 #ifdef QCA_WIFI_QCN9000 515 case TARGET_TYPE_QCN9000: 516 hal->use_register_windowing = true; 517 /* 518 * Static window map is enabled for qcn9000 to use 2mb bar 519 * size and use multiple windows to write into registers. 520 */ 521 hal->static_window_map = true; 522 hal_qcn9000_attach(hal); 523 break; 524 #endif 525 #ifdef QCA_WIFI_QCA5018 526 case TARGET_TYPE_QCA5018: 527 hal->use_register_windowing = true; 528 hal->static_window_map = true; 529 hal_qca5018_attach(hal); 530 break; 531 #endif 532 #ifdef QCA_WIFI_QCN9224 533 case TARGET_TYPE_QCN9224: 534 hal->use_register_windowing = true; 535 hal->static_window_map = true; 536 if (hal->version == 1) 537 qdf_assert_always(0); 538 else 539 hal_qcn9224v2_attach(hal); 540 break; 541 #endif 542 #ifdef QCA_WIFI_QCA5332 543 case TARGET_TYPE_QCA5332: 544 hal->use_register_windowing = true; 545 hal->static_window_map = true; 546 hal_qca5332_attach(hal); 547 break; 548 #endif 549 #ifdef QCA_WIFI_WCN6450 550 case TARGET_TYPE_WCN6450: 551 hal->use_register_windowing = true; 552 hal->static_window_map = true; 553 hal_wcn6450_attach(hal); 554 break; 555 #endif 556 default: 557 break; 558 } 559 } 560 561 uint32_t hal_get_target_type(hal_soc_handle_t hal_soc_hdl) 562 { 563 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 564 struct hif_target_info *tgt_info = 565 hif_get_target_info_handle(hal_soc->hif_handle); 566 567 return tgt_info->target_type; 568 } 569 570 qdf_export_symbol(hal_get_target_type); 571 572 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 573 /** 574 * hal_is_reg_write_tput_level_high() - throughput level for delayed reg writes 575 * @hal: hal_soc pointer 576 * 577 * Return: true if throughput is high, else false. 578 */ 579 static inline bool hal_is_reg_write_tput_level_high(struct hal_soc *hal) 580 { 581 int bw_level = hif_get_bandwidth_level(hal->hif_handle); 582 583 return (bw_level >= PLD_BUS_WIDTH_MEDIUM) ? true : false; 584 } 585 586 static inline 587 char *hal_fill_reg_write_srng_stats(struct hal_srng *srng, 588 char *buf, qdf_size_t size) 589 { 590 qdf_scnprintf(buf, size, "enq %u deq %u coal %u direct %u", 591 srng->wstats.enqueues, srng->wstats.dequeues, 592 srng->wstats.coalesces, srng->wstats.direct); 593 return buf; 594 } 595 596 /* bytes for local buffer */ 597 #define HAL_REG_WRITE_SRNG_STATS_LEN 100 598 599 #ifndef WLAN_SOFTUMAC_SUPPORT 600 void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl) 601 { 602 struct hal_srng *srng; 603 char buf[HAL_REG_WRITE_SRNG_STATS_LEN]; 604 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 605 606 srng = hal_get_srng(hal, HAL_SRNG_SW2TCL1); 607 hal_debug("SW2TCL1: %s", 608 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 609 610 srng = hal_get_srng(hal, HAL_SRNG_WBM2SW0_RELEASE); 611 hal_debug("WBM2SW0: %s", 612 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 613 614 srng = hal_get_srng(hal, HAL_SRNG_REO2SW1); 615 hal_debug("REO2SW1: %s", 616 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 617 618 srng = hal_get_srng(hal, HAL_SRNG_REO2SW2); 619 hal_debug("REO2SW2: %s", 620 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 621 622 srng = hal_get_srng(hal, HAL_SRNG_REO2SW3); 623 hal_debug("REO2SW3: %s", 624 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 625 } 626 627 void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl) 628 { 629 uint32_t *hist; 630 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 631 632 hist = hal->stats.wstats.sched_delay; 633 hal_debug("wstats: enq %u deq %u coal %u direct %u q_depth %u max_q %u sched-delay hist %u %u %u %u", 634 qdf_atomic_read(&hal->stats.wstats.enqueues), 635 hal->stats.wstats.dequeues, 636 qdf_atomic_read(&hal->stats.wstats.coalesces), 637 qdf_atomic_read(&hal->stats.wstats.direct), 638 qdf_atomic_read(&hal->stats.wstats.q_depth), 639 hal->stats.wstats.max_q_depth, 640 hist[REG_WRITE_SCHED_DELAY_SUB_100us], 641 hist[REG_WRITE_SCHED_DELAY_SUB_1000us], 642 hist[REG_WRITE_SCHED_DELAY_SUB_5000us], 643 hist[REG_WRITE_SCHED_DELAY_GT_5000us]); 644 } 645 #else 646 void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl) 647 { 648 } 649 650 /* TODO: Need separate logic for Evros */ 651 void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl) 652 { 653 } 654 #endif 655 656 int hal_get_reg_write_pending_work(void *hal_soc) 657 { 658 struct hal_soc *hal = (struct hal_soc *)hal_soc; 659 660 return qdf_atomic_read(&hal->active_work_cnt); 661 } 662 663 #endif 664 665 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 666 #ifdef MEMORY_DEBUG 667 /* 668 * Length of the queue(array) used to hold delayed register writes. 669 * Must be a multiple of 2. 670 */ 671 #define HAL_REG_WRITE_QUEUE_LEN 128 672 #else 673 #define HAL_REG_WRITE_QUEUE_LEN 32 674 #endif 675 676 /** 677 * hal_process_reg_write_q_elem() - process a register write queue element 678 * @hal: hal_soc pointer 679 * @q_elem: pointer to hal register write queue element 680 * 681 * Return: The value which was written to the address 682 */ 683 static uint32_t 684 hal_process_reg_write_q_elem(struct hal_soc *hal, 685 struct hal_reg_write_q_elem *q_elem) 686 { 687 struct hal_srng *srng = q_elem->srng; 688 uint32_t write_val; 689 690 SRNG_LOCK(&srng->lock); 691 692 srng->reg_write_in_progress = false; 693 srng->wstats.dequeues++; 694 695 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 696 q_elem->dequeue_val = srng->u.src_ring.hp; 697 hal_write_address_32_mb(hal, 698 srng->u.src_ring.hp_addr, 699 srng->u.src_ring.hp, false); 700 write_val = srng->u.src_ring.hp; 701 } else { 702 q_elem->dequeue_val = srng->u.dst_ring.tp; 703 hal_write_address_32_mb(hal, 704 srng->u.dst_ring.tp_addr, 705 srng->u.dst_ring.tp, false); 706 write_val = srng->u.dst_ring.tp; 707 } 708 hal_srng_reg_his_add(srng, write_val); 709 710 q_elem->valid = 0; 711 srng->last_dequeue_time = q_elem->dequeue_time; 712 SRNG_UNLOCK(&srng->lock); 713 714 return write_val; 715 } 716 717 /** 718 * hal_reg_write_fill_sched_delay_hist() - fill reg write delay histogram in hal 719 * @hal: hal_soc pointer 720 * @delay_us: delay in us 721 * 722 * Return: None 723 */ 724 static inline void hal_reg_write_fill_sched_delay_hist(struct hal_soc *hal, 725 uint64_t delay_us) 726 { 727 uint32_t *hist; 728 729 hist = hal->stats.wstats.sched_delay; 730 731 if (delay_us < 100) 732 hist[REG_WRITE_SCHED_DELAY_SUB_100us]++; 733 else if (delay_us < 1000) 734 hist[REG_WRITE_SCHED_DELAY_SUB_1000us]++; 735 else if (delay_us < 5000) 736 hist[REG_WRITE_SCHED_DELAY_SUB_5000us]++; 737 else 738 hist[REG_WRITE_SCHED_DELAY_GT_5000us]++; 739 } 740 741 #ifdef SHADOW_WRITE_DELAY 742 743 #define SHADOW_WRITE_MIN_DELTA_US 5 744 #define SHADOW_WRITE_DELAY_US 50 745 746 /* 747 * Never add those srngs which are performance relate. 748 * The delay itself will hit performance heavily. 749 */ 750 #define IS_SRNG_MATCH(s) ((s)->ring_id == HAL_SRNG_CE_1_DST_STATUS || \ 751 (s)->ring_id == HAL_SRNG_CE_1_DST) 752 753 static inline bool hal_reg_write_need_delay(struct hal_reg_write_q_elem *elem) 754 { 755 struct hal_srng *srng = elem->srng; 756 struct hal_soc *hal; 757 qdf_time_t now; 758 qdf_iomem_t real_addr; 759 760 if (qdf_unlikely(!srng)) 761 return false; 762 763 hal = srng->hal_soc; 764 if (qdf_unlikely(!hal)) 765 return false; 766 767 /* Check if it is target srng, and valid shadow reg */ 768 if (qdf_likely(!IS_SRNG_MATCH(srng))) 769 return false; 770 771 if (srng->ring_dir == HAL_SRNG_SRC_RING) 772 real_addr = SRNG_SRC_ADDR(srng, HP); 773 else 774 real_addr = SRNG_DST_ADDR(srng, TP); 775 if (!hal_validate_shadow_register(hal, real_addr, elem->addr)) 776 return false; 777 778 /* Check the time delta from last write of same srng */ 779 now = qdf_get_log_timestamp(); 780 if (qdf_log_timestamp_to_usecs(now - srng->last_dequeue_time) > 781 SHADOW_WRITE_MIN_DELTA_US) 782 return false; 783 784 /* Delay dequeue, and record */ 785 qdf_udelay(SHADOW_WRITE_DELAY_US); 786 787 srng->wstats.dequeue_delay++; 788 hal->stats.wstats.dequeue_delay++; 789 790 return true; 791 } 792 #else 793 static inline bool hal_reg_write_need_delay(struct hal_reg_write_q_elem *elem) 794 { 795 return false; 796 } 797 #endif 798 799 /** 800 * hal_reg_write_work() - Worker to process delayed writes 801 * @arg: hal_soc pointer 802 * 803 * Return: None 804 */ 805 static void hal_reg_write_work(void *arg) 806 { 807 int32_t q_depth, write_val; 808 struct hal_soc *hal = arg; 809 struct hal_reg_write_q_elem *q_elem; 810 uint64_t delta_us; 811 uint8_t ring_id; 812 uint32_t *addr; 813 uint32_t num_processed = 0; 814 815 q_elem = &hal->reg_write_queue[(hal->read_idx)]; 816 q_elem->work_scheduled_time = qdf_get_log_timestamp(); 817 q_elem->cpu_id = qdf_get_cpu(); 818 819 /* Make sure q_elem consistent in the memory for multi-cores */ 820 qdf_rmb(); 821 if (!q_elem->valid) 822 return; 823 824 q_depth = qdf_atomic_read(&hal->stats.wstats.q_depth); 825 if (q_depth > hal->stats.wstats.max_q_depth) 826 hal->stats.wstats.max_q_depth = q_depth; 827 828 if (hif_prevent_link_low_power_states(hal->hif_handle)) { 829 hal->stats.wstats.prevent_l1_fails++; 830 return; 831 } 832 833 while (true) { 834 qdf_rmb(); 835 if (!q_elem->valid) 836 break; 837 838 qdf_rmb(); 839 /* buy some more time to make sure all fields 840 * in q_elem is updated per different CPUs, in 841 * case wmb/rmb is not taken effect 842 */ 843 if (qdf_unlikely(!q_elem->srng || 844 (qdf_atomic_read(&q_elem->ring_id) != 845 q_elem->srng->ring_id))) { 846 hal_err_rl("q_elem fields not up to date %d %d", 847 q_elem->srng->ring_id, 848 qdf_atomic_read(&q_elem->ring_id)); 849 qdf_assert_always(0); 850 } 851 852 q_elem->dequeue_time = qdf_get_log_timestamp(); 853 ring_id = q_elem->srng->ring_id; 854 addr = q_elem->addr; 855 delta_us = qdf_log_timestamp_to_usecs(q_elem->dequeue_time - 856 q_elem->enqueue_time); 857 hal_reg_write_fill_sched_delay_hist(hal, delta_us); 858 859 hal->stats.wstats.dequeues++; 860 qdf_atomic_dec(&hal->stats.wstats.q_depth); 861 862 if (hal_reg_write_need_delay(q_elem)) 863 hal_verbose_debug("Delay reg writer for srng 0x%x, addr 0x%pK", 864 q_elem->srng->ring_id, q_elem->addr); 865 866 write_val = hal_process_reg_write_q_elem(hal, q_elem); 867 hal_verbose_debug("read_idx %u srng 0x%x, addr 0x%pK dequeue_val %u sched delay %llu us", 868 hal->read_idx, ring_id, addr, write_val, delta_us); 869 870 qdf_trace_dp_del_reg_write(ring_id, q_elem->enqueue_val, 871 q_elem->dequeue_val, 872 q_elem->enqueue_time, 873 q_elem->dequeue_time); 874 875 num_processed++; 876 hal->read_idx = (hal->read_idx + 1) & 877 (HAL_REG_WRITE_QUEUE_LEN - 1); 878 q_elem = &hal->reg_write_queue[(hal->read_idx)]; 879 } 880 881 hif_allow_link_low_power_states(hal->hif_handle); 882 /* 883 * Decrement active_work_cnt by the number of elements dequeued after 884 * hif_allow_link_low_power_states. 885 * This makes sure that hif_try_complete_tasks will wait till we make 886 * the bus access in hif_allow_link_low_power_states. This will avoid 887 * race condition between delayed register worker and bus suspend 888 * (system suspend or runtime suspend). 889 * 890 * The following decrement should be done at the end! 891 */ 892 qdf_atomic_sub(num_processed, &hal->active_work_cnt); 893 } 894 895 static void __hal_flush_reg_write_work(struct hal_soc *hal) 896 { 897 qdf_flush_work(&hal->reg_write_work); 898 qdf_disable_work(&hal->reg_write_work); 899 } 900 901 void hal_flush_reg_write_work(hal_soc_handle_t hal_handle) 902 { __hal_flush_reg_write_work((struct hal_soc *)hal_handle); 903 } 904 905 /** 906 * hal_reg_write_enqueue() - enqueue register writes into kworker 907 * @hal_soc: hal_soc pointer 908 * @srng: srng pointer 909 * @addr: iomem address of register 910 * @value: value to be written to iomem address 911 * 912 * This function executes from within the SRNG LOCK 913 * 914 * Return: None 915 */ 916 static void hal_reg_write_enqueue(struct hal_soc *hal_soc, 917 struct hal_srng *srng, 918 void __iomem *addr, 919 uint32_t value) 920 { 921 struct hal_reg_write_q_elem *q_elem; 922 uint32_t write_idx; 923 924 if (srng->reg_write_in_progress) { 925 hal_verbose_debug("Already in progress srng ring id 0x%x addr 0x%pK val %u", 926 srng->ring_id, addr, value); 927 qdf_atomic_inc(&hal_soc->stats.wstats.coalesces); 928 srng->wstats.coalesces++; 929 return; 930 } 931 932 write_idx = qdf_atomic_inc_return(&hal_soc->write_idx); 933 934 write_idx = write_idx & (HAL_REG_WRITE_QUEUE_LEN - 1); 935 936 q_elem = &hal_soc->reg_write_queue[write_idx]; 937 938 if (q_elem->valid) { 939 hal_err("queue full"); 940 QDF_BUG(0); 941 return; 942 } 943 944 qdf_atomic_inc(&hal_soc->stats.wstats.enqueues); 945 srng->wstats.enqueues++; 946 947 qdf_atomic_inc(&hal_soc->stats.wstats.q_depth); 948 949 q_elem->srng = srng; 950 q_elem->addr = addr; 951 qdf_atomic_set(&q_elem->ring_id, srng->ring_id); 952 q_elem->enqueue_val = value; 953 q_elem->enqueue_time = qdf_get_log_timestamp(); 954 955 /* 956 * Before the valid flag is set to true, all the other 957 * fields in the q_elem needs to be updated in memory. 958 * Else there is a chance that the dequeuing worker thread 959 * might read stale entries and process incorrect srng. 960 */ 961 qdf_wmb(); 962 q_elem->valid = true; 963 964 /* 965 * After all other fields in the q_elem has been updated 966 * in memory successfully, the valid flag needs to be updated 967 * in memory in time too. 968 * Else there is a chance that the dequeuing worker thread 969 * might read stale valid flag and the work will be bypassed 970 * for this round. And if there is no other work scheduled 971 * later, this hal register writing won't be updated any more. 972 */ 973 qdf_wmb(); 974 975 srng->reg_write_in_progress = true; 976 qdf_atomic_inc(&hal_soc->active_work_cnt); 977 978 hal_verbose_debug("write_idx %u srng ring id 0x%x addr 0x%pK val %u", 979 write_idx, srng->ring_id, addr, value); 980 981 qdf_queue_work(hal_soc->qdf_dev, hal_soc->reg_write_wq, 982 &hal_soc->reg_write_work); 983 } 984 985 /** 986 * hal_delayed_reg_write_init() - Initialization function for delayed reg writes 987 * @hal: hal_soc pointer 988 * 989 * Initialize main data structures to process register writes in a delayed 990 * workqueue. 991 * 992 * Return: QDF_STATUS_SUCCESS on success else a QDF error. 993 */ 994 static QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal) 995 { 996 hal->reg_write_wq = 997 qdf_alloc_high_prior_ordered_workqueue("hal_register_write_wq"); 998 qdf_create_work(0, &hal->reg_write_work, hal_reg_write_work, hal); 999 hal->reg_write_queue = qdf_mem_malloc(HAL_REG_WRITE_QUEUE_LEN * 1000 sizeof(*hal->reg_write_queue)); 1001 if (!hal->reg_write_queue) { 1002 hal_err("unable to allocate memory"); 1003 QDF_BUG(0); 1004 return QDF_STATUS_E_NOMEM; 1005 } 1006 1007 /* Initial value of indices */ 1008 hal->read_idx = 0; 1009 qdf_atomic_set(&hal->write_idx, -1); 1010 return QDF_STATUS_SUCCESS; 1011 } 1012 1013 /** 1014 * hal_delayed_reg_write_deinit() - De-Initialize delayed reg write processing 1015 * @hal: hal_soc pointer 1016 * 1017 * De-initialize main data structures to process register writes in a delayed 1018 * workqueue. 1019 * 1020 * Return: None 1021 */ 1022 static void hal_delayed_reg_write_deinit(struct hal_soc *hal) 1023 { 1024 __hal_flush_reg_write_work(hal); 1025 1026 qdf_flush_workqueue(0, hal->reg_write_wq); 1027 qdf_destroy_workqueue(0, hal->reg_write_wq); 1028 qdf_mem_free(hal->reg_write_queue); 1029 } 1030 1031 #else 1032 static inline QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal) 1033 { 1034 return QDF_STATUS_SUCCESS; 1035 } 1036 1037 static inline void hal_delayed_reg_write_deinit(struct hal_soc *hal) 1038 { 1039 } 1040 #endif 1041 1042 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 1043 #ifdef HAL_RECORD_SUSPEND_WRITE 1044 static struct hal_suspend_write_history 1045 g_hal_suspend_write_history[HAL_SUSPEND_WRITE_HISTORY_MAX]; 1046 1047 static 1048 void hal_event_suspend_record(uint8_t ring_id, uint32_t value, uint32_t count) 1049 { 1050 uint32_t index = qdf_atomic_read(g_hal_suspend_write_history.index) & 1051 (HAL_SUSPEND_WRITE_HISTORY_MAX - 1); 1052 struct hal_suspend_write_record *cur_event = 1053 &hal_suspend_write_event.record[index]; 1054 1055 cur_event->ts = qdf_get_log_timestamp(); 1056 cur_event->ring_id = ring_id; 1057 cur_event->value = value; 1058 cur_event->direct_wcount = count; 1059 qdf_atomic_inc(g_hal_suspend_write_history.index); 1060 } 1061 1062 static inline 1063 void hal_record_suspend_write(uint8_t ring_id, uint32_t value, uint32_t count) 1064 { 1065 if (hif_rtpm_get_state() >= HIF_RTPM_STATE_SUSPENDING) 1066 hal_event_suspend_record(ring_id, value, count); 1067 } 1068 #else 1069 static inline 1070 void hal_record_suspend_write(uint8_t ring_id, uint32_t value, uint32_t count) 1071 { 1072 } 1073 #endif 1074 1075 #ifdef QCA_WIFI_QCA6750 1076 void hal_delayed_reg_write(struct hal_soc *hal_soc, 1077 struct hal_srng *srng, 1078 void __iomem *addr, 1079 uint32_t value) 1080 { 1081 uint8_t vote_access; 1082 1083 switch (srng->ring_type) { 1084 case CE_SRC: 1085 case CE_DST: 1086 case CE_DST_STATUS: 1087 vote_access = hif_get_ep_vote_access(hal_soc->hif_handle, 1088 HIF_EP_VOTE_NONDP_ACCESS); 1089 if ((vote_access == HIF_EP_VOTE_ACCESS_DISABLE) || 1090 (vote_access == HIF_EP_VOTE_INTERMEDIATE_ACCESS && 1091 PLD_MHI_STATE_L0 == 1092 pld_get_mhi_state(hal_soc->qdf_dev->dev))) { 1093 hal_write_address_32_mb(hal_soc, addr, value, false); 1094 hal_srng_reg_his_add(srng, value); 1095 qdf_atomic_inc(&hal_soc->stats.wstats.direct); 1096 srng->wstats.direct++; 1097 } else { 1098 hal_reg_write_enqueue(hal_soc, srng, addr, value); 1099 } 1100 break; 1101 default: 1102 if (hif_get_ep_vote_access(hal_soc->hif_handle, 1103 HIF_EP_VOTE_DP_ACCESS) == 1104 HIF_EP_VOTE_ACCESS_DISABLE || 1105 hal_is_reg_write_tput_level_high(hal_soc) || 1106 PLD_MHI_STATE_L0 == 1107 pld_get_mhi_state(hal_soc->qdf_dev->dev)) { 1108 hal_write_address_32_mb(hal_soc, addr, value, false); 1109 hal_srng_reg_his_add(srng, value); 1110 qdf_atomic_inc(&hal_soc->stats.wstats.direct); 1111 srng->wstats.direct++; 1112 } else { 1113 hal_reg_write_enqueue(hal_soc, srng, addr, value); 1114 } 1115 1116 break; 1117 } 1118 } 1119 #else 1120 void hal_delayed_reg_write(struct hal_soc *hal_soc, 1121 struct hal_srng *srng, 1122 void __iomem *addr, 1123 uint32_t value) 1124 { 1125 if (hal_is_reg_write_tput_level_high(hal_soc) || 1126 pld_is_device_awake(hal_soc->qdf_dev->dev)) { 1127 qdf_atomic_inc(&hal_soc->stats.wstats.direct); 1128 srng->wstats.direct++; 1129 hal_write_address_32_mb(hal_soc, addr, value, false); 1130 hal_srng_reg_his_add(srng, value); 1131 } else { 1132 hal_reg_write_enqueue(hal_soc, srng, addr, value); 1133 } 1134 1135 hal_record_suspend_write(srng->ring_id, value, srng->wstats.direct); 1136 } 1137 #endif 1138 #endif 1139 1140 #ifdef HAL_SRNG_REG_HIS_DEBUG 1141 inline void hal_free_srng_history(struct hal_soc *hal) 1142 { 1143 int i; 1144 1145 for (i = 0; i < HAL_SRNG_ID_MAX; i++) 1146 qdf_mem_free(hal->srng_list[i].reg_his_ctx); 1147 } 1148 1149 inline bool hal_alloc_srng_history(struct hal_soc *hal) 1150 { 1151 int i; 1152 1153 for (i = 0; i < HAL_SRNG_ID_MAX; i++) { 1154 hal->srng_list[i].reg_his_ctx = 1155 qdf_mem_malloc(sizeof(struct hal_srng_reg_his_ctx)); 1156 if (!hal->srng_list[i].reg_his_ctx) { 1157 hal_err("srng_hist alloc failed"); 1158 hal_free_srng_history(hal); 1159 return false; 1160 } 1161 } 1162 1163 return true; 1164 } 1165 #else 1166 inline void hal_free_srng_history(struct hal_soc *hal) 1167 { 1168 } 1169 1170 inline bool hal_alloc_srng_history(struct hal_soc *hal) 1171 { 1172 return true; 1173 } 1174 #endif 1175 1176 void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev) 1177 { 1178 struct hal_soc *hal; 1179 int i; 1180 1181 hal = qdf_mem_common_alloc(sizeof(*hal)); 1182 1183 if (!hal) { 1184 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1185 "%s: hal_soc allocation failed", __func__); 1186 goto fail0; 1187 } 1188 hal->hif_handle = hif_handle; 1189 hal->dev_base_addr = hif_get_dev_ba(hif_handle); /* UMAC */ 1190 hal->dev_base_addr_ce = hif_get_dev_ba_ce(hif_handle); /* CE */ 1191 hal->dev_base_addr_cmem = hif_get_dev_ba_cmem(hif_handle); /* CMEM */ 1192 hal->dev_base_addr_pmm = hif_get_dev_ba_pmm(hif_handle); /* PMM */ 1193 hal->qdf_dev = qdf_dev; 1194 hal->shadow_rdptr_mem_vaddr = (uint32_t *)qdf_mem_alloc_consistent( 1195 qdf_dev, qdf_dev->dev, sizeof(*(hal->shadow_rdptr_mem_vaddr)) * 1196 HAL_SRNG_ID_MAX, &(hal->shadow_rdptr_mem_paddr)); 1197 if (!hal->shadow_rdptr_mem_paddr) { 1198 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1199 "%s: hal->shadow_rdptr_mem_paddr allocation failed", 1200 __func__); 1201 goto fail1; 1202 } 1203 qdf_mem_zero(hal->shadow_rdptr_mem_vaddr, 1204 sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX); 1205 1206 hal->shadow_wrptr_mem_vaddr = 1207 (uint32_t *)qdf_mem_alloc_consistent(qdf_dev, qdf_dev->dev, 1208 sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS, 1209 &(hal->shadow_wrptr_mem_paddr)); 1210 if (!hal->shadow_wrptr_mem_vaddr) { 1211 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1212 "%s: hal->shadow_wrptr_mem_vaddr allocation failed", 1213 __func__); 1214 goto fail2; 1215 } 1216 qdf_mem_zero(hal->shadow_wrptr_mem_vaddr, 1217 sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS); 1218 1219 if (!hal_alloc_srng_history(hal)) 1220 goto fail2; 1221 1222 for (i = 0; i < HAL_SRNG_ID_MAX; i++) { 1223 hal->srng_list[i].initialized = 0; 1224 hal->srng_list[i].ring_id = i; 1225 } 1226 1227 qdf_spinlock_create(&hal->register_access_lock); 1228 hal->register_window = 0; 1229 hal->target_type = hal_get_target_type(hal_soc_to_hal_soc_handle(hal)); 1230 hal->version = hif_get_soc_version(hif_handle); 1231 hal->ops = qdf_mem_malloc(sizeof(*hal->ops)); 1232 1233 if (!hal->ops) { 1234 hal_err("unable to allocable memory for HAL ops"); 1235 goto fail3; 1236 } 1237 1238 hal_target_based_configure(hal); 1239 1240 hal_reg_write_fail_history_init(hal); 1241 1242 qdf_minidump_log(hal, sizeof(*hal), "hal_soc"); 1243 1244 qdf_ssr_driver_dump_register_region("hal_soc", hal, sizeof(*hal)); 1245 1246 qdf_atomic_init(&hal->active_work_cnt); 1247 if (hal_delayed_reg_write_init(hal) != QDF_STATUS_SUCCESS) { 1248 hal_err("unable to initialize delayed reg write"); 1249 goto fail4; 1250 } 1251 1252 hif_rtpm_register(HIF_RTPM_ID_HAL_REO_CMD, NULL); 1253 1254 return (void *)hal; 1255 fail4: 1256 qdf_ssr_driver_dump_unregister_region("hal_soc"); 1257 qdf_minidump_remove(hal, sizeof(*hal), "hal_soc"); 1258 qdf_mem_free(hal->ops); 1259 fail3: 1260 qdf_mem_free_consistent(qdf_dev, qdf_dev->dev, 1261 sizeof(*hal->shadow_wrptr_mem_vaddr) * 1262 HAL_MAX_LMAC_RINGS, 1263 hal->shadow_wrptr_mem_vaddr, 1264 hal->shadow_wrptr_mem_paddr, 0); 1265 fail2: 1266 qdf_mem_free_consistent(qdf_dev, qdf_dev->dev, 1267 sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX, 1268 hal->shadow_rdptr_mem_vaddr, hal->shadow_rdptr_mem_paddr, 0); 1269 fail1: 1270 qdf_mem_common_free(hal); 1271 fail0: 1272 return NULL; 1273 } 1274 qdf_export_symbol(hal_attach); 1275 1276 void hal_get_meminfo(hal_soc_handle_t hal_soc_hdl, struct hal_mem_info *mem) 1277 { 1278 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1279 mem->dev_base_addr = (void *)hal->dev_base_addr; 1280 mem->shadow_rdptr_mem_vaddr = (void *)hal->shadow_rdptr_mem_vaddr; 1281 mem->shadow_wrptr_mem_vaddr = (void *)hal->shadow_wrptr_mem_vaddr; 1282 mem->shadow_rdptr_mem_paddr = (void *)hal->shadow_rdptr_mem_paddr; 1283 mem->shadow_wrptr_mem_paddr = (void *)hal->shadow_wrptr_mem_paddr; 1284 hif_read_phy_mem_base((void *)hal->hif_handle, 1285 (qdf_dma_addr_t *)&mem->dev_base_paddr); 1286 mem->lmac_srng_start_id = HAL_SRNG_LMAC1_ID_START; 1287 return; 1288 } 1289 qdf_export_symbol(hal_get_meminfo); 1290 1291 void hal_detach(void *hal_soc) 1292 { 1293 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1294 1295 hif_rtpm_deregister(HIF_RTPM_ID_HAL_REO_CMD); 1296 hal_delayed_reg_write_deinit(hal); 1297 hal_reo_shared_qaddr_detach((hal_soc_handle_t)hal); 1298 qdf_ssr_driver_dump_unregister_region("hal_soc"); 1299 qdf_minidump_remove(hal, sizeof(*hal), "hal_soc"); 1300 qdf_mem_free(hal->ops); 1301 1302 hal_free_srng_history(hal); 1303 qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev, 1304 sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX, 1305 hal->shadow_rdptr_mem_vaddr, hal->shadow_rdptr_mem_paddr, 0); 1306 qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev, 1307 sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS, 1308 hal->shadow_wrptr_mem_vaddr, hal->shadow_wrptr_mem_paddr, 0); 1309 qdf_mem_common_free(hal); 1310 1311 return; 1312 } 1313 qdf_export_symbol(hal_detach); 1314 1315 #define HAL_CE_CHANNEL_DST_DEST_CTRL_ADDR(x) ((x) + 0x000000b0) 1316 #define HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0x0000ffff 1317 #define HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040) 1318 #define HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1319 1320 /** 1321 * hal_ce_dst_setup() - Initialize CE destination ring registers 1322 * @hal: HAL SOC handle 1323 * @srng: SRNG ring pointer 1324 * @ring_num: ring number 1325 */ 1326 static inline void hal_ce_dst_setup(struct hal_soc *hal, struct hal_srng *srng, 1327 int ring_num) 1328 { 1329 uint32_t reg_val = 0; 1330 uint32_t reg_addr; 1331 struct hal_hw_srng_config *ring_config = 1332 HAL_SRNG_CONFIG(hal, CE_DST); 1333 1334 /* set DEST_MAX_LENGTH according to ce assignment */ 1335 reg_addr = HAL_CE_CHANNEL_DST_DEST_CTRL_ADDR( 1336 ring_config->reg_start[R0_INDEX] + 1337 (ring_num * ring_config->reg_size[R0_INDEX])); 1338 1339 reg_val = HAL_REG_READ(hal, reg_addr); 1340 reg_val &= ~HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK; 1341 reg_val |= srng->u.dst_ring.max_buffer_length & 1342 HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK; 1343 HAL_REG_WRITE(hal, reg_addr, reg_val); 1344 1345 if (srng->prefetch_timer) { 1346 reg_addr = HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR( 1347 ring_config->reg_start[R0_INDEX] + 1348 (ring_num * ring_config->reg_size[R0_INDEX])); 1349 1350 reg_val = HAL_REG_READ(hal, reg_addr); 1351 reg_val &= ~HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK; 1352 reg_val |= srng->prefetch_timer; 1353 HAL_REG_WRITE(hal, reg_addr, reg_val); 1354 reg_val = HAL_REG_READ(hal, reg_addr); 1355 } 1356 1357 } 1358 1359 void hal_reo_read_write_ctrl_ix(hal_soc_handle_t hal_soc_hdl, bool read, 1360 uint32_t *ix0, uint32_t *ix1, 1361 uint32_t *ix2, uint32_t *ix3) 1362 { 1363 uint32_t reg_offset; 1364 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1365 uint32_t reo_reg_base; 1366 1367 reo_reg_base = hal_get_reo_reg_base_offset(hal_soc_hdl); 1368 1369 if (read) { 1370 if (ix0) { 1371 reg_offset = 1372 HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR( 1373 reo_reg_base); 1374 *ix0 = HAL_REG_READ(hal, reg_offset); 1375 } 1376 1377 if (ix1) { 1378 reg_offset = 1379 HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR( 1380 reo_reg_base); 1381 *ix1 = HAL_REG_READ(hal, reg_offset); 1382 } 1383 1384 if (ix2) { 1385 reg_offset = 1386 HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR( 1387 reo_reg_base); 1388 *ix2 = HAL_REG_READ(hal, reg_offset); 1389 } 1390 1391 if (ix3) { 1392 reg_offset = 1393 HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR( 1394 reo_reg_base); 1395 *ix3 = HAL_REG_READ(hal, reg_offset); 1396 } 1397 } else { 1398 if (ix0) { 1399 reg_offset = 1400 HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR( 1401 reo_reg_base); 1402 HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset, 1403 *ix0, true); 1404 } 1405 1406 if (ix1) { 1407 reg_offset = 1408 HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR( 1409 reo_reg_base); 1410 HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset, 1411 *ix1, true); 1412 } 1413 1414 if (ix2) { 1415 reg_offset = 1416 HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR( 1417 reo_reg_base); 1418 HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset, 1419 *ix2, true); 1420 } 1421 1422 if (ix3) { 1423 reg_offset = 1424 HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR( 1425 reo_reg_base); 1426 HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset, 1427 *ix3, true); 1428 } 1429 } 1430 } 1431 1432 qdf_export_symbol(hal_reo_read_write_ctrl_ix); 1433 1434 void hal_srng_dst_set_hp_paddr_confirm(struct hal_srng *srng, uint64_t paddr) 1435 { 1436 SRNG_DST_REG_WRITE_CONFIRM(srng, HP_ADDR_LSB, paddr & 0xffffffff); 1437 SRNG_DST_REG_WRITE_CONFIRM(srng, HP_ADDR_MSB, paddr >> 32); 1438 } 1439 1440 qdf_export_symbol(hal_srng_dst_set_hp_paddr_confirm); 1441 1442 void hal_srng_dst_init_hp(struct hal_soc_handle *hal_soc, 1443 struct hal_srng *srng, 1444 uint32_t *vaddr) 1445 { 1446 uint32_t reg_offset; 1447 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1448 1449 if (!srng) 1450 return; 1451 1452 srng->u.dst_ring.hp_addr = vaddr; 1453 reg_offset = SRNG_DST_ADDR(srng, HP) - hal->dev_base_addr; 1454 HAL_REG_WRITE_CONFIRM_RETRY( 1455 hal, reg_offset, srng->u.dst_ring.cached_hp, true); 1456 1457 if (vaddr) { 1458 *srng->u.dst_ring.hp_addr = srng->u.dst_ring.cached_hp; 1459 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1460 "hp_addr=%pK, cached_hp=%d", 1461 (void *)srng->u.dst_ring.hp_addr, 1462 srng->u.dst_ring.cached_hp); 1463 } 1464 } 1465 1466 qdf_export_symbol(hal_srng_dst_init_hp); 1467 1468 void hal_srng_dst_update_hp_addr(struct hal_soc_handle *hal_soc, 1469 hal_ring_handle_t hal_ring_hdl) 1470 { 1471 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1472 int32_t hw_hp; 1473 int32_t hw_tp; 1474 1475 if (!srng) 1476 return; 1477 1478 if (srng->u.dst_ring.hp_addr) { 1479 hal_get_hw_hptp(hal_soc, hal_ring_hdl, &hw_hp, &hw_tp, 1480 WBM2SW_RELEASE); 1481 *srng->u.dst_ring.hp_addr = hw_hp; 1482 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, 1483 "hw_hp=%d", hw_hp); 1484 } 1485 } 1486 1487 qdf_export_symbol(hal_srng_dst_update_hp_addr); 1488 1489 /** 1490 * hal_srng_hw_init - Private function to initialize SRNG HW 1491 * @hal: HAL SOC handle 1492 * @srng: SRNG ring pointer 1493 * @idle_check: Check if ring is idle 1494 * @idx: ring index 1495 */ 1496 static inline void hal_srng_hw_init(struct hal_soc *hal, 1497 struct hal_srng *srng, bool idle_check, uint32_t idx) 1498 { 1499 if (srng->ring_dir == HAL_SRNG_SRC_RING) 1500 hal_srng_src_hw_init(hal, srng, idle_check, idx); 1501 else 1502 hal_srng_dst_hw_init(hal, srng, idle_check, idx); 1503 } 1504 1505 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 1506 bool hal_srng_is_near_full_irq_supported(hal_soc_handle_t hal_soc, 1507 int ring_type, int ring_num) 1508 { 1509 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1510 struct hal_hw_srng_config *ring_config = 1511 HAL_SRNG_CONFIG(hal, ring_type); 1512 1513 return ring_config->nf_irq_support; 1514 } 1515 1516 /** 1517 * hal_srng_set_msi2_params() - Set MSI2 params to SRNG data structure from 1518 * ring params 1519 * @srng: SRNG handle 1520 * @ring_params: ring params for this SRNG 1521 * 1522 * Return: None 1523 */ 1524 static inline void 1525 hal_srng_set_msi2_params(struct hal_srng *srng, 1526 struct hal_srng_params *ring_params) 1527 { 1528 srng->msi2_addr = ring_params->msi2_addr; 1529 srng->msi2_data = ring_params->msi2_data; 1530 } 1531 1532 /** 1533 * hal_srng_get_nf_params() - Get the near full MSI2 params from srng 1534 * @srng: SRNG handle 1535 * @ring_params: ring params for this SRNG 1536 * 1537 * Return: None 1538 */ 1539 static inline void 1540 hal_srng_get_nf_params(struct hal_srng *srng, 1541 struct hal_srng_params *ring_params) 1542 { 1543 ring_params->msi2_addr = srng->msi2_addr; 1544 ring_params->msi2_data = srng->msi2_data; 1545 } 1546 1547 /** 1548 * hal_srng_set_nf_thresholds() - Set the near full thresholds in SRNG 1549 * @srng: SRNG handle where the params are to be set 1550 * @ring_params: ring params, from where threshold is to be fetched 1551 * 1552 * Return: None 1553 */ 1554 static inline void 1555 hal_srng_set_nf_thresholds(struct hal_srng *srng, 1556 struct hal_srng_params *ring_params) 1557 { 1558 srng->u.dst_ring.nf_irq_support = ring_params->nf_irq_support; 1559 srng->u.dst_ring.high_thresh = ring_params->high_thresh; 1560 } 1561 #else 1562 static inline void 1563 hal_srng_set_msi2_params(struct hal_srng *srng, 1564 struct hal_srng_params *ring_params) 1565 { 1566 } 1567 1568 static inline void 1569 hal_srng_get_nf_params(struct hal_srng *srng, 1570 struct hal_srng_params *ring_params) 1571 { 1572 } 1573 1574 static inline void 1575 hal_srng_set_nf_thresholds(struct hal_srng *srng, 1576 struct hal_srng_params *ring_params) 1577 { 1578 } 1579 #endif 1580 1581 #if defined(CLEAR_SW2TCL_CONSUMED_DESC) 1582 /** 1583 * hal_srng_last_desc_cleared_init - Initialize SRNG last_desc_cleared ptr 1584 * @srng: Source ring pointer 1585 * 1586 * Return: None 1587 */ 1588 static inline 1589 void hal_srng_last_desc_cleared_init(struct hal_srng *srng) 1590 { 1591 srng->last_desc_cleared = srng->ring_size - srng->entry_size; 1592 } 1593 1594 #else 1595 static inline 1596 void hal_srng_last_desc_cleared_init(struct hal_srng *srng) 1597 { 1598 } 1599 #endif /* CLEAR_SW2TCL_CONSUMED_DESC */ 1600 1601 #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING 1602 static inline void hal_srng_update_high_wm_thresholds(struct hal_srng *srng) 1603 { 1604 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_90_to_100] = 1605 ((srng->num_entries * 90) / 100); 1606 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_80_to_90] = 1607 ((srng->num_entries * 80) / 100); 1608 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_70_to_80] = 1609 ((srng->num_entries * 70) / 100); 1610 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_60_to_70] = 1611 ((srng->num_entries * 60) / 100); 1612 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_50_to_60] = 1613 ((srng->num_entries * 50) / 100); 1614 /* Below 50% threshold is not needed */ 1615 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT] = 0; 1616 1617 hal_info("ring_id: %u, wm_thresh- <50:%u, 50-60:%u, 60-70:%u, 70-80:%u, 80-90:%u, 90-100:%u", 1618 srng->ring_id, 1619 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT], 1620 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_50_to_60], 1621 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_60_to_70], 1622 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_70_to_80], 1623 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_80_to_90], 1624 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_90_to_100]); 1625 } 1626 #else 1627 static inline void hal_srng_update_high_wm_thresholds(struct hal_srng *srng) 1628 { 1629 } 1630 #endif 1631 1632 void *hal_srng_setup_idx(void *hal_soc, int ring_type, int ring_num, int mac_id, 1633 struct hal_srng_params *ring_params, bool idle_check, 1634 uint32_t idx) 1635 { 1636 int ring_id; 1637 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1638 hal_soc_handle_t hal_hdl = (hal_soc_handle_t)hal; 1639 struct hal_srng *srng; 1640 struct hal_hw_srng_config *ring_config = 1641 HAL_SRNG_CONFIG(hal, ring_type); 1642 void *dev_base_addr; 1643 int i; 1644 1645 ring_id = hal_get_srng_ring_id(hal_soc, ring_type, ring_num, mac_id); 1646 if (ring_id < 0) 1647 return NULL; 1648 1649 hal_verbose_debug("mac_id %d ring_id %d", mac_id, ring_id); 1650 1651 srng = hal_get_srng(hal_soc, ring_id); 1652 1653 if (srng->initialized) { 1654 hal_verbose_debug("Ring (ring_type, ring_num) already initialized"); 1655 return NULL; 1656 } 1657 1658 hal_srng_reg_his_init(srng); 1659 dev_base_addr = hal->dev_base_addr; 1660 srng->ring_id = ring_id; 1661 srng->ring_type = ring_type; 1662 srng->ring_dir = ring_config->ring_dir; 1663 srng->ring_base_paddr = ring_params->ring_base_paddr; 1664 srng->ring_base_vaddr = ring_params->ring_base_vaddr; 1665 srng->entry_size = ring_config->entry_size; 1666 srng->num_entries = ring_params->num_entries; 1667 srng->ring_size = srng->num_entries * srng->entry_size; 1668 srng->ring_size_mask = srng->ring_size - 1; 1669 srng->ring_vaddr_end = srng->ring_base_vaddr + srng->ring_size; 1670 srng->msi_addr = ring_params->msi_addr; 1671 srng->msi_data = ring_params->msi_data; 1672 srng->intr_timer_thres_us = ring_params->intr_timer_thres_us; 1673 srng->intr_batch_cntr_thres_entries = 1674 ring_params->intr_batch_cntr_thres_entries; 1675 srng->pointer_timer_threshold = 1676 ring_params->pointer_timer_threshold; 1677 srng->pointer_num_threshold = 1678 ring_params->pointer_num_threshold; 1679 1680 if (!idle_check) 1681 srng->prefetch_timer = ring_params->prefetch_timer; 1682 srng->hal_soc = hal_soc; 1683 hal_srng_set_msi2_params(srng, ring_params); 1684 hal_srng_update_high_wm_thresholds(srng); 1685 1686 for (i = 0 ; i < MAX_SRNG_REG_GROUPS; i++) { 1687 srng->hwreg_base[i] = dev_base_addr + ring_config->reg_start[i] 1688 + (ring_num * ring_config->reg_size[i]); 1689 } 1690 1691 /* Zero out the entire ring memory */ 1692 qdf_mem_zero(srng->ring_base_vaddr, (srng->entry_size * 1693 srng->num_entries) << 2); 1694 1695 srng->flags = ring_params->flags; 1696 1697 /* For cached descriptors flush and invalidate the memory*/ 1698 if (srng->flags & HAL_SRNG_CACHED_DESC) { 1699 qdf_nbuf_dma_clean_range( 1700 srng->ring_base_vaddr, 1701 srng->ring_base_vaddr + 1702 ((srng->entry_size * srng->num_entries))); 1703 qdf_nbuf_dma_inv_range( 1704 srng->ring_base_vaddr, 1705 srng->ring_base_vaddr + 1706 ((srng->entry_size * srng->num_entries))); 1707 } 1708 #ifdef BIG_ENDIAN_HOST 1709 /* TODO: See if we should we get these flags from caller */ 1710 srng->flags |= HAL_SRNG_DATA_TLV_SWAP; 1711 srng->flags |= HAL_SRNG_MSI_SWAP; 1712 srng->flags |= HAL_SRNG_RING_PTR_SWAP; 1713 #endif 1714 1715 hal_srng_last_desc_cleared_init(srng); 1716 1717 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1718 srng->u.src_ring.hp = 0; 1719 srng->u.src_ring.reap_hp = srng->ring_size - 1720 srng->entry_size; 1721 srng->u.src_ring.tp_addr = 1722 &(hal->shadow_rdptr_mem_vaddr[ring_id]); 1723 srng->u.src_ring.low_threshold = 1724 ring_params->low_threshold * srng->entry_size; 1725 1726 if (srng->u.src_ring.tp_addr) 1727 qdf_mem_zero(srng->u.src_ring.tp_addr, 1728 sizeof(*hal->shadow_rdptr_mem_vaddr)); 1729 1730 if (ring_config->lmac_ring) { 1731 /* For LMAC rings, head pointer updates will be done 1732 * through FW by writing to a shared memory location 1733 */ 1734 srng->u.src_ring.hp_addr = 1735 &(hal->shadow_wrptr_mem_vaddr[ring_id - 1736 HAL_SRNG_LMAC1_ID_START]); 1737 srng->flags |= HAL_SRNG_LMAC_RING; 1738 1739 if (srng->u.src_ring.hp_addr) 1740 qdf_mem_zero(srng->u.src_ring.hp_addr, 1741 sizeof(*hal->shadow_wrptr_mem_vaddr)); 1742 1743 } else if (ignore_shadow || (srng->u.src_ring.hp_addr == 0)) { 1744 srng->u.src_ring.hp_addr = 1745 hal_get_window_address(hal, 1746 SRNG_SRC_ADDR(srng, HP)); 1747 1748 if (CHECK_SHADOW_REGISTERS) { 1749 QDF_TRACE(QDF_MODULE_ID_TXRX, 1750 QDF_TRACE_LEVEL_ERROR, 1751 "%s: Ring (%d, %d) missing shadow config", 1752 __func__, ring_type, ring_num); 1753 } 1754 } else { 1755 hal_validate_shadow_register(hal, 1756 SRNG_SRC_ADDR(srng, HP), 1757 srng->u.src_ring.hp_addr); 1758 } 1759 } else { 1760 /* During initialization loop count in all the descriptors 1761 * will be set to zero, and HW will set it to 1 on completing 1762 * descriptor update in first loop, and increments it by 1 on 1763 * subsequent loops (loop count wraps around after reaching 1764 * 0xffff). The 'loop_cnt' in SW ring state is the expected 1765 * loop count in descriptors updated by HW (to be processed 1766 * by SW). 1767 */ 1768 hal_srng_set_nf_thresholds(srng, ring_params); 1769 srng->u.dst_ring.loop_cnt = 1; 1770 srng->u.dst_ring.tp = 0; 1771 srng->u.dst_ring.hp_addr = 1772 &(hal->shadow_rdptr_mem_vaddr[ring_id]); 1773 1774 if (srng->u.dst_ring.hp_addr) 1775 qdf_mem_zero(srng->u.dst_ring.hp_addr, 1776 sizeof(*hal->shadow_rdptr_mem_vaddr)); 1777 1778 if (ring_config->lmac_ring) { 1779 /* For LMAC rings, tail pointer updates will be done 1780 * through FW by writing to a shared memory location 1781 */ 1782 srng->u.dst_ring.tp_addr = 1783 &(hal->shadow_wrptr_mem_vaddr[ring_id - 1784 HAL_SRNG_LMAC1_ID_START]); 1785 srng->flags |= HAL_SRNG_LMAC_RING; 1786 1787 if (srng->u.dst_ring.tp_addr) 1788 qdf_mem_zero(srng->u.dst_ring.tp_addr, 1789 sizeof(*hal->shadow_wrptr_mem_vaddr)); 1790 1791 } else if (ignore_shadow || srng->u.dst_ring.tp_addr == 0) { 1792 srng->u.dst_ring.tp_addr = 1793 hal_get_window_address(hal, 1794 SRNG_DST_ADDR(srng, TP)); 1795 1796 if (CHECK_SHADOW_REGISTERS) { 1797 QDF_TRACE(QDF_MODULE_ID_TXRX, 1798 QDF_TRACE_LEVEL_ERROR, 1799 "%s: Ring (%d, %d) missing shadow config", 1800 __func__, ring_type, ring_num); 1801 } 1802 } else { 1803 hal_validate_shadow_register(hal, 1804 SRNG_DST_ADDR(srng, TP), 1805 srng->u.dst_ring.tp_addr); 1806 } 1807 } 1808 1809 if (!(ring_config->lmac_ring)) { 1810 /* 1811 * UMAC reset has idle check enabled. 1812 * During UMAC reset Tx ring halt is set 1813 * by Wi-Fi FW during pre-reset stage, 1814 * avoid Tx ring halt again. 1815 */ 1816 if (idle_check && idx) { 1817 if (!hal->ops->hal_tx_ring_halt_get(hal_hdl)) { 1818 qdf_print("\nTx ring halt not set:Ring(%d, %d)", 1819 ring_type, ring_num); 1820 qdf_assert_always(0); 1821 } 1822 hal_srng_hw_init(hal, srng, idle_check, idx); 1823 goto ce_setup; 1824 } 1825 1826 if (idx) { 1827 hal->ops->hal_tx_ring_halt_set(hal_hdl); 1828 do { 1829 hal_info("Waiting for ring reset"); 1830 } while (!(hal->ops->hal_tx_ring_halt_poll(hal_hdl))); 1831 } 1832 hal_srng_hw_init(hal, srng, idle_check, idx); 1833 1834 if (idx) { 1835 hal->ops->hal_tx_ring_halt_reset(hal_hdl); 1836 } 1837 1838 ce_setup: 1839 if (ring_type == CE_DST) { 1840 srng->u.dst_ring.max_buffer_length = ring_params->max_buffer_length; 1841 hal_ce_dst_setup(hal, srng, ring_num); 1842 } 1843 } 1844 1845 SRNG_LOCK_INIT(&srng->lock); 1846 1847 srng->srng_event = 0; 1848 1849 srng->initialized = true; 1850 1851 return (void *)srng; 1852 } 1853 qdf_export_symbol(hal_srng_setup_idx); 1854 1855 /** 1856 * hal_srng_setup - Initialize HW SRNG ring. 1857 * @hal_soc: Opaque HAL SOC handle 1858 * @ring_type: one of the types from hal_ring_type 1859 * @ring_num: Ring number if there are multiple rings of same type (staring 1860 * from 0) 1861 * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings 1862 * @ring_params: SRNG ring params in hal_srng_params structure. 1863 * @idle_check: Check if ring is idle 1864 * 1865 * Callers are expected to allocate contiguous ring memory of size 1866 * 'num_entries * entry_size' bytes and pass the physical and virtual base 1867 * addresses through 'ring_base_paddr' and 'ring_base_vaddr' in 1868 * hal_srng_params structure. Ring base address should be 8 byte aligned 1869 * and size of each ring entry should be queried using the API 1870 * hal_srng_get_entrysize 1871 * 1872 * Return: Opaque pointer to ring on success 1873 * NULL on failure (if given ring is not available) 1874 */ 1875 void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num, 1876 int mac_id, struct hal_srng_params *ring_params, 1877 bool idle_check) 1878 { 1879 return hal_srng_setup_idx(hal_soc, ring_type, ring_num, mac_id, 1880 ring_params, idle_check, 0); 1881 } 1882 qdf_export_symbol(hal_srng_setup); 1883 1884 void hal_srng_cleanup(void *hal_soc, hal_ring_handle_t hal_ring_hdl, 1885 bool umac_reset_inprogress) 1886 { 1887 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1888 SRNG_LOCK_DESTROY(&srng->lock); 1889 srng->initialized = 0; 1890 if (umac_reset_inprogress) 1891 hal_srng_hw_disable(hal_soc, srng); 1892 } 1893 qdf_export_symbol(hal_srng_cleanup); 1894 1895 uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type) 1896 { 1897 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1898 struct hal_hw_srng_config *ring_config = 1899 HAL_SRNG_CONFIG(hal, ring_type); 1900 return ring_config->entry_size << 2; 1901 } 1902 qdf_export_symbol(hal_srng_get_entrysize); 1903 1904 uint32_t hal_srng_max_entries(void *hal_soc, int ring_type) 1905 { 1906 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1907 struct hal_hw_srng_config *ring_config = 1908 HAL_SRNG_CONFIG(hal, ring_type); 1909 1910 return ring_config->max_size / ring_config->entry_size; 1911 } 1912 qdf_export_symbol(hal_srng_max_entries); 1913 1914 enum hal_srng_dir hal_srng_get_dir(void *hal_soc, int ring_type) 1915 { 1916 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1917 struct hal_hw_srng_config *ring_config = 1918 HAL_SRNG_CONFIG(hal, ring_type); 1919 1920 return ring_config->ring_dir; 1921 } 1922 1923 void hal_srng_dump(struct hal_srng *srng) 1924 { 1925 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1926 hal_debug("=== SRC RING %d ===", srng->ring_id); 1927 hal_debug("hp %u, reap_hp %u, tp %u, cached tp %u", 1928 srng->u.src_ring.hp, 1929 srng->u.src_ring.reap_hp, 1930 *srng->u.src_ring.tp_addr, 1931 srng->u.src_ring.cached_tp); 1932 } else { 1933 hal_debug("=== DST RING %d ===", srng->ring_id); 1934 hal_debug("tp %u, hp %u, cached tp %u, loop_cnt %u", 1935 srng->u.dst_ring.tp, 1936 *srng->u.dst_ring.hp_addr, 1937 srng->u.dst_ring.cached_hp, 1938 srng->u.dst_ring.loop_cnt); 1939 } 1940 } 1941 1942 void hal_get_srng_params(hal_soc_handle_t hal_soc_hdl, 1943 hal_ring_handle_t hal_ring_hdl, 1944 struct hal_srng_params *ring_params) 1945 { 1946 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1947 int i =0; 1948 ring_params->ring_id = srng->ring_id; 1949 ring_params->ring_dir = srng->ring_dir; 1950 ring_params->entry_size = srng->entry_size; 1951 1952 ring_params->ring_base_paddr = srng->ring_base_paddr; 1953 ring_params->ring_base_vaddr = srng->ring_base_vaddr; 1954 ring_params->num_entries = srng->num_entries; 1955 ring_params->msi_addr = srng->msi_addr; 1956 ring_params->msi_data = srng->msi_data; 1957 ring_params->intr_timer_thres_us = srng->intr_timer_thres_us; 1958 ring_params->intr_batch_cntr_thres_entries = 1959 srng->intr_batch_cntr_thres_entries; 1960 ring_params->low_threshold = srng->u.src_ring.low_threshold; 1961 ring_params->flags = srng->flags; 1962 ring_params->ring_id = srng->ring_id; 1963 for (i = 0 ; i < MAX_SRNG_REG_GROUPS; i++) 1964 ring_params->hwreg_base[i] = srng->hwreg_base[i]; 1965 1966 hal_srng_get_nf_params(srng, ring_params); 1967 } 1968 qdf_export_symbol(hal_get_srng_params); 1969 1970 void hal_set_low_threshold(hal_ring_handle_t hal_ring_hdl, 1971 uint32_t low_threshold) 1972 { 1973 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1974 srng->u.src_ring.low_threshold = low_threshold * srng->entry_size; 1975 } 1976 qdf_export_symbol(hal_set_low_threshold); 1977 1978 #ifdef FEATURE_RUNTIME_PM 1979 void 1980 hal_srng_rtpm_access_end(hal_soc_handle_t hal_soc_hdl, 1981 hal_ring_handle_t hal_ring_hdl, 1982 uint32_t rtpm_id) 1983 { 1984 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1985 1986 if (qdf_unlikely(!hal_ring_hdl)) { 1987 qdf_print("Error: Invalid hal_ring\n"); 1988 return; 1989 } 1990 1991 if (hif_rtpm_get(HIF_RTPM_GET_ASYNC, rtpm_id) == 0) { 1992 if (hif_system_pm_state_check(hal_soc->hif_handle)) { 1993 hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl); 1994 hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT); 1995 hal_srng_inc_flush_cnt(hal_ring_hdl); 1996 } else { 1997 hal_srng_access_end(hal_soc_hdl, hal_ring_hdl); 1998 } 1999 2000 hif_rtpm_put(HIF_RTPM_PUT_ASYNC, rtpm_id); 2001 } else { 2002 hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl); 2003 hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT); 2004 hal_srng_inc_flush_cnt(hal_ring_hdl); 2005 } 2006 } 2007 2008 qdf_export_symbol(hal_srng_rtpm_access_end); 2009 #endif /* FEATURE_RUNTIME_PM */ 2010 2011 #ifdef FORCE_WAKE 2012 void hal_set_init_phase(hal_soc_handle_t soc, bool init_phase) 2013 { 2014 struct hal_soc *hal_soc = (struct hal_soc *)soc; 2015 hal_soc->init_phase = init_phase; 2016 } 2017 #endif /* FORCE_WAKE */ 2018