1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include "hal_hw_headers.h" 20 #include "hal_api.h" 21 #include "target_type.h" 22 #include "wcss_version.h" 23 #include "qdf_module.h" 24 25 #ifdef QCA_WIFI_QCA8074 26 void hal_qca6290_attach(struct hal_soc *hal); 27 #endif 28 #ifdef QCA_WIFI_QCA8074 29 void hal_qca8074_attach(struct hal_soc *hal); 30 #endif 31 #if defined(QCA_WIFI_QCA8074V2) || defined(QCA_WIFI_QCA6018) 32 void hal_qca8074v2_attach(struct hal_soc *hal); 33 #endif 34 #ifdef QCA_WIFI_QCA6390 35 void hal_qca6390_attach(struct hal_soc *hal); 36 #endif 37 #ifdef QCA_WIFI_QCA6490 38 void hal_qca6490_attach(struct hal_soc *hal); 39 #endif 40 #ifdef QCA_WIFI_QCN9000 41 void hal_qcn9000_attach(struct hal_soc *hal); 42 #endif 43 #ifdef QCA_WIFI_QCN9100 44 void hal_qcn9100_attach(struct hal_soc *hal); 45 #endif 46 #ifdef QCA_WIFI_QCA6750 47 void hal_qca6750_attach(struct hal_soc *hal); 48 #endif 49 #ifdef QCA_WIFI_QCA5018 50 void hal_qca5018_attach(struct hal_soc *hal); 51 #endif 52 53 #ifdef ENABLE_VERBOSE_DEBUG 54 bool is_hal_verbose_debug_enabled; 55 #endif 56 57 #ifdef ENABLE_HAL_REG_WR_HISTORY 58 struct hal_reg_write_fail_history hal_reg_wr_hist; 59 60 void hal_reg_wr_fail_history_add(struct hal_soc *hal_soc, 61 uint32_t offset, 62 uint32_t wr_val, uint32_t rd_val) 63 { 64 struct hal_reg_write_fail_entry *record; 65 int idx; 66 67 idx = hal_history_get_next_index(&hal_soc->reg_wr_fail_hist->index, 68 HAL_REG_WRITE_HIST_SIZE); 69 70 record = &hal_soc->reg_wr_fail_hist->record[idx]; 71 72 record->timestamp = qdf_get_log_timestamp(); 73 record->reg_offset = offset; 74 record->write_val = wr_val; 75 record->read_val = rd_val; 76 } 77 78 static void hal_reg_write_fail_history_init(struct hal_soc *hal) 79 { 80 hal->reg_wr_fail_hist = &hal_reg_wr_hist; 81 82 qdf_atomic_set(&hal->reg_wr_fail_hist->index, -1); 83 } 84 #else 85 static void hal_reg_write_fail_history_init(struct hal_soc *hal) 86 { 87 } 88 #endif 89 90 /** 91 * hal_get_srng_ring_id() - get the ring id of a descriped ring 92 * @hal: hal_soc data structure 93 * @ring_type: type enum describing the ring 94 * @ring_num: which ring of the ring type 95 * @mac_id: which mac does the ring belong to (or 0 for non-lmac rings) 96 * 97 * Return: the ring id or -EINVAL if the ring does not exist. 98 */ 99 static int hal_get_srng_ring_id(struct hal_soc *hal, int ring_type, 100 int ring_num, int mac_id) 101 { 102 struct hal_hw_srng_config *ring_config = 103 HAL_SRNG_CONFIG(hal, ring_type); 104 int ring_id; 105 106 if (ring_num >= ring_config->max_rings) { 107 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_INFO, 108 "%s: ring_num exceeded maximum no. of supported rings", 109 __func__); 110 /* TODO: This is a programming error. Assert if this happens */ 111 return -EINVAL; 112 } 113 114 if (ring_config->lmac_ring) { 115 ring_id = ring_config->start_ring_id + ring_num + 116 (mac_id * HAL_MAX_RINGS_PER_LMAC); 117 } else { 118 ring_id = ring_config->start_ring_id + ring_num; 119 } 120 121 return ring_id; 122 } 123 124 static struct hal_srng *hal_get_srng(struct hal_soc *hal, int ring_id) 125 { 126 /* TODO: Should we allocate srng structures dynamically? */ 127 return &(hal->srng_list[ring_id]); 128 } 129 130 #define HP_OFFSET_IN_REG_START 1 131 #define OFFSET_FROM_HP_TO_TP 4 132 static void hal_update_srng_hp_tp_address(struct hal_soc *hal_soc, 133 int shadow_config_index, 134 int ring_type, 135 int ring_num) 136 { 137 struct hal_srng *srng; 138 int ring_id; 139 struct hal_hw_srng_config *ring_config = 140 HAL_SRNG_CONFIG(hal_soc, ring_type); 141 142 ring_id = hal_get_srng_ring_id(hal_soc, ring_type, ring_num, 0); 143 if (ring_id < 0) 144 return; 145 146 srng = hal_get_srng(hal_soc, ring_id); 147 148 if (ring_config->ring_dir == HAL_SRNG_DST_RING) { 149 srng->u.dst_ring.tp_addr = SHADOW_REGISTER(shadow_config_index) 150 + hal_soc->dev_base_addr; 151 hal_debug("tp_addr=%pK dev base addr %pK index %u", 152 srng->u.dst_ring.tp_addr, hal_soc->dev_base_addr, 153 shadow_config_index); 154 } else { 155 srng->u.src_ring.hp_addr = SHADOW_REGISTER(shadow_config_index) 156 + hal_soc->dev_base_addr; 157 hal_debug("hp_addr=%pK dev base addr %pK index %u", 158 srng->u.src_ring.hp_addr, 159 hal_soc->dev_base_addr, shadow_config_index); 160 } 161 162 } 163 164 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE 165 void hal_set_one_target_reg_config(struct hal_soc *hal, 166 uint32_t target_reg_offset, 167 int list_index) 168 { 169 int i = list_index; 170 171 qdf_assert_always(i < MAX_GENERIC_SHADOW_REG); 172 hal->list_shadow_reg_config[i].target_register = 173 target_reg_offset; 174 hal->num_generic_shadow_regs_configured++; 175 } 176 177 qdf_export_symbol(hal_set_one_target_reg_config); 178 179 #define REO_R0_DESTINATION_RING_CTRL_ADDR_OFFSET 0x4 180 #define MAX_REO_REMAP_SHADOW_REGS 4 181 QDF_STATUS hal_set_shadow_regs(void *hal_soc) 182 { 183 uint32_t target_reg_offset; 184 struct hal_soc *hal = (struct hal_soc *)hal_soc; 185 int i; 186 struct hal_hw_srng_config *srng_config = 187 &hal->hw_srng_table[WBM2SW_RELEASE]; 188 189 target_reg_offset = 190 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR( 191 SEQ_WCSS_UMAC_REO_REG_OFFSET); 192 193 for (i = 0; i < MAX_REO_REMAP_SHADOW_REGS; i++) { 194 hal_set_one_target_reg_config(hal, target_reg_offset, i); 195 target_reg_offset += REO_R0_DESTINATION_RING_CTRL_ADDR_OFFSET; 196 } 197 198 target_reg_offset = srng_config->reg_start[HP_OFFSET_IN_REG_START]; 199 target_reg_offset += (srng_config->reg_size[HP_OFFSET_IN_REG_START] 200 * HAL_IPA_TX_COMP_RING_IDX); 201 202 hal_set_one_target_reg_config(hal, target_reg_offset, i); 203 return QDF_STATUS_SUCCESS; 204 } 205 206 qdf_export_symbol(hal_set_shadow_regs); 207 208 QDF_STATUS hal_construct_shadow_regs(void *hal_soc) 209 { 210 struct hal_soc *hal = (struct hal_soc *)hal_soc; 211 int shadow_config_index = hal->num_shadow_registers_configured; 212 int i; 213 int num_regs = hal->num_generic_shadow_regs_configured; 214 215 for (i = 0; i < num_regs; i++) { 216 qdf_assert_always(shadow_config_index < MAX_SHADOW_REGISTERS); 217 hal->shadow_config[shadow_config_index].addr = 218 hal->list_shadow_reg_config[i].target_register; 219 hal->list_shadow_reg_config[i].shadow_config_index = 220 shadow_config_index; 221 hal->list_shadow_reg_config[i].va = 222 SHADOW_REGISTER(shadow_config_index) + 223 (uintptr_t)hal->dev_base_addr; 224 hal_debug("target_reg %x, shadow register 0x%x shadow_index 0x%x", 225 hal->shadow_config[shadow_config_index].addr, 226 SHADOW_REGISTER(shadow_config_index), 227 shadow_config_index); 228 shadow_config_index++; 229 hal->num_shadow_registers_configured++; 230 } 231 return QDF_STATUS_SUCCESS; 232 } 233 234 qdf_export_symbol(hal_construct_shadow_regs); 235 #endif 236 237 QDF_STATUS hal_set_one_shadow_config(void *hal_soc, 238 int ring_type, 239 int ring_num) 240 { 241 uint32_t target_register; 242 struct hal_soc *hal = (struct hal_soc *)hal_soc; 243 struct hal_hw_srng_config *srng_config = &hal->hw_srng_table[ring_type]; 244 int shadow_config_index = hal->num_shadow_registers_configured; 245 246 if (shadow_config_index >= MAX_SHADOW_REGISTERS) { 247 QDF_ASSERT(0); 248 return QDF_STATUS_E_RESOURCES; 249 } 250 251 hal->num_shadow_registers_configured++; 252 253 target_register = srng_config->reg_start[HP_OFFSET_IN_REG_START]; 254 target_register += (srng_config->reg_size[HP_OFFSET_IN_REG_START] 255 *ring_num); 256 257 /* if the ring is a dst ring, we need to shadow the tail pointer */ 258 if (srng_config->ring_dir == HAL_SRNG_DST_RING) 259 target_register += OFFSET_FROM_HP_TO_TP; 260 261 hal->shadow_config[shadow_config_index].addr = target_register; 262 263 /* update hp/tp addr in the hal_soc structure*/ 264 hal_update_srng_hp_tp_address(hal_soc, shadow_config_index, ring_type, 265 ring_num); 266 267 hal_debug("target_reg %x, shadow register 0x%x shadow_index 0x%x, ring_type %d, ring num %d", 268 target_register, 269 SHADOW_REGISTER(shadow_config_index), 270 shadow_config_index, 271 ring_type, ring_num); 272 273 return QDF_STATUS_SUCCESS; 274 } 275 276 qdf_export_symbol(hal_set_one_shadow_config); 277 278 QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc) 279 { 280 int ring_type, ring_num; 281 struct hal_soc *hal = (struct hal_soc *)hal_soc; 282 283 for (ring_type = 0; ring_type < MAX_RING_TYPES; ring_type++) { 284 struct hal_hw_srng_config *srng_config = 285 &hal->hw_srng_table[ring_type]; 286 287 if (ring_type == CE_SRC || 288 ring_type == CE_DST || 289 ring_type == CE_DST_STATUS) 290 continue; 291 292 if (srng_config->lmac_ring) 293 continue; 294 295 for (ring_num = 0; ring_num < srng_config->max_rings; 296 ring_num++) 297 hal_set_one_shadow_config(hal_soc, ring_type, ring_num); 298 } 299 300 return QDF_STATUS_SUCCESS; 301 } 302 303 qdf_export_symbol(hal_construct_srng_shadow_regs); 304 305 void hal_get_shadow_config(void *hal_soc, 306 struct pld_shadow_reg_v2_cfg **shadow_config, 307 int *num_shadow_registers_configured) 308 { 309 struct hal_soc *hal = (struct hal_soc *)hal_soc; 310 311 *shadow_config = hal->shadow_config; 312 *num_shadow_registers_configured = 313 hal->num_shadow_registers_configured; 314 } 315 316 qdf_export_symbol(hal_get_shadow_config); 317 318 319 static void hal_validate_shadow_register(struct hal_soc *hal, 320 uint32_t *destination, 321 uint32_t *shadow_address) 322 { 323 unsigned int index; 324 uint32_t *shadow_0_offset = SHADOW_REGISTER(0) + hal->dev_base_addr; 325 int destination_ba_offset = 326 ((char *)destination) - (char *)hal->dev_base_addr; 327 328 index = shadow_address - shadow_0_offset; 329 330 if (index >= MAX_SHADOW_REGISTERS) { 331 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 332 "%s: index %x out of bounds", __func__, index); 333 goto error; 334 } else if (hal->shadow_config[index].addr != destination_ba_offset) { 335 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 336 "%s: sanity check failure, expected %x, found %x", 337 __func__, destination_ba_offset, 338 hal->shadow_config[index].addr); 339 goto error; 340 } 341 return; 342 error: 343 qdf_print("baddr %pK, desination %pK, shadow_address %pK s0offset %pK index %x", 344 hal->dev_base_addr, destination, shadow_address, 345 shadow_0_offset, index); 346 QDF_BUG(0); 347 return; 348 } 349 350 static void hal_target_based_configure(struct hal_soc *hal) 351 { 352 /** 353 * Indicate Initialization of srngs to avoid force wake 354 * as umac power collapse is not enabled yet 355 */ 356 hal->init_phase = true; 357 358 switch (hal->target_type) { 359 #ifdef QCA_WIFI_QCA6290 360 case TARGET_TYPE_QCA6290: 361 hal->use_register_windowing = true; 362 hal_qca6290_attach(hal); 363 break; 364 #endif 365 #ifdef QCA_WIFI_QCA6390 366 case TARGET_TYPE_QCA6390: 367 hal->use_register_windowing = true; 368 hal_qca6390_attach(hal); 369 break; 370 #endif 371 #ifdef QCA_WIFI_QCA6490 372 case TARGET_TYPE_QCA6490: 373 hal->use_register_windowing = true; 374 hal_qca6490_attach(hal); 375 hal->init_phase = false; 376 break; 377 #endif 378 #ifdef QCA_WIFI_QCA6750 379 case TARGET_TYPE_QCA6750: 380 hal->use_register_windowing = true; 381 hal->static_window_map = true; 382 hal_qca6750_attach(hal); 383 break; 384 #endif 385 #if defined(QCA_WIFI_QCA8074) && defined(WIFI_TARGET_TYPE_3_0) 386 case TARGET_TYPE_QCA8074: 387 hal_qca8074_attach(hal); 388 break; 389 #endif 390 391 #if defined(QCA_WIFI_QCA8074V2) 392 case TARGET_TYPE_QCA8074V2: 393 hal_qca8074v2_attach(hal); 394 break; 395 #endif 396 397 #if defined(QCA_WIFI_QCA6018) 398 case TARGET_TYPE_QCA6018: 399 hal_qca8074v2_attach(hal); 400 break; 401 #endif 402 403 #if defined(QCA_WIFI_QCN9100) 404 case TARGET_TYPE_QCN9100: 405 hal->use_register_windowing = true; 406 /* 407 * Static window map is enabled for qcn9000 to use 2mb bar 408 * size and use multiple windows to write into registers. 409 */ 410 hal->static_window_map = true; 411 hal_qcn9100_attach(hal); 412 break; 413 #endif 414 415 #ifdef QCA_WIFI_QCN9000 416 case TARGET_TYPE_QCN9000: 417 hal->use_register_windowing = true; 418 /* 419 * Static window map is enabled for qcn9000 to use 2mb bar 420 * size and use multiple windows to write into registers. 421 */ 422 hal->static_window_map = true; 423 hal_qcn9000_attach(hal); 424 break; 425 #endif 426 #ifdef QCA_WIFI_QCA5018 427 case TARGET_TYPE_QCA5018: 428 hal->use_register_windowing = true; 429 hal->static_window_map = true; 430 hal_qca5018_attach(hal); 431 break; 432 #endif 433 default: 434 break; 435 } 436 } 437 438 uint32_t hal_get_target_type(hal_soc_handle_t hal_soc_hdl) 439 { 440 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 441 struct hif_target_info *tgt_info = 442 hif_get_target_info_handle(hal_soc->hif_handle); 443 444 return tgt_info->target_type; 445 } 446 447 qdf_export_symbol(hal_get_target_type); 448 449 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 450 #ifdef MEMORY_DEBUG 451 /* 452 * Length of the queue(array) used to hold delayed register writes. 453 * Must be a multiple of 2. 454 */ 455 #define HAL_REG_WRITE_QUEUE_LEN 128 456 #else 457 #define HAL_REG_WRITE_QUEUE_LEN 32 458 #endif 459 460 /** 461 * hal_is_reg_write_tput_level_high() - throughput level for delayed reg writes 462 * @hal: hal_soc pointer 463 * 464 * Return: true if throughput is high, else false. 465 */ 466 static inline bool hal_is_reg_write_tput_level_high(struct hal_soc *hal) 467 { 468 int bw_level = hif_get_bandwidth_level(hal->hif_handle); 469 470 return (bw_level >= PLD_BUS_WIDTH_MEDIUM) ? true : false; 471 } 472 473 /** 474 * hal_process_reg_write_q_elem() - process a regiter write queue element 475 * @hal: hal_soc pointer 476 * @q_elem: pointer to hal regiter write queue element 477 * 478 * Return: The value which was written to the address 479 */ 480 static uint32_t 481 hal_process_reg_write_q_elem(struct hal_soc *hal, 482 struct hal_reg_write_q_elem *q_elem) 483 { 484 struct hal_srng *srng = q_elem->srng; 485 uint32_t write_val; 486 487 SRNG_LOCK(&srng->lock); 488 489 srng->reg_write_in_progress = false; 490 srng->wstats.dequeues++; 491 492 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 493 q_elem->dequeue_val = srng->u.src_ring.hp; 494 hal_write_address_32_mb(hal, 495 srng->u.src_ring.hp_addr, 496 srng->u.src_ring.hp, false); 497 write_val = srng->u.src_ring.hp; 498 } else { 499 q_elem->dequeue_val = srng->u.dst_ring.tp; 500 hal_write_address_32_mb(hal, 501 srng->u.dst_ring.tp_addr, 502 srng->u.dst_ring.tp, false); 503 write_val = srng->u.dst_ring.tp; 504 } 505 506 q_elem->valid = 0; 507 SRNG_UNLOCK(&srng->lock); 508 509 return write_val; 510 } 511 512 /** 513 * hal_reg_write_fill_sched_delay_hist() - fill reg write delay histogram in hal 514 * @hal: hal_soc pointer 515 * @delay: delay in us 516 * 517 * Return: None 518 */ 519 static inline void hal_reg_write_fill_sched_delay_hist(struct hal_soc *hal, 520 uint64_t delay_us) 521 { 522 uint32_t *hist; 523 524 hist = hal->stats.wstats.sched_delay; 525 526 if (delay_us < 100) 527 hist[REG_WRITE_SCHED_DELAY_SUB_100us]++; 528 else if (delay_us < 1000) 529 hist[REG_WRITE_SCHED_DELAY_SUB_1000us]++; 530 else if (delay_us < 5000) 531 hist[REG_WRITE_SCHED_DELAY_SUB_5000us]++; 532 else 533 hist[REG_WRITE_SCHED_DELAY_GT_5000us]++; 534 } 535 536 /** 537 * hal_reg_write_work() - Worker to process delayed writes 538 * @arg: hal_soc pointer 539 * 540 * Return: None 541 */ 542 static void hal_reg_write_work(void *arg) 543 { 544 int32_t q_depth, write_val; 545 struct hal_soc *hal = arg; 546 struct hal_reg_write_q_elem *q_elem; 547 uint64_t delta_us; 548 uint8_t ring_id; 549 uint32_t *addr; 550 uint32_t num_processed = 0; 551 552 q_elem = &hal->reg_write_queue[(hal->read_idx)]; 553 q_elem->work_scheduled_time = qdf_get_log_timestamp(); 554 555 /* Make sure q_elem consistent in the memory for multi-cores */ 556 qdf_rmb(); 557 if (!q_elem->valid) 558 return; 559 560 q_depth = qdf_atomic_read(&hal->stats.wstats.q_depth); 561 if (q_depth > hal->stats.wstats.max_q_depth) 562 hal->stats.wstats.max_q_depth = q_depth; 563 564 if (hif_prevent_link_low_power_states(hal->hif_handle)) { 565 hal->stats.wstats.prevent_l1_fails++; 566 return; 567 } 568 569 while (true) { 570 qdf_rmb(); 571 if (!q_elem->valid) 572 break; 573 574 q_elem->dequeue_time = qdf_get_log_timestamp(); 575 ring_id = q_elem->srng->ring_id; 576 addr = q_elem->addr; 577 delta_us = qdf_log_timestamp_to_usecs(q_elem->dequeue_time - 578 q_elem->enqueue_time); 579 hal_reg_write_fill_sched_delay_hist(hal, delta_us); 580 581 hal->stats.wstats.dequeues++; 582 qdf_atomic_dec(&hal->stats.wstats.q_depth); 583 584 write_val = hal_process_reg_write_q_elem(hal, q_elem); 585 hal_verbose_debug("read_idx %u srng 0x%x, addr 0x%pK dequeue_val %u sched delay %llu us", 586 hal->read_idx, ring_id, addr, write_val, delta_us); 587 588 num_processed++; 589 hal->read_idx = (hal->read_idx + 1) & 590 (HAL_REG_WRITE_QUEUE_LEN - 1); 591 q_elem = &hal->reg_write_queue[(hal->read_idx)]; 592 } 593 594 hif_allow_link_low_power_states(hal->hif_handle); 595 /* 596 * Decrement active_work_cnt by the number of elements dequeued after 597 * hif_allow_link_low_power_states. 598 * This makes sure that hif_try_complete_tasks will wait till we make 599 * the bus access in hif_allow_link_low_power_states. This will avoid 600 * race condition between delayed register worker and bus suspend 601 * (system suspend or runtime suspend). 602 * 603 * The following decrement should be done at the end! 604 */ 605 qdf_atomic_sub(num_processed, &hal->active_work_cnt); 606 } 607 608 static void __hal_flush_reg_write_work(struct hal_soc *hal) 609 { 610 qdf_cancel_work(&hal->reg_write_work); 611 612 } 613 614 void hal_flush_reg_write_work(hal_soc_handle_t hal_handle) 615 { __hal_flush_reg_write_work((struct hal_soc *)hal_handle); 616 } 617 618 /** 619 * hal_reg_write_enqueue() - enqueue register writes into kworker 620 * @hal_soc: hal_soc pointer 621 * @srng: srng pointer 622 * @addr: iomem address of regiter 623 * @value: value to be written to iomem address 624 * 625 * This function executes from within the SRNG LOCK 626 * 627 * Return: None 628 */ 629 static void hal_reg_write_enqueue(struct hal_soc *hal_soc, 630 struct hal_srng *srng, 631 void __iomem *addr, 632 uint32_t value) 633 { 634 struct hal_reg_write_q_elem *q_elem; 635 uint32_t write_idx; 636 637 if (srng->reg_write_in_progress) { 638 hal_verbose_debug("Already in progress srng ring id 0x%x addr 0x%pK val %u", 639 srng->ring_id, addr, value); 640 qdf_atomic_inc(&hal_soc->stats.wstats.coalesces); 641 srng->wstats.coalesces++; 642 return; 643 } 644 645 write_idx = qdf_atomic_inc_return(&hal_soc->write_idx); 646 647 write_idx = write_idx & (HAL_REG_WRITE_QUEUE_LEN - 1); 648 649 q_elem = &hal_soc->reg_write_queue[write_idx]; 650 651 if (q_elem->valid) { 652 hal_err("queue full"); 653 QDF_BUG(0); 654 return; 655 } 656 657 qdf_atomic_inc(&hal_soc->stats.wstats.enqueues); 658 srng->wstats.enqueues++; 659 660 qdf_atomic_inc(&hal_soc->stats.wstats.q_depth); 661 662 q_elem->srng = srng; 663 q_elem->addr = addr; 664 q_elem->enqueue_val = value; 665 q_elem->enqueue_time = qdf_get_log_timestamp(); 666 667 /* 668 * Before the valid flag is set to true, all the other 669 * fields in the q_elem needs to be updated in memory. 670 * Else there is a chance that the dequeuing worker thread 671 * might read stale entries and process incorrect srng. 672 */ 673 qdf_wmb(); 674 q_elem->valid = true; 675 676 /* 677 * After all other fields in the q_elem has been updated 678 * in memory successfully, the valid flag needs to be updated 679 * in memory in time too. 680 * Else there is a chance that the dequeuing worker thread 681 * might read stale valid flag and the work will be bypassed 682 * for this round. And if there is no other work scheduled 683 * later, this hal register writing won't be updated any more. 684 */ 685 qdf_wmb(); 686 687 srng->reg_write_in_progress = true; 688 qdf_atomic_inc(&hal_soc->active_work_cnt); 689 690 hal_verbose_debug("write_idx %u srng ring id 0x%x addr 0x%pK val %u", 691 write_idx, srng->ring_id, addr, value); 692 693 qdf_queue_work(hal_soc->qdf_dev, hal_soc->reg_write_wq, 694 &hal_soc->reg_write_work); 695 } 696 697 void hal_delayed_reg_write(struct hal_soc *hal_soc, 698 struct hal_srng *srng, 699 void __iomem *addr, 700 uint32_t value) 701 { 702 if (pld_is_device_awake(hal_soc->qdf_dev->dev) || 703 hal_is_reg_write_tput_level_high(hal_soc)) { 704 qdf_atomic_inc(&hal_soc->stats.wstats.direct); 705 srng->wstats.direct++; 706 hal_write_address_32_mb(hal_soc, addr, value, false); 707 } else { 708 hal_reg_write_enqueue(hal_soc, srng, addr, value); 709 } 710 } 711 712 /** 713 * hal_delayed_reg_write_init() - Initialization function for delayed reg writes 714 * @hal_soc: hal_soc pointer 715 * 716 * Initialize main data structures to process register writes in a delayed 717 * workqueue. 718 * 719 * Return: QDF_STATUS_SUCCESS on success else a QDF error. 720 */ 721 static QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal) 722 { 723 hal->reg_write_wq = 724 qdf_alloc_high_prior_ordered_workqueue("hal_register_write_wq"); 725 qdf_create_work(0, &hal->reg_write_work, hal_reg_write_work, hal); 726 hal->reg_write_queue = qdf_mem_malloc(HAL_REG_WRITE_QUEUE_LEN * 727 sizeof(*hal->reg_write_queue)); 728 if (!hal->reg_write_queue) { 729 hal_err("unable to allocate memory"); 730 QDF_BUG(0); 731 return QDF_STATUS_E_NOMEM; 732 } 733 734 /* Initial value of indices */ 735 hal->read_idx = 0; 736 qdf_atomic_set(&hal->write_idx, -1); 737 return QDF_STATUS_SUCCESS; 738 } 739 740 /** 741 * hal_delayed_reg_write_deinit() - De-Initialize delayed reg write processing 742 * @hal_soc: hal_soc pointer 743 * 744 * De-initialize main data structures to process register writes in a delayed 745 * workqueue. 746 * 747 * Return: None 748 */ 749 static void hal_delayed_reg_write_deinit(struct hal_soc *hal) 750 { 751 __hal_flush_reg_write_work(hal); 752 753 qdf_flush_workqueue(0, hal->reg_write_wq); 754 qdf_destroy_workqueue(0, hal->reg_write_wq); 755 qdf_mem_free(hal->reg_write_queue); 756 } 757 758 static inline 759 char *hal_fill_reg_write_srng_stats(struct hal_srng *srng, 760 char *buf, qdf_size_t size) 761 { 762 qdf_scnprintf(buf, size, "enq %u deq %u coal %u direct %u", 763 srng->wstats.enqueues, srng->wstats.dequeues, 764 srng->wstats.coalesces, srng->wstats.direct); 765 return buf; 766 } 767 768 /* bytes for local buffer */ 769 #define HAL_REG_WRITE_SRNG_STATS_LEN 100 770 771 void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl) 772 { 773 struct hal_srng *srng; 774 char buf[HAL_REG_WRITE_SRNG_STATS_LEN]; 775 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 776 777 srng = hal_get_srng(hal, HAL_SRNG_SW2TCL1); 778 hal_debug("SW2TCL1: %s", 779 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 780 781 srng = hal_get_srng(hal, HAL_SRNG_WBM2SW0_RELEASE); 782 hal_debug("WBM2SW0: %s", 783 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 784 785 srng = hal_get_srng(hal, HAL_SRNG_REO2SW1); 786 hal_debug("REO2SW1: %s", 787 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 788 789 srng = hal_get_srng(hal, HAL_SRNG_REO2SW2); 790 hal_debug("REO2SW2: %s", 791 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 792 793 srng = hal_get_srng(hal, HAL_SRNG_REO2SW3); 794 hal_debug("REO2SW3: %s", 795 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 796 } 797 798 void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl) 799 { 800 uint32_t *hist; 801 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 802 803 hist = hal->stats.wstats.sched_delay; 804 805 hal_debug("enq %u deq %u coal %u direct %u q_depth %u max_q %u sched-delay hist %u %u %u %u", 806 qdf_atomic_read(&hal->stats.wstats.enqueues), 807 hal->stats.wstats.dequeues, 808 qdf_atomic_read(&hal->stats.wstats.coalesces), 809 qdf_atomic_read(&hal->stats.wstats.direct), 810 qdf_atomic_read(&hal->stats.wstats.q_depth), 811 hal->stats.wstats.max_q_depth, 812 hist[REG_WRITE_SCHED_DELAY_SUB_100us], 813 hist[REG_WRITE_SCHED_DELAY_SUB_1000us], 814 hist[REG_WRITE_SCHED_DELAY_SUB_5000us], 815 hist[REG_WRITE_SCHED_DELAY_GT_5000us]); 816 } 817 818 int hal_get_reg_write_pending_work(void *hal_soc) 819 { 820 struct hal_soc *hal = (struct hal_soc *)hal_soc; 821 822 return qdf_atomic_read(&hal->active_work_cnt); 823 } 824 825 #else 826 static inline QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal) 827 { 828 return QDF_STATUS_SUCCESS; 829 } 830 831 static inline void hal_delayed_reg_write_deinit(struct hal_soc *hal) 832 { 833 } 834 #endif 835 836 /** 837 * hal_attach - Initialize HAL layer 838 * @hif_handle: Opaque HIF handle 839 * @qdf_dev: QDF device 840 * 841 * Return: Opaque HAL SOC handle 842 * NULL on failure (if given ring is not available) 843 * 844 * This function should be called as part of HIF initialization (for accessing 845 * copy engines). DP layer will get hal_soc handle using hif_get_hal_handle() 846 * 847 */ 848 void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev) 849 { 850 struct hal_soc *hal; 851 int i; 852 853 hal = qdf_mem_malloc(sizeof(*hal)); 854 855 if (!hal) { 856 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 857 "%s: hal_soc allocation failed", __func__); 858 goto fail0; 859 } 860 hal->hif_handle = hif_handle; 861 hal->dev_base_addr = hif_get_dev_ba(hif_handle); /* UMAC */ 862 hal->dev_base_addr_ce = hif_get_dev_ba_ce(hif_handle); /* CE */ 863 hal->qdf_dev = qdf_dev; 864 hal->shadow_rdptr_mem_vaddr = (uint32_t *)qdf_mem_alloc_consistent( 865 qdf_dev, qdf_dev->dev, sizeof(*(hal->shadow_rdptr_mem_vaddr)) * 866 HAL_SRNG_ID_MAX, &(hal->shadow_rdptr_mem_paddr)); 867 if (!hal->shadow_rdptr_mem_paddr) { 868 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 869 "%s: hal->shadow_rdptr_mem_paddr allocation failed", 870 __func__); 871 goto fail1; 872 } 873 qdf_mem_zero(hal->shadow_rdptr_mem_vaddr, 874 sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX); 875 876 hal->shadow_wrptr_mem_vaddr = 877 (uint32_t *)qdf_mem_alloc_consistent(qdf_dev, qdf_dev->dev, 878 sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS, 879 &(hal->shadow_wrptr_mem_paddr)); 880 if (!hal->shadow_wrptr_mem_vaddr) { 881 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 882 "%s: hal->shadow_wrptr_mem_vaddr allocation failed", 883 __func__); 884 goto fail2; 885 } 886 qdf_mem_zero(hal->shadow_wrptr_mem_vaddr, 887 sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS); 888 889 for (i = 0; i < HAL_SRNG_ID_MAX; i++) { 890 hal->srng_list[i].initialized = 0; 891 hal->srng_list[i].ring_id = i; 892 } 893 894 qdf_spinlock_create(&hal->register_access_lock); 895 hal->register_window = 0; 896 hal->target_type = hal_get_target_type(hal_soc_to_hal_soc_handle(hal)); 897 898 hal_target_based_configure(hal); 899 900 hal_reg_write_fail_history_init(hal); 901 902 qdf_minidump_log(hal, sizeof(*hal), "hal_soc"); 903 904 qdf_atomic_init(&hal->active_work_cnt); 905 hal_delayed_reg_write_init(hal); 906 907 return (void *)hal; 908 909 fail2: 910 qdf_mem_free_consistent(qdf_dev, qdf_dev->dev, 911 sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX, 912 hal->shadow_rdptr_mem_vaddr, hal->shadow_rdptr_mem_paddr, 0); 913 fail1: 914 qdf_mem_free(hal); 915 fail0: 916 return NULL; 917 } 918 qdf_export_symbol(hal_attach); 919 920 /** 921 * hal_mem_info - Retrieve hal memory base address 922 * 923 * @hal_soc: Opaque HAL SOC handle 924 * @mem: pointer to structure to be updated with hal mem info 925 */ 926 void hal_get_meminfo(hal_soc_handle_t hal_soc_hdl, struct hal_mem_info *mem) 927 { 928 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 929 mem->dev_base_addr = (void *)hal->dev_base_addr; 930 mem->shadow_rdptr_mem_vaddr = (void *)hal->shadow_rdptr_mem_vaddr; 931 mem->shadow_wrptr_mem_vaddr = (void *)hal->shadow_wrptr_mem_vaddr; 932 mem->shadow_rdptr_mem_paddr = (void *)hal->shadow_rdptr_mem_paddr; 933 mem->shadow_wrptr_mem_paddr = (void *)hal->shadow_wrptr_mem_paddr; 934 hif_read_phy_mem_base((void *)hal->hif_handle, 935 (qdf_dma_addr_t *)&mem->dev_base_paddr); 936 return; 937 } 938 qdf_export_symbol(hal_get_meminfo); 939 940 /** 941 * hal_detach - Detach HAL layer 942 * @hal_soc: HAL SOC handle 943 * 944 * Return: Opaque HAL SOC handle 945 * NULL on failure (if given ring is not available) 946 * 947 * This function should be called as part of HIF initialization (for accessing 948 * copy engines). DP layer will get hal_soc handle using hif_get_hal_handle() 949 * 950 */ 951 extern void hal_detach(void *hal_soc) 952 { 953 struct hal_soc *hal = (struct hal_soc *)hal_soc; 954 955 hal_delayed_reg_write_deinit(hal); 956 957 qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev, 958 sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX, 959 hal->shadow_rdptr_mem_vaddr, hal->shadow_rdptr_mem_paddr, 0); 960 qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev, 961 sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS, 962 hal->shadow_wrptr_mem_vaddr, hal->shadow_wrptr_mem_paddr, 0); 963 qdf_minidump_remove(hal); 964 qdf_mem_free(hal); 965 966 return; 967 } 968 qdf_export_symbol(hal_detach); 969 970 /** 971 * hal_ce_dst_setup - Initialize CE destination ring registers 972 * @hal_soc: HAL SOC handle 973 * @srng: SRNG ring pointer 974 */ 975 static inline void hal_ce_dst_setup(struct hal_soc *hal, struct hal_srng *srng, 976 int ring_num) 977 { 978 uint32_t reg_val = 0; 979 uint32_t reg_addr; 980 struct hal_hw_srng_config *ring_config = 981 HAL_SRNG_CONFIG(hal, CE_DST); 982 983 /* set DEST_MAX_LENGTH according to ce assignment */ 984 reg_addr = HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR( 985 ring_config->reg_start[R0_INDEX] + 986 (ring_num * ring_config->reg_size[R0_INDEX])); 987 988 reg_val = HAL_REG_READ(hal, reg_addr); 989 reg_val &= ~HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK; 990 reg_val |= srng->u.dst_ring.max_buffer_length & 991 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK; 992 HAL_REG_WRITE(hal, reg_addr, reg_val); 993 994 if (srng->prefetch_timer) { 995 reg_addr = HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR( 996 ring_config->reg_start[R0_INDEX] + 997 (ring_num * ring_config->reg_size[R0_INDEX])); 998 999 reg_val = HAL_REG_READ(hal, reg_addr); 1000 reg_val &= ~HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK; 1001 reg_val |= srng->prefetch_timer; 1002 HAL_REG_WRITE(hal, reg_addr, reg_val); 1003 reg_val = HAL_REG_READ(hal, reg_addr); 1004 } 1005 1006 } 1007 1008 /** 1009 * hal_reo_read_write_ctrl_ix - Read or write REO_DESTINATION_RING_CTRL_IX 1010 * @hal: HAL SOC handle 1011 * @read: boolean value to indicate if read or write 1012 * @ix0: pointer to store IX0 reg value 1013 * @ix1: pointer to store IX1 reg value 1014 * @ix2: pointer to store IX2 reg value 1015 * @ix3: pointer to store IX3 reg value 1016 */ 1017 void hal_reo_read_write_ctrl_ix(hal_soc_handle_t hal_soc_hdl, bool read, 1018 uint32_t *ix0, uint32_t *ix1, 1019 uint32_t *ix2, uint32_t *ix3) 1020 { 1021 uint32_t reg_offset; 1022 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1023 1024 if (read) { 1025 if (ix0) { 1026 reg_offset = 1027 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR( 1028 SEQ_WCSS_UMAC_REO_REG_OFFSET); 1029 *ix0 = HAL_REG_READ(hal, reg_offset); 1030 } 1031 1032 if (ix1) { 1033 reg_offset = 1034 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR( 1035 SEQ_WCSS_UMAC_REO_REG_OFFSET); 1036 *ix1 = HAL_REG_READ(hal, reg_offset); 1037 } 1038 1039 if (ix2) { 1040 reg_offset = 1041 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1042 SEQ_WCSS_UMAC_REO_REG_OFFSET); 1043 *ix2 = HAL_REG_READ(hal, reg_offset); 1044 } 1045 1046 if (ix3) { 1047 reg_offset = 1048 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1049 SEQ_WCSS_UMAC_REO_REG_OFFSET); 1050 *ix3 = HAL_REG_READ(hal, reg_offset); 1051 } 1052 } else { 1053 if (ix0) { 1054 reg_offset = 1055 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR( 1056 SEQ_WCSS_UMAC_REO_REG_OFFSET); 1057 HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset, 1058 *ix0, true); 1059 } 1060 1061 if (ix1) { 1062 reg_offset = 1063 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR( 1064 SEQ_WCSS_UMAC_REO_REG_OFFSET); 1065 HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset, 1066 *ix1, true); 1067 } 1068 1069 if (ix2) { 1070 reg_offset = 1071 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( 1072 SEQ_WCSS_UMAC_REO_REG_OFFSET); 1073 HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset, 1074 *ix2, true); 1075 } 1076 1077 if (ix3) { 1078 reg_offset = 1079 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR( 1080 SEQ_WCSS_UMAC_REO_REG_OFFSET); 1081 HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset, 1082 *ix3, true); 1083 } 1084 } 1085 } 1086 1087 /** 1088 * hal_srng_dst_set_hp_paddr() - Set physical address to dest ring head pointer 1089 * @srng: sring pointer 1090 * @paddr: physical address 1091 */ 1092 void hal_srng_dst_set_hp_paddr(struct hal_srng *srng, 1093 uint64_t paddr) 1094 { 1095 SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, 1096 paddr & 0xffffffff); 1097 SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, 1098 paddr >> 32); 1099 } 1100 1101 /** 1102 * hal_srng_dst_init_hp() - Initialize destination ring head 1103 * pointer 1104 * @hal_soc: hal_soc handle 1105 * @srng: sring pointer 1106 * @vaddr: virtual address 1107 */ 1108 void hal_srng_dst_init_hp(struct hal_soc_handle *hal_soc, 1109 struct hal_srng *srng, 1110 uint32_t *vaddr) 1111 { 1112 uint32_t reg_offset; 1113 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1114 1115 if (!srng) 1116 return; 1117 1118 srng->u.dst_ring.hp_addr = vaddr; 1119 reg_offset = SRNG_DST_ADDR(srng, HP) - hal->dev_base_addr; 1120 HAL_REG_WRITE_CONFIRM_RETRY( 1121 hal, reg_offset, srng->u.dst_ring.cached_hp, true); 1122 1123 if (vaddr) { 1124 *srng->u.dst_ring.hp_addr = srng->u.dst_ring.cached_hp; 1125 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1126 "hp_addr=%pK, cached_hp=%d, hp=%d", 1127 (void *)srng->u.dst_ring.hp_addr, 1128 srng->u.dst_ring.cached_hp, 1129 *srng->u.dst_ring.hp_addr); 1130 } 1131 } 1132 1133 /** 1134 * hal_srng_hw_init - Private function to initialize SRNG HW 1135 * @hal_soc: HAL SOC handle 1136 * @srng: SRNG ring pointer 1137 */ 1138 static inline void hal_srng_hw_init(struct hal_soc *hal, 1139 struct hal_srng *srng) 1140 { 1141 if (srng->ring_dir == HAL_SRNG_SRC_RING) 1142 hal_srng_src_hw_init(hal, srng); 1143 else 1144 hal_srng_dst_hw_init(hal, srng); 1145 } 1146 1147 #ifdef CONFIG_SHADOW_V2 1148 #define ignore_shadow false 1149 #define CHECK_SHADOW_REGISTERS true 1150 #else 1151 #define ignore_shadow true 1152 #define CHECK_SHADOW_REGISTERS false 1153 #endif 1154 1155 /** 1156 * hal_srng_setup - Initialize HW SRNG ring. 1157 * @hal_soc: Opaque HAL SOC handle 1158 * @ring_type: one of the types from hal_ring_type 1159 * @ring_num: Ring number if there are multiple rings of same type (staring 1160 * from 0) 1161 * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings 1162 * @ring_params: SRNG ring params in hal_srng_params structure. 1163 1164 * Callers are expected to allocate contiguous ring memory of size 1165 * 'num_entries * entry_size' bytes and pass the physical and virtual base 1166 * addresses through 'ring_base_paddr' and 'ring_base_vaddr' in 1167 * hal_srng_params structure. Ring base address should be 8 byte aligned 1168 * and size of each ring entry should be queried using the API 1169 * hal_srng_get_entrysize 1170 * 1171 * Return: Opaque pointer to ring on success 1172 * NULL on failure (if given ring is not available) 1173 */ 1174 void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num, 1175 int mac_id, struct hal_srng_params *ring_params) 1176 { 1177 int ring_id; 1178 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1179 struct hal_srng *srng; 1180 struct hal_hw_srng_config *ring_config = 1181 HAL_SRNG_CONFIG(hal, ring_type); 1182 void *dev_base_addr; 1183 int i; 1184 1185 ring_id = hal_get_srng_ring_id(hal_soc, ring_type, ring_num, mac_id); 1186 if (ring_id < 0) 1187 return NULL; 1188 1189 hal_verbose_debug("mac_id %d ring_id %d", mac_id, ring_id); 1190 1191 srng = hal_get_srng(hal_soc, ring_id); 1192 1193 if (srng->initialized) { 1194 hal_verbose_debug("Ring (ring_type, ring_num) already initialized"); 1195 return NULL; 1196 } 1197 1198 dev_base_addr = hal->dev_base_addr; 1199 srng->ring_id = ring_id; 1200 srng->ring_dir = ring_config->ring_dir; 1201 srng->ring_base_paddr = ring_params->ring_base_paddr; 1202 srng->ring_base_vaddr = ring_params->ring_base_vaddr; 1203 srng->entry_size = ring_config->entry_size; 1204 srng->num_entries = ring_params->num_entries; 1205 srng->ring_size = srng->num_entries * srng->entry_size; 1206 srng->ring_size_mask = srng->ring_size - 1; 1207 srng->msi_addr = ring_params->msi_addr; 1208 srng->msi_data = ring_params->msi_data; 1209 srng->intr_timer_thres_us = ring_params->intr_timer_thres_us; 1210 srng->intr_batch_cntr_thres_entries = 1211 ring_params->intr_batch_cntr_thres_entries; 1212 srng->prefetch_timer = ring_params->prefetch_timer; 1213 srng->hal_soc = hal_soc; 1214 1215 for (i = 0 ; i < MAX_SRNG_REG_GROUPS; i++) { 1216 srng->hwreg_base[i] = dev_base_addr + ring_config->reg_start[i] 1217 + (ring_num * ring_config->reg_size[i]); 1218 } 1219 1220 /* Zero out the entire ring memory */ 1221 qdf_mem_zero(srng->ring_base_vaddr, (srng->entry_size * 1222 srng->num_entries) << 2); 1223 1224 srng->flags = ring_params->flags; 1225 #ifdef BIG_ENDIAN_HOST 1226 /* TODO: See if we should we get these flags from caller */ 1227 srng->flags |= HAL_SRNG_DATA_TLV_SWAP; 1228 srng->flags |= HAL_SRNG_MSI_SWAP; 1229 srng->flags |= HAL_SRNG_RING_PTR_SWAP; 1230 #endif 1231 1232 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1233 srng->u.src_ring.hp = 0; 1234 srng->u.src_ring.reap_hp = srng->ring_size - 1235 srng->entry_size; 1236 srng->u.src_ring.tp_addr = 1237 &(hal->shadow_rdptr_mem_vaddr[ring_id]); 1238 srng->u.src_ring.low_threshold = 1239 ring_params->low_threshold * srng->entry_size; 1240 if (ring_config->lmac_ring) { 1241 /* For LMAC rings, head pointer updates will be done 1242 * through FW by writing to a shared memory location 1243 */ 1244 srng->u.src_ring.hp_addr = 1245 &(hal->shadow_wrptr_mem_vaddr[ring_id - 1246 HAL_SRNG_LMAC1_ID_START]); 1247 srng->flags |= HAL_SRNG_LMAC_RING; 1248 } else if (ignore_shadow || (srng->u.src_ring.hp_addr == 0)) { 1249 srng->u.src_ring.hp_addr = 1250 hal_get_window_address(hal, 1251 SRNG_SRC_ADDR(srng, HP)); 1252 1253 if (CHECK_SHADOW_REGISTERS) { 1254 QDF_TRACE(QDF_MODULE_ID_TXRX, 1255 QDF_TRACE_LEVEL_ERROR, 1256 "%s: Ring (%d, %d) missing shadow config", 1257 __func__, ring_type, ring_num); 1258 } 1259 } else { 1260 hal_validate_shadow_register(hal, 1261 SRNG_SRC_ADDR(srng, HP), 1262 srng->u.src_ring.hp_addr); 1263 } 1264 } else { 1265 /* During initialization loop count in all the descriptors 1266 * will be set to zero, and HW will set it to 1 on completing 1267 * descriptor update in first loop, and increments it by 1 on 1268 * subsequent loops (loop count wraps around after reaching 1269 * 0xffff). The 'loop_cnt' in SW ring state is the expected 1270 * loop count in descriptors updated by HW (to be processed 1271 * by SW). 1272 */ 1273 srng->u.dst_ring.loop_cnt = 1; 1274 srng->u.dst_ring.tp = 0; 1275 srng->u.dst_ring.hp_addr = 1276 &(hal->shadow_rdptr_mem_vaddr[ring_id]); 1277 if (ring_config->lmac_ring) { 1278 /* For LMAC rings, tail pointer updates will be done 1279 * through FW by writing to a shared memory location 1280 */ 1281 srng->u.dst_ring.tp_addr = 1282 &(hal->shadow_wrptr_mem_vaddr[ring_id - 1283 HAL_SRNG_LMAC1_ID_START]); 1284 srng->flags |= HAL_SRNG_LMAC_RING; 1285 } else if (ignore_shadow || srng->u.dst_ring.tp_addr == 0) { 1286 srng->u.dst_ring.tp_addr = 1287 hal_get_window_address(hal, 1288 SRNG_DST_ADDR(srng, TP)); 1289 1290 if (CHECK_SHADOW_REGISTERS) { 1291 QDF_TRACE(QDF_MODULE_ID_TXRX, 1292 QDF_TRACE_LEVEL_ERROR, 1293 "%s: Ring (%d, %d) missing shadow config", 1294 __func__, ring_type, ring_num); 1295 } 1296 } else { 1297 hal_validate_shadow_register(hal, 1298 SRNG_DST_ADDR(srng, TP), 1299 srng->u.dst_ring.tp_addr); 1300 } 1301 } 1302 1303 if (!(ring_config->lmac_ring)) { 1304 hal_srng_hw_init(hal, srng); 1305 1306 if (ring_type == CE_DST) { 1307 srng->u.dst_ring.max_buffer_length = ring_params->max_buffer_length; 1308 hal_ce_dst_setup(hal, srng, ring_num); 1309 } 1310 } 1311 1312 SRNG_LOCK_INIT(&srng->lock); 1313 1314 srng->srng_event = 0; 1315 1316 srng->initialized = true; 1317 1318 return (void *)srng; 1319 } 1320 qdf_export_symbol(hal_srng_setup); 1321 1322 /** 1323 * hal_srng_cleanup - Deinitialize HW SRNG ring. 1324 * @hal_soc: Opaque HAL SOC handle 1325 * @hal_srng: Opaque HAL SRNG pointer 1326 */ 1327 void hal_srng_cleanup(void *hal_soc, hal_ring_handle_t hal_ring_hdl) 1328 { 1329 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1330 SRNG_LOCK_DESTROY(&srng->lock); 1331 srng->initialized = 0; 1332 } 1333 qdf_export_symbol(hal_srng_cleanup); 1334 1335 /** 1336 * hal_srng_get_entrysize - Returns size of ring entry in bytes 1337 * @hal_soc: Opaque HAL SOC handle 1338 * @ring_type: one of the types from hal_ring_type 1339 * 1340 */ 1341 uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type) 1342 { 1343 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1344 struct hal_hw_srng_config *ring_config = 1345 HAL_SRNG_CONFIG(hal, ring_type); 1346 return ring_config->entry_size << 2; 1347 } 1348 qdf_export_symbol(hal_srng_get_entrysize); 1349 1350 /** 1351 * hal_srng_max_entries - Returns maximum possible number of ring entries 1352 * @hal_soc: Opaque HAL SOC handle 1353 * @ring_type: one of the types from hal_ring_type 1354 * 1355 * Return: Maximum number of entries for the given ring_type 1356 */ 1357 uint32_t hal_srng_max_entries(void *hal_soc, int ring_type) 1358 { 1359 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1360 struct hal_hw_srng_config *ring_config = 1361 HAL_SRNG_CONFIG(hal, ring_type); 1362 1363 return ring_config->max_size / ring_config->entry_size; 1364 } 1365 qdf_export_symbol(hal_srng_max_entries); 1366 1367 enum hal_srng_dir hal_srng_get_dir(void *hal_soc, int ring_type) 1368 { 1369 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1370 struct hal_hw_srng_config *ring_config = 1371 HAL_SRNG_CONFIG(hal, ring_type); 1372 1373 return ring_config->ring_dir; 1374 } 1375 1376 /** 1377 * hal_srng_dump - Dump ring status 1378 * @srng: hal srng pointer 1379 */ 1380 void hal_srng_dump(struct hal_srng *srng) 1381 { 1382 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1383 hal_debug("=== SRC RING %d ===", srng->ring_id); 1384 hal_debug("hp %u, reap_hp %u, tp %u, cached tp %u", 1385 srng->u.src_ring.hp, 1386 srng->u.src_ring.reap_hp, 1387 *srng->u.src_ring.tp_addr, 1388 srng->u.src_ring.cached_tp); 1389 } else { 1390 hal_debug("=== DST RING %d ===", srng->ring_id); 1391 hal_debug("tp %u, hp %u, cached tp %u, loop_cnt %u", 1392 srng->u.dst_ring.tp, 1393 *srng->u.dst_ring.hp_addr, 1394 srng->u.dst_ring.cached_hp, 1395 srng->u.dst_ring.loop_cnt); 1396 } 1397 } 1398 1399 /** 1400 * hal_get_srng_params - Retrieve SRNG parameters for a given ring from HAL 1401 * 1402 * @hal_soc: Opaque HAL SOC handle 1403 * @hal_ring: Ring pointer (Source or Destination ring) 1404 * @ring_params: SRNG parameters will be returned through this structure 1405 */ 1406 extern void hal_get_srng_params(hal_soc_handle_t hal_soc_hdl, 1407 hal_ring_handle_t hal_ring_hdl, 1408 struct hal_srng_params *ring_params) 1409 { 1410 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1411 int i =0; 1412 ring_params->ring_id = srng->ring_id; 1413 ring_params->ring_dir = srng->ring_dir; 1414 ring_params->entry_size = srng->entry_size; 1415 1416 ring_params->ring_base_paddr = srng->ring_base_paddr; 1417 ring_params->ring_base_vaddr = srng->ring_base_vaddr; 1418 ring_params->num_entries = srng->num_entries; 1419 ring_params->msi_addr = srng->msi_addr; 1420 ring_params->msi_data = srng->msi_data; 1421 ring_params->intr_timer_thres_us = srng->intr_timer_thres_us; 1422 ring_params->intr_batch_cntr_thres_entries = 1423 srng->intr_batch_cntr_thres_entries; 1424 ring_params->low_threshold = srng->u.src_ring.low_threshold; 1425 ring_params->flags = srng->flags; 1426 ring_params->ring_id = srng->ring_id; 1427 for (i = 0 ; i < MAX_SRNG_REG_GROUPS; i++) 1428 ring_params->hwreg_base[i] = srng->hwreg_base[i]; 1429 } 1430 qdf_export_symbol(hal_get_srng_params); 1431 1432 void hal_set_low_threshold(hal_ring_handle_t hal_ring_hdl, 1433 uint32_t low_threshold) 1434 { 1435 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1436 srng->u.src_ring.low_threshold = low_threshold * srng->entry_size; 1437 } 1438 qdf_export_symbol(hal_set_low_threshold); 1439 1440 1441 #ifdef FORCE_WAKE 1442 void hal_set_init_phase(hal_soc_handle_t soc, bool init_phase) 1443 { 1444 struct hal_soc *hal_soc = (struct hal_soc *)soc; 1445 1446 hal_soc->init_phase = init_phase; 1447 } 1448 #endif /* FORCE_WAKE */ 1449