1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "hal_hw_headers.h" 21 #include "hal_api.h" 22 #include "hal_reo.h" 23 #include "target_type.h" 24 #include "qdf_module.h" 25 #include "wcss_version.h" 26 #include <qdf_tracepoint.h> 27 28 struct tcl_data_cmd gtcl_data_symbol __attribute__((used)); 29 30 #ifdef QCA_WIFI_QCA8074 31 void hal_qca6290_attach(struct hal_soc *hal); 32 #endif 33 #ifdef QCA_WIFI_QCA8074 34 void hal_qca8074_attach(struct hal_soc *hal); 35 #endif 36 #if defined(QCA_WIFI_QCA8074V2) || defined(QCA_WIFI_QCA6018) || \ 37 defined(QCA_WIFI_QCA9574) 38 void hal_qca8074v2_attach(struct hal_soc *hal); 39 #endif 40 #ifdef QCA_WIFI_QCA6390 41 void hal_qca6390_attach(struct hal_soc *hal); 42 #endif 43 #ifdef QCA_WIFI_QCA6490 44 void hal_qca6490_attach(struct hal_soc *hal); 45 #endif 46 #ifdef QCA_WIFI_QCN9000 47 void hal_qcn9000_attach(struct hal_soc *hal); 48 #endif 49 #ifdef QCA_WIFI_QCN9224 50 void hal_qcn9224v1_attach(struct hal_soc *hal); 51 void hal_qcn9224v2_attach(struct hal_soc *hal); 52 #endif 53 #if defined(QCA_WIFI_QCN6122) || defined(QCA_WIFI_QCN9160) 54 void hal_qcn6122_attach(struct hal_soc *hal); 55 #endif 56 #ifdef QCA_WIFI_QCA6750 57 void hal_qca6750_attach(struct hal_soc *hal); 58 #endif 59 #ifdef QCA_WIFI_QCA5018 60 void hal_qca5018_attach(struct hal_soc *hal); 61 #endif 62 #ifdef QCA_WIFI_QCA5332 63 void hal_qca5332_attach(struct hal_soc *hal); 64 #endif 65 #ifdef QCA_WIFI_KIWI 66 void hal_kiwi_attach(struct hal_soc *hal); 67 #endif 68 69 #ifdef ENABLE_VERBOSE_DEBUG 70 bool is_hal_verbose_debug_enabled; 71 #endif 72 73 #define HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(x) ((x) + 0x4) 74 #define HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR(x) ((x) + 0x8) 75 #define HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc) 76 #define HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10) 77 78 #ifdef ENABLE_HAL_REG_WR_HISTORY 79 struct hal_reg_write_fail_history hal_reg_wr_hist; 80 81 void hal_reg_wr_fail_history_add(struct hal_soc *hal_soc, 82 uint32_t offset, 83 uint32_t wr_val, uint32_t rd_val) 84 { 85 struct hal_reg_write_fail_entry *record; 86 int idx; 87 88 idx = hal_history_get_next_index(&hal_soc->reg_wr_fail_hist->index, 89 HAL_REG_WRITE_HIST_SIZE); 90 91 record = &hal_soc->reg_wr_fail_hist->record[idx]; 92 93 record->timestamp = qdf_get_log_timestamp(); 94 record->reg_offset = offset; 95 record->write_val = wr_val; 96 record->read_val = rd_val; 97 } 98 99 static void hal_reg_write_fail_history_init(struct hal_soc *hal) 100 { 101 hal->reg_wr_fail_hist = &hal_reg_wr_hist; 102 103 qdf_atomic_set(&hal->reg_wr_fail_hist->index, -1); 104 } 105 #else 106 static void hal_reg_write_fail_history_init(struct hal_soc *hal) 107 { 108 } 109 #endif 110 111 /** 112 * hal_get_srng_ring_id() - get the ring id of a described ring 113 * @hal: hal_soc data structure 114 * @ring_type: type enum describing the ring 115 * @ring_num: which ring of the ring type 116 * @mac_id: which mac does the ring belong to (or 0 for non-lmac rings) 117 * 118 * Return: the ring id or -EINVAL if the ring does not exist. 119 */ 120 static int hal_get_srng_ring_id(struct hal_soc *hal, int ring_type, 121 int ring_num, int mac_id) 122 { 123 struct hal_hw_srng_config *ring_config = 124 HAL_SRNG_CONFIG(hal, ring_type); 125 int ring_id; 126 127 if (ring_num >= ring_config->max_rings) { 128 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_INFO, 129 "%s: ring_num exceeded maximum no. of supported rings", 130 __func__); 131 /* TODO: This is a programming error. Assert if this happens */ 132 return -EINVAL; 133 } 134 135 /** 136 * Some DMAC rings share a common source ring, hence don't provide them 137 * with separate ring IDs per LMAC. 138 */ 139 if (ring_config->lmac_ring && !ring_config->dmac_cmn_ring) { 140 ring_id = (ring_config->start_ring_id + ring_num + 141 (mac_id * HAL_MAX_RINGS_PER_LMAC)); 142 } else { 143 ring_id = ring_config->start_ring_id + ring_num; 144 } 145 146 return ring_id; 147 } 148 149 static struct hal_srng *hal_get_srng(struct hal_soc *hal, int ring_id) 150 { 151 /* TODO: Should we allocate srng structures dynamically? */ 152 return &(hal->srng_list[ring_id]); 153 } 154 155 #ifndef SHADOW_REG_CONFIG_DISABLED 156 #define HP_OFFSET_IN_REG_START 1 157 #define OFFSET_FROM_HP_TO_TP 4 158 static void hal_update_srng_hp_tp_address(struct hal_soc *hal_soc, 159 int shadow_config_index, 160 int ring_type, 161 int ring_num) 162 { 163 struct hal_srng *srng; 164 int ring_id; 165 struct hal_hw_srng_config *ring_config = 166 HAL_SRNG_CONFIG(hal_soc, ring_type); 167 168 ring_id = hal_get_srng_ring_id(hal_soc, ring_type, ring_num, 0); 169 if (ring_id < 0) 170 return; 171 172 srng = hal_get_srng(hal_soc, ring_id); 173 174 if (ring_config->ring_dir == HAL_SRNG_DST_RING) { 175 srng->u.dst_ring.tp_addr = SHADOW_REGISTER(shadow_config_index) 176 + hal_soc->dev_base_addr; 177 hal_debug("tp_addr=%pK dev base addr %pK index %u", 178 srng->u.dst_ring.tp_addr, hal_soc->dev_base_addr, 179 shadow_config_index); 180 } else { 181 srng->u.src_ring.hp_addr = SHADOW_REGISTER(shadow_config_index) 182 + hal_soc->dev_base_addr; 183 hal_debug("hp_addr=%pK dev base addr %pK index %u", 184 srng->u.src_ring.hp_addr, 185 hal_soc->dev_base_addr, shadow_config_index); 186 } 187 188 } 189 #endif 190 191 #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE 192 void hal_set_one_target_reg_config(struct hal_soc *hal, 193 uint32_t target_reg_offset, 194 int list_index) 195 { 196 int i = list_index; 197 198 qdf_assert_always(i < MAX_GENERIC_SHADOW_REG); 199 hal->list_shadow_reg_config[i].target_register = 200 target_reg_offset; 201 hal->num_generic_shadow_regs_configured++; 202 } 203 204 qdf_export_symbol(hal_set_one_target_reg_config); 205 206 #define REO_R0_DESTINATION_RING_CTRL_ADDR_OFFSET 0x4 207 #define MAX_REO_REMAP_SHADOW_REGS 4 208 QDF_STATUS hal_set_shadow_regs(void *hal_soc) 209 { 210 uint32_t target_reg_offset; 211 struct hal_soc *hal = (struct hal_soc *)hal_soc; 212 int i; 213 struct hal_hw_srng_config *srng_config = 214 &hal->hw_srng_table[WBM2SW_RELEASE]; 215 uint32_t reo_reg_base; 216 217 reo_reg_base = hal_get_reo_reg_base_offset(hal_soc); 218 219 target_reg_offset = 220 HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR(reo_reg_base); 221 222 for (i = 0; i < MAX_REO_REMAP_SHADOW_REGS; i++) { 223 hal_set_one_target_reg_config(hal, target_reg_offset, i); 224 target_reg_offset += REO_R0_DESTINATION_RING_CTRL_ADDR_OFFSET; 225 } 226 227 target_reg_offset = srng_config->reg_start[HP_OFFSET_IN_REG_START]; 228 target_reg_offset += (srng_config->reg_size[HP_OFFSET_IN_REG_START] 229 * HAL_IPA_TX_COMP_RING_IDX); 230 231 hal_set_one_target_reg_config(hal, target_reg_offset, i); 232 return QDF_STATUS_SUCCESS; 233 } 234 235 qdf_export_symbol(hal_set_shadow_regs); 236 237 QDF_STATUS hal_construct_shadow_regs(void *hal_soc) 238 { 239 struct hal_soc *hal = (struct hal_soc *)hal_soc; 240 int shadow_config_index = hal->num_shadow_registers_configured; 241 int i; 242 int num_regs = hal->num_generic_shadow_regs_configured; 243 244 for (i = 0; i < num_regs; i++) { 245 qdf_assert_always(shadow_config_index < MAX_SHADOW_REGISTERS); 246 hal->shadow_config[shadow_config_index].addr = 247 hal->list_shadow_reg_config[i].target_register; 248 hal->list_shadow_reg_config[i].shadow_config_index = 249 shadow_config_index; 250 hal->list_shadow_reg_config[i].va = 251 SHADOW_REGISTER(shadow_config_index) + 252 (uintptr_t)hal->dev_base_addr; 253 hal_debug("target_reg %x, shadow register 0x%x shadow_index 0x%x", 254 hal->shadow_config[shadow_config_index].addr, 255 SHADOW_REGISTER(shadow_config_index), 256 shadow_config_index); 257 shadow_config_index++; 258 hal->num_shadow_registers_configured++; 259 } 260 return QDF_STATUS_SUCCESS; 261 } 262 263 qdf_export_symbol(hal_construct_shadow_regs); 264 #endif 265 266 #ifndef SHADOW_REG_CONFIG_DISABLED 267 268 QDF_STATUS hal_set_one_shadow_config(void *hal_soc, 269 int ring_type, 270 int ring_num) 271 { 272 uint32_t target_register; 273 struct hal_soc *hal = (struct hal_soc *)hal_soc; 274 struct hal_hw_srng_config *srng_config = &hal->hw_srng_table[ring_type]; 275 int shadow_config_index = hal->num_shadow_registers_configured; 276 277 if (shadow_config_index >= MAX_SHADOW_REGISTERS) { 278 QDF_ASSERT(0); 279 return QDF_STATUS_E_RESOURCES; 280 } 281 282 hal->num_shadow_registers_configured++; 283 284 target_register = srng_config->reg_start[HP_OFFSET_IN_REG_START]; 285 target_register += (srng_config->reg_size[HP_OFFSET_IN_REG_START] 286 *ring_num); 287 288 /* if the ring is a dst ring, we need to shadow the tail pointer */ 289 if (srng_config->ring_dir == HAL_SRNG_DST_RING) 290 target_register += OFFSET_FROM_HP_TO_TP; 291 292 hal->shadow_config[shadow_config_index].addr = target_register; 293 294 /* update hp/tp addr in the hal_soc structure*/ 295 hal_update_srng_hp_tp_address(hal_soc, shadow_config_index, ring_type, 296 ring_num); 297 298 hal_debug("target_reg %x, shadow register 0x%x shadow_index 0x%x, ring_type %d, ring num %d", 299 target_register, 300 SHADOW_REGISTER(shadow_config_index), 301 shadow_config_index, 302 ring_type, ring_num); 303 304 return QDF_STATUS_SUCCESS; 305 } 306 307 qdf_export_symbol(hal_set_one_shadow_config); 308 309 QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc) 310 { 311 int ring_type, ring_num; 312 struct hal_soc *hal = (struct hal_soc *)hal_soc; 313 314 for (ring_type = 0; ring_type < MAX_RING_TYPES; ring_type++) { 315 struct hal_hw_srng_config *srng_config = 316 &hal->hw_srng_table[ring_type]; 317 318 if (ring_type == CE_SRC || 319 ring_type == CE_DST || 320 ring_type == CE_DST_STATUS) 321 continue; 322 323 if (srng_config->lmac_ring) 324 continue; 325 326 for (ring_num = 0; ring_num < srng_config->max_rings; 327 ring_num++) 328 hal_set_one_shadow_config(hal_soc, ring_type, ring_num); 329 } 330 331 return QDF_STATUS_SUCCESS; 332 } 333 334 qdf_export_symbol(hal_construct_srng_shadow_regs); 335 #else 336 337 QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc) 338 { 339 return QDF_STATUS_SUCCESS; 340 } 341 342 qdf_export_symbol(hal_construct_srng_shadow_regs); 343 344 QDF_STATUS hal_set_one_shadow_config(void *hal_soc, int ring_type, 345 int ring_num) 346 { 347 return QDF_STATUS_SUCCESS; 348 } 349 qdf_export_symbol(hal_set_one_shadow_config); 350 #endif 351 352 void hal_get_shadow_config(void *hal_soc, 353 struct pld_shadow_reg_v2_cfg **shadow_config, 354 int *num_shadow_registers_configured) 355 { 356 struct hal_soc *hal = (struct hal_soc *)hal_soc; 357 358 *shadow_config = &hal->shadow_config[0].v2; 359 *num_shadow_registers_configured = 360 hal->num_shadow_registers_configured; 361 } 362 qdf_export_symbol(hal_get_shadow_config); 363 364 #ifdef CONFIG_SHADOW_V3 365 void hal_get_shadow_v3_config(void *hal_soc, 366 struct pld_shadow_reg_v3_cfg **shadow_config, 367 int *num_shadow_registers_configured) 368 { 369 struct hal_soc *hal = (struct hal_soc *)hal_soc; 370 371 *shadow_config = &hal->shadow_config[0].v3; 372 *num_shadow_registers_configured = 373 hal->num_shadow_registers_configured; 374 } 375 qdf_export_symbol(hal_get_shadow_v3_config); 376 #endif 377 378 static bool hal_validate_shadow_register(struct hal_soc *hal, 379 uint32_t *destination, 380 uint32_t *shadow_address) 381 { 382 unsigned int index; 383 uint32_t *shadow_0_offset = SHADOW_REGISTER(0) + hal->dev_base_addr; 384 int destination_ba_offset = 385 ((char *)destination) - (char *)hal->dev_base_addr; 386 387 index = shadow_address - shadow_0_offset; 388 389 if (index >= MAX_SHADOW_REGISTERS) { 390 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 391 "%s: index %x out of bounds", __func__, index); 392 goto error; 393 } else if (hal->shadow_config[index].addr != destination_ba_offset) { 394 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 395 "%s: sanity check failure, expected %x, found %x", 396 __func__, destination_ba_offset, 397 hal->shadow_config[index].addr); 398 goto error; 399 } 400 return true; 401 error: 402 qdf_print("baddr %pK, destination %pK, shadow_address %pK s0offset %pK index %x", 403 hal->dev_base_addr, destination, shadow_address, 404 shadow_0_offset, index); 405 QDF_BUG(0); 406 return false; 407 } 408 409 static void hal_target_based_configure(struct hal_soc *hal) 410 { 411 /** 412 * Indicate Initialization of srngs to avoid force wake 413 * as umac power collapse is not enabled yet 414 */ 415 hal->init_phase = true; 416 417 switch (hal->target_type) { 418 #ifdef QCA_WIFI_QCA6290 419 case TARGET_TYPE_QCA6290: 420 hal->use_register_windowing = true; 421 hal_qca6290_attach(hal); 422 break; 423 #endif 424 #ifdef QCA_WIFI_QCA6390 425 case TARGET_TYPE_QCA6390: 426 hal->use_register_windowing = true; 427 hal_qca6390_attach(hal); 428 break; 429 #endif 430 #ifdef QCA_WIFI_QCA6490 431 case TARGET_TYPE_QCA6490: 432 hal->use_register_windowing = true; 433 hal_qca6490_attach(hal); 434 break; 435 #endif 436 #ifdef QCA_WIFI_QCA6750 437 case TARGET_TYPE_QCA6750: 438 hal->use_register_windowing = true; 439 hal->static_window_map = true; 440 hal_qca6750_attach(hal); 441 break; 442 #endif 443 #ifdef QCA_WIFI_KIWI 444 case TARGET_TYPE_KIWI: 445 case TARGET_TYPE_MANGO: 446 hal->use_register_windowing = true; 447 hal_kiwi_attach(hal); 448 break; 449 #endif 450 #if defined(QCA_WIFI_QCA8074) && defined(WIFI_TARGET_TYPE_3_0) 451 case TARGET_TYPE_QCA8074: 452 hal_qca8074_attach(hal); 453 break; 454 #endif 455 456 #if defined(QCA_WIFI_QCA8074V2) 457 case TARGET_TYPE_QCA8074V2: 458 hal_qca8074v2_attach(hal); 459 break; 460 #endif 461 462 #if defined(QCA_WIFI_QCA6018) 463 case TARGET_TYPE_QCA6018: 464 hal_qca8074v2_attach(hal); 465 break; 466 #endif 467 468 #if defined(QCA_WIFI_QCA9574) 469 case TARGET_TYPE_QCA9574: 470 hal_qca8074v2_attach(hal); 471 break; 472 #endif 473 474 #if defined(QCA_WIFI_QCN6122) 475 case TARGET_TYPE_QCN6122: 476 hal->use_register_windowing = true; 477 /* 478 * Static window map is enabled for qcn9000 to use 2mb bar 479 * size and use multiple windows to write into registers. 480 */ 481 hal->static_window_map = true; 482 hal_qcn6122_attach(hal); 483 break; 484 #endif 485 486 #if defined(QCA_WIFI_QCN9160) 487 case TARGET_TYPE_QCN9160: 488 hal->use_register_windowing = true; 489 /* 490 * Static window map is enabled for qcn9160 to use 2mb bar 491 * size and use multiple windows to write into registers. 492 */ 493 hal->static_window_map = true; 494 hal_qcn6122_attach(hal); 495 break; 496 #endif 497 498 #ifdef QCA_WIFI_QCN9000 499 case TARGET_TYPE_QCN9000: 500 hal->use_register_windowing = true; 501 /* 502 * Static window map is enabled for qcn9000 to use 2mb bar 503 * size and use multiple windows to write into registers. 504 */ 505 hal->static_window_map = true; 506 hal_qcn9000_attach(hal); 507 break; 508 #endif 509 #ifdef QCA_WIFI_QCA5018 510 case TARGET_TYPE_QCA5018: 511 hal->use_register_windowing = true; 512 hal->static_window_map = true; 513 hal_qca5018_attach(hal); 514 break; 515 #endif 516 #ifdef QCA_WIFI_QCN9224 517 case TARGET_TYPE_QCN9224: 518 hal->use_register_windowing = true; 519 hal->static_window_map = true; 520 if (hal->version == 1) 521 hal_qcn9224v1_attach(hal); 522 else 523 hal_qcn9224v2_attach(hal); 524 break; 525 #endif 526 #ifdef QCA_WIFI_QCA5332 527 case TARGET_TYPE_QCA5332: 528 hal->use_register_windowing = true; 529 hal->static_window_map = true; 530 hal_qca5332_attach(hal); 531 break; 532 #endif 533 default: 534 break; 535 } 536 } 537 538 uint32_t hal_get_target_type(hal_soc_handle_t hal_soc_hdl) 539 { 540 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 541 struct hif_target_info *tgt_info = 542 hif_get_target_info_handle(hal_soc->hif_handle); 543 544 return tgt_info->target_type; 545 } 546 547 qdf_export_symbol(hal_get_target_type); 548 549 #if defined(FEATURE_HAL_DELAYED_REG_WRITE) 550 /** 551 * hal_is_reg_write_tput_level_high() - throughput level for delayed reg writes 552 * @hal: hal_soc pointer 553 * 554 * Return: true if throughput is high, else false. 555 */ 556 static inline bool hal_is_reg_write_tput_level_high(struct hal_soc *hal) 557 { 558 int bw_level = hif_get_bandwidth_level(hal->hif_handle); 559 560 return (bw_level >= PLD_BUS_WIDTH_MEDIUM) ? true : false; 561 } 562 563 static inline 564 char *hal_fill_reg_write_srng_stats(struct hal_srng *srng, 565 char *buf, qdf_size_t size) 566 { 567 qdf_scnprintf(buf, size, "enq %u deq %u coal %u direct %u", 568 srng->wstats.enqueues, srng->wstats.dequeues, 569 srng->wstats.coalesces, srng->wstats.direct); 570 return buf; 571 } 572 573 /* bytes for local buffer */ 574 #define HAL_REG_WRITE_SRNG_STATS_LEN 100 575 576 void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl) 577 { 578 struct hal_srng *srng; 579 char buf[HAL_REG_WRITE_SRNG_STATS_LEN]; 580 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 581 582 srng = hal_get_srng(hal, HAL_SRNG_SW2TCL1); 583 hal_debug("SW2TCL1: %s", 584 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 585 586 srng = hal_get_srng(hal, HAL_SRNG_WBM2SW0_RELEASE); 587 hal_debug("WBM2SW0: %s", 588 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 589 590 srng = hal_get_srng(hal, HAL_SRNG_REO2SW1); 591 hal_debug("REO2SW1: %s", 592 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 593 594 srng = hal_get_srng(hal, HAL_SRNG_REO2SW2); 595 hal_debug("REO2SW2: %s", 596 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 597 598 srng = hal_get_srng(hal, HAL_SRNG_REO2SW3); 599 hal_debug("REO2SW3: %s", 600 hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf))); 601 } 602 603 void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl) 604 { 605 uint32_t *hist; 606 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 607 608 hist = hal->stats.wstats.sched_delay; 609 hal_debug("wstats: enq %u deq %u coal %u direct %u q_depth %u max_q %u sched-delay hist %u %u %u %u", 610 qdf_atomic_read(&hal->stats.wstats.enqueues), 611 hal->stats.wstats.dequeues, 612 qdf_atomic_read(&hal->stats.wstats.coalesces), 613 qdf_atomic_read(&hal->stats.wstats.direct), 614 qdf_atomic_read(&hal->stats.wstats.q_depth), 615 hal->stats.wstats.max_q_depth, 616 hist[REG_WRITE_SCHED_DELAY_SUB_100us], 617 hist[REG_WRITE_SCHED_DELAY_SUB_1000us], 618 hist[REG_WRITE_SCHED_DELAY_SUB_5000us], 619 hist[REG_WRITE_SCHED_DELAY_GT_5000us]); 620 } 621 622 int hal_get_reg_write_pending_work(void *hal_soc) 623 { 624 struct hal_soc *hal = (struct hal_soc *)hal_soc; 625 626 return qdf_atomic_read(&hal->active_work_cnt); 627 } 628 629 #endif 630 631 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 632 #ifdef MEMORY_DEBUG 633 /* 634 * Length of the queue(array) used to hold delayed register writes. 635 * Must be a multiple of 2. 636 */ 637 #define HAL_REG_WRITE_QUEUE_LEN 128 638 #else 639 #define HAL_REG_WRITE_QUEUE_LEN 32 640 #endif 641 642 /** 643 * hal_process_reg_write_q_elem() - process a register write queue element 644 * @hal: hal_soc pointer 645 * @q_elem: pointer to hal register write queue element 646 * 647 * Return: The value which was written to the address 648 */ 649 static uint32_t 650 hal_process_reg_write_q_elem(struct hal_soc *hal, 651 struct hal_reg_write_q_elem *q_elem) 652 { 653 struct hal_srng *srng = q_elem->srng; 654 uint32_t write_val; 655 656 SRNG_LOCK(&srng->lock); 657 658 srng->reg_write_in_progress = false; 659 srng->wstats.dequeues++; 660 661 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 662 q_elem->dequeue_val = srng->u.src_ring.hp; 663 hal_write_address_32_mb(hal, 664 srng->u.src_ring.hp_addr, 665 srng->u.src_ring.hp, false); 666 write_val = srng->u.src_ring.hp; 667 } else { 668 q_elem->dequeue_val = srng->u.dst_ring.tp; 669 hal_write_address_32_mb(hal, 670 srng->u.dst_ring.tp_addr, 671 srng->u.dst_ring.tp, false); 672 write_val = srng->u.dst_ring.tp; 673 } 674 675 q_elem->valid = 0; 676 srng->last_dequeue_time = q_elem->dequeue_time; 677 SRNG_UNLOCK(&srng->lock); 678 679 return write_val; 680 } 681 682 /** 683 * hal_reg_write_fill_sched_delay_hist() - fill reg write delay histogram in hal 684 * @hal: hal_soc pointer 685 * @delay: delay in us 686 * 687 * Return: None 688 */ 689 static inline void hal_reg_write_fill_sched_delay_hist(struct hal_soc *hal, 690 uint64_t delay_us) 691 { 692 uint32_t *hist; 693 694 hist = hal->stats.wstats.sched_delay; 695 696 if (delay_us < 100) 697 hist[REG_WRITE_SCHED_DELAY_SUB_100us]++; 698 else if (delay_us < 1000) 699 hist[REG_WRITE_SCHED_DELAY_SUB_1000us]++; 700 else if (delay_us < 5000) 701 hist[REG_WRITE_SCHED_DELAY_SUB_5000us]++; 702 else 703 hist[REG_WRITE_SCHED_DELAY_GT_5000us]++; 704 } 705 706 #ifdef SHADOW_WRITE_DELAY 707 708 #define SHADOW_WRITE_MIN_DELTA_US 5 709 #define SHADOW_WRITE_DELAY_US 50 710 711 /* 712 * Never add those srngs which are performance relate. 713 * The delay itself will hit performance heavily. 714 */ 715 #define IS_SRNG_MATCH(s) ((s)->ring_id == HAL_SRNG_CE_1_DST_STATUS || \ 716 (s)->ring_id == HAL_SRNG_CE_1_DST) 717 718 static inline bool hal_reg_write_need_delay(struct hal_reg_write_q_elem *elem) 719 { 720 struct hal_srng *srng = elem->srng; 721 struct hal_soc *hal; 722 qdf_time_t now; 723 qdf_iomem_t real_addr; 724 725 if (qdf_unlikely(!srng)) 726 return false; 727 728 hal = srng->hal_soc; 729 if (qdf_unlikely(!hal)) 730 return false; 731 732 /* Check if it is target srng, and valid shadow reg */ 733 if (qdf_likely(!IS_SRNG_MATCH(srng))) 734 return false; 735 736 if (srng->ring_dir == HAL_SRNG_SRC_RING) 737 real_addr = SRNG_SRC_ADDR(srng, HP); 738 else 739 real_addr = SRNG_DST_ADDR(srng, TP); 740 if (!hal_validate_shadow_register(hal, real_addr, elem->addr)) 741 return false; 742 743 /* Check the time delta from last write of same srng */ 744 now = qdf_get_log_timestamp(); 745 if (qdf_log_timestamp_to_usecs(now - srng->last_dequeue_time) > 746 SHADOW_WRITE_MIN_DELTA_US) 747 return false; 748 749 /* Delay dequeue, and record */ 750 qdf_udelay(SHADOW_WRITE_DELAY_US); 751 752 srng->wstats.dequeue_delay++; 753 hal->stats.wstats.dequeue_delay++; 754 755 return true; 756 } 757 #else 758 static inline bool hal_reg_write_need_delay(struct hal_reg_write_q_elem *elem) 759 { 760 return false; 761 } 762 #endif 763 764 /** 765 * hal_reg_write_work() - Worker to process delayed writes 766 * @arg: hal_soc pointer 767 * 768 * Return: None 769 */ 770 static void hal_reg_write_work(void *arg) 771 { 772 int32_t q_depth, write_val; 773 struct hal_soc *hal = arg; 774 struct hal_reg_write_q_elem *q_elem; 775 uint64_t delta_us; 776 uint8_t ring_id; 777 uint32_t *addr; 778 uint32_t num_processed = 0; 779 780 q_elem = &hal->reg_write_queue[(hal->read_idx)]; 781 q_elem->work_scheduled_time = qdf_get_log_timestamp(); 782 q_elem->cpu_id = qdf_get_cpu(); 783 784 /* Make sure q_elem consistent in the memory for multi-cores */ 785 qdf_rmb(); 786 if (!q_elem->valid) 787 return; 788 789 q_depth = qdf_atomic_read(&hal->stats.wstats.q_depth); 790 if (q_depth > hal->stats.wstats.max_q_depth) 791 hal->stats.wstats.max_q_depth = q_depth; 792 793 if (hif_prevent_link_low_power_states(hal->hif_handle)) { 794 hal->stats.wstats.prevent_l1_fails++; 795 return; 796 } 797 798 while (true) { 799 qdf_rmb(); 800 if (!q_elem->valid) 801 break; 802 803 q_elem->dequeue_time = qdf_get_log_timestamp(); 804 ring_id = q_elem->srng->ring_id; 805 addr = q_elem->addr; 806 delta_us = qdf_log_timestamp_to_usecs(q_elem->dequeue_time - 807 q_elem->enqueue_time); 808 hal_reg_write_fill_sched_delay_hist(hal, delta_us); 809 810 hal->stats.wstats.dequeues++; 811 qdf_atomic_dec(&hal->stats.wstats.q_depth); 812 813 if (hal_reg_write_need_delay(q_elem)) 814 hal_verbose_debug("Delay reg writer for srng 0x%x, addr 0x%pK", 815 q_elem->srng->ring_id, q_elem->addr); 816 817 write_val = hal_process_reg_write_q_elem(hal, q_elem); 818 hal_verbose_debug("read_idx %u srng 0x%x, addr 0x%pK dequeue_val %u sched delay %llu us", 819 hal->read_idx, ring_id, addr, write_val, delta_us); 820 821 qdf_trace_dp_del_reg_write(ring_id, q_elem->enqueue_val, 822 q_elem->dequeue_val, 823 q_elem->enqueue_time, 824 q_elem->dequeue_time); 825 826 num_processed++; 827 hal->read_idx = (hal->read_idx + 1) & 828 (HAL_REG_WRITE_QUEUE_LEN - 1); 829 q_elem = &hal->reg_write_queue[(hal->read_idx)]; 830 } 831 832 hif_allow_link_low_power_states(hal->hif_handle); 833 /* 834 * Decrement active_work_cnt by the number of elements dequeued after 835 * hif_allow_link_low_power_states. 836 * This makes sure that hif_try_complete_tasks will wait till we make 837 * the bus access in hif_allow_link_low_power_states. This will avoid 838 * race condition between delayed register worker and bus suspend 839 * (system suspend or runtime suspend). 840 * 841 * The following decrement should be done at the end! 842 */ 843 qdf_atomic_sub(num_processed, &hal->active_work_cnt); 844 } 845 846 static void __hal_flush_reg_write_work(struct hal_soc *hal) 847 { 848 qdf_flush_work(&hal->reg_write_work); 849 qdf_disable_work(&hal->reg_write_work); 850 } 851 852 void hal_flush_reg_write_work(hal_soc_handle_t hal_handle) 853 { __hal_flush_reg_write_work((struct hal_soc *)hal_handle); 854 } 855 856 /** 857 * hal_reg_write_enqueue() - enqueue register writes into kworker 858 * @hal_soc: hal_soc pointer 859 * @srng: srng pointer 860 * @addr: iomem address of register 861 * @value: value to be written to iomem address 862 * 863 * This function executes from within the SRNG LOCK 864 * 865 * Return: None 866 */ 867 static void hal_reg_write_enqueue(struct hal_soc *hal_soc, 868 struct hal_srng *srng, 869 void __iomem *addr, 870 uint32_t value) 871 { 872 struct hal_reg_write_q_elem *q_elem; 873 uint32_t write_idx; 874 875 if (srng->reg_write_in_progress) { 876 hal_verbose_debug("Already in progress srng ring id 0x%x addr 0x%pK val %u", 877 srng->ring_id, addr, value); 878 qdf_atomic_inc(&hal_soc->stats.wstats.coalesces); 879 srng->wstats.coalesces++; 880 return; 881 } 882 883 write_idx = qdf_atomic_inc_return(&hal_soc->write_idx); 884 885 write_idx = write_idx & (HAL_REG_WRITE_QUEUE_LEN - 1); 886 887 q_elem = &hal_soc->reg_write_queue[write_idx]; 888 889 if (q_elem->valid) { 890 hal_err("queue full"); 891 QDF_BUG(0); 892 return; 893 } 894 895 qdf_atomic_inc(&hal_soc->stats.wstats.enqueues); 896 srng->wstats.enqueues++; 897 898 qdf_atomic_inc(&hal_soc->stats.wstats.q_depth); 899 900 q_elem->srng = srng; 901 q_elem->addr = addr; 902 q_elem->enqueue_val = value; 903 q_elem->enqueue_time = qdf_get_log_timestamp(); 904 905 /* 906 * Before the valid flag is set to true, all the other 907 * fields in the q_elem needs to be updated in memory. 908 * Else there is a chance that the dequeuing worker thread 909 * might read stale entries and process incorrect srng. 910 */ 911 qdf_wmb(); 912 q_elem->valid = true; 913 914 /* 915 * After all other fields in the q_elem has been updated 916 * in memory successfully, the valid flag needs to be updated 917 * in memory in time too. 918 * Else there is a chance that the dequeuing worker thread 919 * might read stale valid flag and the work will be bypassed 920 * for this round. And if there is no other work scheduled 921 * later, this hal register writing won't be updated any more. 922 */ 923 qdf_wmb(); 924 925 srng->reg_write_in_progress = true; 926 qdf_atomic_inc(&hal_soc->active_work_cnt); 927 928 hal_verbose_debug("write_idx %u srng ring id 0x%x addr 0x%pK val %u", 929 write_idx, srng->ring_id, addr, value); 930 931 qdf_queue_work(hal_soc->qdf_dev, hal_soc->reg_write_wq, 932 &hal_soc->reg_write_work); 933 } 934 935 /** 936 * hal_delayed_reg_write_init() - Initialization function for delayed reg writes 937 * @hal_soc: hal_soc pointer 938 * 939 * Initialize main data structures to process register writes in a delayed 940 * workqueue. 941 * 942 * Return: QDF_STATUS_SUCCESS on success else a QDF error. 943 */ 944 static QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal) 945 { 946 hal->reg_write_wq = 947 qdf_alloc_high_prior_ordered_workqueue("hal_register_write_wq"); 948 qdf_create_work(0, &hal->reg_write_work, hal_reg_write_work, hal); 949 hal->reg_write_queue = qdf_mem_malloc(HAL_REG_WRITE_QUEUE_LEN * 950 sizeof(*hal->reg_write_queue)); 951 if (!hal->reg_write_queue) { 952 hal_err("unable to allocate memory"); 953 QDF_BUG(0); 954 return QDF_STATUS_E_NOMEM; 955 } 956 957 /* Initial value of indices */ 958 hal->read_idx = 0; 959 qdf_atomic_set(&hal->write_idx, -1); 960 return QDF_STATUS_SUCCESS; 961 } 962 963 /** 964 * hal_delayed_reg_write_deinit() - De-Initialize delayed reg write processing 965 * @hal_soc: hal_soc pointer 966 * 967 * De-initialize main data structures to process register writes in a delayed 968 * workqueue. 969 * 970 * Return: None 971 */ 972 static void hal_delayed_reg_write_deinit(struct hal_soc *hal) 973 { 974 __hal_flush_reg_write_work(hal); 975 976 qdf_flush_workqueue(0, hal->reg_write_wq); 977 qdf_destroy_workqueue(0, hal->reg_write_wq); 978 qdf_mem_free(hal->reg_write_queue); 979 } 980 981 #else 982 static inline QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal) 983 { 984 return QDF_STATUS_SUCCESS; 985 } 986 987 static inline void hal_delayed_reg_write_deinit(struct hal_soc *hal) 988 { 989 } 990 #endif 991 992 #ifdef FEATURE_HAL_DELAYED_REG_WRITE 993 #ifdef HAL_RECORD_SUSPEND_WRITE 994 static struct hal_suspend_write_history 995 g_hal_suspend_write_history[HAL_SUSPEND_WRITE_HISTORY_MAX]; 996 997 static 998 void hal_event_suspend_record(uint8_t ring_id, uint32_t value, uint32_t count) 999 { 1000 uint32_t index = qdf_atomic_read(g_hal_suspend_write_history.index) & 1001 (HAL_SUSPEND_WRITE_HISTORY_MAX - 1); 1002 struct hal_suspend_write_record *cur_event = 1003 &hal_suspend_write_event.record[index]; 1004 1005 cur_event->ts = qdf_get_log_timestamp(); 1006 cur_event->ring_id = ring_id; 1007 cur_event->value = value; 1008 cur_event->direct_wcount = count; 1009 qdf_atomic_inc(g_hal_suspend_write_history.index); 1010 } 1011 1012 static inline 1013 void hal_record_suspend_write(uint8_t ring_id, uint32_t value, uint32_t count) 1014 { 1015 if (hif_rtpm_get_state() >= HIF_RTPM_STATE_SUSPENDING) 1016 hal_event_suspend_record(ring_id, value, count); 1017 } 1018 #else 1019 static inline 1020 void hal_record_suspend_write(uint8_t ring_id, uint32_t value, uint32_t count) 1021 { 1022 } 1023 #endif 1024 1025 #ifdef QCA_WIFI_QCA6750 1026 void hal_delayed_reg_write(struct hal_soc *hal_soc, 1027 struct hal_srng *srng, 1028 void __iomem *addr, 1029 uint32_t value) 1030 { 1031 uint8_t vote_access; 1032 1033 switch (srng->ring_type) { 1034 case CE_SRC: 1035 case CE_DST: 1036 case CE_DST_STATUS: 1037 vote_access = hif_get_ep_vote_access(hal_soc->hif_handle, 1038 HIF_EP_VOTE_NONDP_ACCESS); 1039 if ((vote_access == HIF_EP_VOTE_ACCESS_DISABLE) || 1040 (vote_access == HIF_EP_VOTE_INTERMEDIATE_ACCESS && 1041 PLD_MHI_STATE_L0 == 1042 pld_get_mhi_state(hal_soc->qdf_dev->dev))) { 1043 hal_write_address_32_mb(hal_soc, addr, value, false); 1044 qdf_atomic_inc(&hal_soc->stats.wstats.direct); 1045 srng->wstats.direct++; 1046 } else { 1047 hal_reg_write_enqueue(hal_soc, srng, addr, value); 1048 } 1049 break; 1050 default: 1051 if (hif_get_ep_vote_access(hal_soc->hif_handle, 1052 HIF_EP_VOTE_DP_ACCESS) == 1053 HIF_EP_VOTE_ACCESS_DISABLE || 1054 hal_is_reg_write_tput_level_high(hal_soc) || 1055 PLD_MHI_STATE_L0 == 1056 pld_get_mhi_state(hal_soc->qdf_dev->dev)) { 1057 hal_write_address_32_mb(hal_soc, addr, value, false); 1058 qdf_atomic_inc(&hal_soc->stats.wstats.direct); 1059 srng->wstats.direct++; 1060 } else { 1061 hal_reg_write_enqueue(hal_soc, srng, addr, value); 1062 } 1063 1064 break; 1065 } 1066 } 1067 #else 1068 void hal_delayed_reg_write(struct hal_soc *hal_soc, 1069 struct hal_srng *srng, 1070 void __iomem *addr, 1071 uint32_t value) 1072 { 1073 if (hal_is_reg_write_tput_level_high(hal_soc) || 1074 pld_is_device_awake(hal_soc->qdf_dev->dev)) { 1075 qdf_atomic_inc(&hal_soc->stats.wstats.direct); 1076 srng->wstats.direct++; 1077 hal_write_address_32_mb(hal_soc, addr, value, false); 1078 } else { 1079 hal_reg_write_enqueue(hal_soc, srng, addr, value); 1080 } 1081 1082 hal_record_suspend_write(srng->ring_id, value, srng->wstats.direct); 1083 } 1084 #endif 1085 #endif 1086 1087 /** 1088 * hal_attach - Initialize HAL layer 1089 * @hif_handle: Opaque HIF handle 1090 * @qdf_dev: QDF device 1091 * 1092 * Return: Opaque HAL SOC handle 1093 * NULL on failure (if given ring is not available) 1094 * 1095 * This function should be called as part of HIF initialization (for accessing 1096 * copy engines). DP layer will get hal_soc handle using hif_get_hal_handle() 1097 * 1098 */ 1099 void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev) 1100 { 1101 struct hal_soc *hal; 1102 int i; 1103 1104 hal = qdf_mem_malloc(sizeof(*hal)); 1105 1106 if (!hal) { 1107 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1108 "%s: hal_soc allocation failed", __func__); 1109 goto fail0; 1110 } 1111 hal->hif_handle = hif_handle; 1112 hal->dev_base_addr = hif_get_dev_ba(hif_handle); /* UMAC */ 1113 hal->dev_base_addr_ce = hif_get_dev_ba_ce(hif_handle); /* CE */ 1114 hal->dev_base_addr_cmem = hif_get_dev_ba_cmem(hif_handle); /* CMEM */ 1115 hal->qdf_dev = qdf_dev; 1116 hal->shadow_rdptr_mem_vaddr = (uint32_t *)qdf_mem_alloc_consistent( 1117 qdf_dev, qdf_dev->dev, sizeof(*(hal->shadow_rdptr_mem_vaddr)) * 1118 HAL_SRNG_ID_MAX, &(hal->shadow_rdptr_mem_paddr)); 1119 if (!hal->shadow_rdptr_mem_paddr) { 1120 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1121 "%s: hal->shadow_rdptr_mem_paddr allocation failed", 1122 __func__); 1123 goto fail1; 1124 } 1125 qdf_mem_zero(hal->shadow_rdptr_mem_vaddr, 1126 sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX); 1127 1128 hal->shadow_wrptr_mem_vaddr = 1129 (uint32_t *)qdf_mem_alloc_consistent(qdf_dev, qdf_dev->dev, 1130 sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS, 1131 &(hal->shadow_wrptr_mem_paddr)); 1132 if (!hal->shadow_wrptr_mem_vaddr) { 1133 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1134 "%s: hal->shadow_wrptr_mem_vaddr allocation failed", 1135 __func__); 1136 goto fail2; 1137 } 1138 qdf_mem_zero(hal->shadow_wrptr_mem_vaddr, 1139 sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS); 1140 1141 for (i = 0; i < HAL_SRNG_ID_MAX; i++) { 1142 hal->srng_list[i].initialized = 0; 1143 hal->srng_list[i].ring_id = i; 1144 } 1145 1146 qdf_spinlock_create(&hal->register_access_lock); 1147 hal->register_window = 0; 1148 hal->target_type = hal_get_target_type(hal_soc_to_hal_soc_handle(hal)); 1149 hal->version = hif_get_soc_version(hif_handle); 1150 hal->ops = qdf_mem_malloc(sizeof(*hal->ops)); 1151 1152 if (!hal->ops) { 1153 hal_err("unable to allocable memory for HAL ops"); 1154 goto fail3; 1155 } 1156 1157 hal_target_based_configure(hal); 1158 1159 hal_reg_write_fail_history_init(hal); 1160 1161 qdf_minidump_log(hal, sizeof(*hal), "hal_soc"); 1162 1163 qdf_atomic_init(&hal->active_work_cnt); 1164 hal_delayed_reg_write_init(hal); 1165 1166 hal_reo_shared_qaddr_setup((hal_soc_handle_t)hal); 1167 1168 hif_rtpm_register(HIF_RTPM_ID_HAL_REO_CMD, NULL); 1169 1170 return (void *)hal; 1171 fail3: 1172 qdf_mem_free_consistent(qdf_dev, qdf_dev->dev, 1173 sizeof(*hal->shadow_wrptr_mem_vaddr) * 1174 HAL_MAX_LMAC_RINGS, 1175 hal->shadow_wrptr_mem_vaddr, 1176 hal->shadow_wrptr_mem_paddr, 0); 1177 fail2: 1178 qdf_mem_free_consistent(qdf_dev, qdf_dev->dev, 1179 sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX, 1180 hal->shadow_rdptr_mem_vaddr, hal->shadow_rdptr_mem_paddr, 0); 1181 fail1: 1182 qdf_mem_free(hal); 1183 fail0: 1184 return NULL; 1185 } 1186 qdf_export_symbol(hal_attach); 1187 1188 /** 1189 * hal_mem_info - Retrieve hal memory base address 1190 * 1191 * @hal_soc: Opaque HAL SOC handle 1192 * @mem: pointer to structure to be updated with hal mem info 1193 */ 1194 void hal_get_meminfo(hal_soc_handle_t hal_soc_hdl, struct hal_mem_info *mem) 1195 { 1196 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1197 mem->dev_base_addr = (void *)hal->dev_base_addr; 1198 mem->shadow_rdptr_mem_vaddr = (void *)hal->shadow_rdptr_mem_vaddr; 1199 mem->shadow_wrptr_mem_vaddr = (void *)hal->shadow_wrptr_mem_vaddr; 1200 mem->shadow_rdptr_mem_paddr = (void *)hal->shadow_rdptr_mem_paddr; 1201 mem->shadow_wrptr_mem_paddr = (void *)hal->shadow_wrptr_mem_paddr; 1202 hif_read_phy_mem_base((void *)hal->hif_handle, 1203 (qdf_dma_addr_t *)&mem->dev_base_paddr); 1204 mem->lmac_srng_start_id = HAL_SRNG_LMAC1_ID_START; 1205 return; 1206 } 1207 qdf_export_symbol(hal_get_meminfo); 1208 1209 /** 1210 * hal_detach - Detach HAL layer 1211 * @hal_soc: HAL SOC handle 1212 * 1213 * Return: Opaque HAL SOC handle 1214 * NULL on failure (if given ring is not available) 1215 * 1216 * This function should be called as part of HIF initialization (for accessing 1217 * copy engines). DP layer will get hal_soc handle using hif_get_hal_handle() 1218 * 1219 */ 1220 extern void hal_detach(void *hal_soc) 1221 { 1222 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1223 1224 hif_rtpm_deregister(HIF_RTPM_ID_HAL_REO_CMD); 1225 hal_delayed_reg_write_deinit(hal); 1226 hal_reo_shared_qaddr_detach((hal_soc_handle_t)hal); 1227 qdf_mem_free(hal->ops); 1228 1229 qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev, 1230 sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX, 1231 hal->shadow_rdptr_mem_vaddr, hal->shadow_rdptr_mem_paddr, 0); 1232 qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev, 1233 sizeof(*(hal->shadow_wrptr_mem_vaddr)) * HAL_MAX_LMAC_RINGS, 1234 hal->shadow_wrptr_mem_vaddr, hal->shadow_wrptr_mem_paddr, 0); 1235 qdf_minidump_remove(hal, sizeof(*hal), "hal_soc"); 1236 1237 qdf_mem_free(hal); 1238 1239 return; 1240 } 1241 qdf_export_symbol(hal_detach); 1242 1243 #define HAL_CE_CHANNEL_DST_DEST_CTRL_ADDR(x) ((x) + 0x000000b0) 1244 #define HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0x0000ffff 1245 #define HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040) 1246 #define HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1247 /** 1248 * hal_ce_dst_setup - Initialize CE destination ring registers 1249 * @hal_soc: HAL SOC handle 1250 * @srng: SRNG ring pointer 1251 */ 1252 static inline void hal_ce_dst_setup(struct hal_soc *hal, struct hal_srng *srng, 1253 int ring_num) 1254 { 1255 uint32_t reg_val = 0; 1256 uint32_t reg_addr; 1257 struct hal_hw_srng_config *ring_config = 1258 HAL_SRNG_CONFIG(hal, CE_DST); 1259 1260 /* set DEST_MAX_LENGTH according to ce assignment */ 1261 reg_addr = HAL_CE_CHANNEL_DST_DEST_CTRL_ADDR( 1262 ring_config->reg_start[R0_INDEX] + 1263 (ring_num * ring_config->reg_size[R0_INDEX])); 1264 1265 reg_val = HAL_REG_READ(hal, reg_addr); 1266 reg_val &= ~HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK; 1267 reg_val |= srng->u.dst_ring.max_buffer_length & 1268 HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK; 1269 HAL_REG_WRITE(hal, reg_addr, reg_val); 1270 1271 if (srng->prefetch_timer) { 1272 reg_addr = HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR( 1273 ring_config->reg_start[R0_INDEX] + 1274 (ring_num * ring_config->reg_size[R0_INDEX])); 1275 1276 reg_val = HAL_REG_READ(hal, reg_addr); 1277 reg_val &= ~HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK; 1278 reg_val |= srng->prefetch_timer; 1279 HAL_REG_WRITE(hal, reg_addr, reg_val); 1280 reg_val = HAL_REG_READ(hal, reg_addr); 1281 } 1282 1283 } 1284 1285 /** 1286 * hal_reo_read_write_ctrl_ix - Read or write REO_DESTINATION_RING_CTRL_IX 1287 * @hal: HAL SOC handle 1288 * @read: boolean value to indicate if read or write 1289 * @ix0: pointer to store IX0 reg value 1290 * @ix1: pointer to store IX1 reg value 1291 * @ix2: pointer to store IX2 reg value 1292 * @ix3: pointer to store IX3 reg value 1293 */ 1294 void hal_reo_read_write_ctrl_ix(hal_soc_handle_t hal_soc_hdl, bool read, 1295 uint32_t *ix0, uint32_t *ix1, 1296 uint32_t *ix2, uint32_t *ix3) 1297 { 1298 uint32_t reg_offset; 1299 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 1300 uint32_t reo_reg_base; 1301 1302 reo_reg_base = hal_get_reo_reg_base_offset(hal_soc_hdl); 1303 1304 if (read) { 1305 if (ix0) { 1306 reg_offset = 1307 HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR( 1308 reo_reg_base); 1309 *ix0 = HAL_REG_READ(hal, reg_offset); 1310 } 1311 1312 if (ix1) { 1313 reg_offset = 1314 HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR( 1315 reo_reg_base); 1316 *ix1 = HAL_REG_READ(hal, reg_offset); 1317 } 1318 1319 if (ix2) { 1320 reg_offset = 1321 HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR( 1322 reo_reg_base); 1323 *ix2 = HAL_REG_READ(hal, reg_offset); 1324 } 1325 1326 if (ix3) { 1327 reg_offset = 1328 HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR( 1329 reo_reg_base); 1330 *ix3 = HAL_REG_READ(hal, reg_offset); 1331 } 1332 } else { 1333 if (ix0) { 1334 reg_offset = 1335 HAL_REO_DESTINATION_RING_CTRL_IX_0_ADDR( 1336 reo_reg_base); 1337 HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset, 1338 *ix0, true); 1339 } 1340 1341 if (ix1) { 1342 reg_offset = 1343 HAL_REO_DESTINATION_RING_CTRL_IX_1_ADDR( 1344 reo_reg_base); 1345 HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset, 1346 *ix1, true); 1347 } 1348 1349 if (ix2) { 1350 reg_offset = 1351 HAL_REO_DESTINATION_RING_CTRL_IX_2_ADDR( 1352 reo_reg_base); 1353 HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset, 1354 *ix2, true); 1355 } 1356 1357 if (ix3) { 1358 reg_offset = 1359 HAL_REO_DESTINATION_RING_CTRL_IX_3_ADDR( 1360 reo_reg_base); 1361 HAL_REG_WRITE_CONFIRM_RETRY(hal, reg_offset, 1362 *ix3, true); 1363 } 1364 } 1365 } 1366 1367 qdf_export_symbol(hal_reo_read_write_ctrl_ix); 1368 1369 /** 1370 * hal_srng_dst_set_hp_paddr_confirm() - Set physical address to dest ring head 1371 * pointer and confirm that write went through by reading back the value 1372 * @srng: sring pointer 1373 * @paddr: physical address 1374 * 1375 * Return: None 1376 */ 1377 void hal_srng_dst_set_hp_paddr_confirm(struct hal_srng *srng, uint64_t paddr) 1378 { 1379 SRNG_DST_REG_WRITE_CONFIRM(srng, HP_ADDR_LSB, paddr & 0xffffffff); 1380 SRNG_DST_REG_WRITE_CONFIRM(srng, HP_ADDR_MSB, paddr >> 32); 1381 } 1382 1383 qdf_export_symbol(hal_srng_dst_set_hp_paddr_confirm); 1384 1385 /** 1386 * hal_srng_dst_init_hp() - Initialize destination ring head 1387 * pointer 1388 * @hal_soc: hal_soc handle 1389 * @srng: sring pointer 1390 * @vaddr: virtual address 1391 */ 1392 void hal_srng_dst_init_hp(struct hal_soc_handle *hal_soc, 1393 struct hal_srng *srng, 1394 uint32_t *vaddr) 1395 { 1396 uint32_t reg_offset; 1397 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1398 1399 if (!srng) 1400 return; 1401 1402 srng->u.dst_ring.hp_addr = vaddr; 1403 reg_offset = SRNG_DST_ADDR(srng, HP) - hal->dev_base_addr; 1404 HAL_REG_WRITE_CONFIRM_RETRY( 1405 hal, reg_offset, srng->u.dst_ring.cached_hp, true); 1406 1407 if (vaddr) { 1408 *srng->u.dst_ring.hp_addr = srng->u.dst_ring.cached_hp; 1409 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 1410 "hp_addr=%pK, cached_hp=%d, hp=%d", 1411 (void *)srng->u.dst_ring.hp_addr, 1412 srng->u.dst_ring.cached_hp, 1413 *srng->u.dst_ring.hp_addr); 1414 } 1415 } 1416 1417 qdf_export_symbol(hal_srng_dst_init_hp); 1418 1419 /** 1420 * hal_srng_hw_init - Private function to initialize SRNG HW 1421 * @hal_soc: HAL SOC handle 1422 * @srng: SRNG ring pointer 1423 * @idle_check: Check if ring is idle 1424 */ 1425 static inline void hal_srng_hw_init(struct hal_soc *hal, 1426 struct hal_srng *srng, bool idle_check) 1427 { 1428 if (srng->ring_dir == HAL_SRNG_SRC_RING) 1429 hal_srng_src_hw_init(hal, srng, idle_check); 1430 else 1431 hal_srng_dst_hw_init(hal, srng, idle_check); 1432 } 1433 1434 #if defined(CONFIG_SHADOW_V2) || defined(CONFIG_SHADOW_V3) 1435 #define ignore_shadow false 1436 #define CHECK_SHADOW_REGISTERS true 1437 #else 1438 #define ignore_shadow true 1439 #define CHECK_SHADOW_REGISTERS false 1440 #endif 1441 1442 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ 1443 /** 1444 * hal_srng_is_near_full_irq_supported() - Check if near full irq is 1445 * supported on this SRNG 1446 * @hal_soc: HAL SoC handle 1447 * @ring_type: SRNG type 1448 * @ring_num: ring number 1449 * 1450 * Return: true, if near full irq is supported for this SRNG 1451 * false, if near full irq is not supported for this SRNG 1452 */ 1453 bool hal_srng_is_near_full_irq_supported(hal_soc_handle_t hal_soc, 1454 int ring_type, int ring_num) 1455 { 1456 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1457 struct hal_hw_srng_config *ring_config = 1458 HAL_SRNG_CONFIG(hal, ring_type); 1459 1460 return ring_config->nf_irq_support; 1461 } 1462 1463 /** 1464 * hal_srng_set_msi2_params() - Set MSI2 params to SRNG data structure from 1465 * ring params 1466 * @srng: SRNG handle 1467 * @ring_params: ring params for this SRNG 1468 * 1469 * Return: None 1470 */ 1471 static inline void 1472 hal_srng_set_msi2_params(struct hal_srng *srng, 1473 struct hal_srng_params *ring_params) 1474 { 1475 srng->msi2_addr = ring_params->msi2_addr; 1476 srng->msi2_data = ring_params->msi2_data; 1477 } 1478 1479 /** 1480 * hal_srng_get_nf_params() - Get the near full MSI2 params from srng 1481 * @srng: SRNG handle 1482 * @ring_params: ring params for this SRNG 1483 * 1484 * Return: None 1485 */ 1486 static inline void 1487 hal_srng_get_nf_params(struct hal_srng *srng, 1488 struct hal_srng_params *ring_params) 1489 { 1490 ring_params->msi2_addr = srng->msi2_addr; 1491 ring_params->msi2_data = srng->msi2_data; 1492 } 1493 1494 /** 1495 * hal_srng_set_nf_thresholds() - Set the near full thresholds in SRNG 1496 * @srng: SRNG handle where the params are to be set 1497 * @ring_params: ring params, from where threshold is to be fetched 1498 * 1499 * Return: None 1500 */ 1501 static inline void 1502 hal_srng_set_nf_thresholds(struct hal_srng *srng, 1503 struct hal_srng_params *ring_params) 1504 { 1505 srng->u.dst_ring.nf_irq_support = ring_params->nf_irq_support; 1506 srng->u.dst_ring.high_thresh = ring_params->high_thresh; 1507 } 1508 #else 1509 static inline void 1510 hal_srng_set_msi2_params(struct hal_srng *srng, 1511 struct hal_srng_params *ring_params) 1512 { 1513 } 1514 1515 static inline void 1516 hal_srng_get_nf_params(struct hal_srng *srng, 1517 struct hal_srng_params *ring_params) 1518 { 1519 } 1520 1521 static inline void 1522 hal_srng_set_nf_thresholds(struct hal_srng *srng, 1523 struct hal_srng_params *ring_params) 1524 { 1525 } 1526 #endif 1527 1528 #if defined(CLEAR_SW2TCL_CONSUMED_DESC) 1529 /** 1530 * hal_srng_last_desc_cleared_init - Initialize SRNG last_desc_cleared ptr 1531 * 1532 * @srng: Source ring pointer 1533 * 1534 * Return: None 1535 */ 1536 static inline 1537 void hal_srng_last_desc_cleared_init(struct hal_srng *srng) 1538 { 1539 srng->last_desc_cleared = srng->ring_size - srng->entry_size; 1540 } 1541 1542 #else 1543 static inline 1544 void hal_srng_last_desc_cleared_init(struct hal_srng *srng) 1545 { 1546 } 1547 #endif /* CLEAR_SW2TCL_CONSUMED_DESC */ 1548 1549 #ifdef WLAN_DP_SRNG_USAGE_WM_TRACKING 1550 static inline void hal_srng_update_high_wm_thresholds(struct hal_srng *srng) 1551 { 1552 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_90_to_100] = 1553 ((srng->num_entries * 90) / 100); 1554 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_80_to_90] = 1555 ((srng->num_entries * 80) / 100); 1556 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_70_to_80] = 1557 ((srng->num_entries * 70) / 100); 1558 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_60_to_70] = 1559 ((srng->num_entries * 60) / 100); 1560 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_50_to_60] = 1561 ((srng->num_entries * 50) / 100); 1562 /* Below 50% threshold is not needed */ 1563 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT] = 0; 1564 1565 hal_info("ring_id: %u, wm_thresh- <50:%u, 50-60:%u, 60-70:%u, 70-80:%u, 80-90:%u, 90-100:%u", 1566 srng->ring_id, 1567 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT], 1568 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_50_to_60], 1569 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_60_to_70], 1570 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_70_to_80], 1571 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_80_to_90], 1572 srng->high_wm.bin_thresh[HAL_SRNG_HIGH_WM_BIN_90_to_100]); 1573 } 1574 #else 1575 static inline void hal_srng_update_high_wm_thresholds(struct hal_srng *srng) 1576 { 1577 } 1578 #endif 1579 1580 /** 1581 * hal_srng_setup - Initialize HW SRNG ring. 1582 * @hal_soc: Opaque HAL SOC handle 1583 * @ring_type: one of the types from hal_ring_type 1584 * @ring_num: Ring number if there are multiple rings of same type (staring 1585 * from 0) 1586 * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings 1587 * @ring_params: SRNG ring params in hal_srng_params structure. 1588 * @idle_check: Check if ring is idle 1589 * 1590 * Callers are expected to allocate contiguous ring memory of size 1591 * 'num_entries * entry_size' bytes and pass the physical and virtual base 1592 * addresses through 'ring_base_paddr' and 'ring_base_vaddr' in 1593 * hal_srng_params structure. Ring base address should be 8 byte aligned 1594 * and size of each ring entry should be queried using the API 1595 * hal_srng_get_entrysize 1596 * 1597 * Return: Opaque pointer to ring on success 1598 * NULL on failure (if given ring is not available) 1599 */ 1600 void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num, 1601 int mac_id, struct hal_srng_params *ring_params, bool idle_check) 1602 { 1603 int ring_id; 1604 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1605 struct hal_srng *srng; 1606 struct hal_hw_srng_config *ring_config = 1607 HAL_SRNG_CONFIG(hal, ring_type); 1608 void *dev_base_addr; 1609 int i; 1610 1611 ring_id = hal_get_srng_ring_id(hal_soc, ring_type, ring_num, mac_id); 1612 if (ring_id < 0) 1613 return NULL; 1614 1615 hal_verbose_debug("mac_id %d ring_id %d", mac_id, ring_id); 1616 1617 srng = hal_get_srng(hal_soc, ring_id); 1618 1619 if (srng->initialized) { 1620 hal_verbose_debug("Ring (ring_type, ring_num) already initialized"); 1621 return NULL; 1622 } 1623 1624 dev_base_addr = hal->dev_base_addr; 1625 srng->ring_id = ring_id; 1626 srng->ring_type = ring_type; 1627 srng->ring_dir = ring_config->ring_dir; 1628 srng->ring_base_paddr = ring_params->ring_base_paddr; 1629 srng->ring_base_vaddr = ring_params->ring_base_vaddr; 1630 srng->entry_size = ring_config->entry_size; 1631 srng->num_entries = ring_params->num_entries; 1632 srng->ring_size = srng->num_entries * srng->entry_size; 1633 srng->ring_size_mask = srng->ring_size - 1; 1634 srng->ring_vaddr_end = srng->ring_base_vaddr + srng->ring_size; 1635 srng->msi_addr = ring_params->msi_addr; 1636 srng->msi_data = ring_params->msi_data; 1637 srng->intr_timer_thres_us = ring_params->intr_timer_thres_us; 1638 srng->intr_batch_cntr_thres_entries = 1639 ring_params->intr_batch_cntr_thres_entries; 1640 if (!idle_check) 1641 srng->prefetch_timer = ring_params->prefetch_timer; 1642 srng->hal_soc = hal_soc; 1643 hal_srng_set_msi2_params(srng, ring_params); 1644 hal_srng_update_high_wm_thresholds(srng); 1645 1646 for (i = 0 ; i < MAX_SRNG_REG_GROUPS; i++) { 1647 srng->hwreg_base[i] = dev_base_addr + ring_config->reg_start[i] 1648 + (ring_num * ring_config->reg_size[i]); 1649 } 1650 1651 /* Zero out the entire ring memory */ 1652 qdf_mem_zero(srng->ring_base_vaddr, (srng->entry_size * 1653 srng->num_entries) << 2); 1654 1655 srng->flags = ring_params->flags; 1656 1657 /* For cached descriptors flush and invalidate the memory*/ 1658 if (srng->flags & HAL_SRNG_CACHED_DESC) { 1659 qdf_nbuf_dma_clean_range( 1660 srng->ring_base_vaddr, 1661 srng->ring_base_vaddr + 1662 ((srng->entry_size * srng->num_entries))); 1663 qdf_nbuf_dma_inv_range( 1664 srng->ring_base_vaddr, 1665 srng->ring_base_vaddr + 1666 ((srng->entry_size * srng->num_entries))); 1667 } 1668 #ifdef BIG_ENDIAN_HOST 1669 /* TODO: See if we should we get these flags from caller */ 1670 srng->flags |= HAL_SRNG_DATA_TLV_SWAP; 1671 srng->flags |= HAL_SRNG_MSI_SWAP; 1672 srng->flags |= HAL_SRNG_RING_PTR_SWAP; 1673 #endif 1674 1675 hal_srng_last_desc_cleared_init(srng); 1676 1677 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1678 srng->u.src_ring.hp = 0; 1679 srng->u.src_ring.reap_hp = srng->ring_size - 1680 srng->entry_size; 1681 srng->u.src_ring.tp_addr = 1682 &(hal->shadow_rdptr_mem_vaddr[ring_id]); 1683 srng->u.src_ring.low_threshold = 1684 ring_params->low_threshold * srng->entry_size; 1685 1686 if (srng->u.src_ring.tp_addr) 1687 qdf_mem_zero(srng->u.src_ring.tp_addr, 1688 sizeof(*hal->shadow_rdptr_mem_vaddr)); 1689 1690 if (ring_config->lmac_ring) { 1691 /* For LMAC rings, head pointer updates will be done 1692 * through FW by writing to a shared memory location 1693 */ 1694 srng->u.src_ring.hp_addr = 1695 &(hal->shadow_wrptr_mem_vaddr[ring_id - 1696 HAL_SRNG_LMAC1_ID_START]); 1697 srng->flags |= HAL_SRNG_LMAC_RING; 1698 1699 if (srng->u.src_ring.hp_addr) 1700 qdf_mem_zero(srng->u.src_ring.hp_addr, 1701 sizeof(*hal->shadow_wrptr_mem_vaddr)); 1702 1703 } else if (ignore_shadow || (srng->u.src_ring.hp_addr == 0)) { 1704 srng->u.src_ring.hp_addr = 1705 hal_get_window_address(hal, 1706 SRNG_SRC_ADDR(srng, HP)); 1707 1708 if (CHECK_SHADOW_REGISTERS) { 1709 QDF_TRACE(QDF_MODULE_ID_TXRX, 1710 QDF_TRACE_LEVEL_ERROR, 1711 "%s: Ring (%d, %d) missing shadow config", 1712 __func__, ring_type, ring_num); 1713 } 1714 } else { 1715 hal_validate_shadow_register(hal, 1716 SRNG_SRC_ADDR(srng, HP), 1717 srng->u.src_ring.hp_addr); 1718 } 1719 } else { 1720 /* During initialization loop count in all the descriptors 1721 * will be set to zero, and HW will set it to 1 on completing 1722 * descriptor update in first loop, and increments it by 1 on 1723 * subsequent loops (loop count wraps around after reaching 1724 * 0xffff). The 'loop_cnt' in SW ring state is the expected 1725 * loop count in descriptors updated by HW (to be processed 1726 * by SW). 1727 */ 1728 hal_srng_set_nf_thresholds(srng, ring_params); 1729 srng->u.dst_ring.loop_cnt = 1; 1730 srng->u.dst_ring.tp = 0; 1731 srng->u.dst_ring.hp_addr = 1732 &(hal->shadow_rdptr_mem_vaddr[ring_id]); 1733 1734 if (srng->u.dst_ring.hp_addr) 1735 qdf_mem_zero(srng->u.dst_ring.hp_addr, 1736 sizeof(*hal->shadow_rdptr_mem_vaddr)); 1737 1738 if (ring_config->lmac_ring) { 1739 /* For LMAC rings, tail pointer updates will be done 1740 * through FW by writing to a shared memory location 1741 */ 1742 srng->u.dst_ring.tp_addr = 1743 &(hal->shadow_wrptr_mem_vaddr[ring_id - 1744 HAL_SRNG_LMAC1_ID_START]); 1745 srng->flags |= HAL_SRNG_LMAC_RING; 1746 1747 if (srng->u.dst_ring.tp_addr) 1748 qdf_mem_zero(srng->u.dst_ring.tp_addr, 1749 sizeof(*hal->shadow_wrptr_mem_vaddr)); 1750 1751 } else if (ignore_shadow || srng->u.dst_ring.tp_addr == 0) { 1752 srng->u.dst_ring.tp_addr = 1753 hal_get_window_address(hal, 1754 SRNG_DST_ADDR(srng, TP)); 1755 1756 if (CHECK_SHADOW_REGISTERS) { 1757 QDF_TRACE(QDF_MODULE_ID_TXRX, 1758 QDF_TRACE_LEVEL_ERROR, 1759 "%s: Ring (%d, %d) missing shadow config", 1760 __func__, ring_type, ring_num); 1761 } 1762 } else { 1763 hal_validate_shadow_register(hal, 1764 SRNG_DST_ADDR(srng, TP), 1765 srng->u.dst_ring.tp_addr); 1766 } 1767 } 1768 1769 if (!(ring_config->lmac_ring)) { 1770 hal_srng_hw_init(hal, srng, idle_check); 1771 1772 if (ring_type == CE_DST) { 1773 srng->u.dst_ring.max_buffer_length = ring_params->max_buffer_length; 1774 hal_ce_dst_setup(hal, srng, ring_num); 1775 } 1776 } 1777 1778 SRNG_LOCK_INIT(&srng->lock); 1779 1780 srng->srng_event = 0; 1781 1782 srng->initialized = true; 1783 1784 return (void *)srng; 1785 } 1786 qdf_export_symbol(hal_srng_setup); 1787 1788 /** 1789 * hal_srng_cleanup - Deinitialize HW SRNG ring. 1790 * @hal_soc: Opaque HAL SOC handle 1791 * @hal_srng: Opaque HAL SRNG pointer 1792 */ 1793 void hal_srng_cleanup(void *hal_soc, hal_ring_handle_t hal_ring_hdl) 1794 { 1795 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1796 SRNG_LOCK_DESTROY(&srng->lock); 1797 srng->initialized = 0; 1798 hal_srng_hw_disable(hal_soc, srng); 1799 } 1800 qdf_export_symbol(hal_srng_cleanup); 1801 1802 /** 1803 * hal_srng_get_entrysize - Returns size of ring entry in bytes 1804 * @hal_soc: Opaque HAL SOC handle 1805 * @ring_type: one of the types from hal_ring_type 1806 * 1807 */ 1808 uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type) 1809 { 1810 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1811 struct hal_hw_srng_config *ring_config = 1812 HAL_SRNG_CONFIG(hal, ring_type); 1813 return ring_config->entry_size << 2; 1814 } 1815 qdf_export_symbol(hal_srng_get_entrysize); 1816 1817 /** 1818 * hal_srng_max_entries - Returns maximum possible number of ring entries 1819 * @hal_soc: Opaque HAL SOC handle 1820 * @ring_type: one of the types from hal_ring_type 1821 * 1822 * Return: Maximum number of entries for the given ring_type 1823 */ 1824 uint32_t hal_srng_max_entries(void *hal_soc, int ring_type) 1825 { 1826 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1827 struct hal_hw_srng_config *ring_config = 1828 HAL_SRNG_CONFIG(hal, ring_type); 1829 1830 return ring_config->max_size / ring_config->entry_size; 1831 } 1832 qdf_export_symbol(hal_srng_max_entries); 1833 1834 enum hal_srng_dir hal_srng_get_dir(void *hal_soc, int ring_type) 1835 { 1836 struct hal_soc *hal = (struct hal_soc *)hal_soc; 1837 struct hal_hw_srng_config *ring_config = 1838 HAL_SRNG_CONFIG(hal, ring_type); 1839 1840 return ring_config->ring_dir; 1841 } 1842 1843 /** 1844 * hal_srng_dump - Dump ring status 1845 * @srng: hal srng pointer 1846 */ 1847 void hal_srng_dump(struct hal_srng *srng) 1848 { 1849 if (srng->ring_dir == HAL_SRNG_SRC_RING) { 1850 hal_debug("=== SRC RING %d ===", srng->ring_id); 1851 hal_debug("hp %u, reap_hp %u, tp %u, cached tp %u", 1852 srng->u.src_ring.hp, 1853 srng->u.src_ring.reap_hp, 1854 *srng->u.src_ring.tp_addr, 1855 srng->u.src_ring.cached_tp); 1856 } else { 1857 hal_debug("=== DST RING %d ===", srng->ring_id); 1858 hal_debug("tp %u, hp %u, cached tp %u, loop_cnt %u", 1859 srng->u.dst_ring.tp, 1860 *srng->u.dst_ring.hp_addr, 1861 srng->u.dst_ring.cached_hp, 1862 srng->u.dst_ring.loop_cnt); 1863 } 1864 } 1865 1866 /** 1867 * hal_get_srng_params - Retrieve SRNG parameters for a given ring from HAL 1868 * 1869 * @hal_soc: Opaque HAL SOC handle 1870 * @hal_ring: Ring pointer (Source or Destination ring) 1871 * @ring_params: SRNG parameters will be returned through this structure 1872 */ 1873 extern void hal_get_srng_params(hal_soc_handle_t hal_soc_hdl, 1874 hal_ring_handle_t hal_ring_hdl, 1875 struct hal_srng_params *ring_params) 1876 { 1877 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1878 int i =0; 1879 ring_params->ring_id = srng->ring_id; 1880 ring_params->ring_dir = srng->ring_dir; 1881 ring_params->entry_size = srng->entry_size; 1882 1883 ring_params->ring_base_paddr = srng->ring_base_paddr; 1884 ring_params->ring_base_vaddr = srng->ring_base_vaddr; 1885 ring_params->num_entries = srng->num_entries; 1886 ring_params->msi_addr = srng->msi_addr; 1887 ring_params->msi_data = srng->msi_data; 1888 ring_params->intr_timer_thres_us = srng->intr_timer_thres_us; 1889 ring_params->intr_batch_cntr_thres_entries = 1890 srng->intr_batch_cntr_thres_entries; 1891 ring_params->low_threshold = srng->u.src_ring.low_threshold; 1892 ring_params->flags = srng->flags; 1893 ring_params->ring_id = srng->ring_id; 1894 for (i = 0 ; i < MAX_SRNG_REG_GROUPS; i++) 1895 ring_params->hwreg_base[i] = srng->hwreg_base[i]; 1896 1897 hal_srng_get_nf_params(srng, ring_params); 1898 } 1899 qdf_export_symbol(hal_get_srng_params); 1900 1901 void hal_set_low_threshold(hal_ring_handle_t hal_ring_hdl, 1902 uint32_t low_threshold) 1903 { 1904 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 1905 srng->u.src_ring.low_threshold = low_threshold * srng->entry_size; 1906 } 1907 qdf_export_symbol(hal_set_low_threshold); 1908 1909 #ifdef FEATURE_RUNTIME_PM 1910 void 1911 hal_srng_rtpm_access_end(hal_soc_handle_t hal_soc_hdl, 1912 hal_ring_handle_t hal_ring_hdl, 1913 uint32_t rtpm_id) 1914 { 1915 if (qdf_unlikely(!hal_ring_hdl)) { 1916 qdf_print("Error: Invalid hal_ring\n"); 1917 return; 1918 } 1919 1920 if (hif_rtpm_get(HIF_RTPM_GET_ASYNC, rtpm_id) == 0) { 1921 hal_srng_access_end(hal_soc_hdl, hal_ring_hdl); 1922 hif_rtpm_put(HIF_RTPM_PUT_ASYNC, rtpm_id); 1923 } else { 1924 hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl); 1925 hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT); 1926 hal_srng_inc_flush_cnt(hal_ring_hdl); 1927 } 1928 } 1929 1930 qdf_export_symbol(hal_srng_rtpm_access_end); 1931 #endif /* FEATURE_RUNTIME_PM */ 1932 1933 #ifdef FORCE_WAKE 1934 void hal_set_init_phase(hal_soc_handle_t soc, bool init_phase) 1935 { 1936 struct hal_soc *hal_soc = (struct hal_soc *)soc; 1937 hal_soc->init_phase = init_phase; 1938 } 1939 #endif /* FORCE_WAKE */ 1940